Multi-valued logic circuit based on multifunctional thermal emitter transistor and construction method
Through the multi-valued logic circuit design based on multi-functional heat emitter transistors, a low-power multi-valued logic circuit is constructed using its ultra-low sub-threshold swing and high negative differential resistance peak-to-grough current ratio, a low-power multi-valued logic circuit is solved, and the power consumption problem of traditional digital circuits is achieved and efficient multi-valued logic operation is achieved.
Patent Information
- Application Number
- CN202410210080.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-26
- Publication Date
- 2025-08-29
AI Technical Summary
The power consumption problem of traditional digital circuits limits its further development. The existing multi-value logic circuits have shortcomings in materials and devices, making it difficult to achieve low-power and efficient multi-value logic operations.
Based on the multifunctional thermal emitter transistor, a multi-value logic circuit is constructed using its ultra-low sub-threshold swing and high negative differential resistance peak-to-valve current ratio, and a low-power quad-digital logic inverter, adjustable ternary digital inverter, follower and adder are formed by connecting three parallel transistors in parallel.
It realizes a multi-value logic circuit with low power consumption and high transconductance gain, which can generate large current changes under small voltage changes, reduce circuit complexity and increase switching speed, and is suitable for integration and expansion in the high-speed information age.
Smart Images
Figure CN120568833A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the research, development and application of multifunctional device logic circuits, and specifically to a multi-valued logic circuit based on a multifunctional hot emitter transistor and a construction method thereof. Background Art
[0002] Digital circuits are characterized by the use of discrete information to process signals, often using the "binary" system, typically two discrete digits: "0" and "1." This signal processing method offers the advantages of high accuracy and reliability, as well as strong resistance to noise and interference. As long as the logical state remains unchanged, the accuracy of the final result remains unchanged. Binary logic systems have revolutionized modern electronics and our daily lives. However, with increasing circuit integration and growing application demands, power consumption has become a key factor limiting the further development of traditional digital circuits. Increasing data levels through the implementation of multi-valued logic has received increasing attention. In digital processing, the transition from binary to multi-valued logic significantly increases information density, allowing more information to be processed using fewer devices, significantly reducing power consumption and the complexity of circuit integration. In recent years, multi-valued logic circuits based on various new materials have made significant progress. In particular, new device concepts based on specialized arrays and novel semiconductor and nanomaterials are expected to expand the application of multi-valued logic circuits.
[0003] Research on hybrid dimensional electronic devices combining bulk and low-dimensional materials has been booming recently. Different dimensional materials offer advantages across various material scales, electrical, and optical properties. In particular, the rich band structures of low-dimensional materials can form various barriers with bulk materials, thereby controlling carrier transport. Multifunctional hot emitter transistors fabricated from graphene and germanium utilize carrier injection and acceleration to construct novel devices with ultra-low subthreshold swings in transfer characteristics and significant negative differential resistance in output characteristics. This ultra-low subthreshold swing allows for large current variations with minimal voltage changes, enabling the construction of low-power circuits. In the output characteristics, since the position at which each collector current reaches its maximum is controlled by its base bias, different base bias combinations result in different logic states in the output signal, making them tunable and capable of exhibiting diverse functions. Therefore, multifunctional hot emitter transistors can be used to construct low-power, tunable integrated circuits. Here, three parallel transistors are connected in parallel to fabricate a multi-valued logic circuit. The present invention is based on a multifunctional hot emitter transistor and utilizes its ultra-low subthreshold swing and negative differential resistance to construct a multi-valued logic circuit, realizing a low-power quaternary digital logic inverter with high transconductance gain, as well as a ternary digital inverter, follower, and adder with adjustable functions, providing an integrable, scalable, and adjustable high-speed, low-power logic circuit for the rapidly developing information age. Summary of the Invention
[0004] The purpose of the present invention is to provide a multi-valued logic circuit based on a multifunctional hot emitter transistor and a construction method thereof. By utilizing the ultra-low subthreshold swing in the transfer characteristics of the multifunctional hot emitter transistor, a quaternary digital logic inverter with low power consumption is constructed, and its transconductance gain can reach 900μAμm -1 V -1 ; The high negative differential resistance peak-to-valley current ratio in the output characteristics is used to construct inverters, followers and adders under different input voltages, thus constructing a new low-power, adjustable logic circuit.
[0005] The technical solution of the present invention:
[0006] A multi-valued logic circuit based on multifunctional hot emitter transistors consists of three parallel multifunctional hot emitter transistors connected in parallel. From top to bottom, the circuit includes a graphene channel with a gap at the top, a hafnium oxide insulating layer and a germanium substrate, as well as base and emitter metal electrodes located on both sides of the graphene channel and in contact with the graphene channel. The metal electrodes are a top-down stacked composite structure of gold / titanium. Below the emitter and base are a hafnium oxide insulating layer and a germanium substrate. A metal collector is arranged at the bottom of the germanium substrate. The metal collector is a top-down stacked composite structure of Ti / Au. The emitters are connected to each other, while the bases are independent of each other.
[0007] The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor comprises the following steps:
[0008] (1) The germanium substrate was ultrasonically cleaned with acetone and isopropanol to remove surface impurities, and then washed with diluted hydrofluoric acid and deionized water to remove surface oxides;
[0009] (2) depositing a hafnium oxide insulating layer on a germanium substrate by atomic layer deposition;
[0010] (3) Scrape the back of the germanium substrate using a diamond cutter and deposit gold / titanium electrodes using electron beam evaporation;
[0011] (4) using photolithography technology to prepare a photoresist mask layer, and exposing the base and emitter metal electrode patterns to obtain the metal electrode area on the hafnium oxide insulating layer, and using vacuum electron beam evaporation to evaporate gold / titanium electrodes;
[0012] (5) using photolithography technology to prepare a photoresist mask layer, and exposing the required window pattern, and using reactive ion etching to etch the hafnium oxide window to expose the germanium substrate;
[0013] (6) growing a graphene film on a platinum foil by chemical vapor deposition and transferring the graphene film to a prepared germanium substrate by bubbling transfer;
[0014] (7) using photolithography technology to prepare a photoresist mask layer, and exposing the desired graphene channel pattern to obtain the graphene channel area and the gap in the graphene channel;
[0015] (8) Using oxygen ion etching technology, oxygen is introduced to clean away the excess graphene film exposed outside the base and emitter metal electrodes.
[0016] The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor comprises the following steps: in step (1), the germanium substrate is a p-type lightly doped germanium sheet having a thickness of 500 μm and a resistivity of 1 to 10 Ω·cm; the diluted hydrofluoric acid is obtained by diluting the original concentration hydrofluoric acid with deionized water in a volume ratio of 1:8, the original hydrofluoric acid concentration is 40 wt%, and the treatment time in both the dilute hydrofluoric acid and the deionized water is 1 minute.
[0017] In the method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor, in step (2), an atomic layer deposition is used to deposit a hafnium oxide insulating layer at 200° C. with a thickness of 30 nm.
[0018] The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor comprises the following steps: in step (3), using a diamond cutter to scrape the oxide layer on the back of the germanium wafer; using an electron beam evaporator to evaporate the Ti layer of the top metal electrode to a thickness ranging from 5 to 6 nm, and then continuing to evaporate the Au layer to a thickness ranging from 50 to 60 nm.
[0019] The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor comprises the following steps: in step (4), sequentially spin-coating LOR3A and S-1813 double-layer photoresists and exposing for 4.5 seconds; using an electron beam evaporator to evaporate the Ti layer of the top metal electrode to a thickness ranging from 5 to 6 nm, and then continuing to evaporate the Au layer to a thickness ranging from 50 to 60 nm.
[0020] The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor comprises the following steps: in step (5), sequentially spin-coating LOR3A and S-1813 double-layer photoresists on the hafnium oxide insulating layer, and exposing for 4.5 seconds to obtain the desired window pattern; using reactive ion etching to form the window, the conditions are: using tetrafluoromethane with a flow rate of 50 sccm as the etching gas, a pressure of 5.0 Pa, a power of 200 W, and an etching time of 5 minutes; then, cleaning with the dilute hydrofluoric acid used in step (1) for 30 seconds.
[0021] In the method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor, in step (7), S-1813 photoresist is spin-coated on the graphene and exposed for 4.5 seconds.
[0022] In the method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor, in step (8), an oxygen ion cleaner is used for etching, and the etching conditions are: using oxygen with a flow rate of 180 sccm as the etching gas, a pressure of 1.5 to 2.5 Pa, a power of 200 W, and an etching time of 2 minutes.
[0023] The design concept of the present invention is:
[0024] Multifunctional hot emitter transistors (HETs) exhibit ultra-low subthreshold swing and a negative differential resistance peak-to-valley current ratio exceeding 100. This phenomenon is due to the stimulated emission of hot carriers. The ultra-low subthreshold swing is primarily affected by the distance between the base and emitter, while the high negative differential resistance peak-to-valley current ratio is due to the location of negative resistance at different base biases. Based on this, we designed a multivalued logic circuit based on HETs.
[0025] The present invention proposes a multi-valued logic circuit based on a multifunctional hot emitter transistor. The multifunctional hot emitter transistor has an ultra-low subthreshold swing and a negative differential resistance peak-to-valley current ratio exceeding 100. That is, the ultra-low subthreshold swing of the multifunctional hot emitter transistor is utilized to construct a quaternary digital logic circuit with low power consumption and high speed; the high negative differential resistance peak-to-valley current ratio is utilized to construct inverters, followers, and adders under different input voltages, providing an integrable, scalable, and adjustable high-speed and low-power logic circuit for the rapidly developing information age.
[0026] The advantages and beneficial effects of the present invention are:
[0027] 1. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor involved in the present invention expands the application of the multifunctional hot emitter transistor and rationally utilizes its advantages of having a small subthreshold swing and negative differential resistance.
[0028] 2. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor involved in the present invention has a simple process flow and can expand more logic values by increasing the number of parallel transistors according to the multi-value number requirements.
[0029] 3. The present invention constructs a multi-valued logic circuit based on a multifunctional hot emitter transistor, and utilizes the small subthreshold swing of its transfer characteristic to prepare a four-value inverter with high transconductance gain, thereby achieving large current changes under relatively low voltage changes, improving the switching speed, and reducing circuit power consumption.
[0030] 4. The present invention constructs a multi-valued logic circuit based on a multifunctional hot emitter transistor, utilizing its high output characteristic of negative differential resistance peak-to-valley current ratio, and changing the working state of the device by changing the base voltage, thereby realizing an inverter, a follower, and an adder in one circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 This is an optical microscope image of a parallel circuit of three multifunctional hot emitter transistors, with a common Ti / Au emitter, a Ge collector, and three separate bases. In the image, "Windows of HfO2" represents the hafnium oxide window, "base-Gr" represents the graphene channel base, and "emitter-Gr" represents the graphene channel emitter.
[0032] Figure 2 The equivalent circuit diagram of three multifunctional hot emitter transistors in parallel shows three separate base V b1 -V b3 and the common emitter (V e , I e ) and the common collector (V c , I c).
[0033] Figure 3 It is a quaternary digital logic inverter. Its input (IN) and output (OUT) are voltage and current signals respectively. b3 Changes in I c There are three mutations, showing a four-valued logic inverter. In the figure, the horizontal axis V b3 Represents the base voltage of the third transistor (V), the vertical axis I c represents the collector current (10 2 μA -1 μm -1 ).
[0034] Figure 4 for Figure 3 The logic inverter has a high transconductance gain of about 800μAμm -1 V -1 In the figure, the horizontal axis V b3 Represents the base voltage of the third transistor (V), the vertical axis g m represents the transconductance gain (10 2 μAμm -1 V -1 ).
[0035] Figure 5 is the emitter current I e The quaternary digital logic inverter is displayed as the voltage changes. In the figure, the horizontal axis V b3 Represents the base voltage of the third transistor (V), the vertical axis I e represents the emitter current (10 2 μA -1 μm -1 ).
[0036] Figure 6 for Figure 5 The logic inverter has a high transconductance gain of about 900μAμm -1 V -1 In the figure, the horizontal axis V b3 Represents the base voltage of the third transistor (V), the vertical axis g m represents the transconductance gain (10 2 μAμm -1 V -1 ).
[0037] Figure 7 It is a three-value digital logic inverter, the input logic signal (IN) is (2, 1, 0), and the output logic signal (OUT) is (0, 1, 2). c Represents the transistor collector voltage (V), the vertical axis I crepresents the collector current (10 2 μA -1 μm -1 ).
[0038] Figure 8 For a three-value digital logic follower, the input logic signal (IN) is (2, 1, 0), and the output logic signal (OUT) is (2, 1, 0). In the figure, the horizontal axis V c Represents the transistor collector voltage (V), the vertical axis I c represents the collector current (10 2 μA -1 μm -1 ).
[0039] Figure 9 For a three-value digital logic adder, the input logic signal (IN) is (2, 1, 0), and the output logic signal (OUT) is (0, 2, 1). c Represents the transistor collector voltage (V), the vertical axis I c represents the collector current (10 2 μA -1 μm -1 ). DETAILED DESCRIPTION
[0040] In a specific implementation, the present invention proposes a multi-valued logic circuit based on a multifunctional hot emitter transistor and its fabrication method. Three parallel multifunctional hot emitter transistors are connected in parallel, and then their emitters are interconnected, while their bases are independent, to construct a multi-valued logic circuit. Utilizing the ultra-low subthreshold swing of the multifunctional hot emitter transistor, a low-power quaternary digital logic inverter with high transconductance gain is constructed, with a transconductance gain of approximately 900μAμm. -1 V -1 By utilizing the high negative differential resistance peak-to-valley current ratio of the multifunctional hot emitter transistor, a follower, inverter, and adder capable of operating at different input voltages are constructed.
[0041] The method for preparing the multi-valued logic circuit of the multifunctional hot emitter transistor prepared by the present invention is as follows:
[0042] It is necessary to pre-treat p-type germanium to prepare the required p-type lightly doped germanium substrate and transfer graphene to the target substrate; it is necessary to design and prepare a parallel circuit with three transistors; and it is necessary to determine the test and evaluation method for the performance of multi-valued logic circuits in different operating modes. Among them, the p-type lightly doped germanium substrate is doped with Ga element with a doping concentration of 1.2×10 15 ~1.9×10 16 cm -3 , the resistivity is 1~10Ω.
[0043] In the specific experiment, the following steps are taken respectively:
[0044] (1) Pre-treat the p-type germanium substrate. Use p-type germanium with a resistivity of 1 to 10 Ω·cm as the substrate. First, ultrasonically clean it with acetone and isopropyl alcohol for 5 minutes to remove surface impurities. Then soak it in diluted hydrofluoric acid solution and deionized water for 1 minute each to remove the natural oxide on the germanium surface. The diluted hydrofluoric acid aqueous solution used is obtained by diluting the original concentration of hydrofluoric acid and deionized water in a volume ratio of 1:8. The original concentration of hydrofluoric acid is 40wt%. Then, a 30nm thick HfO2 insulating layer is deposited on the germanium substrate by atomic layer deposition (ALD), and gold / titanium electrodes are evaporated. On the germanium substrate with the gold / titanium electrodes evaporated, the HfO2 insulating layer on the substrate is etched by reactive ion etching (RIE) to open a window to expose the germanium substrate. Then, the etched germanium substrate is cleaned with the diluted hydrofluoric acid solution for 30 seconds to remove the residual HfO2 in the window. A graphene film was grown on a platinum foil using the CVD method, and then transferred to a target substrate (p-type germanium substrate) using the bubble transfer method to construct a graphene / germanium Schottky junction.
[0045] (2) Preparation of a parallel circuit with three transistors: On the graphene-transferred germanium substrate, S-1813 photoresist was spin-coated, heated at 120°C for 2 minutes, and then developed by photolithography to obtain a graphene channel region with a gap width of 2 μm. Excess graphene was etched away using an oxygen ion cleaner (O-plasma). The etching parameters were: oxygen flow rate of 180 sccm, pressure of 1.5-2.5 Pa, power of 200 W, and etching time of 2 minutes.
[0046] (3) Test and analyze the multi-valued logic circuit in different working modes: Apply different voltages at different ends of the circuit to explore the working performance of the multi-valued logic circuit in different working modes. Select multiple circuits for multiple experimental tests and analyses to prove the repeatability of the experiment and the accuracy of the data.
[0047] The feasibility of the present invention is further demonstrated below by examples.
[0048] Example
[0049] In this embodiment, the method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor is as follows:
[0050] (1) A p-type germanium substrate with a resistivity of 1 to 10 Ω·cm was ultrasonically cleaned in acetone and then isopropyl alcohol to remove surface impurities. The substrate was then cleaned in dilute hydrofluoric acid and then deionized water to remove surface oxides. The washing time for each dilute hydrofluoric acid and deionized water was 1 minute. The dilute hydrofluoric acid used was prepared by diluting a 40 wt% hydrofluoric acid solution with deionized water in a 1:8 volume ratio. A 30 nm thick HfO2 insulating layer was then deposited on the cleaned germanium substrate by ALD at 200°C.
[0051] (2) The back of the germanium substrate, on which the HfO2 insulating layer had been deposited, was scratched with a diamond cutter to create defects. The substrate was then ultrasonically cleaned with acetone and then isopropyl alcohol, using the following cleaning parameters: power 60W, time 5 minutes. Subsequently, a metal collector was deposited on the bottom of the substrate using an electron beam evaporator. After the Ti layer was deposited to a thickness of 5-6 nm, an Au layer was deposited to a thickness of 50-60 nm to form a good ohmic contact on the bottom.
[0052] A double layer of LOR3A and S-1813 photoresists was spin-coated sequentially on a germanium substrate with an HfO2 insulating layer. The desired independent base and interconnected emitter electrode patterns were obtained by photolithography and development. The base and emitter metal electrodes were then deposited using an electron beam evaporator. The Au layer for the top metal electrode was deposited using an electron beam evaporator to a thickness of 50 to 60 nm, followed by a Ti layer with a thickness of 5 to 6 nm.
[0053] (3) The germanium substrate with the HfO2 insulating layer on the top was spin-coated with LOR3A and S-1813 double-layer photoresists in sequence, and the photolithography was developed and exposed for 4.5 seconds to obtain the required three parallel window patterns on the HfO2 insulating layer. The HfO2 insulating layer was then etched by RIE to expose the required germanium substrate portion. The etching parameters were: tetrafluoromethane with a flow rate of 50 sccm as the etching gas, a pressure of 5.0 Pa, a power of 200 W, and an etching time of 5 minutes. The etched germanium substrate was then cleaned with the dilute hydrofluoric acid in step (1) for 30 seconds to remove the residual HfO2.
[0054] (4) Graphene was prepared on a platinum foil substrate using chemical vapor deposition. Polymethyl methacrylate (PMMA) was then spin-coated on the graphene-grown platinum foil substrate using a bubble transfer method. The PMMA / graphene layer was then separated from the platinum foil in a 1 mol / L sodium hydroxide aqueous solution and transferred to a target germanium substrate. The PMMA was then washed off with acetone at 50°C.
[0055] (5) The germanium substrate with the transferred graphene was used to prepare a photoresist mask layer using photolithography technology, and the desired graphene channel pattern was exposed to obtain the graphene channel area; S-1813 was spin-coated and exposed for 4.5 seconds before development. The development parameters were: CD-26 developer was used for development for 15 seconds, followed by rinsing in deionized water for 1 minute to remove the residual developer. The germanium substrate after photolithography was etched using oxygen ion etching technology in an oxygen ion cleaning machine to remove excess graphene. The etching parameters were: oxygen with a flow rate of 180 sccm as the etching gas, a pressure of 1.5 to 2.5 Pa, a power of 200 W, and an etching time of 2 minutes.
[0056] This multi-valued logic circuit comprises a top metal gate electrode, base and emitter metal electrodes, a graphene channel, a germanium substrate, and a metal collector electrode beneath the germanium substrate. Its basic structure, from top to bottom, consists of a graphene channel with a gap at the top, a hafnium oxide insulating layer, and a germanium substrate. A metal electrode, the emitter and base, are located on either side of the graphene channel. Both electrodes are Au / Ti top-down laminated composite structures. Below the emitter and base are an HfO2 insulating layer and a p-type germanium substrate. A metal collector, a Ti / Au top-down laminated composite structure, is located beneath the p-type germanium substrate. The emitters are connected, while the bases are independent.
[0057] like Figure 1-Figure 2 As shown, graphene (Gr) is transferred onto a prepared germanium substrate. Three transistors T1, T2, and T3 are arranged in parallel. The graphene channel of the transistor is the contact portion between the graphene and the germanium substrate in the window, with a length of 80μm and a width of 20μm. The graphene channel is divided into two parts, the emitter and the base, by a gap of 2μm. Au / Ti electrodes on the HfO2 insulating layer serve as electrodes for these two parts. The connected part is the emitter, and the independent part is the base. An Au / Ti electrode is set at the bottom of the germanium substrate as the collector.
[0058] like Figure 2 As shown, three transistors T1, T2, and T3 are connected in parallel, and the emitters are connected to each other and V e Bias voltage, its current is I e , V is applied to the independent bases b1 、V b2 、V b3 The voltage of the common collector is applied V c Bias voltage, the corresponding current is I c .
[0059] like Figure 3 As shown, the common V c Apply -5V voltage, V e -3V voltage is applied to the terminal, and voltage V is applied to transistors T1 and T2 respectively.b1 =0V, V b2 = -1V to control I c The shape of the curve and the location of the mutation, transistor T3 applies V b3 The voltage that continuously changes from 0V to -10V is used as the input signal (IN), I c As the output signal (OUT), since the time when the carriers arrive at each transistor is different, the time when each transistor undergoes ultra-low subthreshold swing current mutation will also be different. Therefore, the current will undergo three mutations. The voltage of each mutation is recorded as the input signal (3, 2, 1, 0), and the output signal is marked as (0, 1, 2, 3) according to the current size. In this way, a quaternary digital logic inverter can be obtained.
[0060] like Figure 4 As shown, Figure 3 The corresponding current curve is differentiated with respect to the voltage change to obtain its transconductance gain. When the first current mutation occurs, the transconductance gain is about 300μAμm -1 V -1 The transconductance gain of the second current mutation is about 800μAμm -1 V -1 , the third transconductance gain is also about 300μAμm -1 V -1 This shows that very small voltage changes can produce large current changes, indicating that the circuit can achieve low power operation.
[0061] like Figure 5 As shown, the common V c Apply -3V voltage, V e The three transistors V b1 、V b2 Floating, V b3 Apply a voltage that continuously changes from -2V to -12V as the input signal (IN), I e As the output signal (OUT), and I e Also with V b3 The current changes three times, and the voltage at each change is recorded as the input signal (3, 2, 1, 0). The output signal is marked as (0, 1, 2, 3) according to the current magnitude. This can be used to obtain a quaternary digital logic inverter at the emitter end, which provides greater flexibility in circuit design.
[0062] like Figure 6 As shown, Figure 5 The corresponding current curve is differentiated with respect to the voltage change to obtain its transconductance gain. When the first current mutation occurs, the transconductance gain is about 600μAμm -1 V -1The transconductance gain of the second current mutation is about 900μAμm -1 V -1 , the third transconductance gain also exceeds 700μAμm -1 V -1 This shows that a very small voltage change can produce a large current change, indicating that the I e Current can also achieve low power operation.
[0063] like Figure 7 As shown, in order to demonstrate the adjustable logic state, the output characteristics I c -V c . V c As input signal (IN), collector current I c As output signal (OUT). c is the sum of the collector currents of the three transistors. The position where each collector current reaches its maximum value is controlled by its base bias voltage. Therefore, when different base bias voltage combinations are applied, the logic state of the output signal is different, so they are adjustable, thus showing different functions. c Apply a voltage of -1V to -7V continuously, V e The three transistors V b1 、V b2 、V b3 Applying -4V, -5V, and -8V voltages, respectively, will cause each transistor's collector current to reach its maximum value at different locations and magnitudes due to the different bias voltages, resulting in three peaks. The voltage at each transistor's peak is recorded as the input signal (2, 1, 0), and the output signal is labeled (0, 1, 2) based on the peak current magnitude. This creates a three-value digital logic inverter.
[0064] like Figure 8 As shown, the common V c Apply a voltage of -4V to -8V continuously, V e The three transistors V b1 、V b2 、V b3 Applying voltages of -7.5V, -7.7V, and -8V respectively will result in three more peak currents. The voltage at which each transistor reaches its peak value is recorded as the input signal (2, 1, 0), and the output signal is marked as (2, 1, 0) according to the size of the peak current. This is a three-value digital logic follower.
[0065] like Figure 9 As shown, the common V c Apply a voltage of -3V to -10V continuously, V eThe three transistors V b1 、V b2 、V b3 Apply voltages of -5V, -7.5V, and -10V respectively. At this time, three peak currents different from the above are obtained. The voltage when each transistor reaches the peak value is recorded as the input signal (2, 1, 0), and the output signal is marked as (0, 2, 1) according to the size of the peak current. At this time, it is a three-value digital logic adder.
[0066] By using the above method, the multi-valued logic circuit based on the multifunctional hot emitter transistor proposed in the present invention was successfully prepared.
[0067] The results of the examples show that the multi-valued logic circuit based on the multifunctional hot emitter transistor and its preparation method proposed in the present invention realizes the multifunctional hot emitter transistor multi-valued logic circuit by constructing a parallel circuit of the multifunctional hot emitter transistor. Utilizing the ultra-low subthreshold swing in the transfer characteristics of the multifunctional hot emitter transistor, a quaternary digital logic inverter with low power consumption and high gain is constructed, and its transconductance gain can reach 900μAμm -1 V -1 By leveraging the peak-to-valley current ratio of the highly negative differential resistance in the output characteristic, an inverter, a follower, and an adder can be constructed at different base voltages. This multifunctional transistor-based, low-power, adjustable multivalued logic circuit offers a new, fast, low-power solution for the rapidly evolving information age, with promising applications.
Claims
1. A multi-valued logic circuit based on a multifunctional hot emitter transistor, characterized in that: The circuit consists of three parallel multifunctional hot emitter transistors connected in parallel. From top to bottom, it includes a graphene channel with a gap at the top, a hafnium oxide insulating layer and a germanium substrate, as well as base and emitter metal electrodes located on both sides of the graphene channel and in contact with the graphene channel. The metal electrodes are a top-down stacked composite structure of gold / titanium; below the emitter and base are the hafnium oxide insulating layer and the germanium substrate, and a metal collector is set at the bottom of the germanium substrate. The metal collector is a top-down stacked composite structure of Ti / Au. The emitters are connected to each other, and the bases are independent of each other.
2. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 1, characterized in that: The steps include: (1) The germanium substrate was ultrasonically cleaned with acetone and isopropanol to remove surface impurities, and then washed with diluted hydrofluoric acid and deionized water to remove surface oxides; (2) depositing a hafnium oxide insulating layer on a germanium substrate by atomic layer deposition; (3) Scrape the back of the germanium substrate using a diamond cutter and deposit gold / titanium electrodes using electron beam evaporation; (4) using photolithography technology to prepare a photoresist mask layer, and exposing the base and emitter metal electrode patterns to obtain the metal electrode area on the hafnium oxide insulating layer, and using vacuum electron beam evaporation to evaporate gold / titanium electrodes; (5) using photolithography technology to prepare a photoresist mask layer, and exposing the required window pattern, and using reactive ion etching to etch the hafnium oxide window to expose the germanium substrate; (6) growing a graphene film on a platinum foil by chemical vapor deposition and transferring the graphene film to a prepared germanium substrate by bubbling transfer; (7) using photolithography technology to prepare a photoresist mask layer, and exposing the desired graphene channel pattern to obtain the graphene channel area and the gap in the graphene channel; (8) Using oxygen ion etching technology, oxygen is introduced to clean away the excess graphene film exposed outside the base and emitter metal electrodes.
3. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, characterized in that: In step (1), the germanium substrate is a p-type lightly doped germanium sheet with a thickness of 500 μm and a resistivity of 1 to 10 Ω·cm; the diluted hydrofluoric acid is obtained by diluting the original concentration hydrofluoric acid and deionized water in a volume ratio of 1:8, the concentration of the original hydrofluoric acid is 40 wt%, and the treatment time in both the dilute hydrofluoric acid and deionized water is 1 min.
4. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (2), an insulating layer of hafnium oxide is deposited at 200° C. using atomic layer deposition to a thickness of 30 nm.
5. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (3), a diamond cutter is used to scrape the oxide layer on the back of the germanium sheet; an electron beam evaporator is used to evaporate the Ti layer of the top metal electrode to a thickness ranging from 5 to 6 nm, and then the Au layer is evaporated to a thickness ranging from 50 to 60 nm.
6. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (4), LOR3A and S-1813 double-layer photoresists are spin-coated in sequence and exposed for 4.5 seconds; the Ti layer of the top metal electrode is evaporated using an electron beam evaporator with a thickness ranging from 5 to 6 nm, and then the Au layer is evaporated with a thickness ranging from 50 to 60 nm.
7. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (5), LOR3A and S-1813 double-layer photoresists are spin-coated on the hafnium oxide insulating layer in sequence, and exposed for 4.5 seconds to obtain the desired window pattern; the window is etched out using reactive ion etching under the following conditions: tetrafluoromethane with a flow rate of 50 sccm is used as the etching gas, the pressure is 5.0 Pa, the power is 200 W, and the etching time is 5 minutes; then, the dilute hydrofluoric acid used in step (1) is used for cleaning for 30 seconds.
8. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (7), S-1813 photoresist is spin-coated on the graphene and exposed for 4.5 seconds.
9. The method for constructing a multi-valued logic circuit based on a multifunctional hot emitter transistor according to claim 2, wherein: In step (8), an oxygen ion cleaning machine is used for etching, and the etching conditions are: using oxygen with a flow rate of 180 sccm as the etching gas, a pressure of 1.5 to 2.5 Pa, a power of 200 W, and an etching time of 2 minutes.