Preparation method of calculation unit, calculation module and processor

Abstract

The invention provides a preparation method of a calculation unit, a calculation module and a processor, and the method comprises the steps: forming a blind hole in a slide glass, and forming a first electrode plate layer based on the blind hole; preparing a first metallization layer of the Josephson junction, and enabling the first metallization layer to be electrically connected with the first electrode plate layer; performing in-situ oxidation on the first metallization layer and the first electrode plate layer to form a first dielectric layer and a second dielectric layer; preparing a second metallization layer on the first dielectric layer to form a Josephson junction; forming a second electrode plate layer on the second dielectric layer to be electrically connected with the second metallization layer; performing medium filling on the blind hole wrapped by the second electrode plate layer to form a filling medium layer of the deep groove capacitor; and growing a conductive material to be respectively connected with the first metallization layer and the second metallization layer to form a first bonding pad and a second bonding pad of the calculation unit. According to the preparation method of the calculation unit, the calculation module and the processor provided by the invention, the preparation performance and reliability of the calculation unit are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a computing unit, a computing module, and a processor. Background Art

[0002] Superconducting qubits are core components in quantum computing, and their size directly affects the integration of quantum processors.

[0003] In the structure of superconducting quantum bits, bypass capacitors are usually added to suppress the noise caused by charge fluctuations, which helps the quantum bits to extend the decoherence time. In the currently widely used bit structure designs such as Transmon / Xmon, quantum bits generally use coplanar capacitors, that is, the two plates of the capacitor are on the same horizontal plane. In this case, the capacitor will occupy a larger plane area, which is not conducive to the large-scale expansion and high-density integration of superconducting quantum bits. Therefore, the present invention proposes a novel quantum bit preparation process, which significantly reduces the size of a single quantum bit by introducing a deep trench capacitor. By realizing a superconducting quantum bit structure (similar to a traditional Transmon quantum bit) in which a Josephson junction and a deep trench capacitor are connected in parallel, a large parallel capacitor is added, which helps to reduce the sensitivity to charge noise, is easier to control, and has a longer life. Deep trench capacitors can achieve a much higher capacitance density than planar capacitors under the same area, so the noise suppression effect is more significant.

[0004] As a key technology in the "post-Moore era," three-dimensional integration can significantly improve the integration and computing power of a single processor at the same process node. Therefore, this patent also proposes an adaptive three-dimensional integration technology for this new quantum bit preparation process to achieve a scalable superconducting quantum processor architecture. Summary of the Invention

[0005] In response to the problems in the prior art, embodiments of the present invention provide a method for preparing a computing unit, a computing module, and a processor, which can at least partially solve the problems in the prior art.

[0006] In a first aspect, the present invention provides a method for preparing a computing unit, comprising:

[0007] forming a blind hole in the carrier wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole;

[0008] preparing a first metallization layer of a Josephson junction, and electrically connecting the first metallization layer to the first electrode plate layer;

[0009] performing in-situ oxidation on the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer, and forming a second dielectric layer on the first electrode plate layer;

[0010] preparing a second metallization layer of a Josephson junction on the first dielectric layer;

[0011] forming a second electrode plate layer of a deep trench capacitor on the second dielectric layer, so that the second electrode plate layer is electrically connected to the second metallization layer;

[0012] Filling the blind hole wrapped by the second electrode plate layer with a dielectric to form a filling dielectric layer of the deep trench capacitor;

[0013] The grown conductive material is connected to the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of a computing unit.

[0014] Furthermore, obtaining a first electrode plate layer of a deep trench capacitor based on the blind hole includes:

[0015] Depositing an insulating layer on the surface of the carrier and the blind hole;

[0016] growing a conductive layer on the insulating layer;

[0017] The conductive layer is patterned to form the first electrode plate layer; wherein the first electrode plate layer extends outside the blind hole.

[0018] Furthermore, the step of preparing the first metallization layer of the Josephson junction and electrically connecting the first metallization layer to the first electrode plate layer comprises:

[0019] Coating a double layer of adhesive on the carrier; wherein the double layer of adhesive needs to be selected so that the opening space formed by the lower layer of adhesive after development is larger than that of the upper layer of adhesive;

[0020] performing photolithography and development on the double-layered adhesive to form a double-layered adhesive with a double-opening structure on the carrier wafer;

[0021] A first metallization layer of a Josephson junction is prepared on the carrier at a first angle based on the double-layer glue with the double-opening structure, so that the first metallization layer is electrically connected to the first electrode plate layer.

[0022] Furthermore, after forming a second metallization layer of a Josephson junction on the first dielectric layer, the method further includes:

[0023] If the conductive material of the first electrode plate layer is a preset material, photolithography is performed on the surface of the current structure to obtain a surface pattern of the second dielectric layer;

[0024] An insulating material is deposited on the surface of the second dielectric layer based on the surface pattern of the second dielectric layer, so that the thickness of the second dielectric layer meets insulation requirements.

[0025] In a second aspect, the present invention provides a computing module, which is prepared using the method for preparing a computing unit described in any of the above embodiments.

[0026] In a third aspect, the present invention provides a processor, comprising a first adapter board, a resonant cavity core, and a packaging substrate, wherein:

[0027] The resonant cavity core is bonded to the first adapter plate, and the first adapter plate is arranged on the packaging substrate through a spacer column; the top surface of the first adapter plate includes a plurality of computing units, and an additionally configured resonant cavity is arranged on the back surface of the first adapter plate, and the resonant cavity core includes at least one resonant cavity.

[0028] In a fourth aspect, the present invention provides a processor, comprising the computing module, the second adapter board, and the packaging substrate described in the above embodiment, wherein:

[0029] The computing module is flip-chip bonded on the second adapter plate, and the second adapter plate is arranged on the packaging substrate through spacers; the computing module includes at least one Josephson junction, and the top and bottom surfaces of the second adapter plate are respectively provided with resonant cavities.

[0030] In a fifth aspect, the present invention provides a processor, comprising the computing module, the second adapter board, and the packaging substrate described in the above embodiment, wherein:

[0031] The computing module is flip-chip bonded to the second adapter plate, and the second adapter plate is arranged on the packaging substrate through a spacer column; the computing module includes at least one Josephson junction, and a resonant cavity is arranged on a side surface of the packaging substrate close to the second adapter plate.

[0032] The preparation method, computing module, and processor of a computing unit provided by an embodiment of the present invention form a blind hole in a carrier and form a first electrode plate layer of a deep trench capacitor based on the blind hole; prepare a first metallization layer of a Josephson junction and electrically connect the first metallization layer to the first electrode plate layer; in-situ oxidize the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer, and form a second dielectric layer on the first electrode plate layer; prepare a second metallization layer of a Josephson junction on the first dielectric layer; form a second electrode plate layer of a deep trench capacitor on the second dielectric layer and electrically connect the second electrode plate layer to the second metallization layer; fill the blind hole wrapped by the second electrode plate layer with dielectric to form a filling dielectric layer of the deep trench capacitor; grow a conductive material and connect it to the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of the computing unit. Since the preparation processes of the deep trench capacitor and the Josephson junction are integrated, the preparation process of the computing unit is simplified, the performance and preparation efficiency of the computing unit are improved, and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0034] Figure 1 It is a flowchart of a method for preparing a computing unit provided by the first embodiment of the present invention.

[0035] Figure 2 FIG. 4 is a flow chart of a method for manufacturing a deep trench capacitor provided by a second embodiment of the present invention.

[0036] Figure 3 4 is a flow chart of a method for preparing a Josephson junction provided in the third embodiment of the present invention.

[0037] Figure 4 FIG. 4 is a flow chart of a method for manufacturing a deep trench capacitor provided in accordance with a fourth embodiment of the present invention.

[0038] Figure 5A FIG. 5 is a schematic diagram of the structure of a processor provided by the fifth embodiment of the present invention.

[0039] Figure 5B It is a partial enlarged structural diagram of a processor provided by the fifth embodiment of the present invention.

[0040] Figure 6 FIG. 4 is a schematic diagram of the structure of a processor provided by the sixth embodiment of the present invention.

[0041] Figure 7A FIG. 1 is a structural diagram of a processor provided by the seventh embodiment of the present invention.

[0042] Figure 7B It is a partial enlarged structural diagram of a processor provided by the seventh embodiment of the present invention.

[0043] Figure 8A It is a schematic structural diagram after blind holes are prepared according to the eighth embodiment of the present invention.

[0044] Figure 8B It is a schematic structural diagram of the eighth embodiment of the present invention after depositing the insulating layer.

[0045] Figure 8C It is a schematic structural diagram after forming the first electrode plate layer provided by the eighth embodiment of the present invention.

[0046] Figure 8D3 is a schematic structural diagram of the patterned first electrode plate layer provided in the eighth embodiment of the present invention.

[0047] Figure 8E It is a schematic diagram of the structure after double-layer adhesive coating provided by the eighth embodiment of the present invention.

[0048] Figure 8F It is a schematic structural diagram of a double-layer glue forming a double-opening structure provided by the eighth embodiment of the present invention.

[0049] Figure 8G It is a schematic structural diagram after preparing the first metallization layer provided by the eighth embodiment of the present invention.

[0050] Figure 8H It is a schematic diagram of the structure after in-situ oxidation provided by the eighth embodiment of the present invention.

[0051] Figure 8I It is a schematic structural diagram after preparing the second metallization layer provided by the eighth embodiment of the present invention.

[0052] Figure 8J It is a schematic structural diagram of the eighth embodiment of the present invention after the double-layer adhesive is removed.

[0053] Figure 8K It is a schematic structural diagram after forming the second electrode plate layer provided by the eighth embodiment of the present invention.

[0054] Figure 8L It is a schematic diagram of the structure after dielectric filling provided by the eighth embodiment of the present invention.

[0055] Figure 8M It is a schematic diagram of the structure after photolithography provided by the eighth embodiment of the present invention.

[0056] Figure 8N It is a schematic diagram of the structure behind the growth calculation unit pad provided by the eighth embodiment of the present invention.

[0057] Figure 8O It is a schematic diagram of the structure after the photoresist is removed provided by the eighth embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. Here, the schematic embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other in any way. The acquisition, storage, use, processing, etc. of data in the technical solutions in this application comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant channels, and the acquisition, storage, use, processing, etc. of user information are authorized and agreed by the customer.

[0059] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0060] In the widely used Transmon / Xmon architecture, the bypass capacitors in superconducting qubits are typically coplanar capacitors, meaning the two plates are in the same plane. This occupies a significant area, limiting the qubit integration density. From a scalability perspective, the integration density of current processors is primarily limited by the bypass capacitors and resonant cavity, rather than the Josephson junction itself.

[0061] This application adopts a deep trench capacitor structure to replace the capacitor structure in the planar design, making the superconducting quantum bit itself more compatible with the requirements of core-particle three-dimensional integration, reducing the size of the superconducting quantum bit, and is expected to realize a scalable, large-scale and high-integration-density superconducting quantum processor based on core-particle design.

[0062] The present application proposes a method for preparing a computing unit, in which a deep trench capacitor is prepared at the same time as a Josephson junction, which can simplify the overall preparation process of the computing unit and avoid the interface deterioration problem caused by the thin film interface leaving the high vacuum cavity and being transported in the atmosphere.

[0063] Figure 1 is a flow chart of a method for preparing a computing unit according to a first embodiment of the present invention, as shown in FIG. Figure 1 As shown, the method for preparing a computing unit provided by an embodiment of the present invention includes:

[0064] S101, forming a blind hole in a carrier wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole;

[0065] Specifically, a blind hole is prepared in the carrier, and the blind hole extends from the first surface of the carrier to the second surface of the carrier. A conductive layer is prepared based on the blind hole to obtain the first electrode plate layer of the deep trench capacitor (DTC). There is no limitation on the carrier material, but it is necessary to ensure that the material layer close to the quantum bit has a sufficiently low stray two-level system (TLS) loss so as not to affect the function of the quantum bit. The conductive material of the first electrode plate layer is selected according to actual needs and is not limited in the embodiment of the present invention.

[0066] For example, blind holes can be prepared on the first surface of the silicon-based carrier by photolithography and deep reactive ion etching (DRIE).

[0067] S102, preparing a first metallization layer of a Josephson junction, and electrically connecting the first metallization layer to the first electrode plate layer;

[0068] Specifically, a first metallization layer of a Josephson junction is formed on the carrier, and the first metallization layer is electrically connected to the first electrode plate layer. The first metallization layer can be made of a superconducting metal material such as Al or Nb, which is selected based on actual needs and is not limited in this embodiment of the present invention.

[0069] S103, performing in-situ oxidation on the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer, and forming a second dielectric layer on the first electrode plate layer;

[0070] Specifically, the first metallization layer and the first electrode plate layer are in-situ oxidized, so that an oxide layer as the first dielectric layer is formed on the first metallization layer and an oxide layer as the second dielectric layer is formed on the first electrode plate layer at the same time.

[0071] The simultaneous oxidation of the first metallization layer and the first electrode plate layer in a vacuum chamber not only simplifies the overall process steps, but also avoids the interface deterioration problem caused by the thin film interface leaving the high vacuum chamber and being transported in the atmosphere, providing an interface state that is as ideal as possible, which helps to improve the coherence performance of the Josephson junction and the high capacitance capability of the deep trench capacitor.

[0072] S104, preparing a second metallization layer of a Josephson junction on the first dielectric layer;

[0073] Specifically, a second metallization layer of a Josephson junction is formed on the first dielectric layer. The first dielectric layer serves as a barrier layer for the Josephson junction. The second metallization layer can be made of a superconducting metal material such as Al or Nb, depending on actual needs and is not limited in this embodiment of the present invention.

[0074] For example, after preparing the first metallization layer and performing in-situ oxidation, a superconducting metal material is grown through a double-layer glue with a double-opening structure at a second angle to form a second metallization layer. The selection of the second angle enables the second metallization layer to be formed on the first dielectric layer. Due to the double-layer glue with a double-opening structure, in addition to forming the second metallization layer, an excess metallization layer will also be formed on the surface of the carrier, but it will not have a substantial impact on the structure of the deep trench capacitor, nor will it affect the electrical properties of the computing unit finally obtained. Therefore, there is no need to perform additional processing on the excess metallization layer, which simplifies the complexity of the process. Among them, the second angle is set according to actual experience and is not limited in the embodiment of the present invention.

[0075] S105, forming a second electrode plate layer of a deep trench capacitor on the second dielectric layer, so that the second electrode plate layer is electrically connected to the second metallization layer;

[0076] Specifically, a second electrode plate layer of the deep trench capacitor is formed on the second dielectric layer, and the second electrode plate layer is electrically connected to the second metallization layer. The conductive material of the second electrode plate layer is selected according to actual needs and is not limited in this embodiment of the present invention.

[0077] For example, the current structure is photolithographically processed to block the structure on the surface of the carrier, exposing the surface of the second dielectric layer in the blind hole, and a second electrode plate layer is grown on the surface of the second dielectric layer in the blind hole using a growth method that can fill deep holes.

[0078] S106, filling the blind hole wrapped by the second electrode plate layer with a dielectric to form a filling dielectric layer of the deep trench capacitor;

[0079] Specifically, the blind hole wrapped by the second electrode plate layer is filled with dielectric to form a filling dielectric layer of the deep trench capacitor. The filling dielectric layer is made of insulating material, which is selected according to actual needs and is not limited in the embodiment of the present invention.

[0080] For example, the current structure is photolithographically processed to block the structure on the carrier surface. All parts except the blind hole wrapped by the second electrode plate layer are protected by photoresist, and a dielectric layer is grown or spin-coated in the blind hole to obtain the filling dielectric layer of the deep trench capacitor.

[0081] S107 , growing a conductive material and connecting it to the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of a computing unit.

[0082] Specifically, the grown conductive material is connected to the first metallization layer and the second metallization layer, respectively, to form a first pad and a second pad of the computing unit. The first metallization layer of the Josephson junction is connected to the first electrode plate layer of the deep trench capacitor, and the second metallization layer of the Josephson junction is connected to the second electrode plate layer of the deep trench capacitor. Therefore, the first pad and the second pad of the computing unit also serve as the two plates of the deep trench capacitor, forming a superconducting quantum bit structure in which the Josephson junction and the deep trench capacitor are connected in parallel. This structure is similar to a traditional Transmon quantum bit. The addition of a large parallel capacitor helps reduce sensitivity to charge noise, making it easier to manipulate and having a longer lifespan. Deep trench capacitors can achieve a much higher capacitance density than planar capacitors under the same area, making the effect more significant.

[0083] An embodiment of the present invention provides a method for preparing a computing unit, which forms a blind hole in a carrier and forms a first electrode plate layer of a deep trench capacitor based on the blind hole; prepares a first metallization layer of a Josephson junction, and electrically connects the first metallization layer to the first electrode plate layer; in-situ oxidizes the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer, and forms a second dielectric layer on the first electrode plate layer; prepares a second metallization layer of a Josephson junction on the first dielectric layer; forms a second electrode plate layer of a deep trench capacitor on the second dielectric layer, and electrically connects the second electrode plate layer to the second metallization layer; fills the blind hole wrapped by the second electrode plate layer with dielectric to form a filling dielectric layer of the deep trench capacitor; and grows a conductive material to connect the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of the computing unit. Since the deep trench capacitor and Josephson junction preparation processes are integrated, the preparation process of the computing unit is simplified, the preparation efficiency of the computing unit is improved, and the cost is reduced.

[0084] Figure 2 FIG. 1 is a flow chart of a method for preparing a deep trench capacitor according to a second embodiment of the present invention. Figure 2 As shown, based on the above embodiments, further, the first electrode plate layer of the deep trench capacitor obtained based on the blind hole includes:

[0085] S201, depositing an insulating layer on the surfaces of the carrier wafer and the blind hole;

[0086] Specifically, an insulating layer is deposited on the surface of the carrier and the surface of the blind hole, and the insulating layer can cover the carrier, the sidewall and the bottom of the blind hole.

[0087] For example, a thin film growth technology capable of filling a high aspect ratio is used to deposit a SiO2 film on the surface of the carrier and the sidewalls and bottom of the blind hole to obtain an insulating layer.

[0088] S202, growing a conductive layer on the insulating layer;

[0089] Specifically, a conductive layer is grown on the insulating layer, and the conductive metal material used for the conductive layer is selected according to actual needs, which is not limited in the embodiment of the present invention.

[0090] For example, a metal conductive material is grown on the insulating layer using a thin film growth technology capable of filling a high aspect ratio to form a conductive layer.

[0091] S203 , patterning the conductive layer to form the first electrode plate layer.

[0092] Specifically, the conductive layer can be patterned using photolithography and dry etching to form a first electrode plate layer. The first electrode plate layer can appropriately extend outside the blind hole to facilitate subsequent electrical connection between the first electrode plate layer and the first metallization layer. The first electrode plate layer can extend outside the blind hole.

[0093] Figure 3 FIG. 1 is a flow chart of a method for preparing a Josephson junction according to a third embodiment of the present invention. Figure 3 As shown, based on the above embodiments, further, preparing a first metallization layer of a Josephson junction on the carrier and electrically connecting the first metallization layer to the first electrode plate layer includes:

[0094] S301, coating a double layer of adhesive on the carrier; wherein the double layer of adhesive needs to be selected so that after development, the opening space formed by the lower layer of adhesive is larger than that of the upper layer of adhesive;

[0095] S302, exposing and developing the double-layer adhesive to form a double-layer adhesive with a double opening structure on the carrier;

[0096] Specifically, the double-layer adhesive is exposed and developed to form a double-layer adhesive with a double-opening structure on the carrier. A cavity is formed at the bottom of the double-opening structure to facilitate the preparation of the first metallization layer and the second metallization layer.

[0097] S303 , preparing a first metallization layer of a Josephson junction on the carrier at a first angle based on the double-layer glue with the double-opening structure, so that the first metallization layer is electrically connected to the first electrode plate layer.

[0098] Specifically, a superconducting metal material is grown through the double-layer glue of the double-opening structure at a first angle to form a first metallization layer. The first angle is selected to enable electrical connection between the first metallization layer and the first electrode plate layer. The first angle is set based on practical experience and is not limited in this embodiment of the present invention.

[0099] The first metallization layer and the first electrode plate layer are in-situ oxidized to form a first dielectric layer on the first metallization layer, and a second dielectric layer is formed on the first electrode plate layer.

[0100] Figure 4 FIG. 1 is a flow chart of a method for preparing a deep trench capacitor according to a fourth embodiment of the present invention. Figure 4 As shown, based on the above embodiments, further, after the second dielectric layer is completed, it also includes:

[0101] S401: If the conductive material of the first electrode plate layer is a preset material, photolithography is performed on the surface of the current structure to obtain a surface pattern of the second dielectric layer;

[0102] Specifically, the first dielectric layer serves as a barrier layer for the Josephson junction, while the second dielectric layer serves as an insulating layer between the first and second electrode plates of the deep trench capacitor. The first dielectric layer cannot be too thick to prevent quantum tunneling, and the second dielectric layer cannot be too thin to prevent poor insulation. Due to the functional differences between the barrier layer for the Josephson junction and the insulating layer for the deep trench capacitor, depending on the materials used, it is possible that the first dielectric layer meets the requirements while the second dielectric layer does not. If the conductive material of the first electrode plate is a predetermined material, the second dielectric layer obtained by in-situ oxidation of the first electrode plate may not meet the insulation requirements. The thickness of the second dielectric layer must be increased to ensure that the second dielectric layer meets the insulation requirements. The predetermined material is selected based on actual conditions and is not limited in this embodiment of the present invention. The surface of the current structure is photolithographically patterned to obtain the surface pattern of the second dielectric layer. The current structure is the second dielectric layer structure obtained after in-situ oxidation.

[0103] S402 : Depositing an insulating material on the surface of the second dielectric layer based on the surface pattern of the second dielectric layer, so that the thickness of the second dielectric layer meets insulation requirements.

[0104] Specifically, based on the surface pattern of the second dielectric layer, an insulating material is deposited on the surface of the second dielectric layer, thereby increasing the thickness of the second dielectric layer to meet insulation requirements. The increased thickness of the second dielectric layer is set based on actual needs and is not limited in this embodiment of the present invention. The insulating material is selected based on actual needs and is not limited in this embodiment of the present invention.

[0105] On the basis of the above embodiments, multiple computing units are further formed on the carrier.

[0106] Specifically, a plurality of Josephson junctions and deep trench capacitors corresponding to the respective Josephson junctions can be simultaneously prepared on the wafer.

[0107] A computing module provided by an embodiment of the present invention is manufactured using the manufacturing method of a computing unit described in any of the above embodiments. The manufactured computing unit includes a Josephson junction and a deep trench capacitor.

[0108] Josephson junctions can be prepared using materials such as Al-based, Nb-based, and Ta-based materials. Josephson junctions and other necessary functional auxiliary structures are used to construct various types of superconducting qubits. Superconducting qubits can be qubit types such as flux, charge, phase, and Transmon. Deep trench capacitors, as bypass capacitors for superconducting qubits, can not only help significantly extend the decoherence time of qubits, but also reduce the area occupied, thereby reducing the planar size of superconducting qubits. When the size of the deep trench capacitor is very small, reaching the order of hundreds of nanometers, the Josephson junction itself may limit the integration density, rather than the bypass capacitance, which is the main limiting factor at this stage. This significantly improves the integration density of active devices compared to the current process. Deep trench capacitors can provide very high capacitance values ​​at a smaller planar size, thereby significantly improving area utilization.

[0109] Figure 5A is a schematic diagram of the structure of a processor provided by a fifth embodiment of the present invention, Figure 5B is a partially enlarged structural diagram of a processor provided by a fifth embodiment of the present invention, Figure 5B for Figure 5A The enlarged picture of point A in the middle is as follows: Figure 5A and Figure 5B As shown, the processor provided by the embodiment of the present invention includes the first adapter board 501, the resonant cavity core 502 and the packaging substrate 503 described in the above embodiment, wherein:

[0110] The resonant cavity core particle 502 is bonded to the first adapter plate 501, and the first adapter plate 501 is set on the packaging substrate 503 through the spacer column 504; the first adapter plate 501 includes multiple Josephson junctions 505, and a part of the resonant cavity 506 can also be set on the back of the first adapter plate 501.

[0111] Specifically, the resonant cavity 506 adopts a traditional planar resonant cavity structure. Due to the large size of the traditional planar resonant cavity, if it is arranged on the same plane, the spacing between adjacent quantum bits will inevitably be completely limited by the resonant cavity, thereby reducing the integration density of the device. Therefore, the embodiment of the present invention proposes that part of the resonant cavity 506 is provided in the form of a core particle, arranged on the resonant cavity core particle 502, and connected to the superconducting quantum bit below by flip-chip bonding. The other part of the resonant cavity 506 is arranged on the back of the first adapter plate 501. In this way, the problem of loose quantum bit density caused by the coplanar arrangement of the resonant cavity can be effectively alleviated.

[0112] The first adapter plate 501 includes multiple Josephson junctions 505, each with a corresponding resonant cavity 506 and a deep trench capacitor 507. The first adapter plate 501 also includes a first carrier (the adapter plate containing the superconducting qubit) 508, which is used to support each Josephson junction 505 and the corresponding deep trench capacitor 507. The resonant cavity 506 is disposed on a surface of the first carrier 508 adjacent to the packaging substrate 503. The resonant cavity core 502 includes a resonant cavity 506 and a second carrier 509, with the resonant cavity 506 disposed on a surface adjacent to the first adapter plate 501. The multiple Josephson junctions 505 are alternately coupled to the resonant cavities 506 included in the first adapter plate 501 and the resonant cavity core 502. The resonant cavities 506 are used to implement measurement and control of the Josephson junctions 505. The first adapter plate 501 is disposed on the packaging substrate 503 via spacers 504.

[0113] Each Josephson junction 505 can receive a control signal through a first data transmission link 510 and output calculation data through a second data transmission link 511. The second data transmission link 511 passes through a resonant cavity 506 included in the first adapter plate 501.

[0114] Figure 5A As shown, on the basis of the above embodiments, further, the first data transmission link 510 includes a first transmission line 510-1, a first conductive portion 510-2, a first bump bonding pair 510-3, a second conductive portion 510-4 and a coaxial line 510-5 connected in sequence; the first transmission line 510-1 is coupled to the first pad 505-1 of the Josephson junction 505, the first conductive portion 510-2 passes through the first carrier 508, and the second conductive portion 510-4 passes through the packaging substrate 503.

[0115] The first conductive portion 510-2 may be a coaxial through-hole obtained by drilling a hole on the first carrier 508, filling it with a dielectric layer and a superconducting metal, and then chemically mechanically polishing it. The second conductive portion 510-4 may also be a coaxial through-hole obtained by drilling a hole on the package substrate 503, filling it with a dielectric layer and a superconducting metal, and then chemically mechanically polishing it. The superconducting metal includes, but is not limited to, aluminum, niobium, titanium nitride, etc. The dielectric layer may be silicon dioxide, benzocyclobutene (BCB), polyimide (PI), etc., and the selection is based on actual needs and is not limited in the embodiment of the present invention.

[0116] Figure 5A As shown, based on the above embodiments, further, if the resonant cavity 506 corresponding to the Josephson junction 505 is on the resonant cavity core particle 502, then the second data transmission link 511 includes a first bump bonding pair 511-1, the resonant cavity 506, the second transmission line 511-2, the third conductive portion 511-3 and the coaxial line 511-4; the first end of the first bump bonding pair 511-1 is coupled to the second pad 505-2 of the Josephson junction 505, the second end of the first bump bonding pair 511-1 is coupled to the first end of the resonant cavity 506 corresponding to the Josephson junction 505, the second end of the resonant cavity 506 is coupled to the first end of the second transmission line 511-2, and the second end of the second transmission line 511-2 is connected to the coaxial line 511-4.

[0117] The second pad 505-2 of the Josephson junction 505 and the first end of the first bump bond pair 511-1 can be capacitively coupled. The second end of the first bump bond pair 511-1 and the first end of the resonant cavity 506 can be capacitively coupled. The third conductive portion 511-3 can be a coaxial through-hole formed by drilling a hole in the resonant cavity core 502, filling it with a dielectric layer and superconducting metal, and then chemically mechanically polishing it.

[0118] Figure 5AAs shown, based on the above embodiments, further, if the resonant cavity 506 corresponding to the Josephson junction 505 is at the bottom of the first adapter plate 501, then the second data transmission link 511 includes a third transmission line 511-5, a fourth conductive portion 511-6, a resonant cavity 506, a fourth transmission line 511-7, a second bump bonding pair 511-8, a fifth conductive portion 511-9 and a coaxial line 511-10; a first end of the third transmission line 511-5 is coupled to the second pad 505-2 of the Josephson junction 505, and a second end of the third transmission line 511-5 is coupled to a first end of the fourth conductive portion 511-6. The second end of the fourth conductive part 511-6 is coupled to the first end of the resonant cavity 506 corresponding to the Josephson junction 505, the second end of the resonant cavity 506 is coupled to the first end of the fourth transmission line 511-7, the second end of the fourth transmission line 511-7 is connected to the first end of the second bump bonding pair 511-8, the second end of the second bump bonding pair 511-8 is connected to the first end of the fifth conductive part 511-9, the second end of the fifth conductive part 511-9 is connected to the coaxial line 511-10, the fourth conductive part 511-6 passes through the first carrier 508, and the fifth conductive part 511-9 passes through the packaging substrate 503.

[0119] The second pad 505-2 of the Josephson junction 505 and the first end of the third transmission line 511-5 can be capacitively coupled. The second end of the fourth conductive portion 511-6 and the first end of the resonant cavity 506 can be capacitively coupled. The fourth conductive portion 511-6 can be a coaxial through-hole formed by drilling a hole in the first carrier 508, filling it with a dielectric layer and a superconducting metal, and then chemically mechanically polishing it. The fifth conductive portion 511-9 can be a coaxial through-hole formed by drilling a hole in the packaging substrate 503, filling it with a dielectric layer and a superconducting metal, and then chemically mechanically polishing it.

[0120] Figure 6 FIG. 1 is a schematic diagram of the structure of a processor provided by a sixth embodiment of the present invention. Figure 6 As shown, the processor provided by the embodiment of the present invention includes the computing module 601, the second adapter board 602 and the packaging substrate 603 described in the above embodiment, wherein:

[0121] The computing module 601 is flip-chip bonded on the second adapter plate 602, and the second adapter plate 602 is set on the packaging substrate 603 through the spacer 604; the computing module 601 includes at least one Josephson junction 605, and the first surface and second surface of the second adapter plate 602 are respectively provided with a resonant cavity 606.

[0122] Specifically, the computing module 601 is provided in the form of a core particle, and the integration density is improved by respectively providing a resonant cavity 606 on the two surfaces of the second adapter plate 602. Since the second adapter plate 602 mainly includes a mature resonant cavity 606 structure, the process yield is high. Compared with the low-yield computing module 601, the yield of the second adapter plate 602 is less sensitive to area, and thus allows a similar "fan-out" method to be used to fully disperse the area outside the corresponding area of ​​the computing module 601. When the resonant cavity 606 of the second adapter plate 602 is reasonably arranged, the integration density of the processor will be mainly related to the area of ​​the computing module 601 and the size of the Josephson junction, thereby giving full play to the small size advantage of the new quantum bit proposed in this patent.

[0123] The computing module 601 includes multiple Josephson junctions 605, each of which is equipped with a corresponding deep trench capacitor 607. The computing module 601 is supported by a third substrate 608, which supports each Josephson junction 605 and its corresponding deep trench capacitor 607. The computing module 601 is flip-chip bonded to a second adapter plate 602, with resonant cavities 606 disposed on the first and second surfaces of the second adapter plate 602, respectively. The second adapter plate 602 is secured to the packaging substrate 603 via spacers 604.

[0124] Each Josephson junction 605 can receive a control signal via a third data transmission link 609 and transmit output data via a fourth data transmission link 610. The fourth data transmission link 610 passes through the resonant cavity 606 corresponding to the Josephson junction 605.

[0125] Figure 7A is a schematic diagram of the structure of a processor provided by the seventh embodiment of the present invention, Figure 7B is a partial enlarged structural diagram of a processor provided by a seventh embodiment of the present invention, Figure 7B for Figure 7A The enlarged picture at C in the middle is as follows: Figure 7A and 7B As shown, the processor provided by the embodiment of the present invention includes the computing module 701, the second adapter board 702 and the packaging substrate 703 described in the above embodiment, wherein:

[0126] The computing module 701 is flip-chip bonded to the second adapter plate 702, and the second adapter plate 702 is set on the packaging substrate 703 through the spacer column 704; the computing module 701 includes at least one Josephson junction 705, and a resonant cavity 706 is set on the side surface of the packaging substrate 703 close to the second adapter plate 702.

[0127] Specifically, the computing module 701 is provided in the form of a core particle, and the structure of the resonant cavity 706 can adopt a spiral configuration, a coaxial configuration, etc., which can greatly reduce the planar area of ​​the resonant cavity 706. In this case, the integration density of the processor will be completely limited by the quantum bits themselves. At the same time, it is not required that the second adapter plate 702 is larger than the computing module 701 to achieve an effective arrangement of the input / output ports. The second adapter plate 702 and the computing module 701 can occupy the same planar area. Figure 5A and Figure 6 The structure of the processor shown occupies a smaller area and has a higher integration density.

[0128] The computing module 701 includes at least one Josephson junction 705, each corresponding to a trench capacitor 707. The computing module 701 also includes a fourth carrier 708, which is used to support each Josephson junction 705 and the corresponding trench capacitor 707. The computing module 701 is flip-chip bonded to a second adapter plate 702, which is secured to a packaging substrate 703 via spacers 704. A resonant cavity 706 is provided on a surface of the packaging substrate 703 adjacent to the second adapter plate 702, with each Josephson junction 705 corresponding to a resonant cavity 706.

[0129] Each Josephson junction 705 can receive a control signal via a fifth data transmission link 709 and transmit output data via a sixth data transmission link 710. The sixth data transmission link 710 passes through the resonant cavity 706 corresponding to the Josephson junction 705.

[0130] like Figure 7A As shown, on the basis of the above embodiments, further, the fifth data transmission link 709 includes a third bump bonding pair 709-1, a fifth transmission line 709-2, an eighth conductive part 709-3, a fourth bump 709-4, a ninth conductive part 709-5 and a coaxial line 709-6 connected in sequence; the third bump bonding pair 709-1 is coupled to the first pad 705-1 of the Josephson junction 705, the eighth conductive part 709-3 passes through the second adapter board 702, and the ninth conductive part 709-5 passes through the packaging substrate 703.

[0131] The external control signal is transmitted to the first pad 705-1 of the Josephson junction 705 in sequence through the coaxial line 709-6, the ninth conductive portion 709-5, the fourth bump 709-4, the eighth conductive portion 709-3, the fifth transmission line 709-2, and the third bump bonding pair 709-1. The eighth conductive portion 709-3 can be a coaxial through-hole obtained by drilling a hole in the second adapter plate 702, filling it with a dielectric layer and a superconducting metal, and chemically mechanically polishing it. The ninth conductive portion 709-5 can be a coaxial through-hole obtained by drilling a hole in the packaging substrate 703, filling it with a dielectric layer and a superconducting metal, and chemically mechanically polishing it. The superconducting metal includes, but is not limited to, aluminum, niobium, titanium nitride, etc., and is selected according to actual needs and is not limited in the embodiment of the present invention.

[0132] like Figure 7A As shown, based on the above embodiments, further, the sixth data transmission link 710 includes a fourth bump 710-1, a sixth transmission line 710-2, a tenth conductive portion 710-3, an eleventh conductive portion 710-4, a seventh transmission line 710-5, a coaxial line 710-6 and a coaxial line 710-7; the first end of the fourth bump 710-1 is coupled to the second pad 705-2 of the Josephson junction 705, the second end of the fourth bump 710-1 is connected to the first end of the sixth transmission line 710-2, and the second end of the sixth transmission line 710-2 is connected to the first end of the tenth conductive portion 710-3. The second end of the tenth conductive part 710-3 is coupled to the first end of the resonant cavity 706 corresponding to the Josephson junction 705, the second end of the resonant cavity 706 is coupled to the first end of the eleventh conductive part 710-4, the second end of the eleventh conductive part 710-4 is connected to the first end of the seventh transmission line 710-5, the second end of the seventh transmission line 710-5 is connected to the coaxial line 710-6, and the third end of the seventh transmission line 710-5 is connected to the coaxial line 710-7; the tenth conductive part 710-3 passes through the second adapter board 702, and the eleventh conductive part 710-4 passes through the packaging substrate 703.

[0133] If the packaging substrate 703 is made of a semiconductor material such as silicon, a separate dielectric region needs to be provided between the resonant cavity 706 corresponding to the Josephson junction 705 and the first end of the eleventh conductive portion 710-4 to achieve a coupling connection between the resonant cavity 706 and the first end of the eleventh conductive portion 710-4. The resonant cavity 706 and the first end of the eleventh conductive portion 710-4 can be capacitively coupled. The second end of the tenth conductive portion 710-3 and the resonant cavity 706 can be capacitively coupled. The tenth conductive portion 710-3 can be a coaxial through-hole obtained by drilling a hole in the second adapter plate 702, filling it with a dielectric layer and a superconducting metal, and chemically mechanically polishing it. The eleventh conductive portion 710-4 can be a coaxial through-hole obtained by drilling a hole in the packaging substrate 703, filling it with a dielectric layer and a superconducting metal, and chemically mechanically polishing it. The superconducting metal includes, but is not limited to, aluminum, niobium, titanium nitride, etc., and is selected based on actual needs and is not limited in the present embodiment.

[0134] On the basis of the above embodiments, further, the resonant cavity 706 may adopt a coplanar helical or coaxial configuration.

[0135] It should be noted that all inter-chip interconnections in this application allow the use of solder bumps, nail head bumps, etc. The adapter plate can be silicon-based, glass-based, etc., and each conductive part can be made of through-silicon via technology (TSV), through-glass via technology (TGV), molded through-hole technology (TMV), etc.; various film layer preparations can be replaced by compatible sputtering, CVD, PVD, ALD, electroplating, chemical plating and other commonly used material growth technologies; various grooves, holes, and protrusion structures can be replaced by compatible additive and subtractive processes, such as machining, dry etching, wet etching, material growth technology, 3D printing and other common industry technologies; various material layers that perform electrical functions can be replaced by other materials with superconducting properties, such as TiN, Al, Ti, W, Ru, AlCu, In, Nb, Ta, NbN and NbTiN-based, etc.

[0136] The following is a specific example to illustrate the specific implementation process of the method for preparing the computing unit provided by the embodiment of the present invention.

[0137] The first step is to prepare blind holes. Blind holes 802 are prepared on the surface of the carrier 801 by photolithography and DRIE. Figure 8A shown.

[0138] The second step is to deposit an insulating layer. A thin film growth technique capable of filling a high aspect ratio is used to deposit a SiO2 film on the surface of the carrier 801 and the sidewalls and bottom of the blind hole as the insulating layer 803. Figure 8B shown.

[0139] The third step is to form a conductive layer. A metal conductive material is grown on the insulating layer 803 using a thin film growth technology that can fill a high aspect ratio to form a conductive layer 804. Figure 8C shown.

[0140] Step 4: Form the first electrode plate layer. Use photolithography and dry etching to pattern the conductive layer to form the first electrode plate layer 805. Figure 8D shown.

[0141] Step 5: Apply double-layer glue. Apply double-layer glue 806 on the carrier 801 so that the double-layer glue covers the insulating layer 803 and the first electrode plate layer 805. Figure 8E In the double-layered adhesive 806 , the development removal rate of the lower adhesive layer 806 - 1 is higher than that of the upper adhesive layer 806 - 2 , so as to form a subsequent double-opening structure.

[0142] Step 6: Form a double-layered adhesive with a double-opening structure. Perform electron beam direct writing and development on the double-layered adhesive 806 to form a double-layered adhesive with a double-opening structure. Figure 8F shown.

[0143] Step 7: Prepare the first metallization layer. Grow superconducting metal material on the insulating layer 803 through the double-layer glue 806 with double openings at a first angle to form the first metallization layer 807 and the redundant electrode 808. The first metallization layer 807 is connected to the first electrode plate layer 805. Figure 8G Furthermore, during the preparation of the first metallization layer 807, superconducting metal material may also be grown simultaneously on the first electrode plate layer 805 within the blind via. Since this superconducting metal material is grown directly on the first electrode plate layer 805, it has minimal impact on the electrical performance of the deep trench capacitor, eliminating the need for separate processing of the superconducting metal material grown on the first electrode plate layer 805, thereby improving process flexibility. Superconducting metal materials can be selected from commonly used superconducting metals such as Al and Nb in the preparation of Josephson junctions.

[0144] Step 8: In-situ oxidation. When preparing the first metallization layer 807, it will be carried out in a vacuum environment. Keeping the vacuum environment unchanged, in-situ oxidation will be directly performed to form an oxide layer on the first metallization layer 807, the redundant electrode 808 and the first electrode plate layer 805. The oxide layer on the first metallization layer 807 constitutes the first dielectric layer 809, and the oxide layer on the first electrode plate layer constitutes the second dielectric layer 810. Figure 8H shown.

[0145] Step 9: Prepare the second metallization layer. A superconducting metal material is grown on the first dielectric layer 809 and the second dielectric layer 810 located on the carrier 801 through the double-layer glue 806 with a double opening structure at a second angle to form a second metallization layer 811. A redundant electrode 812 is also formed on the insulating layer 803. Figure 8I Furthermore, during the preparation of the second metallization layer 811, excess superconducting metal material may grow on the second dielectric layer 810 of the blind via. As described above, this excess superconducting metal material does not need to be processed, thereby improving process flexibility. The second angle is set based on practical experience and is not limited in this embodiment of the present invention.

[0146] Step 10: Remove the double-layer adhesive. Use an organic solvent such as acetone to remove the double-layer adhesive 806 to expose the structure on the slide 801, such as Figure 8J shown.

[0147] Furthermore, after removing the double-layer adhesive, if the conductive material of the first electrode plate layer 805 is the preset material, and the thickness of the second dielectric layer formed after in-situ oxidation is insufficient to provide the high dielectric properties required for the deep trench capacitor, then photolithography is required to block all structures outside the blind hole to form a surface pattern of the second dielectric layer. Based on the surface pattern of the second dielectric layer, insulating material is further deposited on the second dielectric layer on the sidewalls and bottom of the blind hole so that the thickness of the second dielectric layer on the sidewalls and bottom of the blind hole meets the high dielectric properties required for the deep trench capacitor.

[0148] It should be noted that the first electrode plate layer 805 should preferably be made of a conductive material that can form a second dielectric layer with high dielectric properties required by deep trench capacitors after oxidation, so as to avoid the implementation of the above-mentioned process step of increasing the thickness of the second dielectric layer and reduce the complexity of the process.

[0149] Step 11: Form the second electrode plate layer. Perform photolithography on the current structure to form a photoresist that blocks all structures outside the blind hole, forming a second electrode plate layer surface pattern. Based on the second electrode plate layer surface pattern, a second electrode plate layer 813 is grown using a growth method that can fill deep holes, such as Figure 8K shown.

[0150] Step 12: Perform dielectric filling. Perform photolithography on the current structure to form a photoresist 815 that blocks all structures on the carrier 801 except the blind hole wrapped by the second electrode plate layer 813, forming a surface pattern of the filling dielectric layer. Based on the surface pattern of the filling dielectric layer, a dielectric is grown in the blind hole wrapped by the second electrode plate layer 813 to perform dielectric filling to form a filling dielectric layer 814. Figure 8L The filling dielectric layer 814 is made of insulating material.

[0151] Step 13: Remove the oxide layer. Before growing the conductive material, the photoresist 815 is removed by acetone and ultrasound, and then the oxide layer on the surface of the exposed first metallization layer 807 and the redundant electrode 808 is removed. Removing the oxide layer on the surface of the exposed first pad and the redundant electrode 808 specifically includes: covering the second metallization layer 811, part of the first dielectric layer 809 and the deep trench capacitor with photoresist 816, and removing the oxide layer on the surface of the exposed first metallization layer 807 (i.e., the exposed part of the first dielectric layer 809) and the oxide layer on the surface of the redundant electrodes 808 and 812 by dry etching, as shown in FIG. Figure 8M shown.

[0152] Step 14: Grow conductive material. Grow conductive material on the insulating layer 803 to form the first pad 817 and the second pad 818 of the Josephson junction. Figure 8N As shown, the first pad 817 is connected to the first electrode plate layer 805 of the deep trench capacitor, and the second pad 818 is connected to the second electrode plate layer 813. The first pad 817 and the second pad 818 are also the first pad and the second pad of the deep trench capacitor, that is, the Josephson junction and the deep trench capacitor form a parallel structure.

[0153] Step 15: Remove the photoresist. Remove the photoresist 816 with acetone, such as Figure 8O shown.

[0154] The manufacturing method of the computing unit, the computing module, and the processor provided by the embodiments of the present invention have the following advantages:

[0155] (1) The physical size of components is significantly reduced, and the integration density is significantly increased. Vertical structures with high aspect ratios can be used to construct deep trench capacitor structures with very small planar areas and large capacitance values. Therefore, they can replace the coplanar capacitors required for quantum bits. At the same time, they are more conducive to the use of three-dimensional interconnect structures such as FC and TSV as vertical coupling nodes for quantum bits and resonant cavities.

[0156] (2) The novel process of simultaneous preparation of the oxide layer of the Josephson junction and the oxide layer of the deep trench capacitor in this application, and in-situ oxidation, not only simplifies the overall process steps, but also avoids the interface deterioration problem caused by the metal-metal oxide interface being transported in the atmosphere after leaving the high vacuum chamber, providing an interface state that is as ideal as possible, helping to improve the coherence performance of the Josephson junction and the high capacitance capability of the deep trench capacitor. The Josephson junction and the deep trench capacitor share the first and second pads, achieving a direct parallel electrical connection and avoiding other additional parasitic effects.

[0157] (3) The introduction of three-dimensional interconnect structures such as deep trench capacitors directly inside the core quantum components gives them significant advantages in three-dimensional integration process compatibility and modular assembly, and is more conducive to the physical realization of the core particle architecture.

[0158] (4) The steps of core particle bonding and core particle-adapter package bonding can be completed as a whole through a one-time bonding process after placement, which shortens the process complexity and reduces the adverse effects of repeated heating and cooling processes on the Josephson junction.

[0159] (5) The packaging substrate allows for the installation of multiple adapter plates, and different adapter plates can carry different types of quantum bit cores, which significantly improves the large-scale scalability of the system while ensuring the yield rate. At the same time, it helps to provide a convenient testing platform for the horizontal comparison of the performance of different types of quantum bits.

[0160] Throughout this specification, reference to terms such as "one embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0161] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a computing unit, characterized in that: include: forming a blind hole in the carrier wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole; preparing a first metallization layer of a Josephson junction, and electrically connecting the first metallization layer to the first electrode plate layer; performing in-situ oxidation on the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer, and forming a second dielectric layer on the first electrode plate layer; preparing a second metallization layer on the first dielectric layer to form a Josephson junction; forming a second electrode plate layer of a deep trench capacitor on the second dielectric layer, so that the second electrode plate layer is electrically connected to the second metallization layer; Filling the blind hole wrapped by the second electrode plate layer with a dielectric to form a filling dielectric layer of the deep trench capacitor; The grown conductive material is connected to the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of a computing unit.

2. The method according to claim 1, characterized in that The method of obtaining a first electrode plate layer of a deep trench capacitor based on the blind hole comprises: Depositing an insulating layer on the surface of the carrier and the blind hole; growing a conductive layer on the insulating layer; The conductive layer is patterned to form the first electrode plate layer.

3. The method according to claim 1, characterized in that The step of preparing the first metallization layer of the Josephson junction and electrically connecting the first metallization layer to the first electrode plate layer comprises: Coating a double layer of adhesive on the carrier; wherein the double layer of adhesive needs to be selected so that the opening space formed by the lower layer of adhesive after development is larger than that of the upper layer of adhesive; exposing and developing the double-layer adhesive to form a double-layer adhesive with a double opening structure on the slide; A first metallization layer of a Josephson junction is prepared on the carrier at a first angle based on the double-layer glue with the double-opening structure, so that the first metallization layer is electrically connected to the first electrode plate layer.

4. The method according to claim 1, wherein After forming a second metallization layer of a Josephson junction on the first dielectric layer, the method further includes: If the conductive material of the first electrode plate layer is a preset material, photolithography is performed on the surface of the current structure to obtain a surface pattern of the second dielectric layer; An insulating material is deposited on the surface of the second dielectric layer based on the surface pattern of the second dielectric layer, so that the thickness of the second dielectric layer meets insulation requirements.

5. The method according to any one of claims 1 to 4, characterized in that A plurality of computing units are formed on a slide.

6. A calculation module, characterized in that: Comprising at least one computing unit prepared by the preparation method according to any one of claims 1 to 5.

7. A processor, characterized in that: It includes a first adapter plate, a resonant cavity core particle and a packaging substrate, wherein: The resonant cavity core particle includes at least one resonant cavity and is bonded to the first adapter board; at least one computing unit is arranged on the top surface of the first adapter board, and at least one resonant cavity is arranged on the bottom surface, which is arranged on the packaging substrate through a spacer column.

8. A processor, characterized in that: It includes a computing module, a second adapter board and a packaging substrate, wherein: The computing module is flip-chip bonded on the second adapter plate, and the second adapter plate is arranged on the packaging substrate through a spacer column; the computing module includes at least one Josephson junction, and at least one resonant cavity is respectively arranged on the first surface and the second surface of the second adapter plate.

9. A processor, characterized in that: It includes a computing module, a second adapter board and a packaging substrate, wherein: The computing module is flip-chip bonded to the second adapter plate, and the second adapter plate is arranged on the packaging substrate through a spacer column; the computing module includes at least one Josephson junction, and a resonant cavity is arranged on a side surface of the packaging substrate close to the second adapter plate.

Images