Indium gallium nitride structures and devices

Abstract

Disclosed herein is an InGaN layer characterized by an in-plane lattice parameter in a range of # imgabs 0 # to # imgabs 1 #. The InGaN layer is grown by coalescing InGaN grown on a plurality of GaN seed regions. The InGaN layer may be used to fabricate optical and electronic devices in light sources for lighting and display applications.

Description

[0001] Description of the case

[0002] This application is a divisional application of U.S. Patent Application No. 20208007616.6, filed on November 19, 2020, entitled “Indium Gallium Nitride Structures and Devices,” which is incorporated herein by reference in its entirety. This application claims priority to U.S. Application No. 16 / 689,064, filed on November 19, 2019. Technical Field

[0003] The present disclosure relates to an indium gallium nitride (InGaN) layer having a substantially relaxed region and devices fabricated on the InGaN layer. The substantially relaxed wurtzite (0001) InGaN region has a value greater than or equal to The substantially relaxed InGaN region is grown on multiple Group III nitride seed regions, such as GaN, InGaN, AlGaN, or AlN seed regions. During growth, the InGaN grown on the seed regions relaxes and coalesces to provide a substantially relaxed InGaN region that can serve as a growth surface for other semiconductor materials. The InGaN layer can be used to fabricate optical and electronic devices used as light sources in lighting and display applications. Background Art

[0004] Compound semiconductor materials are typically deposited or grown in an atomic lattice-matched manner onto a growth substrate to avoid growth defects such as dislocations. In some cases, it is desirable to alter the lattice parameters of a compound semiconductor material to provide a material and / or device and / or system with specific properties.

[0005] InGaN is currently the material of choice for active layers of GaN-based optoelectronic devices, including, for example, blue- or violet-emitting light-emitting diodes (LEDs), which are currently the basis of most LED-based lighting and display systems commercialized to date, and violet-emitting laser diodes (LDs), which are blue- or violet-emitting laser diodes. TM The foundation of the industry. Today, such devices are manufactured using an InGaN active layer pseudomorphically grown on a gallium-nitride (GaN) epitaxial layer. Unfortunately, the crystalline atomic lattice parameter of InGaN is larger than that of GaN, resulting in severe strain, and the material quality deteriorates as the InN mole fraction or thickness of the InGaN grown on GaN (InGaN / GaN) increases. This limits the performance of optoelectronic devices based on InGaN / GaN, including, for example, LEDs and LDs.

[0006] To date, attempts to grow high-quality, planar, relaxed InGaN for device applications have not been successfully commercialized. The graded layer approach used in some III-V material systems has been attempted for InGaN using low-temperature molecular beam epitaxy (MBE). However, the relaxation mechanism is associated with the emergence of high-density misfit dislocations, stacking faults, and line dislocations, resulting in poor material quality. Similar approaches using commercially preferred metalorganic chemical vapor deposition (MOCVD) for c-plane InGaN are compromised by the lack of a slip system for (polar) c-plane growth, and attempts to utilize nonpolar and semipolar growth planes result in materials with a high defect density. Hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers in an attempt to reduce crystal defects, but the method is limited in the achievable InN mole fraction and is only applicable to N-polar surfaces, and thus is not ideal for low-cost manufacturing. Growth of strained InGaN layers that can be peeled off and bonded to a compliant carrier to facilitate relaxation has been attempted, but the method results in limited lattice expansion and a non-planar trench surface. Using nanocolumn or nanorod device structures designed to avoid the strain limits of conventional heteroepitaxy results in non-planar device geometries that are not suitable for manufacturing and may exhibit low optical quality.

[0007] The use of patterning and regrowth has been used to grow high-quality, lattice-mismatched heteroepitaxies for single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc blende semiconductors. However, similar approaches for wurtzite semiconductors and / or ternary alloys such as InGaN have not been successful. Summary of the Invention

[0008] According to the present invention, a group III nitride semiconductor structure comprises (a) a seed region comprising In x Ga 1-x N (0 ≤ x < 1) and having a wurtzite group III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group III nitride structure and intersecting the seed region; wherein the intersection of the first plane with a first edge of the seed region locates an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; the In x Ga 1-x N / In y Ga 1-y(c) locating a III-nitride heterojunction in any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region, wherein the III-nitride heterojunction is coplanar with the second crystal plane of the seed region; and (d) a (0001) InGaN region overlying the seed region, wherein the (0001) InGaN region is characterized by being greater than An in-plane lattice parameter of a, wherein each of the first crystal plane and the second crystal plane are crystallographically equivalent.

[0009] According to the present invention, a semiconductor device includes the III-V semiconductor structure according to the present invention.

[0010] According to the present invention, a lighting system comprises the semiconductor device according to the present invention.

[0011] According to the present invention, a display system includes the semiconductor device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Those skilled in the art will appreciate that the drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure.

[0013] Figures 1A to 1E An example of a process flow for fabricating an InGaN layer with a relaxed InGaN region provided by the present disclosure is shown.

[0014] Figures 2A to 2E An example of a process flow for fabricating an InGaN layer with a relaxed InGaN region provided by the present disclosure is shown.

[0015] Figures 3A to 3E An example of a process flow for fabricating an InGaN layer with a relaxed InGaN region provided by the present disclosure is shown.

[0016] Figures 4A to 4E An example of a process flow for fabricating an InGaN layer with a relaxed InGaN region provided by the present disclosure is shown.

[0017] Figure 5 Examples of positive etch masks having various shapes, sizes, and orientations relative to the (1-100) and (11-20) crystallographic directions of the Group III nitride wurtzite material are shown.

[0018] Figure 6 Examples of negative etch masks having various shapes, sizes, and orientations relative to the (1-100) and (11-20) crystallographic directions of the Group III nitride wurtzite material are shown.

[0019] Figure 7The transition of an InGaN lattice characterized by a lattice parameter "a" similar to that of GaN (solid circles) to a more relaxed InGaN lattice characterized by a lattice parameter "a" (dashed circles) is shown.

[0020] Figure 8 An example of an LED incorporating a Group III nitride semiconductor structure provided in the present disclosure is shown.

[0021] Figures 9A to 9D An example of an LED incorporating a Group III nitride semiconductor structure provided in the present disclosure is shown.

[0022] Figure 10 An example of a laser diode (LD) incorporating a III-nitride semiconductor structure provided by the present disclosure is shown.

[0023] Figure 11 Examples of lighting devices and systems in which LEDs provided by the present disclosure may be incorporated are shown.

[0024] Figure 12 Examples of display devices and systems in which LEDs provided by the present disclosure may be incorporated are shown.

[0025] Figure 13 A cross-sectional view illustrating an example of a Group III nitride semiconductor structure provided by the present disclosure is shown.

[0026] Figures 14A to 14B The ranges of the InN mole fraction and the a-lattice parameter of the (0001) relaxed InGaN region according to the peak emission wavelength are shown, respectively.

[0027] Figures 15A to 15F An example of a process flow for manufacturing the InGaN layer provided by the present disclosure is shown.

[0028] Figures 16A to 16F An example of a process flow for manufacturing the InGaN layer provided by the present disclosure is shown.

[0029] Figure 17A and 17B A cross-sectional view illustrating an example of a Group III nitride semiconductor structure provided by the present disclosure is shown.

[0030] Figures 18A to 18C An example is shown in which InGaN is gradually grown on the (10-11) facet of a Group III nitride semiconductor to fill a “v-pit” structure.

[0031] Figure 19 InGaN is shown to gradually grow on the (10-11) GaN seed facet to provide a relaxed InGaN region.

[0032] Figure 20An example of gradual growth of InGaN on a (10-11) GaN seed facet to provide a relaxed InGaN region is shown. DETAILED DESCRIPTION

[0033] "Substantially uniform lattice parameter" refers to a semiconductor layer characterized in that the local lattice parameter of the semiconductor layer varies less than 1% relative to the average lattice parameter, such as less than 0.5% relative to the average lattice parameter, or less than 0.1% relative to the average lattice parameter.

[0034] "Defect density" refers to the density of extended defects (e.g., dislocations) in a semiconductor layer in a plan view. Defect density can be determined using, for example, etching (and counting etch pit density, EPD), cathodoluminescence to observe and count dark spots, and atomic force microscopy (AFM) to observe and count small pits.

[0035] Lattice parameters can be determined using X-ray diffraction (XRD) and reciprocal space map (RSM) analysis. High-angle or near-grazing incidence XRD techniques can be used to determine the lattice parameters of upper layers in structures where the lattice parameter varies as a function of depth.

[0036] "Group III-V material" refers to a compound semiconductor material containing at least one Group III element and at least one Group V element from the periodic table.

[0037] "Growth plane" refers to a plane parallel to the plane of deposition of material on a planar surface, such as the plane of a conventional substrate growth surface.

[0038] "Substantially perpendicular to the growth plane" refers to a surface that forms an angle of approximately 90 degrees relative to the growth plane, such as from 88 degrees to 92 degrees relative to the growth plane.

[0039] Wurtzite GaN is characterized by having room temperature a and c lattice parameters of and The wurtzite crystal structure. The crystal plane perpendicular to the c lattice parameter direction ("c direction") is the c plane, which has the Ga face (0001) and the N face (000-1). The plane containing the c direction and perpendicular to the a lattice parameter direction ("a direction") is the (11-20) plane or "a plane." The plane containing the c direction and rotated 30 degrees relative to the a direction is the (1-100) plane or "m plane."

[0040] WurtziteIn x Ga 1-x N has the same crystal structure as wurtzite GaN, but includes a non-zero mole fraction x of InNr to form a ternary compound in which the specified fraction of the Group III atoms is In and the remainder is Ga. InN has and The room temperature a lattice parameter and c lattice parameter, and according to the mole fraction, In x Ga 1-x N has room temperature a-lattice parameters and c-lattice parameters between those of GaN and InN.

[0041] Although this description focuses on the growth of (0001) InGaN on a GaN seed surface, the method can be applied to other wurtzite materials, such as InGaN on AlN, AlGaN on AlN, and AlGaN on GaN. Furthermore, the invention is applicable to non-basal plane wurtzite structures, such as so-called non-polar and semi-polar GaN and related materials. Finally, the invention can also be applied to other compound semiconductor systems, including zinc blende materials, such as InGaAs on GaAs and InGaSb on GaSb, as well as II-VI compound semiconductor systems.

[0042] "Relaxed InGaN" refers to an InGaN material that exhibits an in-plane lattice parameter equal to or nearly equal to the in-plane lattice parameter of a fully relaxed InGaN material. For example, wurtzite relaxed InGaN has a lattice parameter greater than (0% InN) and at most The room temperature a-plane lattice parameter of InGaN (100% InN) is 1.5 times that of InN (100% InN). This is in contrast to strained InGaN materials, such as InGaN pseudomorphically grown as GaN and thus exhibiting an in-plane lattice parameter equal to or nearly equal to that of GaN (i.e., approximately 3.189), regardless of the InN mole fraction. Such strained InGaN materials are referred to as InGaN / GaN.

[0043] The in-plane lattice parameter refers to the lattice spacing within the growth plane. For (0001) materials, the in-plane lattice parameter is the α lattice parameter.

[0044] "Lateral growth" refers to growth in a direction other than perpendicular to the growth plane, including parallel to the growth plane.

[0045] Reference will now be made in detail to certain embodiments of materials, semiconductor structures, optoelectronic devices, and methods. The disclosed embodiments are not intended to limit the claims. On the contrary, the claims are intended to cover all alternatives, modifications, and equivalents.

[0046] The present invention teaches the formation of large-area, planar, coherent, at least partially but substantially uniformly relaxed layers of compound semiconductor materials for use in optical and / or electronic devices. Large area means greater than 1 mm 2 area, for example, greater than 1 cm in extent 2. Planar refers to a semiconductor layer that exhibits at least one substantially flat surface and has substantially no significant thickness variations over a large area. For example, a planar semiconductor layer can have an RMS roughness of less than 1 nm, as determined using an atomic force microscope. A planar semiconductor layer can have a thickness, for example, within + / - 10% of the average thickness. Coherent refers to a material that is substantially crystalline, rather than amorphous. Relaxed refers to a material whose in-plane lattice parameter is approximately the lattice parameter of a free-standing, coherent, 100% relaxed form of the material. Substantially relaxed refers to a material in which the in-plane lattice parameter of the material is within 30% of the in-plane lattice parameter of the free-standing, coherent, 100% relaxed form of the material. Uniformly refers to an in-plane lattice parameter that is substantially constant over a large area on which optical and / or electronic device structures can be built. In addition, the present invention is applicable to a wide range of semiconductor crystal systems, including the wurtzite crystal structure, and to higher order alloys including ternary and quaternary alloys. Finally, the present invention is applicable to structures grown by a variety of growth methods, particularly metal organic chemical vapor deposition (MOCVD).

[0047] In particular, the present invention teaches the formation of large-area, planar, coherent, at least partially but substantially uniformly relaxed layers of indium gallium nitride (InGaN) material for use as substrates for optical and / or electronic devices. A variety of compositions (i.e., InN mole fractions) can be achieved. Coherent means that the InGaN material is substantially crystalline, rather than amorphous. Relaxed means that the lattice parameters of the InGaN material are approximately the lattice parameters of a free-standing, coherent, 100% relaxed InGaN material of the same composition. Uniformly relaxed means that the lattice parameters of the layer are substantially constant over a substantial portion of the large area in the plane containing the growth plane. In the present invention, such relaxed InGaN material is referred to as relaxed InGaN, e.g., Native InGaN.

[0048] The present invention also teaches the formation of optical and / or electrical devices and systems based on the relaxed InGaN, which may include additional InGaN layers pseudomorphically grown as relaxed InGaN (i.e., InGaN / InGaN), such as Native

[0049] Other features and aspects of the present invention will become apparent from the following description and accompanying drawings. In particular, the teachings of the present invention can be applied to other compound semiconductor device materials, such as aluminum gallium nitride, aluminum gallium indium nitride, III-As, III-P, III-Sb, etc.

[0050] The present invention discloses the use of a semiconductor seed material deposited on a substrate to record the crystalline growth of a compound semiconductor material. The seed material has a plurality of seed regions having edges that are planar seed surface portions, and each normal to these planar seed surface portions has a crystallographically equivalent direction that is not parallel to the normal to a large area of ​​the substrate. The crystallographically equivalent orientations of a limited (preferably one) number of exposed flat seed surfaces ensure uniform relaxation and composition control of the InGaN material grown thereon, avoiding competing growth modes and problems associated with uncontrolled composition control, such as uneven InN incorporation, rough surfaces, etc. when variable seed surface orientations for InGaN growth are simultaneously present. The size of the seed surface portion is limited to a certain extent so that additional compound semiconductor material can be seeded and easily relax to its relaxed lattice parameter during growth. The resulting "relaxed" compound semiconductor material then grows outward and coalesces to form a large area (i.e., greater than 1×1 mm 2 , preferably larger than 1×1 cm 2 Large-area, relaxed films of compound semiconductor materials provide templates for growing improved optical and / or electronic device structures.

[0051] In particular, the present invention discloses the use of a GaN seed region having a seed surface portion to record the crystalline growth of InGaN. The size and geometry associated with the GaN seed surface are constrained to a certain extent so that the InGaN material can be seeded and easily relax to its relaxed lattice parameters during growth. The crystallographic directions characterizing the normal to the planar seed surface portion can be non-polar directions, such as (11-20) or (1-100) or planes rotated between them, or semi-polar directions, such as (1-101). The (relaxed) InGaN layer then grows outward and coalesces into a planar, large-area film. The large-area, relaxed InGaN film provides a template for growing improved InGaN-based optical and / or electronic device structures.

[0052] Figures 1A to 1E An example of a method for growing a relaxed InGaN region is shown.

[0053] like Figure 1AAs shown, a main (0001), i.e., c-plane GaN (or AlN) layer 102 can be grown on a substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include engineered substrates, such as silicon on insulator (SOI). The GaN layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. The GaN layer 102 can be covered with a mask layer 103 of a material that slowly promotes the nucleation of the group III nitride material. Suitable mask materials include, for example, dielectrics such as silicon nitride, silicon oxide, and aluminum oxide. The mask layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography (e.g., using nanolithography and wet and / or dry etching techniques) to provide a Figure 1B The desired pattern is shown. The etched region 104 where the mask and GaN material have been removed exposes the GaN seed surface 102a. The seed surface can be substantially perpendicular to the GaN (0001) c plane. Figure 1C As shown, the GaN seed surface 102a can be used to grow InGaN 105 at least laterally, thereby forming an InGaN / GaN heterojunction that is not coplanar with the substrate 101. Each exposed GaN seed surface can have an equal crystallographic orientation. For example, the GaN seed surface can be primarily (1-100), i.e., an m-plane, or primarily (11-20), i.e., an a-plane, or any plane rotated between the m-plane and the a-plane. In addition, the seed surface 102a can be intentionally misoriented relative to the main GaN crystal plane, for example, to promote favorable and uniform growth characteristics. Figure 1E Shown are plane 108a passing through the relaxed InGaN region and coplanar with surface 107, and plane 108b bisecting seed region 102 and the InGaN region between seed regions 102. The center of the seed region is indicated by 108c, and the center of the InGaN region between seed regions 102 is indicated by 108d.

[0054] The orientation of the GaN seed surface can be determined by the patterning and the growth orientation of the GaN layer. The orientation of the seed surface also depends on the angle of the etched GaN layer surface. For example, for a (0001) GaN layer and near-vertical etching, the orientation of the GaN seed surface can vary from approximately (1-100) to (11-20), as well as any orientation rotated between them. This orientation can be selected to optimize InGaN growth conditions and InGaN material quality.

[0055] For InGaN growth on certain GaN seed surfaces, particularly those that are substantially perpendicular to the substrate major surface, to promote coalescence, it may be necessary to enhance lateral-vertical growth by optimizing growth conditions and / or selecting a GaN seed surface orientation that promotes fast growth rates.

[0056] The small size of the GaN seed crystal surface promotes the deposition of InGaN material on it and provides a planar crystallographic orientation to promote coherent InGaN growth. During growth, the InGaN grows coherently and relaxes toward its lattice parameter and eventually coalesces with the adjacent InGaN growth front. Figure 1C , InGaN105 is grown from the surface of GaN seed crystal, and Figure 1D InGaN 106 is grown in the etched cavity to fill the etched cavity and cover the mask layer 103. The continuous InGaN growth causes the InGaN grown on the surface of the GaN seed crystal in the adjacent cavity to coalesce. Relaxed InGaN is then grown over the mask layer to form a continuous, planar, relaxed InGaN region or InGaN template at the upper InGaN growth surface 107.

[0057] In the present InGaN growth method, relaxation occurs primarily laterally, i.e., by twisting, rather than by tilting as occurs when attempting InGaN relaxation directly on a GaN (0001) surface. The latter approach introduces vertical InGaN strain gradients that become problematic during the subsequent growth and coalescence of the InGaN. In contrast, the present invention provides reduced tilting, which allows the final coalesced film to be essentially free of strain and / or compositional inhomogeneities, thereby providing a high-quality, planar, relaxed InGaN large-area surface for semiconductor growth. Furthermore, because relaxation occurs uniformly across the GaN seed crystal surface, vertical strain gradients that can arise when a strained layer is first pseudomorphically grown (and then etched and relaxed) are largely avoided.

[0058] In the InGaN growth method provided by the present disclosure, InGaN growth occurs primarily on the surface of the GaN seed material, and InGaN growth on other exposed surfaces should be minimized or completely avoided. For this reason, it may be beneficial to etch through the GaN seed material and into the underlying substrate to move the substrate growth surface away from the InGaN nucleation zone. In addition, the growth conditions of the InGaN layer can be selected to promote growth at one or more GaN seed surfaces, as opposed to InGaN nucleation and growth on the substrate, which would exhibit a competitive growth mode. This method is Figures 2A to 2E , where a GaN layer is etched and a portion of the substrate is etched. By etching the substrate, the distance between competing growth (at the substrate surface) and desired growth at one or more surfaces of the GaN seed material is increased, with the goal of making the InGaN grown on the substrate non-competitive. In addition, etching the substrate can be used to prevent the nucleation and growth of InGaN, which further reduces the possibility of interfering with the competing growth mode.

[0059] Figure 2AA substrate 201, an overlying GaN layer 202, and an overlying mask layer 203 are shown. Figure 2B In FIG. 2 , the mask layer 203, the GaN layer 202, and a portion of the substrate 201 have been etched to provide a cavity 204 with an exposed GaN seed surface 202a. Figure 2C As shown, InGaN 205 grows on the GaN seed crystal surface 202a and laterally grows into the corresponding cavity 204 and above the substrate 201. Figure 2D As shown, the continued InGaN growth 206 causes the lateral growth regions to merge and grow outward from the cavity and onto the mask layer 203. A portion 208 of the cavity 204, i.e., a void, may be created between the substrate 201 and the merged InGaN 206 within the cavity. Figure 2E As shown, the continuous InGaN growth causes the InGaN grown from adjacent cavities to coalesce and form a relaxed InGaN surface 207, which is available for the growth of semiconductor layers. Figure 2E Shown are plane 208a passing through the relaxed InGaN region and coplanar with surface 207, and plane 208b bisecting seed region 202 and the InGaN region between seed regions 202. The center of the seed region is indicated at 208c, and the center of the InGaN region between seed regions 202 is indicated at 208d.

[0060] Figure 13 is Figures 2A to 2EDetailed cross-sectional view of the structure produced by the process flow shown in . A substrate 1301 (e.g., (0001) sapphire) includes an optional etched region 1306 extending into the substrate 1301. A GaN (or AlN) seed layer material 1302 characterized by an in-plane a-lattice parameter a1 overlies the substrate 1301 in the unetched regions and beneath a mask layer 1303. InGaN 1305 has nucleated at the edges of the seed layer material 1302 on the GaN seed surfaces 1307, thereby forming an InGaN / GaN heterojunction 1307 (i.e., the heterojunction is located at the interface between the InGaN region and the GaN seed region), whose normals share an equivalent crystallographic direction that is not parallel to the major surface of the substrate 1301. The InGaN material 1305 has at least partially grown laterally outward to relax toward the relaxed InGaN in-plane a-lattice parameter a2 in the InGaN region between the GaN seed surfaces. A plane 1308b, parallel to the major surface of substrate 1301 and bisecting GaN seed surface 1307, is characterized by different in-plane a-lattice parameters at different locations within the cross-section. For example, at a central point within the GaN seed region, the lattice parameter along plane 1308b is characterized by a1, which is comparable to the GaNa lattice parameter, and at a central point 1305 between GaN seed surfaces 1307, the lattice parameter along plane 1308b is approximately a2, comparable to the lattice parameter of at least partially relaxed InGaN and determined by the epitaxial growth conditions (e.g., temperature and relative flow rate) of an organometallic precursor, such as trimethylindium (TMI), based on the average mole fraction of InN in the InGaN layer, particularly compared to trimethylgallium (TMG) in MOCVD. In the region between these two central points, the lattice parameter along plane 1308b is characterized by an in-plane a-lattice parameter greater than a1 and less than a2, since a2>a1. In a plan view (not shown), the variation in the in-plane a lattice parameter within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figure 5 and 6 ).

[0061] The InGaN material coalesces on the mask layer 1303 to form a relaxed InGaN region 1304 having a flat InGaN surface 1305c. A plane 1308a parallel to the major surface of the original growth substrate and located within the relaxed InGaN region 1304 is primarily characterized by an in-plane a-lattice parameter a2. In particular, at a center point 1305 between the GaN seed surfaces, the InGaN lattice parameter along plane 1308a is characterized by a2, while at a center point above the GaN seed surface, the InGaNa lattice parameter along plane 1308a is slightly less than a2. In a plan view (not shown), the variation in the in-plane a-lattice parameter within plane 1308a is characterized by the two-dimensional mask pattern applied to the GaN seed layer (see FIG. Figure 5 and6 For example, XRD and RSM can be used to detect variations in the in-plane α-lattice parameter of InGaN, and grazing incidence techniques can be used to resolve these variations at the submicron scale and on the surface. The midpoint of the plane 1308b within the seed region is shown as 1308c, while the midpoint of the plane 1308b between the seed regions is shown as 1308d.

[0062] The GaN seed region 1302 has an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed region 1302 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302, for example, the width of the GaN seed region 1302, can be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 can be, for example, 0.01 μm to 1 μm, 0.02 μm to 0.8 μm, 0.05 μm to 0.5 μm, or 0.1 μm to 0.4 μm.

[0063] Figures 3A to 3E An example of a process flow for fabricating relaxed InGaN using an SOI substrate is shown. In this embodiment, it may be desirable to include a strain-controlling interlayer, such as GaN, AlGaN, or AlInGaN, within the semiconductor structure (not shown) to manage wafer bow, as is well known for growing GaN on Si.

[0064] Figure 3A A substrate 301 , oxide and silicon layers 301 a and 301 b , a seed layer 302 , and a mask layer 303 are shown. Figure 3B Cavity 304 is shown after etching down to silicon layer 301 b , which forms a seed region from seed layer 302 . Figure 3C InGaN is shown to be grown laterally on the edge surface of the seed region from the seed layer 302 within the cavity 304. This InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. Figure 3D In the example, InGaN growth 306 from seed layer 302 has grown outward and merged to fill the cavity and extend over mask 303. Figure 3E As shown, the continued InGaN growth provides a planar relaxed InGaN layer 307 . Figure 3E Shown are plane 308a passing through the relaxed InGaN region and coplanar with surface 307, and plane 308b bisecting seed region 302 and the InGaN region between seed regions 302. The center of the seed region is indicated at 308c, and the center of the InGaN region between seed regions 302 is indicated at 308d.

[0065] Figures 4A to 4EAnother example of a process flow for fabricating a relaxed InGaN layer using an SOI substrate is shown. Figures 3A to 3E , where the top silicon layer and buried oxide layer 401a of the SOI substrate 401b are removed by etching (in region 404) to minimize competing growth of InGaN on the silicon substrate and favor InGaN growth on the seed crystal surface.

[0066] Figure 4A An SOI substrate 401 , oxide layer 401 a and silicon layer 401 b , a seed layer 402 and an overlying mask layer 403 are shown. Figure 4B A cavity 404 is shown, created by etching down to the substrate 401, forming a seed region from the seed layer 402. Figure 4C In the embodiment, lateral InGaN growth 405 extends from the edge surface of the seed layer 402 into the cavity 404. This InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. Figure 4D As shown, the continuous InGaN growth 406 causes the InGaN grown from the opposite seed surface to merge and grow vertically to fill the upper portion of the cavity and extend over the mask layer 403. Compared to the growth on the substrate, the preferential growth from the seed surface creates a space 408, i.e., a gap, between the substrate 401 and the InGaN layer 406. Figure 4E As shown, the continued InGaN growth provides a planar relaxed InGaN layer 407 . Figure 4E Shown are plane 408a passing through the relaxed InGaN region and coplanar with surface 407, and plane 408b bisecting seed region 402 and the InGaN region between seed regions 402. The center of the seed region is indicated at 408c, and the center of the InGaN region between seed regions 402 is indicated at 408d.

[0067] Figure 5 Example mask patterns for etching seed materials are shown, including stripes, rectangles, triangles, and hexagons. For wurtzite materials such as Group III nitride materials, including InGaN, preferred pattern features are pattern features with edges that share the same crystallographic orientation, such as hexagons or triangles. Other shapes and other relative sizes can be used. The narrowest dimension of the mask pattern can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern can be aligned with certain crystal planes. For example, for wurtzite materials having a (0001) principal growth plane, the mask edges can be aligned with the (1-100) or (11-20) planes, or any orientation between these planes, to facilitate the growth of high-quality, relaxed InGaN layers.

[0068] Figure 6 A set of alternative mask patterns are shown, which are Figure 5Negative image of the mask pattern shown, but similar in other respects.

[0069] Figure 7 A conceptual planar cross-sectional view of a patterned GaN seed material having a lattice parameter a is shown on the side surfaces of which lateral heteroepitaxy is performed to grow an InGaN layer that is allowed to relax to a relaxed lattice parameter a' by distortion. For sufficiently small dimensions, the deformation is completely elastic and no defects are formed. For larger dimensions, some plastic deformation may occur, but this may be tolerable if the final defect density in the subsequently deposited overlying semiconductor layer is sufficiently low. For example, it is desirable that the extension defect density in the subsequently deposited semiconductor layer be less than 5E9 cm 2 , for example, less than 5E8 cm 2 or less than 5E7 cm 2 The present disclosure provides a lateral InGaN growth and coalescence method that facilitates the annihilation of threading dislocations in Group III nitride materials.

[0070] Further control over the thickness and composition uniformity of the relaxed InGaN growth can be provided by growing a multilayer structure rather than using a bulk InGaN layer. For example, a 25% bulk InGaN layer can be formed by, for example, 3nm of GaN and 1nm of InN, or 2nm of GaN and 2nm of In 0.5 Ga 0.5 The epitaxial stack is replaced by alternating layers of N. The thickness of each layer can be, for example, 0.5 nm to 100 nm, such as 1 nm to 30 nm. The multilayer structure is not limited to the base layer, but can be used in the entire epitaxial stack or in the layer between the relaxed InGaN base layer and the device layer, which includes semiconductor device layers, such as n-type, p-type, and active layers, overlying the relaxed InGaN layer.

[0071] The increased lattice parameter of the relaxed InGaN layer allows the growth of subsequently deposited semiconductor layers at much higher temperatures than InGaN / GaN. For example, with a temperature of approximately 1000 nm, compared to about 4% for InGaN / GaN, the increased lattice parameter of the relaxed InGaN layer allows the growth of subsequently deposited semiconductor layers at much higher temperatures than for InGaN / GaN. InGaN with a lattice parameter of α has been shown to incorporate approximately 7% InN. Because the mole fraction of InN incorporated into GaN is inversely proportional to the growth temperature in MOCVD, this suggests that an increase in the InGaNa lattice parameter of approximately 0.015 to 0.020 can increase the useful growth temperature by approximately 50°C. Further increases in the InGaNa lattice parameter would allow the use of even higher temperatures for the same InN mole fraction. This effect can be used not only to achieve higher quality semiconductor layers grown on relaxed InGaN by reducing point defect formation at higher temperatures, but also by reducing or eliminating pits that appear at the sites of threading dislocations in the InGaN film surface. Ideally, the growth temperature of the InGaN layer is kept high enough to eliminate or at least limit pits to diameters well below 1 μm, for example, less than 200 nm, or less than 50 nm. Small pits can be "filled" using a thin, high-temperature GaN or AlGaN layer grown on the pitted InGaN film.

[0072] The method provided by the present disclosure can include recursion, which can help to obtain large lattice parameter changes. For example, a relaxed InGaN layer can be used as a seed layer to provide a seed surface for growing a higher-InN mole fraction layer. The resulting new relaxed InGaN layer can then be used as a seed layer in another round of the process, and so on. The method can help to obtain a relaxed InGaN layer with a very high InN mole fraction, which can be suitable as a base layer for growing an active semiconducting layer for emitting long wavelengths, such as beyond the red, to the deep red and even infrared emission, at wavelengths in the range of, for example, 700 nm to 1.6 μm.

[0073] The relaxed InGaN layers provided by the present disclosure can be used as templates and / or support structures for growing optical and / or electrical devices. Very large area wafers are possible, including 150 mm, 200 mm or larger diameter wafers, which facilitate high volume, low cost manufacturing of these devices.

[0074] As an example, Figure 8 An LED structure is shown, which is formed by growing an n-type layer 806 (e.g., doped with Si or Ge) on the relaxed InGaN surface of an InGaN layer 804, followed by growing an active region 807 comprising InGaN, an optional p-type electron blocking layer 808 comprising, for example, GaN, AlGaN, or InGaN (or a multilayer comprising these alloys), and then growing a p-type layer 809 such as a p-type GaN or InGaN layer. A highly doped (e.g., Mg-doped) p-type contact layer 810 comprising, for example, GaN or InGaN overlies the p-type layer 809 and provides ohmic contact to the device on the p-side. Figure 8As shown, the semiconductor structure beneath the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. To the extent that there is a refractive index contrast between these different features, their presence can help improve light extraction from the device. The resulting semiconductor wafer can undergo a series of process steps, such as photolithography, etching, and semiconductor deposition, to form isolated LED regions with suitable electrical contact materials to the n-type and p-type layers. Such contact materials can include those with suitable optical properties (e.g., high light reflectivity and / or transparency). Electrode metallization layers 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned to provide electrical connections, for example, using wirebonds. Various transparent conductive oxide (TCO) materials (not shown), such as indium tin oxide (ITO), can be used to facilitate current spreading layer 811, particularly for the resistive p-type layer. After fabricating the semiconductor structure, the wafer can be diced to provide individual devices that can be mounted in a suitable package by various means, including epoxy die attach or soldering. For example, wire bonding can be used to electrically contact the p-type and n-type layers to form a functional device to which power can ultimately be supplied. The device can further include luminescent down-conversion materials and / or encapsulation materials, such as silicone, to provide desired light output characteristics, including white light for lighting applications. The device can be used in lighting systems and / or display applications.

[0075] like Figures 9A to 9D As shown, various flip-chip (FC) LED structures are possible, including (a) standard, (b) thin film flip-chip (TFFC) in which the initial growth substrate has been removed but the mask and seed layer portions remain, (c) TFFC with the mask and seed layer portions removed, and (d) TFFC with the mask and seed layer portions removed and the exposed InGaN layer textured (for light extraction purposes) by techniques such as photolithography and / or chemical-based etching.

[0076] Figures 9A to 9D The semiconductor structure shown includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and an initial InGaN growth region 905, an n-type layer 906, an active region 907 containing InGaN, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization layer 911, and an n-side electrode metallization layer 912. Figure 9B In the Figure 9C In the , the growth and mask regions have been removed, and in Figure 9D In FIG. 9 , a portion of the relaxed InGaN region 904 has been removed and / or roughened 904a, for example to enhance certain optical properties of the device.

[0077] Figure 10 Figure 2 shows a laser diode structure grown on a relaxed InGaN layer. Figure 10 As shown, a relaxed InGaN layer 1004 including an initial InGaN region 1005 covers a mask region 1003, a seed region 1002, and a substrate 1001. A laser diode can be formed by growing an n-type optical confinement ("cladding") layer 1007 on the relaxed InGaN material 1004 and an n-type contact layer 1006, and then growing an InGaN-based active region including a waveguide region comprising waveguide layers 1008 and 1010 on either side of an InGaN-containing active layer 1009, followed by growing a p-type optical confinement ("cladding") layer 1011. Layers 1012 and 1013 cover the p-cladding layer 1011. Wafer fabrication for laser diodes is similar to that for LEDs, except that the devices are formed into stripes to form the laser cavity. After cutting and forming the etched or cleaved mirrors, highly reflective and anti-reflective dielectric coatings can be deposited on the rear and front facets, respectively (not shown). Depending on the material selection and application details, the laser diode can be mounted in an appropriate package, either epitaxial side down or substrate side down. Electrical contact can be made to the highly doped p-type contact layer 1014 and n-type contact layer 1006 via electrode metallization layers 1015a and 1015b, respectively, to form a functional device to which electrical power can be supplied. Laser diodes are used in lighting systems and / or display applications.

[0078] The relaxed InGaN layers provided by the present disclosure are applicable to a wide range of compound semiconductor devices, which impact the performance of a wide range of system solutions for various applications, including lighting devices and systems ( Figure 11 ) and display device and system ( Figure 12 ).

[0079] The target composition of the relaxed InGaN layer can be selected based on the intended device, application, and performance requirements. For conventional InGaN light-emitting diodes that are lattice-matched to GaN, the best performing devices are those that emit in the violet wavelength range. At these wavelengths, the strain state of the InGaN quantum well relative to the GaN base layer is about 1% to 2%. The corresponding composition difference is high enough that the bandgap design can provide very high quantum efficiency devices, while the strain state is low enough to allow relatively thick InGaN quantum well (QW) layers, which are used to reduce carrier density and mitigate non-radiative Auger recombination (also known as "attenuation"). Applying this acceptable range of strain states to other emission wavelengths, the preferred composition range of the relaxed InGaN base layer provided by the present disclosure can be calculated for a wide range of emitters from blue (about 450nm) to infrared (about 1.3μm) wavelengths. The preferred ranges are listed in Tables 1 and 2.

[0080] Table 1. Emission color according to (PWL = peak wavelength in nm, Eg = band gap in eV, a_base = The lattice parameter a in the base plane at 300K is calculated as follows: a_QW = Preferred range of InN mole fraction in a relaxed InGaN(0001) based layer for light emitting diodes and laser diodes (calculated in the quantum well layer at 300K) (lattice parameter a).

[0081]

[0082] Table 2. Emission color according to (PWL = peak wavelength in nm, Eg = band gap in eV, a_base = The lattice parameter a in the base plane at 300K is calculated as follows: a_QW = Preferred range of InN mole fraction in a relaxed InGaN(0001) based layer for light emitting diodes and laser diodes (calculated in the quantum well layer at 300K) (lattice parameter a).

[0083]

[0084]

[0085] Figure 14A and 14B The preferred ranges of InN mole fraction and a lattice parameter of a (0001) relaxed InGaN layer used as a template for fabricating light emitting diodes and laser diodes according to the peak emission wavelength are shown in the figure, which are consistent with the parameters given in Tables 1 and 2. For example, as a function of the peak emission wavelength a, the relaxed InN x Ga 1-x The InN mole fraction x of the N-based layer should satisfy the condition x min ≤x≤x max , where X min and X max They are defined by Equation 1 and Equation 2 respectively:

[0086] x min =-6.046E-07 λ 2 +1.837E-03 λ -6.917E-01, (λ ≥ 440 nm) Equation 1

[0087] x max =-6.152E-07 λ 2 +1.847E-03 λ - 6.142E-01, (λ ≥ 440 nm) Equation 2

[0088] Similarly, as a function of the peak emission wavelength λ, the relaxed In x Ga 1-x The in-plane ("a") lattice parameter a of the N-based layer should satisfy the condition a min ≤a≤a max , where a min and a max They are defined by Equation 3 and Equation 4 respectively:

[0089] a min =-2.067E-07 λ 2 +6.366E-04 λ-2.951, (λ ≥ 440 nm) Equation 3

[0090] a max =-2.190E-07 λ 2 +6.575E-04 λ-2.970, (λ ≥ 440 nm) Equation 4

[0091] The method and semiconductor structure provided by the present disclosure can be applied to the manufacture of vertical cavity surface emitting layers (VCSELs). The composition selection of the relaxed InGaN-based layer for LDs or VCSELs is similar to that for LEDs and is shown in Tables 1 and 2.

[0092] Figures 15A to 15F A method for fabricating a relaxed InGaN layer on a faceted GaN seed region edge surface is shown. In this method, a (0001) GaN or AlN seed layer 1502 is provided on a substrate 1501 . Figure 15A Shown is a substrate 1501, an overlying seed layer 1502, and an overlying mask layer 1503. The GaN seed layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. Figures 15A to 15F In the process flow shown, the seed layer 1502 can be covered with a mask layer 1503 containing a material that slowly promotes GaN nucleation. The mask layer 1503 can be patterned and etched into the various patterns described above using any suitable lithography including nanolithography and etching techniques (wet or dry or a combination thereof). The exposed GaN created by etching the openings in the mask 1504 can then be used to nucleate the GaN seed material 1506, as shown in FIG. Figure 15C and 15D As shown, the seed material can grow outward from the opening in the mask and, by appropriate selection of growth conditions, allows the formation of a seed region having edges, such as triangular faces with a hexagonal base. For example, the structure can be a hexagonal structure with a hexagonal base and having triangular faces that are {1-101} equivalent planes. Once the facets are as shown, the seed material can be grown outward from the opening in the mask and, by appropriate selection of growth conditions, allows the formation of a seed region having edges, such as triangular faces with a hexagonal base. For example, the structure can be a hexagonal structure with a hexagonal base and having triangular faces that are {1-101} equivalent planes. Figure 15DAs shown fully formed, the triangular facet surface 1507 can be used as a seed surface for at least lateral growth of InGaN, thereby forming a heterojunction that is not coplanar with the substrate surface. As the thickness of the InGaN increases, the small size of the GaN seed surface (facet) and the choice of InGaN composition promote relaxation of the overgrown InGaN while providing a flat, crystallographically equivalent orientation to ensure coherence. Figure 15E As shown, InGaN 1508 grows coherently and relaxes its lattice parameters to form a hexagonal structure with triangular faces of relaxed InGaN. These InGaN facets can further grow outward and eventually merge with adjacent InGaN growth fronts of other planar seed facets. Figure 15F As shown, the coalesced InGaN is then grown over the mask layer and seed region, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN layer or template 1509 as the upper region of the structure. This method has the advantage of not requiring etching of the GaN (or InGaN, AlGaN, or AlN) seed material to provide a portion of the seed surface for InGaN nucleation. In addition, this method is very suitable when the growth substrate is a Group III nitride material, such as a GaN or AlN substrate. Therefore, this method is beneficial for the fabrication of LD devices where a low dislocation density (e.g., less than 5E7 cm for a GaN substrate) is preferred for long lifetime operation (>10,000 hours). -2 ).

[0093] Figures 16A to 16F Another method for fabricating a relaxed InGaN layer on a faceted GaN surface is shown. Figures 15A to 15F The method shown in FIG. 1 is similar to the method shown in FIG. 1 , except that the GaN seed material is nucleated on a substrate. In this method, a substrate 1601 suitable for GaN nucleation, such as sapphire, SiC, sapphire, AlN, or GaN, may be provided. Figure 16A , the substrate 1601 may be covered with a mask layer 1602 of a material that slowly promotes GaN nucleation. Figure 16B As shown, the mask layer 1602 is patterned and etched into various patterns 1604 using lithography such as nanolithography and etching techniques (wet or dry or a combination thereof). Figure 16C As shown, the exposed substrate 1603 created by etching in the openings of the mask can then be used to nucleate GaN seed material 1605, which grows outward from the openings in the mask and, by appropriate selection of growth conditions, allows the formation of a GaN seed region having edges that are triangular faces and have a hexagonal base. For example, the seed region can be hexagonal and have triangular faces that are {1-101} crystallographically equivalent planes. Figure 16DAs shown, after the seed region is fully formed, the triangular facet surface 1607 serves as a seed surface for at least lateral growth of InGaN to form six heterojunctions in crystallographically equivalent planes that are not coplanar with the substrate. The small size of the GaN seed surface and the selection of the target composition of the grown InGaN material promote relaxation of the InGaN grown on the seed surface. In addition, each seed surface provides a flat, crystallographically equivalent orientation to ensure coherence of the entire outwardly grown InGaN material. The InGaN grows coherently and relaxes its lattice parameters to form a Figure 16E The relaxed InGaN facets 1608 are shown. These facets grow further outward and eventually coalesce with adjacent InGaN growth fronts growing from other seed regions. Figure 16F As shown, the agglomerated InGaN is then grown over the mask layer, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN region 1609 or template across the substrate. This method has the advantage of not requiring etching of the GaN (or AlN) material to provide a seed surface for InGaN nucleation. This method also has the advantage of providing the entire process in a single epitaxial growth process. In addition, this method is very suitable when the growth substrate is a Group III nitride material, such as a GaN or AlN substrate.

[0094] Figure 17A Provided by Figures 15A to 15FDetailed cross-sectional view of the structure obtained by the process flow in FIG. A substrate 1701 such as (0001) sapphire is used as the main growth substrate for a GaN (or InGaN, AlGaN or AlN) seed layer 1702, characterized by an in-plane a lattice parameter a1. The GaN seed layer 1702 has grown outward between mask regions 1703 to form a GaN seed region 1702a having an exposed edge of a crystallographically equivalent flat GaN seed surface. InGaN material has nucleated on the triangular GaN seed surface of the GaN seed region to form a heterojunction 1707 that is not parallel to the main surface of the original growth substrate 1701. The heterojunction 1707 can be formed on a stable crystallographically equivalent facet of the GaN seed region, for example on a {1-101} crystallographically equivalent facet. In order to relax towards the relaxed InGaN in-plane a lattice parameter a2 in the region 1705 between the GaN seed surfaces, the InGaN material is at least partially grown laterally outward. A plane 1708b, parallel to the major surface of the original growth substrate and bisecting the GaN seed material, is characterized by different in-plane a lattice parameters at different locations along the plane. In particular, at a center point within the GaN seed region 1702a, it is characterized by a lattice parameter a1, and at a center point 1705 between the GaN seed regions 1702a, the lattice parameter is approximately a2. In the GaN region between these two center points, the in-plane a lattice parameter is greater than a1 and less than a2, because a2>a1. In a plan view (not shown), the variation in the GaN in-plane a lattice parameter within plane 1708b is characterized by a two-dimensional mask pattern (see FIG. 1 ) that has been applied to the GaN seed layer material. Figure 5 and 6 ).

[0095] like Figure 17A and 17B As shown, plane 1708b intersects the edge of seed region 1702a to locate heterojunction 1709b at the interface between InGaN region 1704 and the seed region. The heterojunction is coplanar with the first crystal plane of the seed region. Any plane, such as plane 1708b, which is parallel to the main growth surface and intersects the InGaN region (such as 1708c) and seed region 1702a, intersects the edge of seed region 1702a to locate heterojunction 1709c at the interface between the InGaN region and the seed region, which interface is coplanar with the second crystal plane of the seed region. Figure 17A and 17B As shown, the first and second crystal planes are the same. The first and second crystal planes may be crystallographically equivalent crystal planes.

[0096] The InGaN material coalesces on the mask layer 1703 to form a relaxed InGaN layer 1704 having a flat surface 1705c. A plane 1708a within the InGaN layer 1704 that is parallel to the major surface of the original growth substrate and is located near the surface 1705c is characterized by an in-plane a lattice parameter a2 of the InGaN plane. At the center point 1705 between the GaN seed regions, the InGaN lattice parameter is a2, and at the center point within the GaN seed regions, the in-plane a lattice parameter is slightly less than a2. In a plan view (not shown), the variation of the in-plane a lattice parameter within the plane 1708b is characterized by a two-dimensional mask pattern applied to the seed layer material (see Figure 5 and 6 ). The variation of the in-plane a lattice parameter can be detected by measurement techniques such as XRD and RSM and can be resolved on the sub-micron scale. The midpoint along the plane 1708b within the seed region 1702a is denoted as 1708c, while the midpoint between the seed regions 1702a is denoted as 1708d.

[0097] The GaN seed regions 1702a can have in-plane dimensions, such as less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask material 1703 can be, for example, from 0.01 μm to 1 μm. Figure 17B A detailed cross-sectional view of a structure obtained by the process flow in Figures 16A to 16F is provided. The structure is similar to the structure of Figure 17A , and similar elements are identified by the same numerical manner. However, in the structure of Figure 17B , there is no planar starting GaN (or AlN) seed layer 1702. Instead, the GaN (or AlN) seed material directly nucleates on the substrate 1701 within the openings between the mask regions 1703. The substrate can be sapphire, GaN, AlN, silicon, etc.

[0098] A group-III nitride semiconductor structure can comprise (a) seed regions comprising In x Ga 1-x N (0 ≤ x <1) and a wurtzite group-III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group-III nitride structure and intersecting the seed regions; wherein, the intersection of the first plane with the first edge of the seed regions locates an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; the Inx Ga 1-x N / In y Ga 1-y N hetero - junction is coplanar with the first crystal plane of the seed region; (c) Any second plane parallel to the (0001) plane of the wurtzite group - III nitride crystal structure and intersecting the second edge of the seed region locates a group - III nitride hetero - junction, wherein the group - III nitride hetero - junction is coplanar with the second crystal plane of the seed region; and (d) Covering the (0001) InGaN region of the seed region, wherein the (0001) InGaN region is characterized by an in - plane a lattice parameter greater than such that each of the first crystal plane and the second crystal plane is crystallographically equivalent.

[0099] The first parallel plane can intersect two facets of the seed region. The facets of the seed region are parallel to the crystal planes of the seed region, such as the crystal planes of the wurtzite crystal structure. The facets of the seed region can be crystallographically equivalent facets. The intersection points of the first parallel plane and the facets of the seed region locate hetero - junctions, such as In x Ga 1-x N / In y Ga 1-y N, where 0 ≤ x < 1, 0 < y ≤ 1, and y > x.

[0100] Any second plane parallel to the (0001) plane of the wurtzite group - III nitride crystal structure and intersecting the seed region locates a group - III nitride hetero - junction. The second plane can intersect the same facets as the first plane. The second plane can intersect the facets of the seed region that are coplanar with the crystal planes of the seed region. Each of the crystallographic planes can be crystallographically equivalent planes. Each of the seed regions is characterized by facets parallel to the crystal planes of the seed region, such as the crystal planes of the wurtzite crystal structure. Each of the crystal planes can be crystallographically equivalent planes. Each of the crystal planes can be crystallographically equivalent to the {10 - 11} plane. Each of the crystal planes can be crystallographically equivalent to the {1 - 100} plane. Each of the crystal planes can be crystallographically equivalent to the {11 - 20} plane. Each of the crystal planes can be the (1 - 100) plane or the (11 - 20) plane.

[0101] The InGaN region is located between the seed regions. The InGaN region, or at least a portion of the InGaN region between the seed regions, can be a partially relaxed InGaN region. The InGaN region can contain more than one InGaN layer, where each of the InGaN layers has a different elemental composition. The (0001) InGaN region can cover the seed region. The (0001) InGaN region can be a fully relaxed InGaN region and can have a greater than (such as from to )’s in-plane lattice parameter.

[0102] The seed region can have 2 or more facets, such as 2, 3, 4, 5, or 6 facets. The seed region can have 3 or 6 facets. The seed region can have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. The seed region can have a triangular base or a hexagonal base.

[0103] Each seed region may comprise, for example, GaN, and may have, for example, approximately Each seed region may contain GaN and In x Ga 1-x N / In y Ga 1-y Each of the N heterojunction and the Group III nitride heterojunction is a GaN-InGaN heterojunction.

[0104] 18 to 20 illustrate various aspects of the present invention. Figure 18A 、 18B 18C shows a schematic plan view of a so-called "v-pit" structure that can form in the growth of group III nitrides on the basal plane. In particular, for group III nitride materials grown at low temperatures, such as GaN grown at temperatures less than 800°C using MOCVD, the adatom dynamics make the semiconductor material less inclined to fill the nearby dislocation cores, resulting in the formation of a pit at the center from the stable (10-11) plane with the dislocation core. As growth continues under low temperature conditions, the pit becomes larger ( Figure 18B ) and collide( Figure 18C As the pits become larger, the total surface area of ​​the exposed (10-11) facets becomes comparable to or even larger than that of the exposed (0001) surface. The presence of this large surface area of ​​(10-11) facets, where each facet is crystallographically equivalent, provides an opportunity to form high-quality, relaxed InGaN (e.g., GaN) on the (10-11) seed surface, as contemplated by the present invention.

[0105] For example, Figure 19 As shown, GaN can be nucleated at low temperatures onto a suitable substrate, such as GaN, sapphire, Si, SiC, AlN, etc. Once a reasonably high quality GaN epitaxial film is obtained, for example by growing the GaN epitaxial film at an elevated temperature (e.g., greater than 900°C), the growth conditions can be changed again so that v-pits are formed, for example by growing the GaN at a temperature below 800°C. The growth can then be stopped, the GaN structure removed from the MOCVD reactor, and a suitable growth mask layer, such as SiO2 or SiN, can be selectively deposited on the (0001) surface rather than on the (10-11) surface. xdielectric layer. This can be achieved in various ways, such as by using high angle sputtering or deposition, or by selectively depositing a photoresist into the v-pits, followed by, for example, deposition and lift-off. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. InGaN can then be selectively grown on the exposed GaN seed region material on the (10-11) facet, optionally preceded by deposition of a thin GaN layer. The InN mole fraction can be targeted so as to induce large strain and therefore relaxation at increasing InGaN layer thickness. The InGaN growth can be allowed to continue to grow outward on the masked areas and coalesce, providing planar, high quality, relaxed InGaN (0001) regions that can be used as templates for device fabrication, as described in the present disclosure. The InGaN layer can be grown at temperatures higher than typical temperatures for InGaN / GaN growth, such as at temperatures greater than 900°C, which is possible because the relaxed InGaN material is more easily doped with In than the InGaN pseudomorph. Increased growth temperature allows filling of v-pit defects and provides coalesced planar films. Control of the morphology and composition uniformity of the relaxed InGaN growth can be facilitated by growing a multilayer structure rather than by using a bulk InGaN layer. For example, a 25% bulk InGaN layer can consist of 3nm of GaN and 1nm of InN, or 2nm of GaN and 2nm of In 0.5 Ga 0.5 The thickness of each layer can be, for example, 0.5 nm to 100 nm, for example 1 nm to 30 nm. Many periods of this multilayer structure can be used, for example 2 to 10 layers, 2 to 100 layers or more than 100 layers.

[0106] In another example, the masking step can be eliminated and the entire process can be done in situ in the growth chamber. Figure 20As shown, GaN can be nucleated onto a suitable substrate, such as GaN, sapphire, Si, AlN, etc. After achieving a reasonably high quality GaN epitaxial film, for example by growing at elevated temperatures (e.g., >900°C), the growth conditions can be changed again so that v-pits are formed, for example by growing GaN at temperatures below 800°C. The v-pits can be grown outward so that the exposed surface area of ​​the {10-11} equivalent facets is greater than the exposed surface area of ​​the (0001) GaN. Preferably, the exposed surface area of ​​the (10-11) facets is more than twice the exposed surface area of ​​the (0001) GaN, more preferably more than ten times the exposed surface area of ​​the (0001) GaN. InGaN can then be selectively grown on the (10-11) facets as seed regions. The InN composition can be targeted so as to induce large strain and therefore relaxation at increased InGaN layer thickness. The InGaN growth may be allowed to continue outward growth and coalesce, providing a planar, high-quality, relaxed InGaN (0001) region that may be used as a template for device fabrication, as described in this disclosure.

[0107] Because the (0001) growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing the InGaN to relax and become the dominant growth surface as the film thickness increases. It is useful to grow InGaN layers at temperatures higher than the typical temperatures for InGaN / GaN growth. This is possible because the relaxed InGaN material can be more easily incorporated into GaN than the InGaN pseudomorph. The increased growth temperature allows the v-pit defects to fill to provide a coalesced planar film. Control of the morphology and composition uniformity of the relaxed InGaN growth can be facilitated by growing a multilayer structure rather than by using a bulk InGaN layer. For example, a 25% bulk InGaN layer can consist of 3nm of GaN and 1nm of InN, or 2nm of GaN and 2nm of In 0.5 Ga 0.5 The thickness of each layer can be, for example, 0.5 nm to 100 nm, for example 1 nm to 30 nm. Many periods of this multilayer structure can be used, for example 2 to 10 layers, 2 to 100 layers or more than 100 layers.

[0108] For example, a c-plane (0001) sapphire substrate can be loaded into an MOCVD reactor capable of supplying at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be provided, followed by higher-temperature GaN growth, which can include the formation of three-dimensional islands before coalescing into a two-dimensional (0001) GaN film. This three-dimensional to two-dimensional transition helps to redirect threading dislocations laterally and helps to reduce the total line dislocation density at the growth surface, which can be reduced to less than 1E9 cm -2Finally, 1E8 cm can be achieved in the planar GaN layer. -2 Next, the growth temperature can be lowered (e.g., to less than 800°C) to form a v-pit structure at the dislocation core, characterized by tilted (10-11) planes. These planes can form an angle of approximately 63 degrees relative to the (0001) growth surface. The thickness of the low-temperature layer controls the v-pit height and increases through growth so that the total surface area of ​​the exposed {10-11} facets is greater than the surface area of ​​the (0001), as shown in Table 3 for this particular example.

[0109] Table 3. Examples of growth structures.

[0110]

[0111] For example, at a dislocation density of 1E8 cm -2 In this case, the target v-pit height can be 0.14 μm or greater.

[0112] After the target surface area ratio between the (10-11) and (0001) materials can be achieved, TMI is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed region and induce strain relaxation. The InGaN layers can be periodically alternating with the GaN layers. For example, each InGaN layer can be 0.5nm to 100nm thick, such as 1nm to 30nm thick, and can be sandwiched between GaN layers of similar thickness. In order to induce strain relaxation, the average composition of the strain relaxation layer should be quite high, for example, the average InN content can be greater than 5%. After or before starting strain relaxation, the growth temperature can be increased to help flatten the growth and obtain a flat, uniform, relaxed (0001) InGaN layer for device fabrication.

[0113] It is important to note that while the preceding discussion has focused on GaN seed regions, InGaN (or AlGaN) seed regions can also be utilized, as long as the material is pseudomorphic to any underlying GaN layers (e.g., GaN nucleation and / or buffer layers). The seed region is the area near the InGaN-GaN (or InGaN-InGaN) heterojunction that ultimately induces relaxation. The seed material underlying these regions is referred to as the seed material rather than the seed region.

[0114] The relaxed InGaN layers and semiconductor structures containing relaxed InGaN layers provided by the present disclosure can be used to manufacture electronic and optoelectronic devices, including InGaN-based optoelectronic devices, such as LEDs and LDs (and VCSELs). The LEDs and LDs containing relaxed InGaN layers provided by the present disclosure can be used in lighting systems and display systems. In particular, for LEDs, the device can be formed on a relaxed InGaN-based layer on a substrate. The substrate can be thinned by techniques such as grinding, lapping or etching, and can be cut by methods known in the art (such as sawing, scribing and breaking or laser scribing and breaking) to provide individual LED chips or dies. The LED chip or die size can be, for example, 250 μm 2 Up to 10mm 2 . The individual LED chips can then be attached to a suitable packaging component that provides leads for electrical contact and heat dissipation of the device. The tube die attachment can be achieved using any suitable method, such as epoxy or silicone attachment, or solder-based attachment. The electrical connection of the chip to the package can be accomplished by using bonding wires such as Au or Ag wires to connect the anode and cathode leads in the package to the corresponding contact metallization layers, i.e. electrodes, on the LED chip. In the case of a flip-chip device, electrical contact can be made through an intermediate substrate located between the LED chip and the package. The chip electrodes can be attached to the substrate carrier by means such as solder attachment or gold bump attachment. The substrate carrier can be cut and then mounted into the package by any suitable method.

[0115] The desired emission color from a packaged LED device is obtained by manufacturing and providing relaxed InGaN-based LEDs having a desired peak emission wavelength. A plurality of such LED chips, optionally having different peak emission wavelengths, may be included in separate packages, or combined together in a multi-chip package. For example, a single package may include red-emitting, green-emitting, and blue-emitting LED chips, which may be arranged in a circuit and electrically coupled to a driver circuit within or outside the package for operating the LEDs. The circuit details and drivers may be selected to allow the different color LEDs to be operated individually or together to provide a wide range of total emission characteristics, including white light emission for use in lighting applications, or as a backlight for a liquid crystal display (LCD) device (e.g., a television display, a computer monitor, a mobile phone display, a wearable display device, etc.).

[0116] One or more LED chips can be combined with a luminescent down-conversion material to provide a desired emission spectrum. Such a luminescent down-conversion material can include a phosphor, semiconductor nanoparticles (e.g., quantum dots), or a perovskite material. Multiple luminescent down-conversion materials can be combined in a single package. The LED chip emission wavelength can be selected to excite the luminescent down-conversion material so that the emission from the package is a combination of direct emission from the LED chip and emission from the luminescent down-conversion material, or the emission can be primarily only emission from the luminescent down-conversion material, wherein the LED chip light is completely absorbed by the luminescent down-conversion material or is blocked or filtered without leaving the package. Packaged LEDs using luminescent down-conversion materials can be used to generate white light, which can be used for lighting applications. Such devices can be electrically coupled to a driver circuit, powered by an external power source such as a power supply or battery power supply, thermally coupled to a radiator, and optically coupled to various optical devices or lenses to provide a lighting device such as an LED lamp or LED lamp.

[0117] The present invention can be used to manufacture LED chips with smaller sizes. In particular, it is possible to manufacture LED chips with a size of 1 μm. 2 to 50μm 2 Devices of this type, so-called "micro-LEDs". For micro-LEDs, conventional cutting techniques are less suitable, and therefore other ways of singulating the devices are often used. For example, cutting can be achieved by forming LEDs of the desired size on a substrate, and then bonding the top surface of the LEDs to a carrier (e.g. a blue ribbon or substrate carrier), and then removing the substrate. The individual devices can then be picked up and placed into a packaging component or onto a backplane for a micro-LED-based display. As is known in the art, advanced die processing techniques can be used to process micro-LED devices. Specifically, red-emitting, green-emitting and blue-emitting LEDs according to the present invention can be formed as micro-LEDs and arranged to provide micro-LED displays and incorporated into systems such as televisions, computer monitors, tablets, mobile phones, wearable devices, and the like.

[0118] The LDs provided in the present disclosure incorporating relaxed InGaN layers can also be incorporated into various systems. The LD packages are similar to the LED packages described herein, except that a means is provided for thermally managing the higher power density in the LD device and a means is provided for optically accessing the laser facets. LDs of multiple emission colors can be provided in separate packages or combined into a single package. The LDs can be coupled to luminescent down-conversion materials to provide the desired emission spectrum. LDs are useful in applications requiring very high optical density, such as in automotive front lighting systems or projection displays, which may include light modulating devices such as grating optics, micromirror devices, or LCD modulators.

[0119] Figure 11 and 12 Examples of lighting and display systems are shown.

[0120] Aspects of the Invention

[0121] The present invention is further defined by the following aspects.

[0122] Aspect 1. A Group III nitride semiconductor structure comprising an InGaN region, wherein the InGaN region comprises a relaxed (0001) InGaN region; and the relaxed (0001) InGaN region has an in-plane a lattice parameter characterized by periodicity in at least one direction.

[0123] Aspect 2. The semiconductor structure of aspect 1, wherein the relaxed InGaN region is characterized by a c-plane growth orientation.

[0124] Aspect 3. A semiconductor structure according to any one of aspects 1 to 2, wherein the relaxed InGaN region is characterized by being greater than The average in-plane lattice parameter of .

[0125] Aspect 4. The semiconductor structure of any one of aspects 1 to 3, wherein the relaxed InGaN region has a thickness of less than 3 μm.

[0126] Aspect 5. The semiconductor structure according to any one of aspects 1 to 4, wherein the relaxed InGaN region has a thickness of 20 nm to 1 μm.

[0127] Aspect 6. The semiconductor structure of any one of aspects 1 to 5, wherein the relaxed InGaN region has a relative humidity less than 5E9 cm 2 defect density.

[0128] Aspect 7. The semiconductor structure of any one of aspects 1 to 6, wherein the relaxed InGaN region comprises an InGaN-GaN superlattice.

[0129] Aspect 8. The semiconductor structure of any one of aspects 1 to 7, further comprising: a plurality of mask regions underlying the first portion of the relaxed InGaN region; and a plurality of non-mask regions underlying the second portion of the relaxed InGaN region.

[0130] Aspect 9. The semiconductor structure of aspect 8, wherein each of the plurality of mask regions comprises a dielectric material.

[0131] Aspect 10. The semiconductor structure of aspect 9, wherein the dielectric material comprises silicon nitride, silicon oxide, or aluminum oxide.

[0132] Aspect 11. The semiconductor structure of any one of aspects 8 to 10, wherein each of the plurality of mask regions has a thickness of 20 nm to 2 μm.

[0133] Aspect 12. The semiconductor structure of any one of aspects 8 to 10, wherein each of the plurality of mask regions has a thickness of less than 2 μm.

[0134] Aspect 13. The semiconductor structure of any one of aspects 8 to 12, wherein a maximum in-plane dimension of each of the plurality of non-mask regions is less than 1 μm.

[0135] Aspect 14. The semiconductor structure of any one of aspects 8 to 13, further comprising a seed region underlying each of the plurality of mask regions.

[0136] Aspect 15. The semiconductor structure of aspect 14, wherein the seed region comprises GaN, AlN, or AlGaN.

[0137] Aspect 16. The semiconductor structure according to any one of aspects 14 to 15, wherein the seed region has a thickness of 20 nm to 2 μm.

[0138] Aspect 17. The semiconductor structure of any one of aspects 14 to 16, wherein the seed region has a thickness of less than 2 μm.

[0139] Aspect 18. A semiconductor structure according to any one of Aspects 14 to 17, wherein the seed region comprises a horizontal interface and a seed interface; the horizontal interface is substantially coplanar with the (0001) InGaN crystal plane; and the seed interface comprises a planar seed portion that is not parallel to the horizontal interface.

[0140] Aspect 19. The semiconductor structure of aspect 18, wherein the planar seed portion comprises an a-plane, an m-plane, or a plane between the a-plane and the m-plane.

[0141] Aspect 20. The semiconductor structure of aspect 19, wherein the horizontal interface is characterized by a c-plane orientation; and the planar seed portion is non-coplanar with the horizontal interface.

[0142] Aspect 21. The semiconductor structure of any one of aspects 19 to 20, wherein the planar seed portion comprises a heterojunction.

[0143] Aspect 22. The semiconductor structure of aspect 21, wherein the heterojunction is a GaN-InGaN heterojunction.

[0144] Aspect 23. A semiconductor structure according to Aspect 22, wherein the seed region comprises GaN; the planar seed portion comprises a GaN / InGaN heterojunction; and the GaN / InGaN heterojunction is substantially parallel to the GaN (1-100) crystal plane, the GaN (11-20) crystal plane, or a crystal plane between the GaN (1-100) crystal plane and the GaN (11-20) crystal plane.

[0145] Aspect 24. The semiconductor structure of any one of aspects 8 to 23, wherein the plurality of non-mask regions comprise InGaN.

[0146] Aspect 25. The semiconductor structure of any one of aspects 8 to 24, wherein the plurality of non-mask regions are characterized by a pattern.

[0147] Aspect 26. The semiconductor structure of any one of aspects 8 to 25, wherein the plurality of non-mask regions are characterized by non-mask region periodicity in at least one dimension.

[0148] Aspect 27. The semiconductor structure of aspect 26, wherein the periodicity of the in-plane a-lattice parameter of the relaxed InGaN region corresponds to the non-mask region periodicity.

[0149] Aspect 28. The semiconductor structure of any one of aspects 8 to 27, wherein the plurality of non-mask regions are characterized by an array of shapes.

[0150] Aspect 29. The semiconductor structure of aspect 28, wherein the shape comprises an edge oriented relative to a crystal plane of InGaN.

[0151] Aspect 30. The semiconductor structure of aspect 29, wherein the edge is misaligned by + / - 1° relative to the InGaNa plane or the InGaNm plane.

[0152] Aspect 31. The semiconductor structure according to any one of aspects 29 to 30, wherein the edge is oriented parallel to a (1-100) InGaN crystal plane.

[0153] Aspect 32. The semiconductor structure according to any one of aspects 29 to 31, wherein the edge is oriented parallel to the (11-20) InGaN crystal plane.

[0154] Aspect 33. The semiconductor structure of any one of aspects 29 to 31, wherein the edge orientation is in a direction that is non-parallel to a (1-100) InGaN crystal plane and non-parallel to a (11-20) InGaN crystal plane.

[0155] Aspect 34. The semiconductor structure of any one of aspects 8 to 33, further comprising a substrate underlying each of the plurality of non-mask regions and each of the plurality of mask regions.

[0156] Aspect 35. The semiconductor structure of aspect 34, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[0157] Aspect 36. The semiconductor structure of any one of aspects 8 to 35, further comprising: a substrate underlying each of the plurality of unmasked regions; and a cavity within the unmasked region and covering a portion of the substrate.

[0158] Aspect 37. The semiconductor structure of any one of aspects 1 to 36, wherein the III-V semiconductor structure has an area defined by a width and a length; and the area is greater than 0.1 mm 2 .

[0159] Aspect 38. The semiconductor structure of aspect 37, wherein the periodicity is characterized by a period that is at least 10 times smaller than the width and / or at least 10 times smaller than the length.

[0160] Aspect 39. The semiconductor structure of any one of aspects 37 to 38, wherein the number of non-masked regions within the area is greater than 10.

[0161] Aspect 40. The semiconductor structure of any one of Aspects 1 to 39, wherein within a period associated with the periodicity, the in-plane a lattice parameter varies between a minimum value and a maximum value that are less than 1% around an average in-plane a lattice parameter.

[0162] Aspect 41. A semiconductor structure according to any one of Aspects 1 to 40, further comprising a plurality of seed regions below the first portion of the relaxed InGaN region, wherein each of the plurality of seed regions comprises a plurality of planar seed portions; and each of the plurality of planar seed portions is not a coplanar (0001) InGaN crystal plane.

[0163] Aspect 42. The semiconductor structure of aspect 41, wherein the planar seed portion forms at least a portion of a pyramidal shape having a hexagonal base.

[0164] Aspect 43. The semiconductor structure of any one of aspects 41 to 42, wherein each of the plurality of planar seed portions is characterized by a (1-101) crystal plane.

[0165] Aspect 44. The semiconductor structure of any one of aspects 41 to 43, further comprising a plurality of mask regions beneath the second portion of the relaxed InGaN region, wherein each of the plurality of seed portions extends over the plurality of mask regions.

[0166] Aspect 45. The semiconductor structure of aspect 44, further comprising a seed layer located beneath each of the plurality of mask regions and beneath each of the plurality of seed regions.

[0167] Aspect 46. The semiconductor structure of aspect 45, wherein the seed layer and each of the plurality of seed regions are contiguous.

[0168] Aspect 47. The semiconductor structure of aspect 46, further comprising a substrate below the seed layer.

[0169] Aspect 48. The semiconductor structure of any one of aspects 44 to 47, further comprising a substrate beneath each of the plurality of seed regions and beneath each of the plurality of mask regions.

[0170] Aspect 49. A semiconductor structure according to any one of aspects 1 to 48, wherein in a plane parallel to the InGaN c-plane and passing through the relaxed InGaN region, the in-plane a-plane lattice parameter is greater than

[0171] Aspect 50. A semiconductor structure according to any one of Aspects 1 to 49, further comprising a plurality of non-mask regions underlying a portion of the relaxed InGaN region, wherein the periodicity of the lattice parameter of the relaxed InGaN region corresponds to the periodicity of the plurality of non-mask regions.

[0172] Aspect 51. A semiconductor structure according to any one of Aspects 1 to 50, further comprising a plurality of seed regions beneath a portion of the relaxed InGaN region, wherein each of the plurality of seed regions is characterized by an in-plane a lattice parameter a1; the relaxed InGaN region is characterized by an in-plane a lattice parameter a2; and a2 is greater than a1.

[0173] Aspect 52. A semiconductor structure according to any one of Aspects 1 to 51, further comprising a plurality of seed regions beneath a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is not parallel to the growth plane of the seed region and the relaxed InGaN region.

[0174] Aspect 53. A semiconductor structure according to any one of Aspects 1 to 52, further comprising a plurality of seed regions beneath a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is perpendicular to the c-plane of the relaxed InGaN region.

[0175] Aspect 54. A semiconductor structure according to any one of Aspects 1 to 53, further comprising a plurality of seed regions below a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is parallel to the InGaNa plane, parallel to the InGaN m-plane, or at an angle between the InGaNa plane and the InGaN m-plane.

[0176] Aspect 55. A semiconductor structure according to any one of Aspects 1 to 54, further comprising a plurality of seed regions beneath a portion of the relaxed InGaN region, wherein the plurality of seed regions are characterized by periodicity in at least one direction; and the periodicity of the in-plane a lattice parameter of the relaxed InGaN region corresponds to the periodicity of the plurality of seed regions.

[0177] Aspect 56. The semiconductor structure of aspect 55, wherein the periodicity of the in-plane a-lattice parameter of the relaxed InGaN region is the same as the periodicity of the plurality of seed regions.

[0178] Aspect 57. The semiconductor structure according to any one of aspects 1 to 56, further comprising an n-doped semiconductor layer, an active semiconductor layer, and a p-doped semiconductor layer covering the relaxed InGaN region.

[0179] Aspect 58. The semiconductor structure according to any one of aspects 1 to 57, further comprising a plurality of semiconductor epitaxial layers covering the relaxed InGaN region.

[0180] Aspect 59. A Group III nitride semiconductor structure comprising: an InGaN region, wherein the InGaN region comprises a relaxed (0001) InGaN region; a plurality of mask regions below a first portion of the relaxed InGaN region; a plurality of non-mask regions below a second portion of the relaxed InGaN region; and a seed region located below each of the mask regions.

[0181] Aspect 60. The semiconductor structure of aspect 59, wherein the seed regions comprise GaN; and the non-mask regions between the seed regions and beneath the second portion of the InGaN region comprise InGaN.

[0182] Aspect 61. A semiconductor structure according to any one of Aspects 59 to 60, wherein, in a plane parallel to the c-plane of the relaxed InGaN region and bisecting the seed region, the in-plane a lattice parameter within the seed region is less than the in-plane a lattice parameter between the seed region and below the second portion of the InGaN region.

[0183] Aspect 62. A semiconductor device comprising the III-V semiconductor structure according to any one of aspects 1 to 61.

[0184] Aspect 63. The semiconductor device of aspect 62, wherein the semiconductor device comprises an optoelectronic device.

[0185] Aspect 64. The semiconductor device of aspect 62, wherein the semiconductor device comprises a light emitting diode or a laser diode.

[0186] Aspect 65. The semiconductor device of aspect 64, further comprising a peak emission wavelength.

[0187] Aspect 66. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 440 nm and 460 nm, and the in-plane α lattice parameter is between and between.

[0188] Aspect 67. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 520 nm and 540 nm, and the in-plane α lattice parameter is between and between.

[0189] Aspect 68. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 580 nm and 600 nm, and the in-plane α lattice parameter is between and between.

[0190] Aspect 69. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 620 and 640 nm, and the in-plane a lattice parameter is between 3.282 and 3.296 Å.

[0191] Aspect 70. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 690 and 710 nm, and the in-plane α lattice parameter is between and between.

[0192] Aspect 71. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 840 nm and 870 nm, and the in-plane α lattice parameter is between and between.

[0193] Aspect 72. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 940 nm and 980 nm, and the in-plane α lattice parameter is between and between.

[0194] Aspect 73. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 1300 nm and 1350 nm, and the in-plane α lattice parameter is between and between.

[0195] Aspect 74. A lighting system comprising the semiconductor device according to any one of aspects 62 to 73.

[0196] Aspect 75. A display system comprising the semiconductor device according to any one of aspects 62 to 73.

[0197] Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the claims are not to be limited to the details given herein, but may be modified within the scope and equivalents thereof.

Claims

1. A Group III nitride semiconductor structure comprising: (a) a plurality of seed regions, wherein: Each of the seed regions contains In x Ga 1-x N(0≤x<1); Each of the seed regions has a wurtzite Group III nitride crystal structure; Each of the seed regions has a pyramidal shape having a hexagonal base with six triangular facets; and Each of said facets is characterized as being crystallographically equivalent; and (b) an agglomerated relaxed (0001) InGaN region overlying the seed region, wherein the agglomerated relaxed (0001) InGaN region is characterized by being greater than The in-plane lattice parameter a.

2. The group-III nitride semiconductor structure according to claim 1, wherein the relaxed (0001) InGaN region comprises the wurtzite group-III nitride crystal structure, and the wurtzite group-III nitride crystal structure comprises In y Ga 1-y N, where 0 < y ≤ 1 and y > x. 3 . The III-nitride semiconductor structure of claim 1 , wherein each of the facets is a crystallographically equivalent {10-11} plane. 4 . The III-nitride semiconductor structure according to claim 1 , comprising partially relaxed InGaN covering the plurality of seed regions and beneath the relaxed (0001) InGaN region. 5 . The III-nitride semiconductor structure of claim 4 , wherein the partially relaxed InGaN region comprises more than one InGaN layer, wherein each InGaN layer has a different elemental content.

6. The III-nitride semiconductor structure according to any one of claims 1 to 5, wherein each of the seed regions comprises GaN and has a thickness of approximately The in-plane lattice parameter a.

7. The III-nitride semiconductor structure according to any one of claims 1 and 6, wherein the (0001) InGaN region has to The in-plane lattice parameter a.

8. The III-nitride semiconductor structure according to any one of claims 1 to 7, wherein Each seed region contains GaN, and In x Ga 1-x N / In y Ga 1-y Each of the N heterojunction and the Group III nitride heterojunction is a GaN-InGaN heterojunction.

9. The III-nitride semiconductor structure according to any one of claims 1 to 8, further comprising a substrate and a mask region, wherein the seed region covers a first portion of the substrate and the mask region covers a second portion of the substrate, or the mask region covers the seed region.

10. The III-nitride semiconductor structure of claim 9, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride. 11 . A semiconductor device comprising the III-nitride semiconductor structure according to claim 1 .

12. The semiconductor device according to claim 11, wherein the semiconductor device comprises: an n-type III-nitride layer covering the (0001) InGaN region; a p-type Group III nitride layer covering the (0001) InGaN region; an InGaN-containing active region between the n-type Group III nitride layer and the p-type Group III nitride layer; a first electrical contact metallization layer in electrical contact with the p-type Group III-nitride layer; and A second electrical contact metallization layer is in electrical contact with the n-type Group III-nitride layer. 13 . A lighting system or a display system comprising the semiconductor device according to claim 11 .

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