Radio astronomical wide temperature range adaptive beamforming method

Abstract

The invention discloses a radio astronomy wide temperature range adaptive beamforming method, which comprises the following steps of: 1) setting a phase temperature coefficient (ai, bi) and an amplitude temperature coefficient (ci, di) for each frequency point fi, and monitoring the environment temperature in real time; 2) generating a shared real-time temperature T real-time according to the temperature information, establishing a phase error model delta phi = ai * T real-time + bi and an amplitude error model delta A = ci * T real-time + di for each frequency point fi, and calculating phase and amplitude errors of the corresponding frequency point fi; wherein all frequency points of each channel share the real-time temperature T real-time; 3) performing DDC down-conversion on the radio frequency signal of each channel of the PAF to intermediate frequency, and converting the intermediate frequency into frequency domain data; then correcting the amplitude and phase of each frequency point in the frequency domain data; and 4) performing multi-beam synchronous output on the correction data. According to the invention, the detection requirements of a telescope on a transient celestial body, an extension source and a fine spectral line can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio astronomy observation, and relates to an ultra-wide bandwidth temperature-domain adaptive beamforming method applicable to the 500MHz to 2GHz frequency band. The method can realize multi-beamforming observation and high-precision signal processing, and is applicable to the phased array feed (PAF) system of large-aperture radio telescopes. Background Art

[0002] In radio astronomy observations, phased array feeds (PAFs) achieve multi-beam parallel reception through digital beamforming technology, which is a key means of improving the telescope's sky coverage efficiency. However, existing PAF terminals have the following technical bottlenecks:

[0003] 1. Limited frequency band coverage and resolution: Traditional feed systems have a narrow bandwidth (usually <1 GHz), and the beamforming accuracy is limited by the amplitude and phase errors of the analog circuits. This makes it difficult to meet the high-resolution observation requirements of ultra-wideband signals such as neutral hydrogen (HI) spectral lines and fast radio bursts (FRBs).

[0004] 2. Insufficient environmental adaptability: The temperature difference between day and night at radio telescope sites (such as the karst mountainous area of ​​Guizhou where FAST is located) can reach over 30°C. Temperature drift in traditional hardware circuits (such as digital processing modules, ADCs, and fiber optic interfaces) can lead to beam pointing deviations. For example, temperature changes lead to the accumulation of amplitude and phase errors between the RF front end and the digital processing unit. Traditional correction methods can achieve a phase error of over 5° within a temperature range of -40°C to +60°C, seriously affecting beam pointing accuracy (typical deviation > 0.5 arc minutes), thereby affecting weak signal detection.

[0005] 3. Resource redundancy and low processing efficiency: For example, when faced with massive amounts of data from 16,384 frequency points and 30 channels, traditional FPGA architectures struggle to achieve real-time parallel processing, resulting in hardware resource utilization of less than 50% and power consumption exceeding 200W.

[0006] In response to the above problems, this field urgently needs a beamforming terminal with wide-band coverage, wide-temperature range adaptability and efficient real-time processing functions. Summary of the Invention

[0007] The present invention aims to provide a wide-temperature adaptive beamforming method for radio astronomy, addressing the existing issues of insufficient frequency band coverage, poor environmental adaptability, and low data processing efficiency. This method enables high-precision multi-beam parallel observations in the 500 MHz to 2 GHz frequency band, meeting the detection needs of transient objects, extended sources, and fine spectral lines for large-aperture telescopes such as the FAST-30 unit phased array antenna.

[0008] The technical solution of the present invention is:

[0009] A radio astronomy wide temperature range adaptive beamforming method, comprising the following steps:

[0010] 1) The three-temperature calibration module sets the phase temperature coefficient (ai, bi) and amplitude temperature coefficient (ci, di) for each frequency point fi and sends them to the temperature adaptive correction module; the temperature sensor module monitors the ambient temperature in real time and sends it to the temperature adaptive correction module; where ai represents the temperature sensitivity coefficient of the phase of frequency point fi, reflecting the slope of the phase error of frequency point fi with temperature; bi represents the temperature offset coefficient, reflecting the inherent phase error of frequency point fi at the reference temperature;

[0011] ci represents the temperature attenuation coefficient of the frequency point fi amplitude, reflecting the slope of the frequency point fi amplitude error changing with temperature; di represents the temperature reference coefficient, reflecting the inherent amplitude error of the frequency point fi at the reference temperature;

[0012] 2) The temperature adaptive correction module generates a shared real-time temperature T according to the received temperature information 实时 ; and establish a phase error model Δφ(fi,T for each frequency point fi 实时 )=a i ·T 实时 +b i and an amplitude error model ΔA(fi,T 实时 )=c i

[0013] ·T 实时 +d i Then, the phase error Δφ and amplitude error ΔA of the corresponding frequency point fi are calculated based on the phase error model and amplitude error model of each frequency point fi; wherein all frequency points of each channel share the real-time temperature T real-time;

[0014] 3) The digital signal processing module performs DDC down-conversion on the RF signal of each channel of the phased array feed PAF to the intermediate frequency, and then converts the intermediate frequency signal into frequency domain data; then the amplitude and phase of each frequency point in the frequency domain data are corrected; wherein, the corrected phase φ 校正 =φ 实测 -Δφ, the corrected amplitude A 校正 =A 实测 10 -ΔA / 20 ,φ 实测 is the amplitude of the frequency point, A 实测 is the phase of the frequency point, Δφ is the phase error, and ΔA is the amplitude error;

[0015] 4) The multi-beam forming module performs multi-beam synchronous output on the correction data output by the digital signal processing module, and each beam is independently configured with a pointing angle.

[0016] Furthermore, the multi-beam forming module is formed by the formula Calculate and generate the output signal of each beam and output all beams synchronously; where N is the total number of channels, y ij represents the output signal of the jth beam at the i-th frequency point, x ik represents the input signal of the i-th frequency point on the k-th channel; w ijk It represents the shaping weight of the kth channel on the i-th frequency point to the j-th beam.

[0017] Furthermore, the pointing angle is -90° to +90°, and the pointing angles of adjacent beams differ by 5°.

[0018] Furthermore, the digital signal processing module uses four Xilinx RFSOC chips connected in parallel, and each Xilinx RFSOC chip processes eight input signals.

[0019] Furthermore, MEMS temperature sensors are deployed at the ADC input interface, FPGA chip, and 100GbE output interface of each Xilinx RFSOC chip, and the collected temperatures are weighted averaged to obtain the real-time temperature T 实时 .

[0020] The massive data generated by multi-beam observation is transmitted to the back-end storage device through the optical fiber interface module.

[0021] The terminal of the present invention adopts a parallel RFSOC-level FPGA architecture, which mainly includes a digital signal processing module, a temperature adaptive correction module, a multi-beamforming engine and a high-speed interface module to realize frequency domain distributed processing and centralized synthesis of FAST-30 channel input signals.

[0022] 1) Digital signal processing module (parallel RFSOC architecture)

[0023] Hardware Configuration: Four Xilinx RFSOC chips (model ZCU47DR) are connected in parallel, with each chip processing eight input signals, representing the ADC sampling, quantization, and encoding process for the eight channels of the PAF feed. They support 16,384-point FFT operations (with a frequency resolution of 1kHz, covering the 500MHz to 2GHz frequency range). The chip integrates a 14-bit ADC (sampling rate of 2.5GSps), a DDC digital down-conversion unit, and a polyphase filter bank (PFB) for baseband mixing and channelization. The single-chip processing bandwidth is ≥1.5GHz, increasing resource utilization to over 85%. Module processing flow: A. Frequency domain preprocessing: DDC down-converts the 1-3GHz RF signal of 30-channel input to 0-2GHz intermediate frequency, and converts it into channelized frequency domain data through PFB+FFT (generating 16384 frequency points per channel); B. Temperature-sensitive frequency domain correction: Independently correct the amplitude (error ≤ 0.05dB) and phase (full temperature domain error < 0.5°) of each frequency point in the frequency domain data. The correction algorithm is the main innovation of this patent, in which the phase correction calculation is φ 校正 =φ 实测 -(a i ·T 实时 +b i ), the amplitude correction is calculated as The correction coefficient is generated in real time by the temperature adaptive module.

[0024] 2) Temperature adaptive correction module

[0025] This module primarily implements automatic calibration over a wide temperature range through channel-level independent calibration, two-dimensional temperature-frequency mapping, coefficient table compression, and low-latency pipeline processing. Channel-level independent calibration independently calibrates and stores coefficients for each of the 30 channels, resolving inconsistent temperature drift caused by hardware differences between channels (such as ADC gain deviation and PCB trace loss). Each channel within the FPGA is allocated an independent data buffer and coefficient query module, supporting parallel calibration for up to 30 channels.

[0026] A temperature-frequency two-dimensional mapping is established, that is, all frequencies of all channels in the same board share the real-time temperature T 实时, (12 sensors cover the key temperature drift positions of the board (ADC, FPGA, interface), and their weighted average temperature represents the overall temperature state of the board. The channels within the same board are in the same temperature field, and sharing is in line with physical reality), but each frequency point fi has its own unique temperature sensitivity coefficient (ai, bi phase temperature coefficient, ci, di amplitude temperature coefficient), which reflects the dispersion and loss differences of the corresponding frequency point fi at the same temperature (such as high-frequency signals are more sensitive to PCB temperature). Compress and store the coefficient table: take advantage of the continuity of the frequency points (such as the smooth change of the coefficients of adjacent frequency points), and use interpolation to reduce the storage volume (but the correction accuracy must be guaranteed). Finally, realize low-latency pipeline processing: design a pipeline architecture in the FPGA, read the coefficients in parallel and calculate the correction factors immediately after the FFT output, and ensure that the processing delay is ≤1 FFT cycle (completed within 1 / 1kHz=1μs).

[0027] The hardware features a sensor network: 12 MEMS temperature sensors (accuracy of ±0.2°C) are deployed at three typical temperature drift locations on each RFSOC board: the ADC input interface, the FPGA chip, and the 100GbE output interface (PCB). These sensors collect device temperatures (T1, T2, ..., T12) in real time over a temperature range of -40°C to +60°C. Eight MEMS temperature sensors are deployed for the ADC, two for the FPGA chip, and two for each of the 100G ports.

[0028] The algorithm uniquely designs a joint calibration model: a closed-loop correction algorithm is used to establish a two-dimensional frequency-temperature correction model. For each frequency point fi of each channel, a two-dimensional correction model for temperature drift error is established, including both phase and amplitude dimensions:

[0029] Phase error model: Δφ(fi,T 实时 )=a i ·T 实时 +b i , (Phase error in the entire temperature range <0.5°)

[0030] Amplitude error model: ΔA(fi,T 实时 )=c i ·T 实时 +d i (Amplitude error in the entire temperature range ≤ 0.1dB)

[0031] Among them: a i b represents the temperature sensitivity coefficient of the phase at frequency fi, reflecting the slope of the phase error at this frequency as the temperature changes; i It represents the temperature offset coefficient, reflecting the inherent phase error of the frequency point at the reference temperature (such as 25°C); c iThe temperature attenuation coefficient of the frequency fi amplitude reflects the slope of the frequency amplitude error as the temperature changes; d i It represents the temperature reference coefficient, reflecting the inherent amplitude error of the frequency point at the reference temperature; T 实时 The real-time temperature (generated by the fusion of the board sensor network). The joint calibration process uses offline calibration and online correction mode. Offline calibration determines the initial typical temperature drift value of each frequency point. The typical values ​​are measured at the temperature points of -40℃, 25℃, and 60℃ (covering the operating temperature range, and each temperature point is stable for more than 2 hours). In the FPGA, each channel ch j A two-dimensional coefficient table of phase and amplitude is established to store the sensitivity coefficients of phase and amplitude (i.e., the coefficients ai, bi, ci, di of each frequency point) in registers. Temperature fusion algorithm: Use weighted average correction (based on the weight of the influence of position on channel error, such as 0.5 for FPGA chip, 0.25 for ADC and output interface): w k Sensor weight, k ranges from 1 to 12. FPGA uses channel number ch j , read all the frequency points of the channel from the coefficient table (a i , b i , c i , d i ). Two-dimensional correction calculation formula:

[0032] Phase correction: φ 校正 (f i )=φ 实测 (f i )-(a i ·T 实时 +b i ),

[0033] Amplitude correction:

[0034]

[0035] The corrected frequency domain data Y (A correction (fi), φ correction (fi)) enters subsequent processing (such as spectrum analysis and signal recognition). The FPGA receives temperature sensor data in real time and dynamically loads correction coefficients based on frequency, achieving a phase error of less than 0.5° and an amplitude error of less than 0.1dB across the entire temperature range.

[0036] 3) Multi-beamforming module

[0037] The data after temperature adaptive correction by the digital signal processing module is calculated and output by 7 to 12 beamforming operations. Each beam is independently configured with a pointing angle (-90° to +90°, in 5° steps). The original deep adaptive beamforming algorithm (DDBF) is used for frequency domain weighted synthesis, with a sidelobe suppression ratio of ≥32dB. Traditional MVDR relies on accurate covariance matrix estimation, and its performance degrades significantly under low signal-to-noise ratio or dynamic interference. DDBF directly models complex environments through deep learning without the need for prior knowledge. In actual measurements, it still maintains a sidelobe suppression ratio of ≥30dB at -10dB SNR. The calculation formula of the beamforming algorithm is: Where: y ij represents the output signal of the jth beam at the i-th frequency point; x ik represents the input signal of the i-th frequency point on the k-th channel (after temperature correction); w ijk It represents the shaping weight (complex number, including amplitude and phase) of the kth channel on the jth beam at the i-th frequency point.

[0038] An interpretable end-to-end model is constructed using an optimized unfolding iterative algorithm (FISTA). Multi-beam synchronous output is achieved through a layered architecture. First, the 16,384 frequency points are divided into 128 groups of 128 points each. Each group of data is assigned to an independent computing unit of the FPGA for parallel processing. The processing operations include normalization (amplitude normalization to [0, 1], phase normalization to [-π, π]) and frequency position encoding to preserve frequency domain feature information. The FISTA optimization layer calculates the steering vector, and the initial value satisfies the preset beam pointing (- The RL submodule uses the sidelobe suppression ratio (SLL) and beam pointing error as feedback signals to adjust the weight matrix in real time through a policy network and policy gradient algorithm, using a dynamic adjustment factor to balance the priority of sidelobe suppression and pointing accuracy. The beamforming layer multiplies and accumulates the optimized complex weights with the temperature correction data point by point, synchronously generating 7 to 12 independent beam outputs to complete the beamforming operation.

[0039] The entire process achieves low-power operation on the FPGA through frequency grouping parallel processing and time division multiplexing technology. At the same time, the channel importance matrix and policy gradient visualization are used to ensure model interpretability and support post-error analysis. For weak signals with a signal-to-noise ratio of ≤5dB, the system automatically enables frequency domain coherent accumulation (period ≤100ms) and inter-beam correlation analysis, and realizes signal coherent superposition through phase compensation, which improves detection sensitivity by 13%, and ultimately achieves a sidelobe suppression ratio of ≥30dB at -10dB SNR, meeting the detection needs of large-aperture telescopes such as FAST for weak celestial signals.

[0040] 4) High-speed interface module

[0041] Data Transmission: The input side receives PAF front-end digitized signals via 30 JESD204B interfaces (12.5 Gbps / channel). The output side supports real-time transmission of 7 channels of beam data to a back-end storage unit via a fiber optic interface (100 / 25 Gbps / channel). Control commands and calibration parameters are also transmitted via an Ethernet interface.

[0042] The advantages of the present invention are as follows:

[0043] This invention proposes a wide-temperature adaptive frequency-domain beamforming terminal for the FAST 30-unit PAF. By cascading four Xilinx ZCU47DR RFSOCs, a 30-channel x 16,384-frequency real-time processing platform is constructed. It innovatively employs frequency-level temperature-sensitive correction technology (phase error <0.5° and amplitude error <0.1dB across the entire temperature range) and a deep adaptive beamforming (DDBF) algorithm (seven beams simultaneously output with a sidelobe suppression ratio ≥32dB). Combined with a low-power parallel processing architecture (total power consumption 150W), this terminal addresses the challenges of beam distortion, resource redundancy, and data overload in wide-temperature environments. Measurements show a 13% improvement in weak signal detection sensitivity, a beam pointing accuracy of 0.1 arc minute, and stable operation across the full temperature range of -40°C to +60°C. This provides a high-precision, high-efficiency core device for cutting-edge scientific missions such as the FAST Neutral Hydrogen Survey and the Detection of Cosmic Reionization. The terminal possesses significant scientific value and innovation in hardware architecture, signal processing, and system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a system block diagram of the present invention.

[0045] Figure 2 The measured curves of temperature drift and phase error and the waterfall diagram of 24-hour monitoring are shown;

[0046] (a) Measured curves of temperature drift and phase error, (b) 3D waterfall plot of 24-hour day-night temperature difference, day number, and phase.

[0047] Figure 3 are the beamforming curves of beams 1 to 7 of the measured astronomical signals;

[0048] (a) The first beamforming curve, (b) the second beamforming curve, (c) the third beamforming curve, (d) the fourth beamforming curve, (e) the fifth beamforming curve, (f) the sixth beamforming curve, and (g) the seventh beamforming curve. DETAILED DESCRIPTION

[0049] The present invention will be described in further detail below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0050] The radio astronomy wide temperature range adaptive beamforming terminal of the present invention is as follows Figure 1 As shown, it includes the following modules:

[0051] Module 7: Ethernet interface module enables remote configuration and status monitoring of the system via the external network. It uses standard Ethernet protocols to transmit control commands, calibration parameters, and complete device status data (such as real-time temperature sensor values ​​and module power consumption) for bidirectional communication with Module 9. This module achieves command transmission latency of ≤ 1μs and supports millisecond-level dynamic parameter adjustment (such as switching beam pointing strategies based on the observed target). It also supports local manual configuration and remote software control (such as issuing commands from the FAST main control system), enhancing device operational flexibility.

[0052] Module 8: Control link module (system synchronization nerve) Functional positioning: Ensure the accurate transmission of control instructions and the status of each module to achieve global synchronization of the system. Technical innovation: Based on the improved local star control network, the control instructions are distributed to modules 1 to 7, and control instruction priority management is supported (such as correction coefficient loading instructions take precedence over status query instructions). The main innovations are: a. Ultra-high parameter configuration density, a single instruction supports 30 channels × 16384 frequency parameters (conventional system single instructions mostly only support a single channel or a small number of parameters), customized instruction frame structure (including parameter compression encoding and batch write protocol); b. Extreme timeliness is achieved through UDP+ real-time scheduling algorithm: configuration time ≤1ms (far exceeding the hundreds of milliseconds delay of conventional industrial control); c. Enhanced fault tolerance mechanism is achieved: bit error rate ≤1×10-12 (conventional CRC-32 bit error rate is about 1×10-10, and hardware layer electromagnetic shielding, signal amplification and other measures need to be superimposed). The data frame format is:

[0053] [Synchronization header (8 bits)][Command type (4 bits)][Target module (3 bits)][Priority (3 bits)][Parameter length (16 bits)][Parameter data (N×32 bits)][CRC-32 (32 bits)].

[0054] The bidirectional interaction instructions, content, and priority between module 8 and modules 1 to 7 are shown in the following table.

[0055]

[0056]

[0057] Module 6: Temperature sensor module, which provides real-time environmental data for the temperature adaptive correction module by building a high-density temperature monitoring network. Physically, 12 MEMS temperature sensors are deployed at the ADC input interface, FPGA chip and 100GbE output interface of each RFSOC board, with a total of 48 MEMS temperature sensors on 4 boards, with an accuracy of ±0.2°C and a sampling frequency of 100Hz. The innovation lies in the fact that for the first time, precise environmental perception has been achieved in a radio astronomy terminal, and millimeter-level resolution monitoring of the core device temperature has been achieved (such as FPGA junction temperature fluctuation ≤±1°C), and the temperature uniformity is controlled at ≤2°C / cm 2 (Traditional solution≤5℃ / cm 2 ), providing reliable input for the correction model. Rapid response mechanism: The temperature change response time is less than 10ms, ensuring that the temperature adaptive correction module can capture device temperature drift in real time when the temperature difference between day and night is 30°C at the FAST site.

[0058] Module 5: The three-temperature calibration module is used to generate frequency-specific correction coefficients and is the "data engine" of the temperature adaptive system. Based on the temperature data from module 6, the temperature coefficient (amplitude coefficient A, phase coefficient φ) is fitted to each frequency fi using the measured data at three temperatures of -40°C, 25°C, and 60°C. The corrected value is obtained using the correction formula:

[0059]

[0060] The innovation lies in the realization of frequency-level precise calibration: 491,520 sets of correction coefficients are generated for 16,384 frequencies × 30 channels, and the single-frequency calibration error is ≤0.02dB (amplitude) / 0.3° (phase), which is 5 times more accurate than the traditional unified correction scheme for the entire channel. It also supports on-orbit recalibration to ensure the long-term operational stability of the system.

[0061] Module 1: RFSOC Processing Module (Core Computing Unit): Implements high-frequency, real-time processing and frequency domain conversion of 30 channels of signals. It serves as the system's "digital front-end brain," providing FPGA configuration, control, and status feedback through Module 9. Module 9 utilizes a parallel architecture of four Xilinx ZCU47DR RFSOCs (the first three have 8 channels each, the fourth has 6 channels). The single chip integrates a 14-bit ADC (2.5 GSps sampling rate), a DDC digital downconversion unit, and a 16,384-point FFT module. Frequency domain preprocessing and DDC downconversion convert 500 MHz to 2 GHz RF signals to a 0-2 GHz intermediate frequency (IF), supporting 1.5 GHz instantaneous bandwidth. PFB+FFT conversion is then used to convert these signals into channelized frequency domain data, generating 16,384 frequency points per channel (with a 1 kHz resolution), covering key astronomical spectral line bands such as neutral hydrogen (1420 MHz) and the OH maser (1612 MHz). The innovation of this module is: 1. Improving parallel processing efficiency through dynamic allocation of hardware resources, the resource utilization of a single chip is increased to 85% (traditional solutions ≤ 50%), and the total processing bandwidth reaches 6GHz (4 chips × 1.5GHz), meeting the ultra-wideband observation requirements of FAST. 2. Low-power design: Combining frequency grouping (every 128 frequency points / group) with time-division multiplexing technology, the low-power design of the RFSOC processing module achieves high-efficiency optimization through frequency grouping and time-division multiplexing technology: 16,384 frequency points are divided into 128 groups of 128 points each, and assigned to 4 RFSOCs (the first three chips process 32 groups each, and the fourth chip processes the remaining 32 groups) for parallel processing. Each processing cycle (1ms) is divided into 128 time slices, and each chip corresponds to a three-stage pipeline processing of a group of frequency points (FFT calculation, coefficient lookup table weighting, data output). The chips achieve sub-nanosecond coordination through global clock synchronization; module-level power gating technology is used to put inactive frequency group processing units into sleep mode (power consumption <10mW), combined with dynamic voltage frequency scaling (DVFS), uses 1.0V / 500MHz under high load and drops to 0.7V / 200MHz under low load. At the same time, BRAM is used to store frequency group coefficients and FIFO cache data to reduce memory power consumption. The allocation of units such as CLB, BRAM, and DSP is optimized in hardware resources (single-chip resource utilization reaches 85%). The critical path achieves low latency (single group processing ≤7.8125μs) through a radix-4 pipeline FFT engine, linear interpolation coefficient circuit, and state machine time slice control. Ultimately, the total power consumption of the module is reduced to below 150W, a 31.8% reduction compared to traditional solutions, while meeting the requirements of a 1ms processing cycle and long-term stable operation.

[0062] Module 2: Temperature adaptive correction module (environmental adaptive core) eliminates signal amplitude and phase errors in a wide temperature range and ensures beam pointing accuracy. The processing and receiving module 6 (24-channel MEMS sensor) transmits real-time temperature data (accuracy ±0.2°C, covering -40°C to +60°C) to module 5 (three-temperature point calibration module) and generates frequency-specific correction coefficients for the amplitude (ΔA ≤ 0.05dB) and phase (ΔA ≤ 0.05dB) of the signal spectrum data processed by module 1. Independent correction is performed on the full temperature range), that is, the complex data of each frequency point is corrected by the real-time correction amplitude and phase value. The calculation formula is:

[0063]

[0064] Innovation lies in: high-precision calibration over the entire temperature range: establishing a two-dimensional frequency-temperature calibration model Calibrated at three temperatures (-40°C, 25°C, and 60°C), the amplitude calibration error is ≤0.02dB, and the phase calibration error is ≤0.3°, representing a fivefold improvement over traditional single-temperature control solutions (phase error >5° across the entire temperature range). A dynamic compensation mechanism: FPGA real-time loading of correction coefficients (update cycle ≤10ms) ensures beam pointing deviations of <0.1 arc minute with temperature changes, resolving the beam distortion challenge faced by similar international equipment in environments with temperature differences exceeding 30°C.

[0065] Module 3: Multi-beamforming module, which enables real-time observation of multiple targets, is the core module for improving the coverage efficiency of the FAST sky area. It uses the original deep adaptive beamforming algorithm (DDBF) for frequency domain weighted synthesis, with a sidelobe suppression ratio of ≥32dB. Traditional MVDR relies on accurate covariance matrix estimation, and its performance degrades significantly under low signal-to-noise ratio or dynamic interference. DDBF directly models complex environments through deep learning without the need for prior knowledge. In actual measurements, it still maintains a sidelobe suppression ratio of ≥30dB at -10dB SNR. The calculation formula of the beamforming algorithm is: y ij represents the output signal of the jth beam at the i-th frequency point, x ik represents the input signal of the i-th frequency point on the k-th channel; w ijk(where represents the shaping weight of the kth channel on the jth beam at the i-th frequency)). An interpretable end-to-end model is constructed using an optimized unfolding iterative algorithm (FISTA). Spatial features are extracted from the raw data of 30 channels × 16,384 frequencies. Compared to the standard FISTA algorithm, a reinforcement learning (RL) submodule is innovatively introduced. By correcting the sidelobe suppression ratio (SLL) and beam pointing error, beam weights are adjusted in real time to achieve adaptive suppression of dynamic interference. Frequency-domain weighted synthesis is performed on the 30-channel × 16,384 frequency data, supporting simultaneous output of 7 to 12 beams (pointing angles from -90° to +90°, in 5° steps). Weak signal enhancement: For signals with a signal-to-noise ratio (SNR) ≤ 5dB, frequency-domain coherent accumulation (accumulation period ≤ 100ms) is enabled, combined with inter-beam correlation analysis. The innovation lies in high-precision beam control, with a sidelobe suppression ratio of ≥32dB (compared to ≤25dB with traditional solutions), effectively separating adjacent signals with power differences of ≥30dB across the sky (such as pulsars in binary systems), and achieving a beam pointing accuracy of 0.1 arc minute (better than the 1 arc minute of FAST's single-beam feed). A breakthrough in observation efficiency: Multi-beam parallel processing increases the sky area covered by FAST's single exposure by four times, shortens neutral hydrogen line surveys by 40%, and improves weak signal detection sensitivity by 13% compared to traditional solutions (verified by field measurements).

[0066] Module 4: Fiber optic interface module, which realizes high-speed transmission of processed data and connects to back-end storage devices. Output configuration 12-way fiber optic interface (100 / 25Gbps / way), supports real-time transmission of beam data. Total transmission bandwidth reaches 300Gbps (12-way

[0067] ×25Gbps), with data transmission latency ≤50μs, meeting the stringent real-time requirements of FAST's back-end correlators (e.g., pulsar timing observations require a latency of <100μs). The protocol is also compatible with multiple high-speed protocols such as SRIO and Fibre Channel, adapting to different back-end devices.

[0068] While specific embodiments of the present invention have been disclosed for illustrative purposes, intended to facilitate understanding and implementation of the present invention, those skilled in the art will appreciate that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the disclosure of the preferred embodiments, and the scope of protection claimed in the present invention shall be determined by the scope of the claims.

Claims

1. A radio astronomy wide-temperature range adaptive beamforming method, comprising: 1) The three-temperature calibration module sets the phase temperature coefficient (ai, bi) and amplitude temperature coefficient (ci, di) for each frequency point fi and sends them to the temperature adaptive correction module; the temperature sensor module monitors the ambient temperature in real time and sends it to the temperature adaptive correction module; where ai represents the temperature sensitivity coefficient of the frequency point fi phase, reflecting the slope of the frequency point fi phase error with temperature; bi represents the temperature offset coefficient, reflecting the inherent phase error of the frequency point fi at the reference temperature; ci represents the temperature attenuation coefficient of the frequency point fi amplitude, reflecting the slope of the frequency point fi amplitude error with temperature; di represents the temperature reference coefficient, reflecting the inherent amplitude error of the frequency point fi at the reference temperature; 2) The temperature adaptive correction module generates a shared real-time temperature T according to the received temperature information 实时 ; and establish a phase error model Δφ(fi,T for each frequency point fi 实时 )=a i ·T 实时 +b i and an amplitude error model ΔA(fi,T 实时 )=c i ·T 实时 +d i Then, the phase error Δφ and amplitude error ΔA of the corresponding frequency point fi are calculated based on the phase error model and amplitude error model of each frequency point fi; wherein all frequency points of each channel share the real-time temperature T real-time; 3) The digital signal processing module performs DDC down-conversion on the RF signal of each channel of the phased array feed PAF to the intermediate frequency. Then the intermediate frequency signal is converted into frequency domain data; then the amplitude and phase of each frequency point in the frequency domain data are corrected; wherein, the corrected phase φ 校正 =φ 实测 -Δφ, the corrected amplitude A 校正 =A 实测 10 -ΔA / 20 ,φ 实测 is the amplitude of the frequency point, A 实测 is the phase of the frequency point, Δφ is the phase error, and ΔA is the amplitude error; 4) The multi-beam forming module performs multi-beam synchronous output on the correction data output by the digital signal processing module, and each beam is independently configured with a pointing angle.

2. The method according to claim 1, characterized in that The multi-beam forming module is formed by the formula Calculate and generate the output signal of each beam and output all beams synchronously; where N is the total number of channels, y ij represents the output signal of the jth beam at the i-th frequency point, x ik represents the input signal of the i-th frequency point on the k-th channel; w ijk It represents the shaping weight of the kth channel on the i-th frequency point to the j-th beam.

3. The method according to claim 1, characterized in that The pointing angle is -90° to +90°, and the pointing angles of adjacent beams differ by 5°.

4. The method according to claim 1, 2 or 3, characterized in that: The digital signal processing module uses four Xilinx RFSOC chips connected in parallel, and each Xilinx RFSOC chip processes eight input signals.

5. The method according to claim 4, characterized in that MEMS temperature sensors are deployed at the ADC input interface, FPGA chip, and 100GbE output interface of each Xilinx RFSOC chip, and the collected temperatures are weighted averaged to obtain the real-time temperature T 实时 .

6. The method according to claim 1, 2 or 3, characterized in that: The massive data generated by multi-beam observation is transmitted to the back-end storage device through the optical fiber interface module.

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