Large model-based high-voltage PCB current path optimization design method and system

Abstract

The invention relates to the technical field of high-voltage PCB design, and particularly provides a large-model-based high-voltage PCB current path optimization design method and system, and the method comprises the steps: S2, obtaining current distribution according to electrical parameters and layout information through employing an electrical simulation model; s3, acquiring temperature field distribution according to the current distribution, the resistivity of the via hole array and the heat conductivity coefficient of the PCB substrate; s4, acquiring first thermal mechanical stress distribution according to the temperature field distribution, the thermal expansion coefficients of the via hole array and the PCB substrate and the elastic modulus of the via hole array and the PCB substrate; s5, analyzing whether the first thermal mechanical stress distribution meets a preset requirement or not, if yes, taking new layout information as final layout information, and if not, adjusting layout parameters of the via hole array according to the first thermal mechanical stress distribution, and returning to the step S2; according to the method, the problems of local hot spots and thermal mechanical stress caused by uneven current distribution in the high-voltage PCB via hole array can be solved.

Description

Technical Field

[0001] The present application relates to the technical field of high-voltage PCB design, and more specifically, to a large-model-based high-voltage PCB current path optimization design method and system. Background Art

[0002] In the field of electronic devices, high-voltage PCB design significantly reduces product size and achieves high power density by compactly stacking power circuits, control circuits, and driver circuits in a multi-layer structure. The industry generally uses via arrays to carry high currents, and utilizes EDA software for layout and routing. This software calculates the minimum number of vias required based on the total current and the rated current-carrying capacity of each via. These vias tend to be arranged in a regular matrix, beneath the pads of power devices or at the corners of current paths. The design process focuses on macro-performance indicators such as overall voltage drop, temperature rise, and parasitic inductance to meet space constraints and efficiency requirements, driving the technology towards more efficient integration.

[0003] However, current flow follows the principle of the path of least impedance. For a current path entering a PCB surface layer and flowing through a via array to an inner layer, the current is not evenly distributed among each parallel via as in an ideal situation. Instead, due to the current crowding effect, most of the current is concentrated in the first few vias encountered and closest to the current entry point. This results in an uneven distribution of current within the via array, with the edge vias carrying the majority of the current and the center vias receiving minimal current. This leads to highly uneven local heat generation and the formation of microscopic hot spots. Due to the difference in thermal expansion coefficients between the vias and the PCB substrate, this difference causes mismatched expansion of the vias and the PCB substrate with temperature changes, resulting in cyclical thermomechanical stress within the via structure. Each temperature cycle causes stress loading and stress writing within the via structure's grains. Consequently, repeated thermal cycling accelerates material fatigue, initiating microcracks that may develop into open via failures. Existing PCB design methods treat electrical performance, thermal performance, and mechanical reliability as independent optimization targets. This means that existing technologies lack a design approach that can couple current distribution, thermal distribution, and thermomechanical stress for integrated analysis and optimization. Consequently, existing technologies are unable to fundamentally prevent long-term reliability issues caused by uneven current distribution.

[0004] There is no effective technical solution to the above problems. It should be noted that the above information disclosed in this section is only used to understand the background of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] The purpose of this application is to provide a large-model-based high-voltage PCB current path optimization design method and system, which can solve the local hot spots and thermo-mechanical stress problems caused by uneven current distribution in high-voltage PCB via arrays.

[0006] In a first aspect, the present application provides a high-voltage PCB current path optimization design method based on a large model, which includes the following steps: S1. Obtaining electrical parameters of the high-voltage PCB current path and initial layout information of the via array; S2. using an electrical simulation model to obtain current distribution of the via array based on electrical parameters and layout information; S3, obtaining the temperature field distribution of the via array according to the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate; S4. Obtaining a first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, use the new layout information as the final layout information of the via array. If not, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain new layout information, and return to step S2.

[0007] In a second aspect, the present application also provides a high-voltage PCB current path optimization design system based on a large model, which includes: An information acquisition module is used to obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array; A current distribution acquisition module is used to obtain the current distribution of the via array according to electrical parameters and layout information using an electrical simulation model; A temperature field distribution acquisition module is used to obtain the temperature field distribution of the via array based on the current distribution, the resistivity of the via array and the thermal conductivity of the PCB substrate; a stress distribution acquisition module, configured to acquire a first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; The layout optimization module is used to analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information and trigger the current distribution acquisition module to run.

[0008] As can be seen from the above, the present application provides a large-model-based high-voltage PCB current path optimization design method and system. By coupling electrical simulation, thermal simulation, and mechanical simulation, and introducing an iterative optimization mechanism to solve the local hot spots and thermo-mechanical stress problems caused by uneven current distribution in the high-voltage PCB via array, it achieves an integrated optimization design of electrical performance, thermal performance, and mechanical reliability, thereby effectively improving the long-term reliability of the high-voltage PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A flowchart of a large-model-based high-voltage PCB current path optimization design method provided in an embodiment of the present application.

[0010] Figure 2 A schematic diagram of the structure of a large-model-based high-voltage PCB current path optimization design system provided in an embodiment of the present application.

[0011] Reference numerals: 1. information acquisition module; 2. current distribution acquisition module; 3. temperature field distribution acquisition module; 4. stress distribution acquisition module; 5. layout optimization module. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0013] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0014] First, as Figure 1 As shown, the present application provides a high-voltage PCB current path optimization design method based on a large model, which includes the following steps: S1. Obtaining electrical parameters of the high-voltage PCB current path and initial layout information of the via array; S2. using an electrical simulation model to obtain current distribution of the via array based on electrical parameters and layout information; S3, obtaining the temperature field distribution of the via array according to the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate; S4. Obtaining a first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, use the new layout information as the final layout information of the via array. If not, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain new layout information, and return to step S2.

[0015] The electrical parameters of step S1 may include current magnitude, voltage level, operating frequency, signal integrity requirements, etc. The layout information of step S1 may include the initial position coordinates of the vias, the via diameter, the via length, the via shape, and the arrangement of the via array. Step S1 can be implemented by using design input files, CAD data import, manual user input, or extraction from an existing design database to obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array. This embodiment, by collecting this basic data, provides the necessary prerequisites for subsequent simulation and analysis, enabling the entire design process to be based on actual design requirements and physical constraints.

[0016] The electrical simulation model of step S2 can adopt the finite element method (FEM), the finite difference time domain method (FDTD), the transmission line matrix method (TLM), or a SPICE-based circuit simulation model. The specific process of step S2 can be: the electrical parameters and layout information obtained in step S1 are input into a pre-trained three-dimensional electromagnetic field model of the via array. The model calculates the current density distribution inside each via and the entire via array by solving the Swer equations based on the input electrical parameters and layout information to obtain the current distribution. Therefore, this embodiment can use the electrical simulation model to accurately simulate the actual flow of current in the via array based on the electrical parameters and layout information. That is, the current distribution of this embodiment can reveal the current crowding effect and the phenomenon of uneven distribution. This directly addresses the problem caused by uneven current distribution mentioned in the background technology, providing accurate input for subsequent thermal and stress analysis.

[0017] Step S3 correlates electrical performance with thermal performance by obtaining the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate. The resistivity of the via array in step S3 refers to the resistivity of the via material (e.g., copper), which determines the Joule heat generated when current flows through the via array. In this embodiment, the resistivity of the via array can be obtained by querying a material resistivity database based on a preset via material. This resistivity is a preset value or a pre-measured value. The thermal conductivity of the PCB substrate in step S3 refers to the ability of the substrate material (e.g., FR-4) to conduct heat. This thermal conductivity affects heat diffusion within the substrate. In this embodiment, the thermal conductivity of the PCB substrate can be obtained by querying a PCB substrate performance database based on the PCB substrate's identification (e.g., a QR code or barcode affixed to the PCB substrate). This thermal conductivity is a preset value or a pre-measured value. The specific process of step S3 can be as follows: based on the current distribution and the resistivity of the via array, the local heat generation rate (power dissipation) of each via and its surrounding area is calculated; then, using a thermal simulation model (e.g., a finite element method-based thermal conduction model), the heat conduction equation is solved based on these local heat generation rates and the thermal conductivity of the PCB substrate to predict how heat diffuses and accumulates in the via array, thereby obtaining the temperature field distribution of the via array. It should be understood that this embodiment can identify potential microscopic hot spots based on the temperature field distribution. This step is crucial for understanding the root causes of thermomechanical stress, as temperature changes are a direct cause of thermal stress.

[0018] Step S4 can closely integrate thermal and mechanical properties by obtaining a first thermomechanical stress distribution for the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate. The thermal expansion coefficient in step S4 indicates the degree to which a material expands or contracts with temperature changes, while the elastic modulus in step S4 indicates the material's ability to resist elastic deformation. The specific process for step S4 may include: calculating the mismatched expansion or contraction caused by temperature changes using the temperature field distribution combined with the difference in thermal expansion coefficients between the via material (e.g., copper) and the PCB substrate material (e.g., FR-4); quantifying the thermomechanical stress surface resulting from this mismatched expansion using the elastic moduli of the via material and the PCB substrate material. For example, structural mechanics simulation software (e.g., a stress analysis model based on the finite element method) is used to calculate the stress distribution at the via-substrate interface, within the vias, and throughout the via array.

[0019] The preset requirements of step S5 may include maximum allowable stress values, fatigue life requirements, and reliability indicators. Step S5 is equivalent to evaluating the first thermomechanical stress distribution obtained in step S4 according to the preset requirements to determine whether it is within an acceptable range. If the stress is excessive or does not meet the requirements, the layout parameters of the via array are intelligently adjusted based on the stress distribution (the first thermomechanical stress distribution). Specifically, this embodiment can use an optimization algorithm (such as a genetic algorithm, particle swarm optimization, or a machine learning-based optimization algorithm) to guide the adjustment of the layout parameters to reduce stress concentration. This stress feedback-based adjustment mechanism can effectively alleviate stress concentration and optimize the structure of the via array, thereby fundamentally preventing material fatigue and failure caused by repeated thermal cycling. The adjusted new layout information is returned to step S2, forming a closed-loop optimization process to ensure that the final design achieves optimal electrical, thermal, and mechanical performance, effectively solving the problem of the lack of integrated analysis and optimization in the existing technology. The present application can utilize the iterative loop of steps S2 to S5 to couple electrical performance analysis, thermal performance analysis, and mechanical performance analysis to form a unified optimization framework, thereby fundamentally solving the local hot spots and thermomechanical stress caused by uneven current distribution and the long-term reliability problems caused thereby.

[0020] The core innovation of this application lies in the coupled analysis of electrical simulation, thermal simulation and mechanical simulation, and the introduction of an iterative optimization mechanism to solve the local hot spots and thermo-mechanical stress problems caused by uneven current distribution in high-voltage PCB via arrays, thereby achieving an integrated optimization design of electrical performance, thermal performance and mechanical reliability, thereby effectively improving the long-term reliability of high-voltage PCBs.

[0021] Specifically, this method first obtains the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array to provide basic data for subsequent simulation analysis. Next, an electrical simulation model is used to simulate and obtain the current distribution within the via array based on the electrical parameters and layout information to identify areas of current congestion. Based on this, a thermal simulation is performed to calculate the temperature field distribution within the via array, combining the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate to predict possible hotspots. Furthermore, a mechanical simulation is performed to calculate the thermomechanical stress distribution within the via array based on the temperature field distribution and the thermal expansion coefficient and elastic modulus of the via array and the PCB substrate to quantify the mechanical loads on the via array during operation. The calculated thermomechanical stress distribution is then evaluated to determine whether it meets preset reliability requirements. If the stress distribution meets the requirements, the current layout information is determined as the final layout. Otherwise, if the stress distribution does not meet the requirements, the via array layout parameters are adjusted based on the stress analysis results to alleviate stress concentrations, and new layout information is generated. Afterwards, the new layout information is fed back to the electrical simulation step to form a closed-loop iterative optimization process and enable the design to continuously approach the optimal solution, thereby fundamentally solving the thermo-mechanical stress problem caused by uneven current distribution and achieving coupled optimization of electrical, thermal, and mechanical performance.

[0022] As a preferred embodiment, the solution of the present application is specifically implemented as follows: When designing a high-voltage PCB, data such as the current demand of the power module, the PCB stackup structure, and the initial via layout are first input. Then, using electrical simulation software (such as Ansys Maxwell or CST Studio Suite), a current density simulation is performed on the via array based on the current demand, PCB stackup structure, and initial via layout to obtain the current carrying capacity (current distribution) of each via. Based on this current distribution, combined with the resistivity of the via material and the thermal conductivity of the PCB substrate, the temperature field of the via array area is calculated using thermal simulation software (such as Ansys Icepak or Flotherm) to obtain the temperature field distribution and identify possible hotspot locations. Subsequently, the temperature field data is imported into structural mechanics simulation software (such as Ansys Mechanical or Abaqus), and the thermomechanical stress distribution (first thermomechanical stress distribution) at the via-substrate interface is calculated using the thermal expansion coefficient and elastic modulus of the via and substrate. If the calculated maximum stress value exceeds the material's fatigue limit or a preset safety threshold, an optimization algorithm or design rules are used to adjust the relative position of the vias, the via spacing, or the overall shape of the via array based on the thermomechanical stress distribution. For example, the via spacing in areas with high current density can be increased, or the number of vias in those areas can be increased to disperse the current and stress. The adjusted new layout information is then re-entered into the electrical simulation phase, and the simulation and evaluation process is repeated until the thermomechanical stress distribution meets all design requirements, ultimately determining the optimized layout of the high-voltage PCB via array. This method achieves an integrated optimization design that combines electrical performance, thermal performance, and mechanical reliability, avoiding failure modes that cannot be fundamentally prevented by traditional independent optimization methods, thereby improving the stability and service life of high-voltage PCBs under complex operating conditions.

[0023] In some preferred embodiments, the layout parameters include the relative position of the vias, the via spacing, and the overall shape of the via array. The relative position of the vias refers to the relative coordinate relationship between the individual vias in the via array in two-dimensional or three-dimensional space. This embodiment can use a grid coordinate system or a local coordinate system to accurately describe the center point position of each via. This embodiment can also describe the relative coordinate relationship between the individual vias in two-dimensional or three-dimensional space by defining a vector relationship between the vias. The via spacing refers to the straight-line distance between the center points of any two adjacent vias. This embodiment can use uniform spacing, non-uniform spacing, or spacing based on a specific function distribution to set the via spacing. For example, the spacing can be dynamically adjusted according to the current density or thermal stress gradient. The overall shape of the via array refers to the macroscopic geometric outline enclosed by all the vias that constitute the via array. This overall shape can use geometric configurations such as rectangle, circle, ellipse, L-shape, T-shape, or any irregular polygon. This embodiment can determine its macroscopic outline based on the available space on the PCB board or the current flow direction.

[0024] This application provides a clear and actionable dimension for adjusting the via array layout based on a first thermomechanical stress distribution by clearly defining the specific composition of layout parameters, enabling the design method to more accurately address thermomechanical stress issues caused by improper layout. Specifically, when optimizing the via array based on the first thermomechanical stress distribution, the design method can simultaneously consider adjusting the relative positions of the vias, the via spacing, and the overall shape of the via array. This embodiment can finely control the distribution of current in the via array by adjusting the relative positions of the vias. For example, when local stress concentrations or hot spots are detected, specific vias can be strategically moved away from high current density areas or the current path can be more evenly dispersed, thereby reducing local current density and minimizing the formation of microscopic hot spots, thereby alleviating thermomechanical stress concentrations caused by temperature unevenness. This embodiment can optimize the current diffusion path in the via array and the heat conduction efficiency in the PCB substrate by adjusting the via spacing. For example, when stress analysis indicates excessive thermal expansion differences or stress superposition between vias, the distance between adjacent vias can be appropriately increased or decreased to promote heat diffusion in the PCB substrate and reduce local temperature rise. This embodiment optimizes the macroscopic layout of the entire via array by adjusting its overall shape, enabling the array to better adapt to the current paths and spatial constraints of a high-voltage PCB. For example, the array's geometry can be altered to optimize the current inlet and outlet distribution, further balancing current distribution across the array. By combining microscopic adjustments to the relative position and spacing of the vias with macroscopic adjustments to the overall shape of the via array, this embodiment enables a multi-level design approach capable of comprehensively addressing complex electrical, thermal, and mechanical coupling issues. This approach transcends the need for crude adjustments based on macroscopic stress distribution and instead enables detailed intervention at the microstructural level of the via array, effectively reducing thermomechanical stress and improving the long-term reliability of the high-voltage PCB. This refined definition of layout parameters enables a richer and more effective adjustment strategy during iterative optimization based on thermomechanical stress distribution, achieving a better balance between electrical performance, thermal performance, and mechanical reliability, significantly improving the accuracy and effectiveness of the optimized design.

[0025] In some preferred embodiments, the process of adjusting the layout parameters of the via array according to the first thermomechanical stress distribution includes: A1. Obtaining the first electrical performance parameter of the current via array; A2. generating a plurality of candidate via array layout solutions according to the first thermomechanical stress distribution; A3. For each candidate via array layout solution, obtain a second electrical performance parameter and a second thermomechanical stress distribution corresponding to the candidate via array layout solution, then calculate a performance parameter change based on the first electrical performance parameter and the second electrical performance parameter, and obtain a degree of thermomechanical stress balance based on the second thermomechanical stress distribution; A4. Filtering a target via array layout scheme from all candidate via array layout schemes according to the degree of thermomechanical stress balance and the variation of performance parameters, and adjusting the layout parameters of the via array according to the target via array layout scheme.

[0026] The first electrical performance parameter refers to a quantitative indicator of the electrical characteristics of the current via array under a specific working state (such as its resistance, inductance, or impedance). This first electrical performance parameter can provide a benchmark for subsequent evaluation of the impact of different layout schemes on electrical performance. Generating multiple candidate via array layout schemes refers to systematically creating a series of new, potentially optimized via array configurations based on the current thermomechanical stress distribution through algorithms or heuristic rules. Each candidate via array layout scheme can be a set that differs in the number of vias, relative position, spacing, or overall geometry. This embodiment is equivalent to exploring a broader design space by generating multiple candidate via array layout schemes based on the first thermomechanical stress distribution, in order to find a better solution. The performance parameter change indicator is a quantitative difference obtained by comparing the electrical performance parameters of the candidate via array layout scheme with the electrical performance parameters of the current via array. This performance parameter change is used to measure the degree of impact of the new layout scheme on the original electrical performance. The degree of thermomechanical stress balance is an indicator that measures the uniformity of the thermomechanical stress distribution within a via array. This degree of thermomechanical stress balance reflects the degree of stress dispersion across various vias or regions. Generally, the more uniform the stress distribution, the higher the long-term reliability of the via array. In this embodiment, the degree of thermomechanical stress balance can be obtained by calculating the standard deviation of stress values ​​or the ratio of maximum stress to average stress. The step of screening the target via array layout solution involves evaluating the electrical performance changes and thermomechanical stress balance of all candidate via array layout solutions, and then selecting the best performing or most satisfactory via array layout solution based on preset optimization goals or comprehensive evaluation criteria.

[0027] Before initiating layout parameter adjustments, the solution first obtains the first electrical performance parameters of the current via array, providing a quantitative benchmark for subsequently evaluating the impact of new layout solutions on electrical performance. Subsequently, multiple different candidate via array layout solutions are intelligently generated based on the current first thermomechanical stress distribution. This generation process can use information about stress concentration to guide the formation of new solutions. For example, by adjusting the relative position, spacing, or overall shape of the vias to disperse stress, thereby expanding the scope of exploration of the design space. For each generated candidate via array layout solution, the solution performs a comprehensive simulation and evaluation. Specifically, the solution first obtains the second electrical performance parameters and second thermomechanical stress distribution corresponding to the candidate via array layout solution. Then, by comparing the second electrical performance parameters with the previously obtained first electrical performance parameters, the performance parameter change is calculated to quantify the impact of the new solution on electrical performance. Simultaneously, the degree of thermomechanical stress balance of the solution is obtained based on the second thermomechanical stress distribution to measure the uniformity of its stress distribution. By simultaneously evaluating electrical performance and thermomechanical stress, the solution ensures the comprehensiveness of the optimization process, avoiding the problem of neglecting one while focusing on the other. Finally, after a comprehensive evaluation of all candidate solutions, the optimal target via array layout is selected based on the degree of thermomechanical stress balance and the amount of change in performance parameters. This screening process typically involves a comprehensive evaluation metric that balances electrical performance improvement with thermomechanical stress optimization. This ensures that the final layout solution not only effectively reduces thermomechanical stress but also maintains or improves electrical performance, thereby achieving comprehensive optimization of the high-voltage PCB current path. After selecting the target layout solution, the solution then adjusts the via array layout parameters based on the selected solution to complete an iterative optimization. This adjustment process is closely integrated with the analysis of the first thermomechanical stress distribution in the aforementioned solution. If the analysis results indicate that the stress does not meet the requirements, this adjustment process is triggered. By systematically exploring and evaluating multiple layout solutions, an efficient optimization solution that balances electrical performance and thermomechanical stress is found. After the adjustment is completed, the new layout information is fed back to the current distribution acquisition step, forming a closed-loop optimization cycle. This iterative and multi-objective evaluation mechanism makes the optimization process no longer blind or heuristic, but can systematically converge to a more optimal solution, thereby fundamentally solving the problems of local hot spots and stress concentration caused by uneven current distribution, and significantly improving the long-term reliability of the high-voltage PCB current path.

[0028] As a preferred embodiment, professional electrical simulation software (such as ANSYS Q3D Extractor) is used to simulate and analyze the geometric model of the current via array to obtain first electrical performance parameters of the current via array. For example, the total resistance and parasitic inductance of the current via array at a specific operating frequency are used as the first electrical performance parameters. Furthermore, an intelligent optimization algorithm (such as a genetic algorithm or a particle swarm optimization algorithm) is used to generate multiple candidate via array layouts based on the first thermomechanical stress distribution. The algorithm can use the high-stress regions or stress concentration points identified in the first thermomechanical stress distribution as a guide to automatically generate a series of via array layouts with different geometric characteristics. For example, if the stress value of a via or region exceeds a threshold, the algorithm can attempt to increase the number of vias in that region, adjust the relative positions of the vias to disperse the current, or change the overall shape of the via array (such as from a regular rectangular array to a more shaped array that better accommodates the current path) to more effectively disperse the thermomechanical stress. This embodiment fully explores the design space by generating multiple candidate via array layouts based on the first thermomechanical stress distribution. For each candidate via array layout scheme, a detailed simulation analysis is performed using electrical simulation software to obtain the second electrical performance parameters corresponding to the scheme, and the thermomechanical stress distribution of the scheme is obtained using steps S2-S4 to obtain the second thermomechanical stress distribution. Subsequently, these second electrical performance parameters are compared with the first electrical performance parameters obtained previously to calculate the change in performance parameters such as the resistance change rate and the inductance change rate. At the same time, the standard deviation of all via stress values ​​or the ratio of maximum stress to average stress is calculated based on the second thermomechanical stress distribution, which is used as a quantitative indicator of the degree of thermomechanical stress balance. For example, the smaller the stress standard deviation, the more uniform the stress distribution and the higher the degree of thermomechanical stress balance. Finally, when screening the target via array layout, a pre-set comprehensive evaluation function is used to weight the degree of thermomechanical stress balance and the change in performance parameters to balance the importance of different optimization objectives. This comprehensive evaluation function can assign a higher weight to the degree of thermomechanical stress balance while assigning a penalty for deteriorating electrical performance or a reward for improving electrical performance. For example, if the objectives are to minimize both stress standard deviation and resistance increase, the comprehensive evaluation function is: Comprehensive evaluation score = w1 × (stress standard deviation) + w2 × (resistance change), where w1 and w2 are pre-set weight coefficients. By calculating the comprehensive evaluation score for each candidate solution, the solution with the highest (or lowest, depending on the function definition) score is selected as the target via array layout solution. Once the target layout solution is selected, the specific geometric parameters contained in the target layout solution (such as the precise via location, spacing, and overall array shape) are applied to complete the adjustment of the via array layout parameters.This embodiment can fully explore the design space by obtaining the current electrical performance parameters as a benchmark before adjustment and intelligently generating multiple candidate layout solutions based on the thermomechanical stress distribution. For each candidate solution, its electrical performance change and the degree of thermomechanical stress balance are simultaneously evaluated, ensuring the comprehensiveness of the optimization process and avoiding the limitations that may be brought about by a single optimization goal. Ultimately, an optimized solution that takes into account both electrical performance and thermomechanical stress distribution is selected through a comprehensive screening mechanism, thereby fundamentally solving the local hot spots and stress concentration problems caused by uneven current distribution, achieving a comprehensive performance improvement of the high-voltage PCB current path, and significantly enhancing its long-term operational reliability.

[0029] In some preferred embodiments, step A4 includes: A41. Evaluate the manufacturing process feasibility of each candidate via array layout solution based on preset manufacturing process constraint parameters, and then remove candidate via array layout solutions that are evaluated as not having manufacturing process feasibility. The preset manufacturing process constraint parameters include a minimum aperture, a minimum hole spacing, and a minimum line width. A42. For each remaining candidate via array layout solution, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance and the change in performance parameters; A43. Filter out the target via array layout scheme from the remaining candidate via array layout schemes based on the comprehensive evaluation index.

[0030] Preset manufacturing constraints refer to the technical specifications and restrictions that must be followed during the PCB manufacturing process. These can be set based on industry standards, factory equipment capabilities, or specific product requirements. Manufacturing feasibility assessment is a systematic check of whether a design meets these pre-set manufacturing constraints. This can be accomplished using automated design rule checking (DRC) tools or manual review. Failure to meet manufacturing feasibility means a design violates at least one of the pre-set manufacturing constraints, rendering it unmanufacturable through conventional manufacturing processes. Minimum hole diameter refers to the minimum diameter of a via that can be reliably produced in PCB manufacturing. This minimum hole diameter can be determined based on the capabilities of specific drilling equipment or material properties. Minimum hole spacing refers to the minimum allowable distance between adjacent via centers. This can be determined based on drilling accuracy, wiring density, or thermal effects. Minimum line width refers to the minimum width of a conductor that can be reliably etched and maintain an electrical connection on a PCB. This can be determined based on etching process accuracy or current carrying capacity. The comprehensive evaluation index refers to a unified numerical value used to quantitatively evaluate the advantages and disadvantages of different candidate via array layout schemes. It can be calculated using methods such as weighted summation, multi-objective optimization function or fuzzy comprehensive evaluation to comprehensively reflect the performance of the scheme in multiple performance dimensions.

[0031] The screening mechanism of the present application ensures the actual manufacturability of the selected solution by combining the manufacturing process feasibility assessment with the comprehensive assessment of the degree of thermomechanical stress balance and the amount of performance parameter change, thereby improving the practicality and efficiency of the optimization results. Specifically, before screening the target via array layout solution based on the degree of thermomechanical stress balance and the amount of performance parameter change, this embodiment first introduces a manufacturing process feasibility assessment. First, the system performs a manufacturing process feasibility assessment on all generated candidate via array layout solutions based on preset manufacturing process constraint parameters. This assessment aims to identify and eliminate those design solutions that may have excellent performance in theory but cannot be produced in practice at an early stage. This embodiment effectively avoids subsequent invalid calculations and evaluations of these unmanufacturable solutions by excluding solutions that do not have manufacturing process feasibility at the beginning of the screening process, thereby significantly improving the efficiency and practicality of the entire optimization process. Subsequently, for the remaining candidate via array layout solutions that have passed the manufacturing process feasibility assessment, the system calculates a comprehensive evaluation index based on the degree of thermomechanical stress balance and the amount of performance parameter change to scientifically compare the performance of different solutions in multiple dimensions and provide a unified and comprehensive evaluation standard for subsequent screening. Finally, the system selects the optimal solution from the remaining candidate via array layout solutions based on the calculated comprehensive evaluation index as the target via array layout solution. This screening process ensures that the final selected solution not only excels in electrical performance and thermomechanical reliability, but also fully meets the actual manufacturing process requirements. This combination enables optimization design to move beyond the theoretical level and generate a via array layout solution that can be directly applied to actual production. This avoids the problem of optimization results not being implemented or requiring extensive manual intervention, significantly improving the practicality and efficiency of high-voltage PCB current path optimization design.

[0032] In a specific embodiment, when selecting a target solution from multiple candidate via array layouts, the following approach can be used. First, during the manufacturing process feasibility assessment step, a series of manufacturing process constraint parameters can be preset. For example, the minimum hole diameter can be set to 0.2 mm, the minimum hole spacing can be set to 0.4 mm, and the minimum line width can be set to 0.1 mm. The system can use automated design rule checking (DRC) software to scan each candidate via array layout to check whether it meets these preset geometric dimensions and spacing requirements. Any solution that does not meet these parameters (for example, a solution with a via diameter less than 0.2 mm or a center-to-center spacing of adjacent vias less than 0.4 mm) is marked as not manufacturing feasible and removed from the candidate list. Next, a comprehensive evaluation metric is calculated for the remaining candidate via array layouts that pass the manufacturing process feasibility assessment. For example, a weight is assigned to the degree of thermomechanical stress balance and another weight is assigned to the amount of performance parameter change. The weighted sum of the two is then used to obtain the final comprehensive evaluation metric. The weights can be determined based on the emphasis on reliability and electrical performance in the actual application. Finally, the system can filter out the target via array layout scheme from the remaining candidate via array layout schemes based on the comprehensive evaluation index. For example, if the comprehensive evaluation index is as small as possible (for example, representing the comprehensive amount of stress imbalance and performance degradation), the scheme with the smallest comprehensive evaluation index is selected as the target via array layout scheme. If the comprehensive evaluation index is as large as possible (for example, representing the superiority of comprehensive performance), the scheme with the largest comprehensive evaluation index is selected. This scheme introduces a manufacturing process feasibility assessment in the process of screening the target via array layout scheme, and ensures the actual manufacturability of the selected scheme by screening based on the comprehensive evaluation index. Therefore, this embodiment can avoid the situation of generating optimization schemes that cannot be actually applied, thereby reducing the need for subsequent manual intervention and adjustment, thereby effectively improving the practicality and efficiency of the optimized design. In addition, this embodiment can avoid invalid calculations and evaluations of these schemes by excluding non-manufacturable schemes in the early stages, thereby improving the efficiency of the entire optimization process.

[0033] In some preferred embodiments, step A42 includes: A421, obtain the preset operating condition information of the PCB substrate; A422. Determine, based on preset operating condition information, a first weighted weight corresponding to the degree of thermomechanical stress balance and a second weighted weight corresponding to the performance parameter change; A423. For each remaining candidate via array layout scheme, a comprehensive evaluation index is calculated based on the degree of thermomechanical stress balance, the change in performance parameters, the first weighted weight, and the second weighted weight.

[0034] Preset operating condition information refers to data about the operating environment and load conditions of a PCB substrate that is pre-set or acquired in real time before its actual application or during operation. It can be characterized by parameters including operating temperature range, current load, vibration frequency and amplitude, humidity, and heat dissipation conditions. The first weighted weight and the second weighted weight refer to numerical factors used to adjust the relative importance of the degree of thermomechanical stress balance and the change in performance parameters in the calculation of comprehensive evaluation indicators. They can be determined using a rule-based lookup table, an expert system, or a machine learning model generated based on historical data and operating condition information. The comprehensive evaluation index refers to a quantitative value used to comprehensively measure the overall performance of different candidate via array layout schemes under specific operating conditions. It can be calculated using weighted summation, weighted product, or other multi-objective decision-making methods to reflect the comprehensive performance of thermomechanical reliability and electrical performance.

[0035] This application proposes an improved method for calculating comprehensive evaluation indicators. First, by acquiring preset operating condition information for a PCB substrate, important contextual data is provided for the subsequent evaluation process. This operating condition information is the basis for determining the performance and reliability priorities of a via array in actual applications. Subsequently, the system dynamically determines a first weighted value corresponding to the degree of thermomechanical stress balance and a second weighted value corresponding to the change in performance parameters based on the preset operating condition information. This dynamic adjustment mechanism eliminates static, blanket evaluation and allows adjustments to the emphasis on thermomechanical reliability and electrical performance based on specific application scenarios. For example, in operating conditions with high thermomechanical reliability requirements, the first weighted value can be set to a higher value to ensure that the via array can withstand extreme temperature cycling or vibration; whereas in operating conditions with high electrical performance requirements, the second weighted value can be set to a higher value to optimize current transfer efficiency and signal integrity. Then, for each candidate via array layout solution that has undergone a manufacturing process feasibility assessment, the final comprehensive evaluation indicator is calculated by combining the degree of thermomechanical stress balance, the change in performance parameters, and the first and second weighted values ​​dynamically determined based on the current operating conditions. This weighted calculation method ensures that the comprehensive evaluation index accurately reflects the actual performance of each candidate solution under specific operating conditions. In this way, subsequent screening steps can be based on a targeted and accurate comprehensive evaluation index, thereby identifying, from among numerous candidate solutions, the via array layout solutions that perform well and have high reliability under specific operating conditions. This not only improves the optimization effect of the layout solution, but also ensures that the final design is better suited to the needs of the actual application, effectively solving the problem of inaccurate evaluation and poor optimization results caused by the failure to fully consider actual operating conditions in traditional methods.

[0036] In a specific embodiment, the preset operating condition information of the PCB substrate can be obtained through a user interface input. For example, a designer can manually select a preset mode such as "high temperature and high humidity environment," "high frequency signal transmission," or "high current pulse load." The first and second weights can be determined based on the obtained preset operating condition information using a rule-based lookup table or dynamically generated through an expert system. The lookup table is as follows: if the operating condition information indicates "high temperature cycling," the first weight is set to 0.7 and the second weight is set to 0.3 to prioritize thermomechanical stress balance; if the operating condition information indicates "high frequency signal transmission," the first weight is set to 0.3 and the second weight is set to 0.7 to prioritize electrical performance parameter changes. For each remaining candidate via array layout solution, a weighted summation method is used to calculate a comprehensive evaluation index, i.e., the calculation formula for the comprehensive evaluation index is: Comprehensive evaluation index = (first weight × degree of thermomechanical stress balance) + (second weight × performance parameter change). By obtaining preset operating condition information for the PCB substrate and dynamically determining weighted values ​​corresponding to the degree of thermomechanical stress balance and performance parameter changes based on this information, this embodiment can make the calculation of comprehensive evaluation indicators more consistent with actual operating requirements. Therefore, this embodiment can overcome the limitations of traditional fixed-weight evaluations and ensure that the emphasis on the thermomechanical reliability and electrical performance of the via array can be adaptively adjusted under different operating environments. Therefore, this application can screen out a target via array layout solution suitable for specific operating conditions, thereby improving the optimization effect of the final layout solution and enhancing the reliability and performance of the PCB substrate in actual applications.

[0037] In some preferred embodiments, the process of obtaining the degree of thermomechanical stress balance according to the second thermomechanical stress distribution includes: B1. Obtaining stress values ​​of each via according to the second thermomechanical stress distribution; B2. Calculate the stress standard deviation based on all stress values; B3. Determine the degree of thermomechanical stress equilibrium based on the stress standard deviation and the maximum stress value.

[0038] Since the second thermomechanical stress distribution reflects the overall stress state of the via array under this layout scheme, this embodiment can refine the overall stress distribution to each independent via by obtaining the stress value of each via based on the second thermomechanical stress distribution, thereby being able to analyze the stress condition of a single via, which is a prerequisite for accurately evaluating stress uniformity. On this basis, this embodiment quantifies the degree of discreteness of the stress distribution in the via array by calculating the stress standard deviation. Specifically, the standard deviation is an indicator of data volatility in statistics. The smaller the stress standard deviation, the closer the stress value of each via is to the average value, that is, the more uniform the stress distribution; conversely, the larger the standard deviation, the more uneven the stress distribution. This step directly provides the key parameter for measuring the degree of balance and solves the problem of how to objectively evaluate stress uniformity. Finally, even if the standard deviation is small, reliability issues may arise if all stress values ​​are extremely high. Therefore, this embodiment effectively avoids the situation where relying solely on the standard deviation is insufficient to fully assess the degree of balance by determining the degree of thermomechanical stress balance based on the stress standard deviation and the maximum stress value. That is, this embodiment considers both the concentration trend (reflected by the standard deviation) and the extreme values ​​(reflected by the maximum value) of the stress distribution when determining the degree of thermomechanical stress balance, thereby providing a more comprehensive and robust thermomechanical stress balance indicator, thereby optimizing the overall design of the high-voltage PCB current path.

[0039] In some preferred embodiments, step S3 includes: S31, obtaining spatial position information, power dissipation characteristics, and thermal boundary conditions of power devices in the area where the via array is located; S32. Obtaining external heat flux density distribution according to spatial position information, power dissipation characteristics, and thermal boundary conditions; S33, obtaining an internal heat generation rate distribution according to the current distribution and the resistivity of the via array; S34. Obtain the temperature field distribution of the via array according to the external heat flux density distribution, the internal heat generation rate distribution, and the thermal conductivity of the PCB substrate.

[0040] The spatial position information of a power device refers to its specific coordinates, dimensions, and relative positional relationship with the via array on the PCB. This information can be obtained using CAD design files, layout databases, or 3D scanning data. The power dissipation characteristics refer to the amount of heat generated by a power device during operation and how it changes over time or under operating conditions. This information can be obtained using device datasheets, actual test data, or simulation models. Thermal boundary conditions refer to the heat exchange patterns and parameters between the via array and its surroundings, such as ambient temperature, convective heat transfer coefficient, radiative heat transfer coefficient, or contact thermal resistance. This information can be determined using environmental parameter settings, experimental measurements, or standard specifications. The external heat flux density distribution refers to the distribution of heat per unit area transferred from a heat source external to the via array (such as a power device) to the via array region. This embodiment can be obtained using thermal simulation software, infrared thermal imager measurements, or theoretical formula derivation. External heat flux density distribution. The internal heat generation rate distribution refers to the heat distribution per unit volume or per unit area inside the via array due to the Joule heating effect when current flows through the via array. This embodiment can use electrical simulation results combined with material resistivity calculations or local temperature sensor array measurements to obtain the internal heat generation rate distribution.

[0041] This application refines the steps for obtaining the temperature field distribution of a via array, aiming to comprehensively consider the various heat sources that affect the temperature field of the via array, thereby obtaining a more realistic and accurate temperature field distribution. Specifically, first, the main external heat sources are identified and quantified by obtaining the spatial position information, power dissipation characteristics, and thermal boundary conditions of the power devices within the area where the via array is located. Since the layout, heat generation, and heat exchange between the power devices and the surrounding environment directly determine their thermal impact on the via array, this information is the basis for evaluating external thermal effects. Second, the external heat flux density distribution is calculated based on this power device thermal information (spatial position information, power dissipation characteristics, and thermal boundary conditions) to quantify how external heat is transferred to the via array area. At the same time, to fully consider all heat sources, this application obtains the internal heat generation rate distribution based on the current distribution and the resistivity of the via array. The internal heat generation rate distribution reflects the Joule heating effect generated when current flows through the via array itself, ensuring an accurate assessment of the heating generated by the via array itself. Finally, the obtained external heat flux density distribution and internal heat generation rate distribution are coupled and combined with the thermal conductivity of the PCB substrate to perform a comprehensive heat conduction calculation, thereby obtaining the temperature field distribution of the via array. This method of comprehensively considering internal and external heat sources enables the obtained temperature field distribution to more realistically reflect the actual operating temperature of the via array in the high-voltage PCB, thereby effectively improving the accuracy and reliability of the first thermomechanical stress distribution. In the entire high-voltage PCB current path optimization design method, an accurate temperature field is a prerequisite for accurately evaluating the thermomechanical stress of the via array, and accurate stress evaluation is the key to guiding layout parameter adjustments and achieving optimized design. Therefore, this example can more effectively identify potential stress concentration areas and guide layout adjustments by providing a more comprehensive temperature field model, thereby fundamentally improving the long-term reliability of the high-voltage PCB design and avoiding via failure problems caused by thermomechanical stress.

[0042] In a specific embodiment, obtaining the spatial position information, power dissipation characteristics, and thermal boundary conditions of the power devices within the area where the via array is located can be achieved by: deriving the precise coordinates and dimensions of the power devices from PCB design software (e.g., Altium Designer or Cadence Allegro), obtaining the spatial position information, and consulting the power dissipation characteristics of the power devices' manufacturer's datasheets. Based on expert experience, thermal boundary conditions are set according to the system environment in which the PCB is located. For example, if the PCB is installed in a chassis with forced air cooling, the convective heat transfer coefficient and ambient temperature can be set; if a heat sink is present, the thermal resistance and radiation characteristics of the heat sink can be considered. Professional computational fluid dynamics (CFD) or finite element analysis (FEA) thermal simulation software is then used to establish a PCB-level thermal model based on the spatial position, power dissipation, and thermal boundary conditions of the power devices. Simulation calculations are then performed to determine the heat flux density distribution transferred from the power devices to the surrounding PCB area, thereby obtaining the external heat flux density distribution. At the same time, electrical simulation tools (such as SPICE or Ansys Maxwell) are first used to simulate the current distribution of the via array to obtain the current density distribution of each via or via area. Then, Joule's law is used to calculate the heat generation rate distribution within the via array based on the resistivity of the via material and the current density distribution. Finally, when obtaining the temperature field distribution of the via array, the external heat flux density distribution and internal heat generation rate distribution obtained above are used as heat source inputs. Combined with the thermal conductivity of the PCB substrate (including in-plane and vertical thermal conductivity), thermal analysis of the via array area is performed using thermal conduction simulation software (such as a thermal analysis tool based on the finite element method). By solving the heat conduction equation, the three-dimensional temperature field distribution of the via array is obtained under the coupling of internal and external heat sources, thereby providing accurate temperature data for subsequent stress analysis. This application not only considers the heat generated by current within the via array when acquiring the temperature field distribution of the via array, but also takes into account external heat sources such as power devices within the region where the via array is located. This embodiment can therefore obtain a more comprehensive and accurate temperature field distribution of the via array, enabling the temperature field model to more realistically reflect the actual operating thermal environment of the via array in a high-voltage PCB. This provides a more reliable temperature input for subsequent thermomechanical stress analysis, thereby improving the accuracy and reliability of the entire high-voltage PCB current path optimization design method and effectively preventing via failures caused by thermomechanical stress.

[0043] In some preferred embodiments, the thermal conductivity includes an in-plane thermal conductivity and a vertical thermal conductivity perpendicular to the PCB substrate, and step S34 includes: S341, dividing the area where the via array is located into multiple sub-areas; S342. For each sub-region, obtain the heat generation amount based on the external heat flux density distribution and the internal heat generation rate distribution, and then obtain the temperature value of the sub-region based on the heat generation amount, the in-plane thermal conductivity, and the vertical thermal conductivity; S343. Integrate all temperature values ​​to obtain the temperature field distribution of the via array.

[0044] The in-plane thermal conductivity refers to the heat conduction capability of the PCB substrate in the direction parallel to its surface, which can be expressed by the thermal conductivity along the X-axis and Y-axis. The vertical thermal conductivity perpendicular to the PCB substrate refers to the heat conduction capability of the PCB substrate in the direction perpendicular to its surface, which can be expressed by the thermal conductivity along the Z-axis. Dividing the area where the via array is located into multiple sub-areas means discretizing the physical space occupied by the via array into a series of smaller, interconnected calculation units, which can be achieved by numerical discretization methods such as finite element meshing, finite difference meshing, or boundary element meshing. Heat generation refers to the total heat energy generated in a certain sub-area due to the action of current passing through a resistor or an external heat source during a specific time period. This embodiment can obtain the heat generation by integrating or summing the volume of the sub-area, the internal heat generation rate distribution, and the external heat flux density distribution.

[0045] The operating logic of this solution is to first clarify that thermal conductivity includes in-plane thermal conductivity and vertical thermal conductivity perpendicular to the PCB substrate. This assumption reflects the fact that PCB materials have different thermal conductivity capabilities in different directions. By distinguishing these two thermal conductivities, it is possible to more realistically simulate the heat conduction path within the PCB. This is especially true in complex structures such as via arrays, where heat can diffuse along the PCB layers or be conducted vertically through the vias. This consideration of anisotropic thermal conductivity enables temperature field calculations to more accurately reflect the spatial distribution and dissipation of heat, providing a more precise physical model for identifying local hotspots. Furthermore, the area containing the via array is divided into multiple sub-areas, a key prerequisite for resolving the local hotspot problem. Because current distribution within the via array is uneven, resulting in highly uneven local heat generation, this embodiment subdivides the entire area into smaller sub-areas, allowing subsequent temperature calculations to be tailored to the specific heat load of each local area. This avoids the problem of treating the entire array as a homogeneous body and masking local differences, and lays the foundation for capturing microscopic temperature variations. Subsequently, for each sub-region, the heat generation amount is obtained based on the external heat flux density distribution and internal heat generation rate distribution in which it is located. Then, the temperature value of the sub-region is obtained based on the heat generation amount, the in-plane thermal conductivity, and the vertical thermal conductivity. By utilizing the external heat flux density and internal heat generation rate unique to each sub-region (these heat generation rates directly reflect the uneven current distribution), the actual heat load of the sub-region can be accurately calculated. On this basis, the temperature of each sub-region is independently calculated in combination with the in-plane thermal conductivity and vertical thermal conductivity introduced earlier. This localized and refined calculation method fully considers the locality of the heat source and the anisotropy of the material's thermal conductivity. Therefore, this embodiment can make the temperature value of each sub-region highly close to the actual situation, thereby accurately identifying the microscopic hot spots in the via array and their precise location and intensity. Finally, all temperature values ​​are integrated to obtain the temperature field distribution of the via array. By integrating the precise temperature values ​​of all sub-regions, a comprehensive, high-resolution temperature field distribution map of the via array is ultimately formed. This temperature field distribution map not only displays the overall temperature trend but, more importantly, clearly reveals the location of local hotspots and temperature peaks, providing more accurate and reliable input data for subsequent thermomechanical stress analysis. In this way, this solution is closely integrated with the steps of obtaining the external heat flux density distribution and the internal heat generation rate distribution, making the entire temperature field acquisition process more accurate and detailed, thus providing a more reliable foundation for subsequent thermomechanical stress analysis and layout optimization, thereby improving the long-term reliability of high-voltage PCBs.

[0046] In one specific embodiment, to obtain the temperature field distribution of a via array, the thermal conductivity of the PCB substrate in the XY plane and in the Z direction is first obtained from the material supplier. Next, the area containing the via array is meshed using computer-aided design (CAD) software or specialized simulation tools. For example, a quadrilateral or triangular finite element mesh can be used to discretize the entire area into multiple sub-regions. For each sub-region, the heat generation is calculated based on its specific location in the PCB layout, the external heat flux density distribution, and the internal heat generation rate distribution. For example, if a sub-region is located in a high current path, its internal heat generation rate will be higher, resulting in higher heat generation. Subsequently, the stable temperature value of the sub-region is calculated using a heat conduction equation (such as Fourier's law or the energy conservation equation) based on the heat generation, in-plane thermal conductivity, and perpendicular thermal conductivity of the sub-region using a numerical solution method (such as the finite element method or the finite difference method). During the calculation process, a conduction matrix that takes into account anisotropic thermal conductivity can be constructed, and the thermal conductivity coefficients in the plane and perpendicular direction can be substituted separately to accurately simulate the transfer of heat in different directions. Finally, the temperature values ​​calculated in all sub-areas are integrated, for example, these discrete temperature values ​​are mapped into a continuous temperature field map, or a three-dimensional temperature distribution model is generated to obtain the temperature field distribution of the entire via array. This integrated temperature field distribution can be presented in the form of a color isotherm map or a heat map, intuitively showing the temperature conditions at various locations in the via array. This embodiment significantly improves the accuracy of temperature field modeling by introducing anisotropic thermal conductivity and a calculation method for regional division, so that the system can more accurately identify and quantify microscopic hot spots in high-voltage PCBs. Therefore, this embodiment can overcome the problem that the temperature field calculation results of traditional methods deviate from the actual situation due to simplified processing, thereby more effectively predicting and evaluating the thermomechanical stresses that the via array may face in actual operation, thereby guiding layout optimization and fundamentally improving the long-term reliability of high-voltage PCBs.

[0047] In some preferred embodiments, step S4 includes: S41, obtaining a thermal expansion difference between the via array and the PCB substrate according to the temperature field distribution, the thermal expansion coefficient of the via array, and the thermal expansion coefficient of the PCB substrate; S42 , calculating the strain and stress of the via array according to the thermal expansion difference, the elastic modulus of the via array, and the elastic modulus of the PCB substrate to obtain a first thermomechanical stress distribution of the via array.

[0048] Thermal expansion difference refers to the inconsistency in the size or volume change of two or more different materials when they experience the same temperature change due to their different inherent thermal expansion coefficients. In this embodiment, the thermal expansion difference can be obtained by measuring the thermal expansion coefficient of each material through material science experiments and performing theoretical calculations based on the temperature change range. Strain refers to the degree of deformation of a material under the action of external loads or internal stresses. The strain is usually expressed as the deformation per unit length and can be calculated using geometric deformation analysis or continuum mechanics models. Stress refers to the internal force per unit area within a material. Stress is a measure of the material's resistance to deformation and can be calculated using mechanical equilibrium equations or constitutive relationships.

[0049] This embodiment first determines the thermal expansion differential between the via array and the PCB substrate based on the current temperature field distribution, the thermal expansion coefficient of the via array, and the thermal expansion coefficient of the PCB substrate. This step is a critical prerequisite for understanding and calculating thermomechanical stress. It identifies and quantifies the root cause of thermomechanical stress: the mismatched expansion of two materials due to different thermal expansion coefficients under temperature changes, providing accurate physical input for subsequent stress calculations. Next, this embodiment calculates the strain and stress of the via array based on the thermal expansion differential and the elastic moduli of the via array and the PCB substrate, thereby obtaining a first thermomechanical stress distribution for the via array. The elastic modulus characterizes a material's ability to resist deformation. This embodiment converts the thermal expansion differential into actual mechanical strain and stress by considering the elastic moduli of the two materials, ensuring that the calculated stress distribution accurately reflects the material's mechanical response. This step-by-step calculation approach, starting from the physical root of the thermal expansion differential, gradually derives strain and stress, making the process of obtaining the thermomechanical stress distribution clearer, more scientific, and more accurate. This refined and precise calculation method, combined with the overall optimization design approach, enables subsequent layout optimization to be based on more accurate stress data, effectively identifying potential stress concentration areas and enabling targeted layout adjustments. This fundamentally prevents open via failures caused by thermo-mechanical stress and significantly improves the long-term reliability of high-voltage PCBs.

[0050] In one specific embodiment, to obtain a first thermomechanical stress distribution within the via array, step S41 is performed by a thermal expansion difference calculation unit. This unit can receive temperature field distribution data output by a temperature sensor array or thermal simulation software, as well as pre-stored thermal expansion coefficient data for the via material (e.g., copper) and the PCB substrate material (e.g., FR-4). Based on these inputs, this unit can use a thermal expansion formula to calculate the expansion of the vias and substrate at different temperatures, thereby obtaining the expansion difference between them. Subsequently, step S42 is performed by a stress-strain calculation unit. This unit can receive the thermal expansion difference data and pre-stored elastic moduli of the via material and the PCB substrate material. This unit can also use the stress-strain relationship in material mechanics to calculate the strain and stress distribution within the via array under the action of mismatched expansion. For example, finite element analysis (FEA) software is used to establish a geometric model of the vias and the PCB substrate. The thermal expansion difference is applied to the model as a boundary condition or load, and the elastic modulus of the material is input. Through simulation calculation, the stress field distribution within the via array is obtained, thereby obtaining the first thermomechanical stress distribution.

[0051] Second, as Figure 2 As shown, the present application also provides a high-voltage PCB current path optimization design system based on a large model, which includes: Information acquisition module 1, used to obtain electrical parameters of the high-voltage PCB current path and initial layout information of the via array; Current distribution acquisition module 2, used to obtain the current distribution of the via array according to electrical parameters and layout information using an electrical simulation model; The temperature field distribution acquisition module 3 is used to obtain the temperature field distribution of the via array according to the current distribution, the resistivity of the via array and the thermal conductivity of the PCB substrate; A stress distribution acquisition module 4 is configured to acquire a first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; The layout optimization module 5 is used to analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information and trigger the current distribution acquisition module 2 to run.

[0052] A large-model-based high-voltage PCB current path optimization design system provided in this application includes an information acquisition module 1, a current distribution acquisition module 2, a temperature field distribution acquisition module 3, a stress distribution acquisition module 4, and a layout optimization module 5. The large-model-based high-voltage PCB current path optimization design system provided in this embodiment is used to execute the steps of the large-model-based high-voltage PCB current path optimization design method provided in the first aspect above. The principles of the large-model-based high-voltage PCB current path optimization design system provided in this embodiment are the same as those of the large-model-based high-voltage PCB current path optimization design method provided in the first aspect above, and will not be discussed in detail here.

[0053] As can be seen from the above, the present application provides a large-model-based high-voltage PCB current path optimization design method and system. By coupling electrical simulation, thermal simulation, and mechanical simulation, and introducing an iterative optimization mechanism to solve the local hot spots and thermo-mechanical stress problems caused by uneven current distribution in the high-voltage PCB via array, it achieves an integrated optimization design of electrical performance, thermal performance, and mechanical reliability, thereby effectively improving the long-term reliability of the high-voltage PCB.

[0054] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another robot, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0055] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0056] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0057] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A high-voltage PCB current path optimization design method based on a large model, characterized in that: The large model-based high-voltage PCB current path optimization design method includes the following steps: S1. Obtaining electrical parameters of the high-voltage PCB current path and initial layout information of the via array; S2. Obtaining a current distribution of the via array according to the electrical parameters and the layout information using an electrical simulation model; S3. Obtaining a temperature field distribution of the via array according to the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate; S4. Obtaining a first thermomechanical stress distribution of the via array according to the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, use the new layout information as the final layout information of the via array. If not, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain new layout information, and return to step S2.

2. The large model-based high-voltage PCB current path optimization design method according to claim 1, characterized in that: The layout parameters include the relative positions of the vias, the via spacing, and the overall shape of the via array.

3. The large model-based high-voltage PCB current path optimization design method according to claim 1, characterized in that: The process of adjusting the layout parameters of the via array according to the first thermomechanical stress distribution includes: A1. Obtaining the first electrical performance parameter of the current via array; A2. generating a plurality of candidate via array layout solutions according to the first thermomechanical stress distribution; A3. For each candidate via array layout solution, obtain a second electrical performance parameter and a second thermomechanical stress distribution corresponding to the candidate via array layout solution, then calculate a performance parameter change based on the first electrical performance parameter and the second electrical performance parameter, and obtain a degree of thermomechanical stress balance based on the second thermomechanical stress distribution; A4. Filtering a target via array layout solution from all the candidate via array layout solutions according to the degree of thermomechanical stress balance and the variation of the performance parameters, and adjusting the layout parameters of the via array according to the target via array layout solution.

4. The large model-based high-voltage PCB current path optimization design method according to claim 3, characterized in that: Step A4 includes: A41. Evaluate the manufacturing process feasibility of each candidate via array layout solution according to preset manufacturing process constraint parameters, and then remove candidate via array layout solutions that are evaluated as not having manufacturing process feasibility, wherein the preset manufacturing process constraint parameters include a minimum aperture, a minimum hole spacing, and a minimum line width; A42. For each of the remaining candidate via array layout solutions, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance and the change in performance parameters; A43. Filter out a target via array layout solution from the remaining candidate via array layout solutions according to the comprehensive evaluation index.

5. The large model-based high-voltage PCB current path optimization design method according to claim 4, characterized in that: Step A42 includes: A421. Obtaining preset operating condition information of the PCB substrate; A422. Determine, based on the preset operating condition information, a first weight corresponding to the degree of thermomechanical stress balance and a second weight corresponding to the performance parameter change; A423. For each of the remaining candidate via array layout solutions, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance, the change in performance parameters, the first weighted weight, and the second weighted weight.

6. The large model-based high-voltage PCB current path optimization design method according to claim 3, characterized in that: The process of obtaining the degree of thermo-mechanical stress balance according to the second thermo-mechanical stress distribution includes: B1. Obtaining a stress value of each via according to the second thermomechanical stress distribution; B2. calculating the stress standard deviation based on all the stress values; B3. Determine the degree of thermomechanical stress balance according to the stress standard deviation and the maximum value of the stress value.

7. The large model-based high-voltage PCB current path optimization design method according to claim 1, characterized in that: Step S3 includes: S31, obtaining spatial position information, power dissipation characteristics, and thermal boundary conditions of power devices within the region where the via array is located; S32. Obtaining external heat flux density distribution according to the spatial position information, the power dissipation characteristics, and the thermal boundary conditions; S33, obtaining an internal heat generation rate distribution according to the current distribution and the resistivity of the via array; S34. Obtain the temperature field distribution of the via array according to the external heat flux density distribution, the internal heat generation rate distribution, and the thermal conductivity of the PCB substrate.

8. The large model-based high-voltage PCB current path optimization design method according to claim 7, characterized in that: The thermal conductivity coefficient includes an in-plane thermal conductivity coefficient and a vertical thermal conductivity coefficient perpendicular to the PCB substrate direction. Step S34 includes: S341, dividing the area where the via array is located into multiple sub-areas; S342. For each sub-region, obtain a heat generation amount based on the external heat flux density distribution and the internal heat generation rate distribution, and then obtain a temperature value of the sub-region based on the heat generation amount, the in-plane thermal conductivity, and the vertical thermal conductivity; S343: Integrate all the temperature values ​​to obtain the temperature field distribution of the via array.

9. The large model-based high-voltage PCB current path optimization design method according to claim 1, characterized in that: Step S4 includes: S41, obtaining a thermal expansion difference between the via array and the PCB substrate according to the temperature field distribution, the thermal expansion coefficient of the via array, and the thermal expansion coefficient of the PCB substrate; S42. Calculate the strain and stress of the via array according to the thermal expansion difference, the elastic modulus of the via array, and the elastic modulus of the PCB substrate to obtain a first thermomechanical stress distribution of the via array.

10. A high-voltage PCB current path optimization design system based on a large model, characterized in that: The large model-based high-voltage PCB current path optimization design system includes: An information acquisition module is used to obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array; a current distribution acquisition module, configured to acquire the current distribution of the via array according to the electrical parameters and the layout information using an electrical simulation model; a temperature field distribution acquisition module, configured to acquire the temperature field distribution of the via array according to the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate; a stress distribution acquisition module, configured to acquire a first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate; A layout optimization module is used to analyze whether the first thermomechanical stress distribution meets preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information, and the current distribution acquisition module is triggered to run.

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