Fault injection test method and device, computer device and storage medium

Abstract

Embodiments of the present application provide a fault injection test method, a fault injection test device, a computer device and a computer storage medium, and relate to the technical field of information security. The method comprises the following steps: a plurality of registers in a to-be-tested chip are configured with the same number of bit positions in advance; for each target bit position in the same position in the plurality of registers, a fault injection operation is performed on each target bit position based on a TSC comparator, to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; if the output value of the fault test result is the first preset value, it is determined that at least one target bit position in the plurality of registers has a functional fault. The present application reduces the workload and time consumption of fault injection testing, thereby improving the error injection operation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of information security, in particular to a fault injection test method, a fault injection test device, a computer device and a computer storage medium. BACKGROUND

[0002] In the field of information security, fault injection testing is an important project in the security testing of cryptographic chips. Fault injection testing is often used to evaluate the security of chips to ensure the correctness of register protection logic. Taking the automotive application field as an example, with the increasing number of electronic controllers (ECU, Electronic Control Unit) of electric vehicles, the complexity and functionality of ECUs are also increasing, and ECUs gradually adopt more highly integrated system architectures, and functional safety has become a basic requirement for the design of automotive ECU systems. Therefore, test fault injection (also known as error injection testing) has become one of the most important tests in the field of automotive functional safety, and for this reason, international standards require fault injection testing to be performed unconditionally on ASIL-B level or higher level controllers.

[0003] In the fault injection method of the related technical solution, a large number of bit positions in all registers in the chip to be tested need to be sequentially injected with errors to determine the fault point. Therefore, the error injection method in the above related technical solution needs to be injected one by one, and the error injection logic area is large, resulting in long error injection time and low efficiency. SUMMARY

[0004] The embodiments of the present application provide a fault injection test method, a fault injection test device, a computer device and a computer storage medium, thereby at least partially overcoming the technical problems of long error injection time and low efficiency caused by the limitations and defects of related technologies when performing fault injection testing.

[0005] The first aspect of the embodiments of the present application provides a fault injection test method, which comprises: pre-configuring a plurality of registers in a chip to be tested as the same number of bit positions; for each target bit position in the same position in the plurality of registers, performing a fault injection operation on each target bit position based on a TSC comparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; if the output value of the fault test result is the first preset value, it is determined that at least one target bit position in the plurality of registers has a functional fault.

[0006] In a second aspect, the application provides a fault injection testing device, comprising: a bit position configuration module configured to pre-configure a plurality of registers in a chip to be tested to be the same number of bit positions; a fault injection module configured to perform a fault injection operation on each target bit position in the same position in the plurality of registers based on a TSC comparator, to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; and a fault determination module configured to determine that at least one target bit position in the plurality of registers has a functional fault if the output value of the fault test result is the first preset value.

[0007] In a third aspect, the application provides a computer device, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of any of the above fault injection testing methods when executing the computer program.

[0008] In a fourth aspect, the application provides a computer readable storage medium, having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the above fault injection testing methods.

[0009] In a fifth aspect, the application provides a computer program product, comprising a computer program, the computer program being executed by a processor to implement the steps of any of the above fault injection testing methods.

[0010] The technical solution of the application has the following beneficial effects:

[0011] The fault injection test method comprises the following steps: configuring a plurality of registers in a chip to be tested as a same number of bit positions; performing a fault injection operation on each target bit position in the same position in the plurality of registers based on a TSC comparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; if the output value of the fault test result is the first preset value, it is determined that at least one target bit position in the plurality of registers has a functional fault. The method configures a plurality of registers as a same number of bit positions (also referred to as target bit positions), so that subsequent parallel fault injection on the target bit positions in the same position in the plurality of registers by the TSC comparator can be facilitated to realize fault detection. On the one hand, since the TSC comparator can be used to simultaneously test all target bit positions in the chip to be tested, the technical barrier that the related technical solutions cannot use parallel fault injection is overcome, and whether there is a fault problem is determined through the fault test result. On the other hand, the scheme avoids the technical problem of long fault injection time consumption and large workload caused by the related technical solutions of testing a large number of registers and a plurality of bit positions of the registers one by one, thereby realizing the technical effect of reducing the workload and time consumption of fault injection test, and improving the test efficiency. On the other hand, only the target bit positions in the same position in all registers in the chip to be tested are parallel fault injected, and in the case that a fault is determined to exist, further positioning of the fault point can be performed subsequently, so that the function protection of the chip to be tested can be better realized. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application, and do not limit the application. In the drawings:

[0013] Figure 1 A flowchart of a fault injection test method provided by an embodiment of the application;

[0014] Figure 2 A flowchart of a method for configuring a plurality of registers as a same number of bit positions provided by an embodiment of the application;

[0015] Figure 3 A fault injection logic diagram when a plurality of registers have virtual bit positions provided by an embodiment of the application;

[0016] Figure 4 A flowchart of another fault injection test method provided by an embodiment of the application;

[0017] Figure 5 A method flow chart for finding a register with a functional fault is provided for an embodiment of the present application;

[0018] Figure 6 A fault injection test device structure schematic diagram is provided for an embodiment of the present application;

[0019] Figure 7 A computer device structure schematic diagram is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0020] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0021] Moreover, the drawings represent a simplified diagram of the disclosure and are not necessarily drawn to scale. Like reference numerals in different drawings denote the same or similar functionalities, and thus repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily have to correspond to physically or logically independent entities. These functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0022] The flow charts shown in the drawings are only illustrative and do not necessarily include all the steps. For example, some steps can be further broken down, and some steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0023] In the relevant technical background, in the field of information security technology, fault injection testing is an important project in the security testing of cryptographic chips. Fault injection testing is commonly used to evaluate the security of chips to ensure the correctness of register protection logic. Fault injection testing is applied in many fields and has become one of the important means for functional safety detection in various industries. Taking the automotive application field as an example, with the increasing number of electronic controllers (ECU, Electronic Control Unit) in electric vehicles, the complexity and functionality of ECUs are also increasing, and ECUs gradually adopt more highly integrated system architectures, and functional safety has become a basic requirement for automotive ECU system design. And through fault injection testing (Test Fault Injection, also known as error injection testing), it has become one of the very important tests in the field of automotive functional safety.

[0024] Generally speaking, the higher the criticality, the less control the driver has over the application on the car, and the higher the inherent risk and the related Automotive Safety Integrity Level (ASIL). It needs to be explained that ASIL is an important part of ISO 26262 compliance, which is used to assess and quantify the risk related to automotive functional safety. Therefore, during the design and development phase of the system, ASIL must be followed, and the planned functions of the system are checked for any potential hazards, the estimate of this risk is based on the exposure probability, the possible controllability of the driver and the severity of the possible consequences when a critical event occurs, thus obtaining ASIL.

[0025] According to the ISO26262 standard, the automotive safety level can be defined as four ASIL levels, ASIL-A, ASIL-B, ASIL-C and ASIL-D, where D represents the highest safety integrity level, and A represents the lowest level. Through these levels, automobile manufacturers can ensure the safety of their products to meet different functional and safety requirements. Based on the ASIL level, the Single-Point Fault Metric (SPFM) and Latent-fault metric (LFM) should be calculated and further satisfied, as shown in Table 1 below:

[0026] Table 1

[0027]

[0028] The SPFM reflects that the correlation item achieves robustness to single point failure and residual failure through safety mechanism coverage or through design means (mainly safety failure); and the LFM reflects that the correlation item achieves robustness to latent failure through safety mechanism coverage, through identification of the driver before the safety target is violated, or through design means (mainly safety failure). The greater the values of the SPFM and the LFM, the higher the proportion of faults that can be diagnosed, and the function safety is to make more faults be diagnosed to ensure the safety of the function.

[0029] For ease of understanding, the following describes a fault injection test (also referred to as an error injection test): the fault injection test is a reliability verification technology that deliberately introduces faults into a system through controlled experiments, and observes the behavior of the system when the faults exist. For this reason, the ISO26262 international standard requires that controllers of ASIL-B level or higher are unconditionally subjected to fault injection tests.

[0030] In related technical solutions, when performing a fault injection test, error injection is usually performed on checks and register bit logic, and error injection is also performed on or reduction logic.

[0031] In terms of the above or reduction logic error injection method, taking a vehicle regulation ASIL-B as an example, in order to make the LFM of the vehicle reach the requirement of at least 60%, a sufficient proportion of inputs need to be injected with errors to determine the location of the fault according to the output result.

[0032] In terms of the check error injection method, assuming that a single register has 32 bits, and taking the register storage protection method of duplication as an example, the number of input bits is 32*2=64 bits. It needs to be explained that the register storage protection method can also be an error-detection and correction (edc) method, a parity method, and the like. Compared with the above-mentioned register storage protection method of duplication, the number of input bits based on a single register is a relatively small number of bits. At this time, the superposition of the number of input bits corresponding to all registers in the chip to be tested has thousands of bits.

[0033] The error injection method of the related technical solution needs to sequentially inject errors to a large number of bits to accurately determine the position of the fault in the chip to be tested. However, the error injection logic area is large, and a large number of inputs need to be injected with errors. This way of sequentially injecting errors will inevitably lead to low error injection efficiency and long time consumption. The related technical solution cannot simultaneously inject errors to a large number of bits, because the tester cannot accurately determine whether a fault occurs or the accurate position of the fault according to the output result.

[0034] For example, assuming that the output result is 0, which represents that a short circuit to ground is detected, and the output result is 1, which represents that a short circuit to high voltage is detected. If a large number of bits are simultaneously injected with errors, for the error injection of the check logic, when the output result is 1, it can be determined that the chip to be tested must have a fault, that is, it is determined that the chip to be tested has a short circuit to ground or a short circuit to high voltage. However, if the output result is 0, it cannot be determined whether the chip to be tested has a fault. For the orreduction register logic, when the output result is 1, it can also be determined that the chip to be tested has a fault, but if a short circuit to ground occurs, the output result is still 0, and it cannot be determined that a fault occurs. In addition, based on the above method, after determining that a fault occurs, the accurate position of the fault cannot be determined, and it is necessary to sequentially inject errors to exclude one by one.

[0035] It can be seen that the fault injection test method of the related technical solution consumes a long time, has a large workload, and has low test efficiency. Therefore, there is an urgent need for a fault injection test method with higher efficiency to realize rapid testing of the chip to be tested or the hardware circuit to be tested.

[0036] To solve the above technical problems, the embodiments of the present application propose a fault injection test method, which can be applied to any application scenario that needs to be tested by fault injection. However, it should be noted that the fault injection test method proposed in the embodiments of the present application can only detect and prevent single-point faults. If two matching bit positions exist faults at the same time, the method cannot test the functional fault.

[0037] Specifically, the method configures a plurality of registers as the same number of bit positions, thereby facilitating subsequent parallel fault injection of target bit positions in the same position in the plurality of registers by the TSC comparator to achieve fault detection. On the one hand, since the target bit positions of the plurality of registers are tested by the TSC comparator at the same time, the technical barrier that the related technical solution cannot use parallel fault injection is overcome, and whether there is a fault problem is determined by the fault test result. On the other hand, the scheme avoids the technical problem of long fault injection consumption time and large workload caused by the related technical solution of testing a large number of registers and a plurality of bit positions of the registers one by one, thereby reducing the workload and time consumption of fault injection testing, and improving the test efficiency. On the other hand, only the target bit positions in the same position in the plurality of registers are parallel fault injected, and further positioning of the fault point can be performed in the case where it is determined that there is a fault, thereby better protecting the function of the chip under test.

[0038] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0039] The following will be combined with Figure 1 The fault injection test method provided by the embodiments of the present application is exemplarily described. Figure 1 The flowchart of the fault injection test method provided by an embodiment of the present application is shown in FIG. 1. Please refer to Figure 1 The fault injection test method provided by the embodiments of the present application can include the following steps 101-103:

[0040] Step 101, a plurality of registers in the chip under test are pre-configured as the same number of bit positions.

[0041] Step 102, for each target bit position in the same position in the plurality of registers, a fault injection operation is performed on each target bit position based on the TSC comparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value.

[0042] Step 103, if the output value of the fault test result is the first preset value, it is determined that at least one target bit position in the plurality of registers has a functional fault.

[0043] In the technical solution provided in some embodiments of the present disclosure, a plurality of registers in a chip to be tested are configured in advance to have the same number of bit positions; for each target bit position in the same position in the plurality of registers, a fault injection operation is performed on each target bit position based on a TSC comparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; if the output value of the fault test result is the first preset value, it is determined that at least one target bit position in the plurality of registers has a functional fault. The method configures the plurality of registers to have the same number of bit positions, thereby facilitating subsequent parallel fault injection of target bit positions in the same position in the plurality of registers by the TSC comparator to achieve fault detection. On the one hand, since the TSC comparator is used to simultaneously inject faults into the target bit positions of the plurality of registers, the technical barrier that the related technical solution cannot use parallel fault injection is overcome, and whether there is a fault problem is determined through the fault test result. On the other hand, this solution avoids the technical problem of long fault injection time and large workload caused by the related technical solution of sequentially injecting faults into a large number of registers and a plurality of bit positions of the registers, thereby reducing the workload and time consumption of fault injection testing and improving the testing efficiency. On the other hand, only the target bit positions in the same position in the plurality of registers are parallel fault injected, and further positioning of the fault point can be performed in the case where a fault is determined to exist, thereby better protecting the function of the chip to be tested.

[0044] The specific implementation of each step in the embodiments will be described in detail below with reference to specific embodiments: Figure 1

[0045] In step 101, a plurality of registers in a chip to be tested are configured in advance to have the same number of bit positions.

[0046] The chip to be tested can be a design chip that needs to be tested for reliability in any application scenario, such as a computer device in the automotive field, medical equipment, aerospace devices, process equipment, mobile phones, etc. Of course, the object to be tested can also refer to a hardware circuit to be tested, and is not limited to a chip. The embodiments provided in the present application take the chip to be tested as an example for description, and the implementation process of fault injection testing of the hardware circuit to be tested is similar and will not be described here.

[0047] ​The to-be-tested chip contains a plurality of registers, which can be registers configured with software, registers reporting hardware states, or other types of registers, and the embodiments of the present application do not make any special limitation on the above. It needs to be explained that the function of a register is to store binary code, which is composed of flip-flops and gate circuits with storage function. A register is usually composed of a plurality of bits, and each bit can be independently read and written to store specific configuration information. The capacity of a register depends on the number of bits it occupies. For example, 32-bit, 64-bit registers, etc.

[0048] It can be understood that the to-be-tested chip contains a plurality of registers, and the plurality of registers in step 101 can be all the registers in the to-be-tested chip, or part of the registers that the user needs to test, and the embodiments of the present application do not make any special limitation thereon.

[0049] For example, before performing the fault injection test, each register in the to-be-tested chip needs to be configured with the same number of bits, so that subsequent simultaneous fault injection tests can be performed on the bits in the same position in the plurality of registers, thereby achieving the technical effect of improving the fault injection test efficiency. For example, the to-be-tested chip contains register a, register b, and register c, and the corresponding bit positions are 16 bits, 32 bits, and 32 bits, respectively. Before the fault injection test, the bit position of register a is configured to be the same as that of register b and register c, i.e., 32 bits.

[0050] The following will be described in combination with Figure 2 The step of step 101 of pre-configuring the plurality of registers in the to-be-tested chip with the same number of bits will be described exemplarily.

[0051] Figure 2 A method flowchart for configuring a plurality of registers with the same number of bits is provided for an embodiment of the present application. In an optional embodiment of the present application, the method comprises the following steps 201 to 202:

[0052] Step 201, obtaining a target bit position number of a first register in the plurality of registers.

[0053] Step 202, based on the target bit position number of the first register, adding virtual bits to a second register in the plurality of registers to obtain a third register, so that the third register has bits with the target bit position number.

[0054] The first register is the register with the largest number of bits among the plurality of registers, and the second register is the register with a number of bits less than the target number of bits among the plurality of registers. For example, the plurality of registers in the chip to be tested include register a, register b, and register c, and the corresponding bit numbers are 16 bits, 32 bits, and 64 bits, respectively. In this embodiment, the first register is the 64-bit register, and the second register is the 16-bit or 32-bit register.

[0055] For example, in the step of implementing step 101, the plurality of registers in the chip to be tested are configured to have the same number of bits, and the bit number of the second register is increased or supplemented according to the target number of bits of the first register, so that the third register obtained after the virtual bit number is increased also has a bit number of the target number of bits. For example, the 16-bit and 32-bit registers b and c are increased in the virtual bit number, so that the register a, the register b, and the register c included in the chip to be tested all have 64 bits.

[0056] In this embodiment, the virtual bit number is added to the register with a smaller number of bits, so that the bit numbers of all the registers included in the chip to be tested are consistent, facilitating subsequent parallel fault injection on the target bits at the same position and improving the fault injection efficiency.

[0057] In addition to the above embodiment, the first register with a larger number of bits can also be trimmed according to the second register with the smallest number of bits, so as to configure the plurality of registers to have the same number of bits, and the present embodiment does not make any special limitation on this. For this embodiment, the bit number of the trimmed register can be small, and the register can be tested by separate fault injection.

[0058] In step 102, for each target bit at the same position in the plurality of registers, a fault injection operation is performed on each target bit based on a TSC comparator, to obtain a fault test result. The output value of the fault test result is a first preset value or a second preset value.

[0059] The output value of the fault test result has only two values, i.e., the output value of the fault test result can only be the first preset value or the second preset value. When the first preset value is 0, the second preset value is 1. Of course, when the first preset value is 1, the second preset value is 0. It should be explained that the value of the output result needs to be pre-established to have a mapping relationship with the fault test result. For example, 0 represents a short-circuit ground fault, and 1 represents no fault. When the fault detection result output by the fault injection test is 1, it represents no fault. Otherwise, there is a short-circuit ground fault.

[0060] In the embodiment, the first preset value corresponds to detecting a functional failure, and the second preset value corresponds to not detecting a functional failure.

[0061] The TSC comparator can implement a parallel fault injection function. In addition, the TSC comparator has a self-checking function, that is, the TSC comparator can perform self-checking on the fault injection logic when performing the parallel fault injection. Since the more bits of each register in the chip to be detected, the larger the area of the fault injection logic occupied, the detection workload of the fault injection logic is large, time-consuming and prone to errors, and the self-checking function of the TSC comparator can realize automatic detection of the fault injection logic, thereby improving the efficiency of the fault injection operation and improving the accuracy of the fault injection operation.

[0062] For example, after the number of bits of each register is made the same in step 101, the fault injection operation can be performed on each target bit at the same position in all registers based on the TSC comparator to obtain the fault detection result of the target bit.

[0063] For ease of illustration, the determination of the target bits at the same position will be exemplarily described below in combination with specific embodiments.

[0064] In an optional embodiment of the present disclosure, for each register in the chip to be tested, a number is added to each bit in the register according to a preset numbering sequence to obtain the numbering identification of each bit in the register; and the bits with the same numbering identification in the plurality of registers are determined as the target bits at the same position in the plurality of registers.

[0065] The preset numbering sequence can be adding numbers to the plurality of bits in the register in an order from top to bottom or from left to right.

[0066] For example, the same preset numbering sequence can be used to add numbers to the plurality of bits in each register in the chip to be tested to obtain the numbering identification of each bit in the register. At this time, each register contains bits with the same numbering identification, and the bits with the same numbering identification can be determined as the target bits at the same position in the plurality of registers, and then the parallel fault injection operation is performed based on the bits with the same numbering identification to obtain the corresponding fault test result.

[0067] In the embodiment, the method for adding numbers to the plurality of bit positions in the registers in the preset number order to identify the same bit positions in the plurality of registers as the target bit positions in the same position facilitates quick determination of the target bit positions in the same position in the plurality of registers and is less prone to errors, thereby improving the accuracy of the error injection operation.

[0068] In addition, in the above embodiment, in the case where the number of bit positions in each register in the chip to be tested is the same and the virtual bit position is included when the fault injection operation is performed, the embodiment of step 102 can be performed based on the following embodiment in the case where the virtual bit position is included:

[0069] In an optional embodiment of the present disclosure, based on the third register obtained in the above embodiment, no fault injection operation is performed on the virtual bit position in the third register, and the output value of the virtual bit position is the second preset value.

[0070] For example, when the TSC comparator does not perform the error injection operation on the extended virtual bit, the output value of the virtual bit position is the second preset value, which can avoid the situation where the output value of the virtual bit position is normal instead of the fault alarm state when no error injection operation is performed on the virtual bit position.

[0071] Based on the above embodiment, when the TSC comparator performs the fault injection operation on each target bit position to obtain the fault test result in step 102, the output value of the fault test result obtained by performing the fault injection operation on each target bit position based on the TSC comparator is the first preset value, and each target bit position includes the virtual bit position in the third register.

[0072] For example, the TSC comparator can perform the parallel error injection operation on each target bit position in the same position / number in the plurality of registers. Since the virtual bit position is included in each target bit position, the first preset value of the corresponding target bit position of the plurality of registers is obtained. For the virtual bit position of the third register, the default state is no function, and the output value of the corresponding target bit position of the virtual bit position after the error injection operation is the first preset value. At this time, the second output value of the third register is logically ORed with the output values of the other registers, so that the output values of the other registers are the test results of the functional fault regardless of the first preset value or the second preset value. Thus, only the other registers without the virtual bit position can be sequentially fault detected. Compared with the one-by-one detection method of the related art, the workload is smaller.

[0073] The following will be described in combination withFigure 3 The embodiment shown illustrates the process.

[0074] Figure 3 This is a schematic diagram of a fault injection logic when virtual bits exist in multiple registers, provided by one embodiment of the present application. Figure 3 , the original check logic (i.e. check logic) corresponding to other registers is combined with the output value of the virtual bit corresponding to the third register ( Figure 2 The virtual box shown in the figure serves as the input to the OR gate. After the error injection operation is performed on the virtual bit, the resulting output value is a first preset value (indicating a functional failure). The original check logic corresponds to the logic for testing actual bits in the register, while the conversion logic is based on forced conversion logic for virtual bits that do not exist in the third register, ensuring that the output value is the first preset value. After passing through the OR gate, the final fault detection result output value always remains the first preset value.

[0075] The check logic contains two inputs: one is the actual bit input of other registers, and the other is the register protection generator module of the corresponding register.

[0076] This process can put the area of ​​the error injection logic into the register protection, thereby reducing the time consumption of the error injection operation and improving the error injection efficiency.

[0077] In another optional embodiment of the present disclosure, the initial output value of the virtual bit of the third register can be set to a first preset value (indicating a functional failure), and then a second preset value (indicating a functional failure) can be displayed after the fault injection operation. In this case, the register displaying the second preset value is ignored, and the fault injection operation is performed only on the register corresponding to the first preset value to analyze whether a fault problem exists.

[0078] In step 103 , if the output value of the fault test result is a first preset value, it is determined that a functional fault exists in at least one target bit in the plurality of registers.

[0079] The preset value is set by the developer in advance, for example, it can be 1 or 0. When the first preset value is 1, the second preset value is 0; conversely, if the first preset value is 0, the second preset value is 1. The first preset value indicates the presence of a fault, and the corresponding second preset value indicates the absence of a fault.

[0080] For example, if the output value of the fault test result is the first preset value, it indicates that the target bit corresponding to at least one register among all registers has a functional fault, causing the output value to be the first preset value. Through this process, it can be determined that there is a fault point in the target bit corresponding to the register.

[0081] In addition to the embodiment of step 103, the opposite case of step 103 is also included, that is, referring to Figure 4 the step 104 in the step 103: if the output value of the fault test result is the second preset value, it is determined that each target bit in the plurality of registers does not exist functional failure, and the fault injection operation is continued on other target bit in the same position in the plurality of registers.

[0082] For example, if the first preset value is 0 and the second preset value is 1, if the output value of the fault test result is 1, it indicates that all target bits corresponding to the registers have no failure, and the next target bit in the same position in the plurality of registers can be fault injected, and the parallel fault injection process is continued until all bits in all registers are detected. Conversely, if the output value of the fault test result is 0, it indicates that the target bit corresponding to the register has a fault.

[0083] In this embodiment, the output value of the fault test result can quickly determine whether there is a fault, and the efficiency of the fault injection test is improved.

[0084] Further, when the output value of the fault test result is the first preset value in step 103, it is determined that at least one target bit in the plurality of registers has a functional failure, and the specific faulty register can be further determined for subsequent maintenance and other operations. The present application will be described by the following embodiments:

[0085] In the related technical solutions, there are a large number of registers in the chip to be tested, and each register has a plurality of bit positions, and the time consumed by the sequential fault injection is large, resulting in low efficiency of the fault injection test.

[0086] In order to solve the above technical problems, when at least one target bit corresponding to the plurality of registers is obtained by step 103, in order to determine the faulty register, the target bit in the plurality of registers can be sequentially fault injected to obtain the fault test result corresponding to each register, so that the target bit corresponding to the target register having a fault can be determined as the fault point.

[0087] For example, if the chip to be tested includes 10 registers, the target bit in each of the 10 registers is sequentially injected with an error. Assuming that the output value of the fault test result of the 10th register is a first preset value and the output values of the remaining registers are second preset values, it is determined that the fault point is on the target bit of the 10th register. Compared with the related technical solution described above, the present application only needs to perform a fault injection operation on the target bit in the register, without the need to sequentially inject an error into all bits in each register, thereby reducing the error injection time consumption and improving the error injection efficiency.

[0088] In addition to the above embodiments, the determination of the fault point can also be performed in combination with the embodiments shown in Figure 5 Figure 5 For an embodiment of the present application, a method flowchart for determining a target register that has failed is provided, as shown in Figure 5 The method at least includes steps 501-504:

[0089] Step 501: Sort and number the plurality of registers to obtain the numbering identification of each bit in each register.

[0090] Step 502: Perform a fault injection operation on the target bit in the same position of the register with an even numbering identification to obtain a first fault test result.

[0091] Step 503: Perform a fault injection operation on the target bit in the same position of the register with an odd numbering identification to obtain a second fault test result.

[0092] Step 504: Determine the target register that has failed according to the first fault test result and the second fault test result.

[0093] After the target register that has failed is determined, the target bit corresponding to the target register can be determined as the specific fault point.

[0094] In Figure 5 ​In the embodiment shown, the plurality of registers in the chip to be tested can be sorted and numbered so that each register has a unique register number identifier. After determining that the target bit corresponding to at least one of the plurality of registers has a fault, since the fault point can exist only in the register group with an even number identifier, only in the register group with an odd number identifier, or in both the register group with an even number identifier and the register group with an odd number identifier. Therefore, the target bit at the same position corresponding to the register with an even number identifier needs to be simultaneously subjected to the fault injection operation to obtain a first fault test result, and the target bit at the same position corresponding to the register with an odd number identifier needs to be simultaneously subjected to the fault injection operation to obtain a second fault test result, so as to determine the fault point according to the first fault test result and the second fault test result.

[0095] In this embodiment, the parallel fault injection operation on the register with an even number identifier and the parallel fault injection operation on the register with an odd number identifier can quickly determine the position of the fault point, thereby improving the efficiency of the fault injection operation and the determination of the fault point.

[0096] That is, in some example embodiments of the present disclosure, when the fault point is determined according to the first fault test result and the second fault test result in step 504, if the output value of the first fault test result is a non-pre-set value, the target bit at the same position corresponding to the register with an even number identifier is subjected to the sequential fault injection operation to determine the target register with a fault in the register with an even number identifier.

[0097] For example, when the output value of the first fault test result of the parallel fault injection operation on the register with an even number identifier is a non-pre-set value, it indicates that the register group with an even number identifier contains at least one target register with a fault, and the target register with a fault can be found from the register group with an even number identifier by means of the sequential fault injection, so as to determine that the target bit of the target register is the fault point.

[0098] Alternatively, in some other example embodiments of the present disclosure, if the output value of the first fault test result is a pre-set value, it is determined that the target register with a fault is the register with an odd number identifier, and the target bit at the same position corresponding to the register with an odd number identifier is subjected to the sequential fault injection operation to determine the target register.

[0099] For example, if the output value of the first fault test result is the preset value, it indicates that there is no target register in the register with even number identification that has a fault, and it is concluded that the target register is in the register group with odd number identification. At this time, the target bit corresponding to the same position of the register with odd number identification can be sequentially subjected to the fault injection operation to obtain the target register.

[0100] In this embodiment, after the parallel fault injection operation, the fault injection operation is sequentially performed according to the corresponding fault test result to determine the target register with a fault, which can greatly reduce the number of bits in the sequentially fault-injected register, thereby reducing the consumption of fault injection time and improving the efficiency of fault injection testing.

[0101] In addition to the above embodiments, the bisection method can also be used to determine the target register with a fault. For example, when the output value of the target bit in the same position of the plurality of registers is the first preset value based on step 103, the plurality of registers can be divided into two parts, and the target bits of the divided registers can be fault-injected to check the fault detection result, thereby achieving the technical effect of improving the efficiency of finding the target register.

[0102] It should be understood that although each step in the flowchart is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the figure can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be alternately executed with other steps or at least part of the sub-steps or stages of other steps.

[0103] To implement the above fault injection test method, please refer to Figure 6 An embodiment of the present application provides a fault injection test device. The fault injection test device 600 can include a bit position configuration module 601, a fault injection module 602 and a fault determination module 603.

[0104] The bit configuration module 601 is configured to configure a plurality of registers in a chip to be tested as a same number of bits in advance; the fault injection module 602 is configured to perform, for each target bit in the same position in the plurality of registers, a fault injection operation on each target bit based on a TSC comparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; and the fault determination module 603 is configured to determine that at least one target bit in the plurality of registers has a functional fault if the output value of the fault test result is the first preset value.

[0105] In an optional embodiment of the present disclosure, the fault determination module 603 is further configured to determine that each target bit in the plurality of registers does not have a functional fault if the output value of the fault test result is the second preset value, and continue to perform a fault injection operation on other target bits in the same position in the plurality of registers.

[0106] In an optional embodiment of the present disclosure, the bit configuration module 601 is specifically configured to obtain a target bit number of a first register in the plurality of registers, the first register being a register with the largest number of bits in the plurality of registers; add a virtual bit to a second register in the plurality of registers based on the target bit number of the first register to obtain a third register, so that the third register has a bit with the target bit number; wherein the second register is a register with a smaller number of bits than the target bit number in the plurality of registers.

[0107] In an optional embodiment of the present disclosure, the fault injection module 602 is specifically configured to perform a fault injection operation on each target bit based on a TSC comparator to obtain an output value of the fault test result as the first preset value, the each target bit containing a virtual bit in the third register.

[0108] In an optional embodiment of the present disclosure, the fault injection module 602 is specifically configured to not perform a fault injection operation on the virtual bit in the third register, and the output value of the virtual bit is the second preset value.

[0109] In an optional embodiment of the present disclosure, the fault injection module 602 is specifically configured to add a number to a plurality of bits in each register in a preset number order to obtain a number identification of each bit in each register for each register in the chip to be tested; and determine a bit with the same number identification in the plurality of registers as a target bit in the same position in the plurality of registers.

[0110] In an optional embodiment of the present disclosure, the apparatus can further comprise a target register determining module (not shown in the figure), and the fault injection module 602 can be configured to perform a fault injection operation on the target bit corresponding to the same position of the register with an even number identifier to obtain a first fault test result, perform a fault injection operation on the target bit corresponding to the same position of the register with an odd number identifier to obtain a second fault test result, and the target register determining module can be configured to determine the target register that has failed according to the first fault test result and the second fault test result. Figure 6 In an optional embodiment of the present disclosure, the target register determining module can be specifically configured to perform, if the output value of the first fault test result is a first preset value, a sequential fault injection operation on the target bit corresponding to the same position of the register with an even number identifier to determine the target register that has failed in the register with an even number identifier.

[0111] In an optional embodiment of the present disclosure, the target register determining module can be specifically configured to perform, if the output value of the first fault test result is a second preset value, a sequential fault injection operation on the target bit corresponding to the same position of the register with an odd number identifier to determine the target register that has failed in the register with an odd number identifier.

[0112] In an optional embodiment of the present disclosure, the target register determining module can be specifically configured to perform, if the output value of the first fault test result is a second preset value, a sequential fault injection operation on the target bit corresponding to the same position of the register with an odd number identifier to determine the target register that has failed in the register with an odd number identifier.

[0113] The specific limitations of the above-mentioned fault injection test apparatus can refer to the limitations of the fault injection test method in the above, which will not be repeated here. Each module in the above-mentioned fault injection test apparatus can be realized by software, hardware and their combinations in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to call and execute the operations corresponding to each module by the processor.

[0114] In an embodiment, a computer device is provided, and an internal structure diagram of the computer device can be as shown in Figure 7The computer device comprises a processor, a memory, a network interface and a database connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is configured to be executed by the processor to implement the fault injection testing method. The computer program comprises a memory and a processor. The memory stores the computer program. The processor is configured to implement any step of the fault injection testing method when executing the computer program.

[0115] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is configured to be executed by a processor to implement any step of the fault injection testing method.

[0116] Those skilled in the art will understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) containing computer usable program code.

[0117] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as a combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The apparatus that implements the functions specified in one or more flows and / or blocks.

[0118] These computer program instructions can also be stored in a computer readable storage medium that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a manufactured product comprising an instruction apparatus that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1the function specified in the one or more blocks.

[0119] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide a process for implementing the flowchart Figure 1 the flowchart or flowcharts and / or a block Figure 1 Figure 1 the steps of the function specified in the one or more blocks.

[0120] Although preferred embodiments of the application have been described, those skilled in the art will be able to make additional modifications and variations to the described embodiments without departing from the spirit and scope of the application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the application.

[0121] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the application. Accordingly, the application intends to embrace all such modifications and changes as falling within the scope of the claims and their equivalents.

Claims

1. A fault injection testing method, characterized in that: include: Pre-configuring multiple registers in the chip to be tested to have the same number of bits; For each target bit at the same position in the multiple registers, a fault injection operation is performed on each target bit based on a full self-test comparator TSCcomparator to obtain a fault test result; wherein the output value of the fault test result is a first preset value or a second preset value; If the output value of the fault test result is a first preset value, it is determined that a functional fault exists in at least one target bit in the plurality of registers.

2. The method according to claim 1, characterized in that The method further comprises: If the output value of the fault test result is a second preset value, it is determined that no functional fault exists in each corresponding target bit in the multiple registers, and the fault injection operation is continued on other target bits at the same position in the multiple registers.

3. The method according to claim 1, characterized in that The step of pre-configuring multiple registers in the chip to be tested to have the same number of bits includes: Obtaining a target number of bits for a first register among the multiple registers, where the first register is a register with the largest number of bits among the multiple registers; adding virtual bits to a second register of the plurality of registers based on a target number of bits of the first register to obtain a third register, so that the third register has bits of the target number of bits; The second register is a register among the multiple registers whose bit number is smaller than the target bit number.

4. The method according to claim 3, characterized in that The performing a fault injection operation on each target bit based on the full self-check comparator TSC comparator to obtain a fault test result includes: A fault injection operation is performed on each target bit based on a full self-test comparator TSC comparator, and an output value of the fault test result is obtained as the first preset value, and each target bit includes a virtual bit in the third register.

5. The method according to claim 3, characterized in that In response to the virtual bit in the third register not performing a fault injection operation, the output value of the virtual bit is a second preset value.

6. The method according to claim 1, characterized in that The step of performing a fault injection operation on each target bit at the same position in the plurality of registers based on a full self-test comparator TSC comparator to obtain a fault test result includes: For each register in the chip to be tested, numbering multiple bits in the register according to a preset numbering sequence to obtain a number identifier for each bit in each register; Bits with the same encoding identifier in multiple registers are determined as target bits at the same position in the multiple registers.

7. The method according to claim 6, characterized in that The method further comprises: Performing a fault injection operation on a target bit at a same position corresponding to the register identified as an even number, to obtain a first fault test result; Performing a fault injection operation on a target bit at a same position corresponding to the register whose number is an odd number, to obtain a second fault test result; A target register where a fault occurs is determined according to the first fault test result and the second fault test result.

8. A fault injection test device, characterized in that: include: A bit configuration module is configured to pre-configure multiple registers in the chip to be tested to have the same number of bits; a fault injection module configured to perform a fault injection operation on each target bit at the same position in the plurality of registers based on a full self-test comparator (TSC) to obtain a fault test result; wherein an output value of the fault test result is a first preset value or a second preset value; The fault determination module is configured to determine that a functional fault exists in at least one target bit in the plurality of registers if an output value of the fault test result is a first preset value.

9. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the fault injection testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the fault injection testing method according to any one of claims 1 to 7 are implemented.

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