Design tool for automatic placement constraint generation, adapter insertion process, and local and global congestion capture

Abstract

Embodiments of the present disclosure relate to design tools for automatic placement constraint generation, adapter insertion procedures, and local and global congestion capture. A tool is disclosed that automatically generates constraints for placement of network elements, which can be understood by back-end tools that follow the constraints. The tool also constrains placement within a given range, resulting in faster runtime of the back-end tool. In addition, the tool automatically inserts additional elements into the topology to facilitate timed shutdown in downstream or back-end tools. In addition, the tool provides real-time feedback to the user regarding line congestion during editing. The tool also implements a machine-learned model that is trained and receives feedback for the provided solution to further train the model. The tool also includes the ability to use feedback to train a machine learning model for automatic and auxiliary topology analysis and synthesis. The tool generates a physical implementation boot during the physical implementation of the synthetic NoC.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 469,546, filed on May 30, 2023, by Amir CHARIF et al., entitled “DESIGN TOOL FOR AUTOMATED PLACEMENT CONSTRAINT GENERATION, ADAPTER INSERTION PROCESS, AND LOCALAND GLOBAL CONGESTION CAPTURE,” the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present technology is in the field of electronic system design and, more particularly, relates to physical implementation guidance for a fast, incremental process for automatically generating placement constraints for network elements, inserting various adapters along segments, and interactively capturing wire congestion while editing a network-on-chip (NoC) topology within a floorplan. Background Art

[0004] Multiprocessor systems have been implemented in system-on-chips (SoCs) that communicate via a NoC. A community consists of instances of initiator intellectual property (IP) and target IP. Transactions in the form of packets are sent from the initiator to one or more targets using industry-standard protocols. An initiator connected to the NoC sends a request transaction to a target using an address to select the target. The NoC decodes the address and transmits the request from the initiator to the target. The target processes the transaction and sends a response transaction, which the NoC transmits back to the initiator.

[0005] Given a set of performance requirements, such as connectivity and latency between sources and destinations, the frequencies of various components, the maximum area available for NoC logic and its associated routing (wiring), the minimum throughput between source and destination points, the power requirements of the NoC, and the placement of the components connected to the NoC on the floorplan, creating an optimal NoC that meets all of these requirements with the least amount of logic and wires is a complex task. It is typically the job of the chip architect or chip designer to create this optimal NoC, a difficult and time-consuming task. Besides being a difficult task, the NoC design must be modified every time one of the requirements changes, such as when the chip layout is modified, IP components are added or removed, or the expected performance is modified. Consequently, this task requires frequent rework using any tool during the chip's design time.

[0006] Consider a design tool for editing a NoC topology on a floorplan, which can output the results as RTL code. Once the user completes the topology and is satisfied with the current placement, they are ready to output their work and feed it into the back-end tools, which can generate the netlist, perform the final placement and routing, etc. The problem is that if the placement and routing of the back-end tools produce completely different results from the placement generated by the user, many optimizations and configurations become invalid. For example, if the user adds pipelines to close the timing at a certain distance, these pipelines may no longer be valid if the placement has changed drastically. Additionally, once the topology is optimized according to the physical constraints (floor layout space), there is the problem of timing closure.

[0007] Therefore, what is needed is a design tool that automatically generates network element placement constraints. Back-end tools can understand these constraints. Back-end tools follow the constraints and place network elements close to the user's desired locations. Furthermore, keeping placement constraints within a given range results in faster runtimes for back-end tools. Furthermore, what is needed is a tool that automatically inserts additional components into the topology to aid timing closure in back-end or downstream tools. Furthermore, what is needed is a tool that provides users with real-time feedback on line congestion during editing. This allows users to make early changes to the layout and optimize the topology, which is extremely valuable. Summary of the Invention

[0008] According to various embodiments and aspects of the present invention, a design tool is disclosed that automatically generates constraints for the placement of network components, which can be interpreted by back-end tools that follow these constraints in a floorplan. The design tool also constrains placement within a given range, resulting in faster runtimes for back-end tools. Furthermore, the tool automatically inserts additional components into the topology to aid timing closure in downstream or back-end tools. Furthermore, the tool provides users with real-time feedback on line congestion during editing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Screen shots of a tool including a floor plan and data field entry windows are shown according to various aspects and embodiments of the present invention.

[0010] Figure 2 The present invention shows various aspects and embodiments of the present invention. Figure 1 tools.

[0011] Figure 3 A process of using tools to optimize floorplans according to various aspects and embodiments of the present invention is shown.

[0012] Figure 4 The further optimized Figure 3 The process of using the tool.

[0013] Figure 5 Tools for automatically generating and merging regions according to various aspects and embodiments of the present invention are shown.

[0014] Figure 6 A tool for generating complex-shaped polygonal regions without overlapping occlusions according to various aspects and embodiments of the present invention is shown.

[0015] Figure 7 A tool using clock adapters, distance pipelines, and routing links according to various aspects and embodiments of the present invention is shown.

[0016] Figure 8 A process for generating and placing a network on chip (NoC) in a floorplan using optimized area is shown according to various aspects and embodiments of the present invention. DETAILED DESCRIPTION

[0017] Various examples of the present technology are described below to illustrate various aspects and embodiments of the present invention. In general, the examples may use the described aspects in any combination. All statements herein reciting principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Furthermore, these equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed to perform the same function, regardless of structure.

[0018] Note that, as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Throughout this specification, reference to "one aspect," "one aspect," "some aspects," various aspects, or similar language means that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the present invention.

[0019] Throughout this specification, the appearance of the phrases "in one embodiment," "in at least one embodiment," "in an embodiment," "in certain embodiments," and similar language may, but do not necessarily, refer to the same embodiment or similar embodiments. In addition, the various aspects and embodiments of the present invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The disclosed invention is effectively made or used in any embodiment including any novel aspect described herein. All statements describing the principles, aspects, and embodiments of the present invention herein are intended to encompass structural and functional equivalents thereof. Such equivalents include currently known equivalents and equivalents developed in the future.

[0020] As used herein, a transaction can be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0021] As used herein, a node is defined as a distribution point or communication endpoint that is capable of creating, receiving and / or sending information over a communication path or channel. A node may refer to any of the following: a switch, a splitter, a combiner, a buffer, and an adapter. As used herein, splitters and combiners are switches; not all switches are splitters or combiners. As used herein and in accordance with various aspects and embodiments of the present invention, the term "splitter" describes a switch having a single inlet and multiple outlets. As used herein and in accordance with various aspects and embodiments of the present invention, the term "combiner" describes a switch having a single outlet and multiple inlets.

[0022] According to various aspects of the present invention, a system on a chip (SoC) includes multiple clock domains and multiple power domains. A clock domain is defined by all logic fed by a given clock input. The clock input is characterized by the frequency of the clock, which is its most important parameter. A power domain is defined by all logic that draws power from the same power supply. According to various aspects of the present invention, the power supplies are gated so that a power domain can be turned on or off or isolated from other power domains. Therefore, the designer provides a set of clock domain and power domain constraints as part of the initial design.

[0023] Now refer to Figure 1 and Figure 2 , screenshots 100 and 200 of a graphical user interface or display interface of a design tool are shown according to various aspects and embodiments of the present invention. Screenshot 100 shows a floor plan. Screenshot 200 shows a list of modules. The tool creates areas in the available space of the floor plan. According to various aspects and embodiments of the present invention, a user can manually draw areas graphically on the floor plan. According to various aspects and embodiments of the present invention, a user can use a command line interface to create areas. According to various aspects and embodiments of the present invention, the tool can automatically generate new areas based on sizes provided by the user. According to various aspects of the present invention, the tool includes a machine learning model that is trained to provide or generate new areas. The machine learning model then receives feedback from the user based on the new areas generated, and the feedback is used to further train the model.

[0024] According to various aspects of the present invention, the user selects the network elements (e.g., cells or modules) to be constrained within the identified area. The tool can provide a variety of ways to easily select cells (by element type, by network, by regular expression, etc.). The user manually assigns existing modules 210 to the area by selecting the area from a list and specifying these modules. According to various aspects and embodiments of the present invention, for each specified cell, the tool automatically assigns the cell to the new module and constrains the module to the area covering the current location of the cell. According to various aspects and embodiments of the present invention, if there are multiple such areas, the user can configure which area will be used to constrain the cell. The tool automatically removes unused areas, which are areas that are not used to constrain any cells, in order to clean up and optimize the final design. The tool then exports the final constraints to a format understood by the back-end tools.

[0025] Now refer to Figure 3 and Figure 4 , illustrates floorplan optimization 300 and 400 using a tool according to various aspects and embodiments of the present invention. The tool automatically generates regions 310. According to various aspects of the present invention, the tool is a cell-centric optimization. The tool's machine learning model creates regions where needed. These regions can overlap. The tool starts with a list of current network cell locations. The tool detects clusters of proximate cells. For each cluster, the tool creates a region covering the cell with a user-defined size.

[0026] According to various aspects of the present invention, the tool uses a mode for performing / generating a global optimization mesh. The tool organizes the regions within the available floor plan space into a global mesh of rectangular regions 320. By construction, the regions do not overlap with each other. The tool uses a step of combining regions to generate the mesh. The tool generates initial rectangular regions based on the available space of the floor plan. Reference Figure 3 The tool globally and iteratively optimizes the initial segmentation by growing regions toward their neighbors and consuming some of their space. Regions with no remaining space are discarded. According to various aspects and embodiments of the present invention, the tool can use a genetic algorithm. According to various aspects and embodiments of the present invention, the optimization goal is to obtain regions that are as large and as square as possible.

[0027] refer to Figure 4 , showing an optimized floor plan 400 and a target size floor plan 402. The tool divides a large area, such as area 410, into smaller areas 420 based on a user-provided (preferred) target size.

[0028] Now refer to Figure 5, when using a tool for automatically growing regions and merging content according to various aspects of the present invention, various floor plans 502, 504, and 506 are displayed as various stages of the process being performed. The tool ensures that when cells are confined to a given region, the area of ​​the region is sufficient to contain all cells of a certain size and density. The tool imports region information about network cells from an earlier region estimation module or from precise region reports generated by a previous backend run. The tool provides visual information to indicate to the user the degree of utilization of regions, such as by color-coordinating (color-coding) regions by utilization. The tool automatically generates overutilized regions. The tool then merges significantly overlapping regions based on user-defined threshold parameters. When two regions are merged, the content of both regions is now constrained by the new larger region.

[0029] Now refer to Figure 6 , shows a process 600 used by a tool for generating final regions according to aspects of the present invention. The tool grows regions without any overlapping blockages. The tool grows regions (e.g., to fill zone targets) while ensuring that the regions do not overlap with blockages and controllably overlap with other regions. The tool operates at the level of a floorplan grid. According to aspects of the present invention, at a given resolution, the floorplan is typically discretized into small cells or nodes. Cells covered by blockages are marked as "blocked," and cells covered by existing regions are marked with a given region object. A single cell can be marked with multiple regions. Each region is associated with a logical rectangular bounding box. Initially, the bounding box includes all cells in the region. The tool grows regions by iteratively repeating the following:

[0030] 1) Simulate growing the bounding box in each direction (east, west, south, north), laying out cells one column or row at a time;

[0031] 2) In each case, calculate the effective new area by summing the areas of the attached cells; exclude the blocked cells while dividing the areas of the cells marked by other regions accordingly;

[0032] 3) By growing the side with the largest area increase, growth will tend to the direction that makes the region more "square" in shape;

[0033] 4) Select the direction that produces the largest growth and effectively grow the bounding box in the selected direction.

[0034] 5) Mark the newly included cells with the region. The tool continues until the region reaches its target size.

[0035] According to various aspects of the present invention, once all regions have been grown using the above process, the tool performs an overlap check, where if the shared cell area between two regions exceeds a given threshold, the two regions are merged into a single region. To output the final region from its bounding box, the tool performs a scan of the included cells and generates multiple rectangles that only include valid cells. According to various aspects of the present invention, a simple horizontal scan from bottom to top can be used to detect rectangles. This outputs complex-shaped polygons that do not overlap with obstructions.

[0036] Now refer to Figure 7 , shows a process 700 used by a tool according to various aspects of the present invention. For each segment in the network, the tool performs the insertion of elements and routes (edges or links), which can be activated / deactivated and configured by the user. According to various aspects of the present invention, the tool inserts a routing link 702. When a wire is routed between two elements that make up a segment, the route can be complex, i.e., involving many detours and corners. All timing analysis must be based on the complete route. In order to ensure that downstream tools follow the same route as the route calculated by the tool, the tool first inserts a null module 706 at each corner of the routing route in the routing link 702. The null module 706 is part of the routing link 702. The modules of the routing link are constrained to a local area, so the wires will be placed and routed along the same path in the downstream tool.

[0037] According to various aspects of the present invention, the tool inserts a clock adapter 708. If two elements of a segment have different clock domains, the clock adaptation module inserts a clock adapter from the source element 710 to the destination element 720, which can be a clock domain crossing according to various aspects of the present invention. The user can instruct the tool (or the tool can automatically determine using a machine learning model) to place the adapter 708 in the middle of the segment to balance or approximate the faster clock, thereby spreading the slower clock a greater distance and ensuring that the pipeline requires a smaller distance.

[0038] According to various aspects of the present invention, the tool inserts distance pipelines 730. The line delay and clock speed specified by the technology settings are used to calculate the number of distance pipelines that need to be inserted. The tool inserts the distance pipelines in a manner that is evenly distributed along the segment.

[0039] According to various aspects of the present invention, the tool detects congested areas. The tool splits the available space of a floor plan into multiple areas. The split captures as many floor plan channels as possible.

[0040] Now refer to Figure 8, shows a process 800 according to various aspects and embodiments of the present invention. At step 802, the tool receives a floor plan having blocked areas and unblocked areas. At step 804, the tool generates regions within the unblocked areas, which may overlap and have different polygonal shapes on the floor plan. At step 806, the tool receives a list of units and the areas in which these units will be included or subject to placement restrictions. At step 808, the tool merges nearby regions, including some overlapping regions, to generate nearly rectangular regions and removes overlap of regions. When regions are merged, the tool assigns the units to the correct merged regions based on the initial containment / constraint requirements for the units. At step 810, the tool divides the larger region into smaller regions for analysis and / or placement of the units. The tool can provide a final region map on the floor plan that is optimized for unit placement and avoids blocked areas.

[0041] According to various aspects of the present invention, the tool addresses wire capacity data. Based on the metal layer information (spacing, orientation) provided in the process parameters, the tool calculates the maximum total number of horizontal and vertical wires that can be routed through each area. According to various aspects of the present invention, each time a routing route is calculated, the tool updates the horizontal / vertical routing utilization for each congested area it passes through. According to various aspects of the present invention, the tool identifies and generates a congestion heat map. The tool creates a heat map for congested area utilization in the graphics editor.

[0042] According to various aspects of the present invention, the tool provides custom congestion windows. Because the automatic floor plan splitting of congested channels may not capture the channels of interest to the user, the tool provides the user with the ability to define custom areas in the floor plan, for example by drawing rectangles on the graphical view, for which congestion data is tracked and reported. Users can define as many windows as they desire. This is powerful because users can locate areas of interest where congestion issues may occur and avoid unnecessary bookkeeping across the entire floor plan.

[0043] According to various aspects of the present invention, initiators and targets are communicatively connected to a NoC. An initiator is the unit that sends requests. An initiator is typically configured to read and write commands. A target is the unit that services or responds to requests. A target is typically configured to read and write commands. Each initiator is attached to or connected to the NoC via a NIU. The NIU attached to an initiator is called an initiator network interface unit (INIU). Furthermore, each target is connected to the NoC via an NIU. The NIU attached to a target is called a target network interface unit (TNIU). The primary function of the NoC is to transmit each request from an initiator to its intended destination, a target. If a response is required, the NoC transmits each target's response to the corresponding requesting initiator. Initiators and targets have multiple distinct parameters that characterize them. According to various aspects of the present invention, the clock domain and power domain to which each initiator and target belongs are defined. The width of the data bus used to send, write, and receive read payloads is a multiple of bits. According to various aspects of the present invention, the width of the data bus used to send, write requests, and receive write responses (the communication path to and from the target) is also defined. Additionally, the clock and power domain definitions are references to the previously described clock and power domains that exist in a SOC as described herein.

[0044] According to various aspects of the present invention, an initiator need not be able to send requests to all or multiple targets connected to the NoC. The precise definition of the targets that can receive requests from the initiator is outlined or elaborated in a connectivity table such as Table 400. The connectivity and traffic class labeling information can be represented as an explicit or conceptual matrix. There is one row for each initiator and one column for each target. If an initiator must be able to send traffic to a target, then the traffic class label must appear at the intersection between the initiator row and the target column. If no label is present at the intersection, then the tool does not require connectivity between the initiator and the target. According to various aspects of the present invention, the actual format used to represent connectivity can vary, as long as each initiator-target combination has a precise definition of its traffic class, or no classification label if there is no connectivity. Within the scope of the present invention, initiator / target connections support multiple traffic classes.

[0045] Latency, within the scope of the present invention, refers to the number of clock cycles it takes for data to pass through the network. Despite having high bandwidth (frequency), latency causes problems in transmission networks. An example of a "real-time traffic class" is video data from a camera in a self-driving car. It is unacceptable to have long latency in the propagation of data. If some data is lost, the vehicle would be unsafe. Still a real-time, but less important, traffic class is audio and / or video in an entertainment system. Having gaps in this data is undesirable, but not unsafe. An example of non-real-time data is data from a gas pressure gauge sensor in a car. If the data is delayed by a few seconds, it is not a big deal because the rate of change of the data is quite slow compared to the speed of operation of society.

[0046] According to some aspects of the invention, scenarios are not defined for the tool, in which case the tool optimizes the NoC synthesis process for physical cost (eg, lowest gate cost and / or lowest line cost).

[0047] According to various aspects of the present invention, the tool processes the connectivity matrix using the following defined parameters or components:

[0048] One network interface unit per initiator,

[0049] One network interface unit per target,

[0050] Create a switch for each defined service class, called the master switch for that class, A switch after each initiator / initiator NIU that diverts the service to the different master switches that the initiator needs to reach,

[0051] The switch before each destination / target NIU that merges traffic from the different master switches that are sending traffic to that destination

[0052] The data width of each attached interface and its clock domain are used as input to the tool to calculate the data width of each switch and the clock domain it belongs to. According to various aspects of the present invention, each step of converting a network that is part of a NoC also performs calculations of the data width and clock domain of the newly created network elements.

[0053] According to various aspects of the present invention, using the tool, each switch of each combiner in the main switch is further decomposed into a cascade of combiners, each combiner of the cascade being placed at a branch point of the merge roadmap of the attached target. The branch point of the roadmap is defined by the fact that the path is divided into two or more branches. The process of decomposing the splitters in the splitter cascade retains the original splitter functionality, because the number of inputs to the cascade is still 1 and the number of outputs of the cascade is the same as the number of outputs of the original splitters. The process of decomposing the combiners in the combiner cascade retains the original combiner functionality, because the number of outputs of the cascade is still 1 and the number of inputs of the cascade is the same as the number of inputs of the original combiner. According to various aspects of the present invention, the effect of this process is to obtain a set of basic switches, which are represented by combiners and splitters, and are placed physically close to where the actual connections between the switches are required.

[0054] According to various aspects of the present invention, the tool transforms the network to reduce the number of wires used between switches to a minimum while maintaining performance as defined in the scenario, which is a set of minimum throughput requirements between initiators and targets. According to various aspects of the present invention, switches are aggregated for performance-aware switching, and combiners and splitters that are already distributed on the roadmap are treated similarly to ordinary switches.

[0055] According to other aspects of the present invention, an expansion of the clock and power domains on the floor plan is provided, and each component is tested to ensure that it is within the boundaries of the specified clock and power domains. If the test fails, the component is moved until an appropriate position is found where the test passes. Once a suitable position is found for each component, each connection between the components is routed. The wiring process will find a suitable path for the wire group that forms the connection between the components. After routing is completed, if necessary, based on how long it takes for the signal to cover a distance of 1mm, the information provided about the technical capabilities is used to insert pipeline elements that span the distance on the link.

[0056] According to some aspects and embodiments of the present invention, the tool generates one or more computer files describing the generated NoC, including:

[0057] List of network elements with their configuration: data width, clock domain.

[0058] The location of each generated network element on the floor plan.

[0059] The set of routes passes through the network elements that enable connectivity. According to aspects of the present invention, a route is an ordered list of network elements, one for each pair (initiator, target) and one for each pair (target, initiator). The routes indicate how traffic between the pairs will flow and through which elements.

[0060] According to various aspects of the present invention, the tool is used to generate metrics about the generated NoC, such as: wire length distribution histogram, number of switches, switch size histogram.

[0061] According to another aspect of the present invention, the tool automatically inserts various adapters and buffers in the network. The tool inserts adapters based on the required adaptation between two components with different data widths, clocks, and power domains. The tool inserts buffers based on scenarios and detected rate mismatches.

[0062] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for incremental optimization of a NoC, including when one of the constraints provided to the tool is information about a previous run.

[0063] After the synthesis process is performed by the software, the result is produced in a machine-readable form, such as a computer file that captures the information using a well-defined format. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited to a particular format.

[0064] In an embodiment, a mechanism for adapting the timing implementation between a first component and a second component within a NoC includes, but is not limited to, distance pipeline insertion, adding buffer stages, switching buffers to higher drivers or faster buffers, adjusting line widths, and / or indicating which line layer(s) are being used.

[0065] It is within the scope of the present invention to physically implement different mechanisms to overcome timing issues within the synthesized topology, resolving timing issues before they arise by passing constraints and / or guidance of the physical implementation. It is within the scope of the present invention that the physical implementation of connections includes, but is not limited to, the physical placement of objects, components, and / or gates around the NoC topology such that downstream tools do not place a first connection at a sufficiently large distance from a second connection to exceed timing constraints. It is more desirable to synthesize networks for all connections that can meet connectivity requirements and to minimize the number of gates in the synthesized network. It is important to minimize the number of gates in the synthesized network to include, but is not limited to, enable the NoC to fit the topology parameters; ensure that timing requirements are met; be built more efficiently in a smaller network; and minimize the overall power used in the interconnection between signals.

[0066] In another embodiment, components on the driver side are replaced with components with greater drive strength to increase speed. For example, when a signal is forwarded from a first switch to a second switch, if the distance between the first and second switches is too large, the timing requirements are exceeded. A distance line can be placed between the first and second switches. Alternatively, the drive strength can be increased by using a larger wire with lower resistance to make the signal faster, thereby reducing parasitic elements on a particular line.

[0067] In an embodiment, a floorplan region is a mechanism that can include, but is not limited to, constraining components such as switches and / or distance pipeline stages to physical locations and / or approximate physical locations; and / or partitioning a logical interconnect into multiple parts that are sized to the downstream tools for appropriate synthesis. The physical and logical configurations of the interconnect are configured together to form the logical interconnect. Floorplan regions are used to constrain components to specific locations. The need for floorplan regions is a response to the growing size of the networks or interconnects being developed in society. In other words, the networks or interconnects of SoCs have become larger than the capacity of downstream implementation tools, including but not limited to adding wider interconnects and / or interconnecting more components.

[0068] According to various aspects of the present invention, based on data associated with signals received and transmitted by the switch, it may be more desirable to have a switch in a particular restricted location because the performance of the switch may be adversely affected if the switch is moved to a location outside of the restricted location.

[0069] According to various aspects of the present invention, additional constraints can be utilized to place the gates of components, such as switches or tube stages, as close together as possible within each individual component. A current problem with existing placement programs is that they tend to place components too far apart. Within the scope of the present invention, a switch is a single component with multiple gates, each of which needs to be placed. While the netlist facilitates the interconnection of these components, downstream tools physically place the components and route the connections to specify logical connectivity.

[0070] According to various aspects of the present invention, two separate constraints, one from the first aspect and the other from the second aspect, can be used simultaneously. For example, if a switch specified for a certain performance has its components distributed over a larger area than specified, the switch will have lower performance than originally specified. Therefore, it is more desirable to keep the components of the switch close together. Furthermore, with larger networks, it is more desirable to keep components within a specific area or range of the floorplan free space so that the entire network performs as specified or analyzed.

[0071] In one embodiment, a maximum length for a single wire is established to ensure that the overall timing for a specific path can be met, given the approximations of semiconductor processes. Furthermore, it is crucial to ensure that the signal can be moved from a first component to a second component within a given timeframe. Due to the excessive length between the first and second components, moving the signal from the first component to the second component within the given timeframe is unachievable. Consequently, a technical solution requiring the insertion of a remote tube stage, as compared to the prior art, addresses this technical issue.

[0072] According to various aspects of the invention, area estimates for a first component and a second component are received, and timing and other performance requirements are balanced in optimization of a NoC to ensure that the resulting NoC gates are placeable, i.e., they will fit into free space in a floorplan allocated to the NoC.

[0073] According to various aspects of the invention, power requirements for the NoC are also received, and timing and other performance requirements are balanced in the optimization of the NoC to ensure that the resulting NoC will not exceed the power requirements specified in the constraints.

[0074] According to various aspects of the present invention, physical routing congestion data is also included, either as an estimate based on the NoC netlist structure or as feedback from downstream implementation tools, and timing and other performance requirements are balanced in the optimization of the NoC to ensure that the resulting NoC will be routable within the free space in the floorplan allocated to the NoC.

[0075] According to some aspects of the present invention, a method for guiding the physical generation of a NoC is disclosed. The tool may include a machine learning model that is trained and receives feedback, the tool receiving at least one constraint parameter for the NoC, the at least one constraint parameter selected from a constraint group parameter including at least one physical constraint and at least one performance constraint; using the tool, augmenting a physical floorplan of the NoC with information that guides the physical implementation of the NoC; and using the physical floorplan to constrain the physical implementation of connections to locations on the physical floorplan based on the at least one constraint parameter.

[0076] Certain methods according to aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, when executed by one or more processors, cause a system or computer to perform the steps of the methods described herein. Non-transitory computer-readable media include rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically movable or solid-state storage media. Any type of computer-readable medium is suitable for storing code including instructions according to the various examples.

[0077] Certain examples have been described herein, and it will be noted that different combinations of different components from different examples are possible. Highlighted features are given to better explain the examples; however, it is apparent that certain features can be added, modified, and / or omitted without modifying the functional aspects of the examples described.

[0078] Various examples are methods of using the behavior of a machine or combination of machines. The method examples are complete regardless of where in the world most of the constituent steps occur. For example, according to various aspects and embodiments of the present invention, IP elements or units include: a processor (e.g., a CPU or GPU), RAM (e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connection, such as Ethernet, Wi-Fi, 3G, 4G Long Term Evolution (LTE), 5G and other wireless interface standard radios. The IP may also include various I / O interface devices to meet the needs of different peripheral devices, such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (e.g., keyboards and mice, etc.). By executing instructions stored in RAM devices, the processor performs the steps of the methods described herein. .

[0079] Some examples are one or more non-transitory computer-readable media arranged to store such instructions for the methods described herein. The examples may be implemented regardless of what machine holds the non-transitory computer-readable medium including any necessary code. Some examples may be implemented as: a physical device such as a semiconductor chip; a hardware description language representation of the logical or functional behavior of such a device; and one or more non-transitory computer-readable media arranged to store such a hardware description language representation. The description of the principles, aspects, and embodiments recited herein encompasses both structural and functional equivalents thereof. Elements described herein as coupled have an effective relationship that can be achieved by direct connection or indirectly with one or more other intermediate elements.

[0080] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of the disclosed features. The description of the principles, aspects, and embodiments recited herein encompasses both structural and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved through direct or indirect connection using one or more other intermediate elements. Embodiments described herein as "communicating" or "communicating with" another device, module, or element include any form of communication or link and include an effective relationship. For example, a wired connection, a wireless protocol, a near-field protocol, or RFID can be used to establish a communication link.

[0081] To the extent that the terms "includes," "comprising," "having," "having," "with," or variations thereof are used in the detailed description and claims, these terms are intended to be inclusive in a manner similar to the term "comprising."

[0082] Therefore, the scope of the present invention is not limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is embodied by the appended claims.

Claims

1. A method for guiding physical generation of a network-on-chip (NoC), the method comprising: receiving a floor plan having blocking areas and non-blocking areas; generating a plurality of regions within the non-blocked area; receiving a list of cells to be constrained to a first region selected from the plurality of regions; Merging the first region to capture at least a portion of a nearby region of the plurality of regions that overlaps with the first region to generate an optimized first region; splitting the optimized first region into smaller regions meeting a threshold region size to include desired cells and reduce congestion; as well as A final region is provided with utilization data optimized for the final region. The method according to claim 1 , wherein the final area is a polygonal area avoiding the blocked area.

3. A design tool for generating a network-on-chip (NoC) topology in a floorplan, the tool comprising a region builder unit that allows the generation of polygonal regions that avoid blocked areas in the floorplan and optimize each region.

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