A method and system for optimizing the mixed-size layout of integrated circuit physical units

Abstract

The application discloses a kind of integrated circuit physical unit mixed size layout optimization method and system thereof.The method obtains the circuit netlist information of chip, extracts standard cell cluster, double-channel image input feature, the graph structure information of circuit, and is preprocessed;Double-channel image input feature after pre-processing, the graph structure information of circuit is input into the layout optimization model based on depth reinforcement learning and prediction trained to predict the layout action of each macro unit, and then the placement of all macro units is completed;Standard cell is distributed in the adjacent area of corresponding macro unit, to form initial layout;Performing back-end layout optimization tool adjusts standard cell to initial layout, finally realizes mixed size layout optimization on target circuit.The application realizes end-to-end mixed size layout optimization, significantly improves layout quality, reduces congestion, shortens convergence time, and shows good generalization ability on a variety of different scale circuits.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic design automation, and particularly relates to a mixed-size layout optimization method and system for integrated circuit physical units. BACKGROUND

[0002] Placement in chip physical design is a key link for determining the final performance, power consumption and area (PPA) of an integrated circuit. It is responsible for determining the precise physical positions of millions or even billions of standard cells and macro cells (such as memory blocks, IP cores, etc.) on a chip. The quality of placement directly affects the feasibility of subsequent routing, timing convergence and the overall reliability of the chip. With the rapid growth of circuit size under advanced process nodes, the placement problem faces unprecedented challenges, and the design space is extremely large, making it extremely difficult to find a globally optimal solution. Traditional placement methods, especially for mixed-size designs containing macro cells and standard cells, often fail to obtain high-quality solutions within a reasonable time. Mixed-size placement is considered the preferred strategy for modern high-performance chip design because it can optimize the positions of macro cells and standard cells simultaneously, thereby achieving better overall performance. However, this simultaneous optimization feature also significantly increases the complexity of the problem, placing higher demands on the efficiency and effectiveness of placement algorithms, and therefore there is an urgent need to develop more advanced and efficient optimization methods to address this challenge.

[0003] In recent years, machine learning techniques, especially supervised learning and reinforcement learning, have been widely explored and applied to solve complex chip placement problems. Supervised learning-based methods usually learn the mapping relationship from circuit connectivity (netlist) to physical indicators (such as wire length) to guide placement. This kind of method needs to build a large-scale training dataset and predict or generate high-quality placement schemes through model inference. However, its main limitation is the need for a large amount of pre-training time and computing resources to generate the dataset, and there is often a significant difference between synthetic data and real circuits, which may lead to poor performance of the learned strategy in practical applications. In contrast, reinforcement learning (RL)-based methods show more potential. Reinforcement learning learns through the interaction of agents (Agents) with the environment (chip canvas and placement rules) to gradually optimize the placement strategy to maximize the cumulative reward (usually related to wire length, congestion, etc.). Subsequent studies such as DeepPR, MaskPlace, and DeepTH, etc. continuously improve the performance of reinforcement learning in the placement task by introducing richer state representations (such as visual feature embedding), designing more intensive reward functions, and adding additional fine-tuning stages. Although reinforcement learning methods have advantages in self-learning and exploring complex design spaces, existing research mostly adopts a two-stage strategy: first, using reinforcement learning to focus on the placement of macro cells, and then processing standard cells. This separate processing method fails to fully utilize the advantages of mixed-size placement that can optimize both macro cells and standard cells, and breaks the close relationship between the two, often leading to suboptimal placement results and requiring additional optimization iterations to make up for it, thereby prolonging the overall design cycle. In addition, previous methods also have shortcomings in state representation, such as ignoring pin density information which is crucial for routing, or using models (such as traditional CNN) that are not sensitive enough to the features of the edge area of the placement canvas, failing to fully capture valuable global spatial information for placement decisions. SUMMARY

[0004] The present application aims to at least solve the problems of existing mixed-size placement methods that only optimize macro cells, ignore the collaborative placement of macro cells and standard cells, and have poor generalization ability and automatic optimization performance. The present application provides a mixed-size placement optimization method and system for integrated circuit physical units to improve placement quality and accelerate optimization efficiency, and solves the problems of long wire length, severe congestion, and difficult back-end layout in traditional methods.

[0005] To solve the above problems, the present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a mixed-size placement optimization method for integrated circuit physical units, comprising:

[0007] Obtaining circuit netlist information of a chip, constructing a layout dataset, and preprocessing the layout dataset; the layout dataset contains standard cell clusters with macro cells as fixed vertices, double-channel image input features, and graph structure information of the circuit;

[0008] Constructing a layout optimization model based on deep reinforcement learning and prediction, and training the model using the preprocessed layout dataset;

[0009] Extracting standard cell clusters, double-channel image input features, and graph structure information of the circuit from the circuit netlist information of the chip to be optimized, and preprocessing the information;

[0010] Inputting the preprocessed double-channel image input features and graph structure information of the circuit into the trained layout optimization model based on deep reinforcement learning and prediction to predict the layout action of each macro cell, and then completing the placement of all macro cells; distributing standard cells in the adjacent area of the corresponding macro cell to form an initial layout; adjusting the standard cells of the initial layout using a back-end layout optimization tool to finally realize mixed-size layout optimization on the target circuit.

[0011] Preferably, the obtaining circuit netlist information of a chip, constructing a layout dataset includes:

[0012] Extracting the circuit netlist information of the target chip, obtaining macro cells, standard cells, and their connection relationships;

[0013] Setting the macro cells as fixed vertices, performing graph partitioning on the circuit netlist to generate multiple standard cell clusters with macro cells as fixed vertices, i.e., macro-standard cluster structures;

[0014] Generating a macro cell coverage map and a pin density map according to the macro cells and standard cells, and then forming double-channel image input features;

[0015] Modeling the circuit netlist of the chip as a graph, regarding all macro cells and standard cells as nodes in the graph; constructing graph structure information of the circuit according to the connection relationships between the macro cells and the standard cells.

[0016] More preferably, the macro cell coverage map is a region marking on a two-dimensional grid according to the geometric size and position of the placed macro cells; if a pixel grid is covered by a macro cell, the corresponding position is assigned a value of 1, otherwise a value of 0.

[0017] More preferably, the pin density map is formed by extracting the pin positions of each standard cell, counting the number of all pins in each grid, and normalizing the density values.

[0018] More preferably, the graph structure information of the circuit includes an adjacency matrix and node attribute information.

[0019] The adjacency matrix A is a binary matrix, wherein the element in the ith row and jth column satisfies: if there is a connection between nodes, =1; if there is no connection between nodes, =0.

[0020] The node attribute information includes node type, area, whether placed, graph partition cluster number, and current coordinates; the node type is a macro cell or a standard cell.

[0021] Preferably, the layout optimization model based on deep reinforcement learning and prediction comprises a visual Transformer model, a graph attention network, and a policy network.

[0022] The macro cell coverage map and the pin density map are input into the visual Transformer model to extract graph visual features.

[0023] The graph structure information is input into the graph attention network, and the graph structure features of logical connection relationships are extracted through global pooling.

[0024] The graph visual features and the graph structure features are spliced into a layout state vector and input into the policy network.

[0025] The policy network is trained using a reinforcement learning algorithm to output a layout action for each macro cell.

[0026] During the training of the policy network, the following reward function is used for policy updating:

[0027]

[0028] wherein HPWL is the layout length, Congestion is a local congestion index, and λ is a weight coefficient.

[0029] More preferably, the visual Transformer model comprises an image blocking module, a linear embedding module, and a multi-layer Transformer encoder, and the implementation process is as follows:

[0030] The macro cell coverage map and the pin density map are input into the image blocking module to divide the two images into a plurality of patches; the linear embedding module performs linear mapping and position coding on each patch; the image spatial representation is extracted through the multi-layer Transformer encoder to obtain the graph visual features.

[0031] In a second aspect, the application provides an integrated circuit physical cell mixed size layout optimization system, comprising:

[0032] The data acquisition module is responsible for extracting standard cell clusters, double-channel image input features and graph structure information of the circuit of the chip to be optimized, and performing preprocessing;

[0033] The macro cell layout action prediction module is responsible for inputting the preprocessed double-channel image input features and graph structure information of the circuit into the trained layout optimization model based on deep reinforcement learning and prediction to predict the layout action of each macro cell.

[0034] The circuit layout module is responsible for placing all macro cells according to the predicted layout action of each macro cell, distributing standard cells in the adjacent area of the corresponding macro cell to form an initial layout, and adjusting the standard cells of the initial layout by using a back-end layout optimization tool to finally realize mixed-size layout optimization on the target circuit.

[0035] In a third aspect, the present application provides an electronic device comprising a processor and a memory, wherein the memory stores machine executable instructions capable of being executed by the processor, and the processor executes the machine executable instructions to implement the method.

[0036] In a fourth aspect, the present application provides a machine readable storage medium, characterized in that the machine readable storage medium stores machine executable instructions, and the machine executable instructions, when called and executed by a processor, cause the processor to implement the method.

[0037] Compared with the prior art, the present application has the following beneficial effects:

[0038] The present application avoids the layout fragmentation caused by the traditional two-stage optimization by setting the macro cell as a fixed vertex to perform graph partitioning, generating a standard cell cluster centered on the macro cell, establishing the topological correlation between the macro cell and the standard cell, providing a neighboring area guide mechanism for the standard cell, reducing the randomness of the initial layout, and shortening the iteration number of the back-end optimization.

[0039] The present application avoids illegal overlap by introducing a macro cell coverage graph to quantify the physical constraints of the macro cell, and a pin density graph to capture the key area of wiring, and solves the local congestion problem caused by the traditional method ignoring the pin distribution.

[0040] The present application constructs a macro-standard cluster structure through graph partitioning, realizes spatial layout state modeling by combining a macro coverage graph and a pin density graph, introduces a visual Transformer and a graph attention network to jointly extract visual and structural features, uses a PPO reinforcement learning strategy network to output macro layout actions, realizes end-to-end mixed-size layout optimization by guiding the placement position of the standard cell, significantly improves the layout quality, reduces congestion, shortens the convergence time, and exhibits good generalization ability on a variety of different scale circuits. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0042] Figure 1 is a flow chart of the integrated circuit physical unit mixed size layout optimization method provided by the embodiment of the present application.

[0043] Figure 2 is a schematic diagram of the macro-cluster structure division and construction provided by the embodiment of the present application.

[0044] Figure 3 is an architecture diagram of the layout optimization model based on deep reinforcement learning and prediction. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described in detail below with reference to the drawings. It should be understood that the embodiments described herein are only used to illustrate the present application, and are not used to limit the protection scope of the present application. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, different proportions are sometimes used in different drawings to show different emphases.

[0046] The present application provides an integrated circuit physical unit mixed size layout optimization method, and a scheme flow chart is shown as follows. Figure 1 Firstly, a layout data set containing layout information of macro and standard cells is constructed, and image normalization and other preprocessing operations are performed thereon. Secondly, a layout optimization model based on deep reinforcement learning and prediction is constructed, and the preprocessed data set is used for training. Then, the trained strategy model is used to perform layout optimization on the test circuit, and the cluster structure is used to guide the initialization position of the standard cell to realize the mixed size layout.

[0047] Specifically, the embodiment provides an integrated circuit physical unit mixed size layout optimization method, as shown in the accompanying drawings. Figure 1 for improving the joint layout quality of macro cells and standard cells in the physical design stage of integrated circuits. The method comprises the following steps:

[0048] Step S1: Obtain the circuit netlist information of the chip, and construct a layout data set. The layout data set contains standard cell clusters with macro cells as fixed vertices, double-channel image input features, and graph structure information of the circuit;

[0049] Step S2: Preprocess the layout data set;

[0050] Step S3: Construct a layout optimization model based on deep reinforcement learning and prediction, and train it using the preprocessed layout dataset;

[0051] Step S4: Extract standard cell clusters, double-channel image input features, and graph structure information of the circuit from the circuit netlist information of the chip to be optimized, and preprocess them;

[0052] Input the double-channel image input features and the graph structure information of the circuit into the trained layout optimization model based on deep reinforcement learning and prediction to predict the layout action of each macro cell, and then complete the placement of all macro cells;

[0053] Distribute the standard cells in the vicinity of the corresponding macro cells to form an initial layout;

[0054] Execute the backend placement optimization tool DREAMPlace to adjust the standard cells of the initial layout, and finally realize mixed-size layout optimization on the target circuit.

[0055] In one embodiment, the step S1 includes the following sub-steps:

[0056] S101: Extract the circuit netlist information of the chip circuit sample, i.e., the gate-level netlist information, to obtain the macro cells, standard cells, and their connection relationships. The chip circuit sample is a plurality of chip circuit samples with different layout area sizes and macro cell quantities, which are used to improve the generalization ability of the strategy network for circuits of different scales.

[0057] S102: Set the macro cells as fixed vertices, perform graph partitioning on the circuit netlist, and generate a plurality of standard cell clusters with macro cells as fixed vertices, i.e., macro-standard cluster structures;

[0058] Referring to FIG. 2, Figure 2 This embodiment starts from the input gate-level netlist, first extracts the attribute information of the macro cells and standard cells, then constructs a logical connection graph, specifies the macro cells as fixed vertices, and then calls a graph partitioning tool (such as KaHyPar) to divide the standard cells into a plurality of clusters, each cluster is bound to a macro cell, forming a macro-standard cluster structure, providing structural guidance for subsequent layout optimization.

[0059] S103: Generate macro cell coverage maps and pin density maps according to the macro cells and standard cells, respectively, and then form double-channel image input features;

[0060] S104: Perform graph modeling on the circuit netlist of the chip, and regard all macro cells and standard cells as nodes in the graph; according to the connection relationship between the macro cells and the standard cells, construct the graph structure information of the circuit;

[0061] As an example, in the step S103, the macro cell coverage map is to mark the area on the two-dimensional grid according to the geometric size and position of the placed macro cell. If a pixel grid is covered by a macro cell, the corresponding position is assigned a value of 1, otherwise 0.

[0062] The pin density map is formed by extracting the pin position of each standard cell, counting the number of all pins in each grid, and then normalizing the density value.

[0063] As an example, in the step S104, the graph structure information includes an adjacency matrix and node attribute information.

[0064] The adjacency matrix A is a binary matrix, where the element in the ith row and jth column is If there is a connection between nodes, then =1; if there is no connection between nodes, then =0.

[0065] The connection between nodes refers to being in the same logical network or being connected through a port.

[0066] The node attribute information includes node type (i.e. macro cell or standard cell), area, whether placed, graph partition cluster number, current coordinates (if placed), etc. The node type is represented in one-hot encoding form, such as (1, 0) representing a macro cell and (0, 1) representing a standard cell. If the coordinate information is empty, it can be set to 0 or normalized to a placeholder.

[0067] In one embodiment, the step S2 includes the following sub-steps:

[0068] S201: Normalize the macro cell coverage map and the pin density map so that all input images have uniform size and numerical scale;

[0069] S202: Encode each standard cell cluster, with the macro cell number of its own fixed vertex as the cluster structure label;

[0070] S203: Pack the layout state and the cluster structure label into a layout state-label pair form to form the final input data set that can be used for training;

[0071] S204: Divide the complete data set into a training set and a test set.

[0072] In one embodiment, refer to the attached Figure 3, the layout optimization model based on deep reinforcement learning and prediction in the step S3 includes a visual Transformer model, a graph attention network (GAT), and a policy network; the visual Transformer is used to extract graph visual features, the graph attention network (GAT) is used to extract graph structure features, and the policy network is input after the layout state vector is formed by splicing to make action decisions. The policy network is trained and optimized based on the PPO reinforcement learning algorithm.

[0073] S301: input the macro cell coverage map and the pin density map into the visual Transformer model to extract graph visual features;

[0074] S302: input the graph structure information into the graph attention network, and extract the graph structure features of the logical connection relationship through global pooling;

[0075] S303: splice the graph visual features and the graph structure features into a layout state vector, and input the layout state vector into the policy network;

[0076] S304: train the policy network using the reinforcement learning algorithm (PPO) to output the layout action of each macro cell.

[0077] As an example, the visual Transformer model includes an image blocking module, a linear embedding module, and a multi-layer Transformer encoder, and the implementation process is as follows:

[0078] input the macro cell coverage map and the pin density map into the image blocking module, cut the two images into a plurality of patches; the linear embedding module performs linear mapping and position coding on each patch; the multi-layer Transformer encoder is used to extract the image spatial representation to obtain the graph visual features .

[0079] As an example, the adjacency matrix and the node attribute information are extracted through the graph attention network (GAT) to obtain node embedding, and the graph structure features are output through Global Pooling (global pooling) .

[0080] The graph attention network includes a plurality of graph attention layers, each layer is used to aggregate the features of adjacent nodes, and the update mode is as follows:

[0081]

[0082] wherein σ is an activation function, W is a weight matrix, is an attention coefficient, is the feature vector of the updated node , and represents the node original eigenvectors of the graph, denotes the set of neighboring nodes of node i.

[0083] As an example, the graph visual features and the graph structure features After splicing, the layout state vector is generated , the input strategy network , the output current layout action , and the evaluation value of the state is estimated by the value network In the strategy training process, the strategy network is optimized by using the reward function in the following form:

[0084]

[0085] wherein, HPWL is the total wire length of the current layout, Congestion is the local congestion amount, is an adjustable weight coefficient.

[0086] The strategy network is constructed based on the Proximal Policy Optimization (PPO) algorithm, and includes an Actor network and a Critic network.

[0087] The Actor network is used to output the position selection probability distribution of the current macro cell; the Critic network is used to estimate the state value function V(s) and participate in the advantage function calculation ; the strategy update target function is:

[0088]

[0089] wherein:

[0090] The strategy network further includes two output heads, which are respectively used to generate the probability distribution of position selection and the probability distribution of optimization operator selection, so as to jointly determine which position in the sequence and which optimization operator should be applied under the current state.

[0091] The Critic network evaluates the current state and calculates the advantage function in combination with the actual feedback to optimize the parameter update of the strategy network.

[0092] The advantage function At is obtained by calculating the difference between the actually obtained reward (i.e. the output of the reward function) and the state value evaluation result under the current strategy.

[0093] In one embodiment, the step S4 includes the following sub-steps:

[0094] ​S401: In the layout area, the layout action of the macro cell output by the policy network is sequentially placed according to the corresponding macro cell;

[0095] S402: According to the standard cell cluster and the layout state-tag pair, the standard cell is distributed in the adjacent area of the corresponding macro cell to form an initial layout; each standard cell is divided into a certain macro cell cluster; the standard cell will be placed in the adjacent area of the macro cell to which it belongs uniformly and randomly, which is usually set as the area with the macro cell center as the circle center and the radius being d times the diagonal line of the macro cell (for example, d∈[1.5, 2.5]); both the standard cell is ensured to be close to the macro cell, and overlapping is avoided; the value of d can be optimized in the experiment, or can be set as a model hyperparameter.

[0096] S403: The initial layout is adjusted by the backend layout optimization tool DREAMPlace; the DREAMPlace performs backend layout optimization on the standard cell, including position legalization, gradient-driven fine placement, congestion-aware layout and other operations, the whole process aims to eliminate overlapping, meet the row and column constraints, and improve the layout quality through density balance and line length optimization, and finally outputs the final mixed-size layout result.

[0097] Table 1: Experimental environment of the integrated circuit physical unit mixed-size layout optimization method provided by the application

[0098]

[0099] Table 2: Comparison of the application and the prior art in the HPWL index (×10 7 ) on the experimental results table

[0100]

[0101] The application provides an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions capable of being executed by the processor, and the processor executes the machine executable instructions to implement the method.

[0102] The memory configuration related to the application can include fast random access memory (RAM) and non-volatile storage media such as hard disk and other disk storage devices. The system establishes a communication connection with at least one external network element through at least one communication interface (which can be wired or wireless), supports data exchange through various network environments such as the Internet, a wide area network, a local area network or a metropolitan area network.

[0103] The bus can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0104] The memory is used to store program codes. When the processor receives an instruction to execute the programs, it runs the programs stored in the memory. The method flow defined in any embodiment described in the present application can be integrated into the operation of the processor, or implemented by the processor. In short, the processor will execute the programs in the memory after receiving the execution command, to implement the method disclosed in the present application.

[0105] The processor can be an integrated circuit chip with a signal processing function. In the implementation of the method of the present application, each step can be realized by a hardware logic circuit or a software instruction inside the processor. The processor can be a general-purpose processor such as a central processing unit (CPU), a network processor (NP), etc., or a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate and transistor logic device, a discrete hardware component. These processors can realize or execute the various methods, steps and logic flows disclosed in the present application.

[0106] The general-purpose processor can be a microprocessor or any standard processor. The method steps of the present application can be directly executed by a hardware decoding processor, or by a combination of hardware and software modules in a decoding processor. The software modules can be stored in a mature storage medium such as random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM) or electrically erasable programmable memory (EEPROM). These storage media are located in the memory, and the processor reads information from them and combines them with the hardware to complete the steps of the above method.

[0107] One embodiment of the present application provides a computer program product stored in a readable storage medium, containing a series of program codes. The codes contain instructions that can implement the flow described in the foregoing method embodiments. The specific implementation details have been described in detail in the foregoing method embodiments, which will not be repeated here. In short, this computer program product enables the storage medium to be used to execute the method disclosed in the present application.

[0108] The above is the preferred embodiment of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A method for optimizing the layout of mixed-size physical units of an integrated circuit, characterized in that: The method comprises: Obtaining the circuit netlist information of the chip, constructing a layout data set, and preprocessing it; the layout data set includes a standard cell cluster with macro cells as fixed vertices, dual-channel image input features, and circuit graph structure information; Build a layout optimization model based on deep reinforcement learning and prediction, and train it using the preprocessed layout dataset; Extract standard cell clusters, dual-channel image input features, and circuit graph structure information from the circuit netlist information of the chip to be optimized, and perform preprocessing; The preprocessed dual-channel image input features and the circuit's graph structure information are input into a trained layout optimization model based on deep reinforcement learning and prediction to predict the layout action of each macro cell, thereby completing the placement of all macro cells. The standard cells are distributed in the adjacent areas of their corresponding macro cells to form an initial layout. The back-end layout optimization tool is executed to adjust the standard cells in the initial layout, ultimately achieving mixed-size layout optimization on the target circuit.

2. The method according to claim 1, characterized in that The obtaining of the circuit netlist information of the chip and constructing the layout data set includes: Extract the circuit netlist information of the target chip and obtain the macro cells, standard cells and their connection relationships; The macro cell is set as a fixed vertex, and the circuit netlist is partitioned to generate multiple standard cell clusters with the macro cell as a fixed vertex, i.e., a macro-standard cluster structure; Generate macrocell coverage map and pin density map based on macrocell and standard cell respectively, and then form dual-channel image input features; The circuit netlist of the chip is graph-modeled, and all macro cells and standard cells are regarded as nodes in the graph; based on the connection relationship between macro cells and standard cells, the graph structure information of the circuit is constructed.

3. The method according to claim 2, characterized in that The macro unit coverage map is to mark the areas of the placed macro units on a two-dimensional grid according to their geometric size and position. If a pixel grid is covered by a macro unit, the corresponding position is assigned a value of 1, otherwise it is assigned a value of 0.

4. The method according to claim 2, characterized in that The pin density map is formed by extracting the pin positions of each standard unit, counting the number of all pins in each grid, and normalizing the result to obtain a density value.

5. The method according to claim 2, characterized in that The graph structure information of the circuit includes an adjacency matrix and node attribute information; The adjacency matrix A is a binary matrix, where the element in row i and column j is Satisfies: If there is a connection between nodes, then =1; if there is no connection between nodes, then =0; The node attribute information includes node type, area, whether it has been placed, graph partition cluster number, and current coordinates; the node type is a macro cell or a standard cell.

6. The method according to claim 1, characterized in that The layout optimization model based on deep reinforcement learning and prediction includes a visual Transformer model, a graph attention network, and a policy network; The macrocell coverage map and pin density map are fed into the visual Transformer model to extract the visual features of the map. The graph structure information is input into the graph attention network, and the graph structure features of the logical connection relationship are extracted through global pooling; The graph visual features and graph structural features are concatenated into a layout state vector and input into the policy network; Use reinforcement learning algorithms to train a policy network to output the placement actions for each macro unit; During the policy network training process, the following reward function is used to update the policy: ； Where HPWL is the layout wire length, Congestion is the local congestion index, and λ is the weight coefficient.

7. The method according to claim 6, characterized in that The visual Transformer model includes an image partitioning module, a linear embedding module, and a multi-layer Transformer encoder. Its implementation process is as follows: The macrocell coverage map and pin density map are input to the image segmentation module to divide the two images into several patches; the linear embedding module performs linear mapping and position encoding on each patch; through the multi-layer Transformer encoder, the image spatial representation is extracted to obtain the image visual features.

8. An integrated circuit physical unit mixed-size layout optimization system implementing the method according to any one of claims 1 to 7, characterized in that include: The data acquisition module is responsible for extracting standard cell clusters, dual-channel image input features, and circuit graph structure information from the circuit netlist information of the chip to be optimized, and performing preprocessing; The macrocell layout action prediction module is responsible for inputting the preprocessed dual-channel image input features and circuit graph structure information into the trained deep reinforcement learning and prediction-based layout optimization model to predict the layout action of each macrocell; The circuit layout module is responsible for completing the placement of all macrocells based on the predicted layout actions of each macrocell; distributing standard cells in the adjacent areas of their corresponding macrocells to form an initial layout; executing the back-end layout optimization tool to adjust the standard cells in the initial layout, and finally achieving mixed-size layout optimization on the target circuit.

9. A machine-readable storage medium, characterized in that The machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method according to any one of claims 1 to 7.

Images