Feature information synchronization method, device, system and equipment of electric power communication signal frame

Abstract

The invention discloses a feature information synchronization method, device, system and equipment of an electric power communication signal frame, and belongs to the technical field of communication. The method comprises the following steps: in response to a frame synchronization starting signal of a current signal frame, triggering calculation of corresponding feature information, and writing the feature information into a baseband cache; after frame synchronization is completed, the feature information is moved from a baseband cache to a shadow register for subsequent reading of a processing module; and when the data stored in the memory module by the current signal frame is not read by the processing module, if a frame synchronization completion signal of the next signal frame is detected, updating the feature information stored in the shadow register according to a synchronization strategy. According to the method, the shadow register is introduced, and a feature information retention mechanism based on a synchronization strategy is combined, so that the accuracy of feature information synchronization and the system stability are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a method, device, system and equipment for synchronizing characteristic information of power communication signal frames. Background Art

[0002] In high-speed power line communication (HPLC) systems, signal receiving devices typically need to calculate and store channel characteristic information corresponding to received frames, such as channel estimation (CE), received signal strength indicator (RSSI), and signal-to-noise ratio (SNR). This characteristic information is often used to support the development of upper-layer software applications such as protocol parsing, link assessment, and network management. Therefore, ensuring the accurate matching and reliable storage of this information is a key issue in system design.

[0003] However, there is a certain degree of uncertainty between the storage of feature information and its reading by software, which is manifested in the following two aspects: (1) When the receiving device is receiving a signal frame (such as the frame control field FC or the physical layer payload PL), if the software synchronization mechanism is not rigorous, it may read channel characteristic information that does not correspond to the current frame, causing the application layer data and channel information to be misaligned; (2) Since the calculation and update process of characteristic information is usually carried out in parallel with data reception, if the write control or latching strategy is not designed properly, it may lead to inconsistency between the channel characteristic information and the actual received frame, further causing protocol stack misjudgment or state management abnormality.

[0004] Therefore, a reliable latching and access mechanism for feature information is urgently needed to ensure that the channel state information obtained by the processor at any time remains consistent with the current processing context, so as to improve system stability and protocol robustness. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention proposes a method, device, system and equipment for synchronizing characteristic information of power communication signal frames to improve the accuracy of characteristic information synchronization and system stability.

[0006] In a first aspect, the present invention provides a method for synchronizing characteristic information of a power communication signal frame, the method comprising: In response to a frame synchronization start signal of a current signal frame, triggering calculation of corresponding feature information and writing the feature information into a baseband buffer; After completing frame synchronization, the feature information is moved from the baseband cache to the shadow register for subsequent reading by the processing module; During the period when the data of the current signal frame stored in the memory module has not been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the feature information stored in the shadow register is updated according to the synchronization strategy.

[0007] The characteristic information synchronization method of the power communication signal frame provided by the present invention realizes the stable latching and intelligent updating of the characteristic information by introducing shadow registers and synchronization strategies in the frame synchronization stage, thereby improving the robustness of continuous frame reception and the reliability of characteristic synchronization in the power communication system.

[0008] In a second aspect, the present invention provides a device for synchronizing characteristic information of a power communication signal frame, the device comprising: a calculation module, configured to trigger calculation of corresponding feature information in response to a frame synchronization start signal of a current signal frame, and write the feature information into a baseband cache; A moving module, configured to move the feature information from the baseband cache to the shadow register after completing frame synchronization, so as to be subsequently read by the processing module; The synchronization module is used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected during the period when the data of the current signal frame stored in the memory module has not been read by the processing module.

[0009] In a third aspect, the present invention provides a power communication system, the system comprising: A signal sending device, configured to send a power communication signal comprising continuous signal frames; A signal receiving device is used to receive the power communication signal and execute the characteristic information synchronization method of the power communication signal frame as described in the first aspect.

[0010] In a fourth aspect, the present invention provides a signal receiving device, comprising a baseband and a central processing unit, wherein the baseband is configured with a shadow register; wherein: The baseband is configured to trigger calculation of corresponding feature information in response to a frame synchronization start signal of the current signal frame, and write the feature information into a baseband cache; after completing frame synchronization, move the feature information from the baseband cache to a shadow register for subsequent reading by a central processing unit; The baseband is further configured to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected during a period in which the data of the current signal frame stored in the memory module has not yet been read by the processing module; The central processing unit is used to read feature information from the shadow register to perform upper layer application processing.

[0011] In a fifth aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the characteristic information synchronization method of the power communication signal frame as described in the first aspect above.

[0012] In a sixth aspect, the present invention provides a chip comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a computer program or instruction to implement the characteristic information synchronization method of the power communication signal frame as described in the first aspect above.

[0013] In a seventh aspect, the present invention provides a computer program product, comprising a computer program, which, when executed by a processor, implements the characteristic information synchronization method of the power communication signal frame as described in the first aspect above.

[0014] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which: Figure 1 Schematic diagram of an application scenario of a method for synchronizing characteristic information of a power communication signal frame provided in some embodiments of the present invention; Figure 2 is a schematic diagram of a power line carrier communication signal processing process provided in some embodiments of the present invention; Figure 3 is a schematic diagram of a process for synchronizing feature information provided in some embodiments of the present invention; Figure 4 is a signal diagram of a feature information synchronization process provided in some embodiments of the present invention; Figure 5 is a flowchart of a method for synchronizing characteristic information of a power communication signal frame provided in some embodiments of the present invention; Figure 6 It is a schematic diagram of the principle of underlying data interaction provided in some embodiments of the present invention; Figure 7 is a schematic diagram of signals under normal conditions provided in some embodiments of the present invention; Figure 8 is a schematic diagram of signals under a delay condition provided in some embodiments of the present invention; Figure 9 is a signal diagram of a frame conflict handling strategy provided in some embodiments of the present invention; Figure 10 is a signal diagram of another frame conflict handling strategy provided in some embodiments of the present invention; Figure 11 is a signal diagram of a feature information synchronization process provided in some embodiments of the present invention; Figure 12 2 is a schematic structural diagram of a device for synchronizing characteristic information of a power communication signal frame provided in some embodiments of the present invention; Figure 13 It is a structural diagram of a signal receiving device provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0017] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meanings as commonly understood by those skilled in the art to which the present invention pertains. The terms used in the specification and application of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The terms "including" and "having," as well as any variations thereof, in the specification and claims of the present invention and the accompanying drawings are intended to cover non-exclusive inclusions. The terms "first," "second," etc., in the specification and claims of the present invention and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order or a primary-secondary relationship.

[0018] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0019] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "attached" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0020] The term "and / or" in this disclosure simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this disclosure generally indicates that the related objects are in an "or" relationship.

[0021] The term "multiple" used in the present invention refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple sheets" refers to more than two sheets (including two sheets).

[0022] The following describes in detail the method for synchronizing characteristic information of a power communication signal frame provided by the embodiment of the present invention through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0023] Figure 1 The embodiment of the present invention provides a method for synchronizing the characteristic information of the power communication signal frame, which can be applied to the following scenarios: Figure 1 In the application environment of the power communication system shown in FIG. The power communication system includes a signal transmitting device and a signal receiving device. The signal transmitting device is used to transmit a power communication signal, which may include continuous signal frames. The signal receiving device is used to receive the power communication signal and perform subsequent processing such as channel estimation.

[0024] The signal transmitting device and the signal receiving device may be, for example, a computer device, which may be a power line communication terminal, a concentrator device, a smart meter, a device with an embedded communication module, or a communication test terminal. Alternatively, the computer device may be a device or intelligent robot with computing capabilities, configured to perform signal reception, processing, and subsequent processing tasks in the present invention.

[0025] Based on the above application scenarios, the present invention can be applied to scenarios of power line carrier communication signal processing. Figure 2 FIG. 1 is a schematic diagram of a power line carrier communication signal processing process provided in some embodiments of the present invention. Figure 2As shown, in an exemplary embodiment, the transmitter (i.e., the signal transmitting device) encodes the frame control data and payload data, then adds a preamble to the frame signal through an inverse fast Fourier transform (IFFT), a cyclic prefix, and windowing. The preamble is then transmitted to the power line channel via an analog front-end. The receiver (i.e., the signal receiving device) receives the signal through the analog front-end and performs preliminary signal alignment using automatic gain control and a clock or frame synchronization mechanism. The receiver then converts the signal to the frequency domain using a fast Fourier transform (FFT) module and performs symbol recovery through demodulation. The demodulated frame control data and payload data are then decoded to recover the frame control data and data payload. All of this is accomplished within the receiver's baseband. Furthermore, the receiver uses a buffering mechanism to temporarily store relevant frame data for the current signal frame, ensuring data consistency and system stability even when multiple frames arrive consecutively.

[0026] Figure 3 FIG. 1 is a flow chart of feature information synchronization provided in some embodiments of the present invention. Figure 3 As shown, after receiving the frame data (including the preamble, frame control data and data payload), the baseband module first completes the reception and field parsing of the frame data, and extracts the corresponding feature information, such as the channel estimation value, the received signal strength indicator, the signal-to-noise ratio, etc., during the period from the start of frame synchronization (sync-begin) to the completion of frame synchronization (frame-synced), and writes it into the baseband buffer of the baseband. At the same time, the frame data of the frame control data and the data payload are transferred to the memory module to be written into the system memory. Exemplarily, the baseband module first performs a synchronization detection operation on the received signal. When three synchronization peaks are detected consecutively, the baseband module generates a sync-begin signal to mark the starting point of the current frame synchronization process. After the frame synchronization process is completed, the baseband module generates a frame-synced signal corresponding to the frame synchronization completion flag.

[0027] The baseband module then asserts the receive completion signal (rx-end-flag), transitioning from a low-level signal to a high-level signal, indicating the completion of reception and transmission of the current frame data. Upon detecting the high-level signal, the processing module (i.e., the CPU) begins reading the corresponding frame data from system memory and simultaneously retrieves the signature information from the baseband cache for use by upper-layer applications in network analysis, link assessment, and other operations. This mechanism ensures the consistent temporal and structural pairing of frame data and signature information. The receive completion signal enables data synchronization and release control between the baseband and CPU, improving the accuracy of upper-layer service processing and the overall stability of the communication system.

[0028] During the continuous reception of multiple frames, the baseband module uses the frame synchronization start signal as a trigger to continuously update the feature information in the baseband cache. For example, when the baseband module completes feature extraction between sync-begin and frame-synced while receiving frame 1, the corresponding feature information for frame 1 is written to the cache. When the baseband module begins receiving frame 2 and detects the sync-begin signal for frame 2, the baseband cache begins updating the feature information corresponding to frame 2. As a result, the contents of the baseband cache are dynamically refreshed with each frame synchronization, achieving real-time maintenance of the feature data of the currently valid frame.

[0029] Figure 4 This is a signal diagram of the feature information synchronization process provided in some embodiments of the present invention. Figure 4 As shown, at time t0, the baseband module begins frame synchronization processing for frame 1. Between sync-begin and frame-synced (i.e., time t0 to t0'), it calculates frame 1's feature information and writes it to the baseband buffer. Subsequently, at time t1, writing frame 1 data to system memory is complete, and the baseband module asserts the receive completion signal (rx-end-flag), signaling to the processing module (e.g., the CPU) that the current frame data has been received. Ideally, the CPU should promptly respond to the receive completion signal at time t2 and synchronously extract frame 1 data from system memory and frame 1's feature information from the baseband buffer, ensuring a one-to-one correspondence between the frame data and the feature information. However, in some scenarios, due to processing delays in the CPU or upper-layer software, data extraction may not be completed until time t2'. Meanwhile, if the baseband module has already begun receiving frame 2 and detects frame 2's sync-begin signal at time T1, the feature information previously stored in the baseband buffer for frame 1 will be overwritten by the new feature information for frame 2.

[0030] At this point, even if the frame data extracted by the CPU is the complete content of Frame 1, its corresponding feature information has been updated to the content of Frame 2, resulting in a mismatch between the frame data and feature information. If the application processing relies on this feature information (for example, when selecting a network based on the signal-to-noise ratio), it may cause subsequent decision errors.

[0031] This shows that the relevant technologies cannot guarantee the correct binding of frame data and feature information, and data mismatch is particularly prone to occur in high-concurrency scenarios.

[0032] Therefore, the present invention provides a characteristic information synchronization method for power communication signal frames, introduces a shadow register latch mechanism, uses a shadow register to temporarily store the characteristic information of the signal frame, and before receiving the next signal frame, determines whether to retain the current frame or update the information of the next frame according to the synchronization strategy, thereby realizing characteristic information protection and switching control between multiple frames, so as to further improve the integrity of the characteristic information of the signal frame and the synchronization reliability.

[0033] The embodiment of the present invention provides a method for synchronizing characteristic information of a power communication signal frame. The executor of the method can be a signal receiving device or a functional module or functional entity in the signal receiving device that can implement the method for synchronizing characteristic information of a power communication signal frame, such as a baseband module.

[0034] The following describes the method for synchronizing characteristic information of a power communication signal frame provided by an embodiment of the present invention by taking a signal receiving device as an example of an execution subject.

[0035] Among them, the signal receiving device includes a baseband module, a memory module and a processing module. The baseband module is responsible for demodulation and preliminary processing of signal frames, and the memory module is used to store received signal frame data.

[0036] Exemplarily, a baseband module refers to a hardware or software / hardware combination that performs underlying communication operations such as wireless signal demodulation, channel estimation, field identification, and physical layer processing. For example, a baseband module can be a hardware processing unit composed of an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), or an ASIC (Application Specific Integrated Circuit).

[0037] The memory module refers to the system storage resource used to store the complete signal frame data transmitted by the baseband module. It can be on-chip RAM (Random Access Memory), DDR (Double Data Rate) memory, or an embedded cache module.

[0038] The processing module may include an embedded processor (such as an ARM (Advanced RISC Machines) core), an MCU (Microcontroller Unit), or a main control CPU (Central Processing Unit) running in conjunction with an operating system, which is used to read the frame data in the memory module and, based on the feature information, complete further upper-layer business processing, conflict decision-making, control signal issuance, and flag signal clearing operations.

[0039] Figure 5 FIG. 1 is a flow chart of a method for synchronizing characteristic information of a power communication signal frame provided in some embodiments of the present invention. Figure 5 As shown, the characteristic information synchronization method of the power communication signal frame includes: steps 510 to 530.

[0040] Step 510: In response to the frame synchronization start signal of the current signal frame, trigger the calculation of corresponding feature information and write the feature information into the baseband cache.

[0041] The characteristic information refers to data extracted from the received signal frame that characterizes the characteristics of the frame, including but not limited to one or more of the following: channel estimation amplitude (CE), signal-to-noise ratio (SNR), received signal strength indicator (RSSI), etc.

[0042] After detecting the sync-begin signal for the current signal frame, the baseband module enters the feature extraction process. During this process, the baseband module performs frequency domain transforms or matched filtering on the received data of the current signal frame based on the synchronization pattern (SYNCP), pilot symbols, or a predefined reference symbol set. This extracts one or more feature information and writes it to an internal buffer for subsequent transfer operations.

[0043] Step 520: After completing frame synchronization, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the processing module.

[0044] After the current signal frame completes frame synchronization, the baseband module detects the frame synchronization completion signal (frame-synced) of the current signal frame, and then the baseband module moves the feature information version corresponding to the current signal frame in the baseband cache to the shadow register.

[0045] This shadow register serves as a dedicated register area for feature reading and has a write protection mechanism to prevent it from being overwritten by subsequent frame information during CPU reading, thereby ensuring the integrity and consistency of the read data.

[0046] In some embodiments, the baseband module determines that the feature information corresponding to the signal frame is complete and available, thereby triggering a move operation.

[0047] The move operation can trigger the shadow register to write the frame feature information of the current signal frame through the circuit in the baseband, ensuring that the feature information is locked in the corresponding shadow register for subsequent processing modules (such as CPU) to read, process or report.

[0048] Step 530: During the period when the data of the current signal frame stored in the memory module has not been read by the processing module, if a frame synchronization completion signal of the next signal frame is detected, the feature information stored in the shadow register is updated according to the synchronization strategy.

[0049] Assume that the baseband module is processing frame 1. At this point, the data for frame 1 has been successfully transferred to the system memory, and relevant frame characteristics (such as the channel estimation SNR and received signal strength RSSI) have been stored. The baseband module writes this characteristic information to the shadow register and sets the relevant flags, indicating that the frame data is ready for processing.

[0050] If the CPU has not read the frame 1 data during this period, for example, the CPU may be processing other tasks, and the baseband module receives the frame synchronization completion signal of the next frame (i.e., frame 2), indicating that the synchronization process of frame 2 is complete, the baseband module makes a decision based on the preset synchronization strategy, including: One synchronization strategy is to retain the characteristic information of the current frame 1. That is, if the strategy determines to continue to process frame 1 first, the shadow register will not update the latched characteristic information until the CPU completes reading frame 1 and clears its flag.

[0051] Another synchronization strategy involves updating the shadow register. Specifically, if the strategy decides to discard the signature information for frame 1, the baseband module triggers an update based on the sync-begin signal. The shadow register then writes the signature information for frame 2, overwriting the original signature data for frame 1. At this point, the data in the shadow register corresponds to the signature information for frame 2, while the signature information for frame 1 is discarded.

[0052] The above synchronization strategy can ensure that the feature information obtained by the CPU at any time matches the signal frame currently being processed, thereby improving the accuracy of feature information synchronization and system stability.

[0053] The characteristic information synchronization method of the power communication signal frame provided by the embodiment of the present invention improves the real-time and synchronization of characteristic information extraction by triggering characteristic information calculation after detecting a frame synchronization signal; after completing frame synchronization, the characteristic information is moved from the baseband cache to the shadow register for subsequent reading by the processing module. The shadow register is introduced as a stable latch structure to move the calculated characteristic information from the easily overwritten cache area to the latch unit, effectively improving the accessibility and stability of the characteristic information, enabling the subsequent processing module to safely read it at the appropriate time, and improving the access robustness and anti-interference capability of the system; while the data stored in the memory module of the current signal frame has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the characteristic information stored in the shadow register is updated according to the synchronization strategy. By introducing a synchronization strategy judgment mechanism, it is possible to intelligently judge and filter the characteristic information to be retained in the scenario of intensively receiving continuous signal frames, effectively alleviating the characteristic data coverage conflict problem caused by processing resource lag or excessive reception frequency, thereby improving the timeliness of the characteristic information and the stable reception capability of the communication system.

[0054] In related technologies, baseband modules typically only have a standard buffer area (such as a frame buffer register) for temporarily storing feature information, lacking a shadow register structure with independent latching and management capabilities. When consecutive signal frames arrive rapidly, if the previous frame is not processed promptly by the CPU, the feature information of the subsequent frame often directly overwrites the feature information of the previous frame that has not yet been read by the processing module, resulting in premature data discard, seriously affecting frame processing accuracy and system stability.

[0055] To this end, in some embodiments, the update of the characteristic information stored in the shadow register is determined according to the synchronization strategy, including: the shadow register latches the characteristic information corresponding to the current signal frame; or, the shadow register updates the characteristic information corresponding to the current signal frame to the characteristic information corresponding to the next signal frame.

[0056] This embodiment further introduces a judgment mechanism based on a synchronization strategy, which is used to dynamically determine the target feature information retained in the shadow register in a scenario where continuous signal frames are accessed.

[0057] Specifically, if the baseband module detects that the next signal frame has completed frame synchronization, while the current signal frame has not yet been read by the processing module, it determines whether to perform a feature information transfer operation based on a preset synchronization strategy. This synchronization strategy includes: retaining the feature information of the next signal frame in the baseband cache without transferring it to the shadow register to maintain the validity of the feature information of the current signal frame; or, if the transfer conditions are met, transferring the feature information of the next signal frame from the baseband cache to the shadow register to overwrite the feature information of the current signal frame. Transfer conditions may include factors such as the presence of an overflow flag, incomplete reception, or timeout processing triggering.

[0058] It's important to note that shadow register updates aren't directly controlled by the baseband module. Instead, they're automated through hardware logic, such as gates, configured within the module. Specifically, the shadow register's state is automatically triggered by control logic based on changes in the synchronization signal and overflow flag. By controlling the gate state, the shadow register can autonomously choose whether to retain the signature information of the current signal frame or update it to the signature information of the next signal frame.

[0059] When the baseband module detects the frame synchronization completion signal for the next signal frame, the shadow register is automatically updated according to the preset synchronization strategy. This update operation relies on a hardware trigger mechanism, which controls the write and read paths of the shadow register through gate circuits to ensure that no information conflicts or losses occur during frame data processing.

[0060] Therefore, the state change of the shadow register is completely controlled by hardware and does not require the direct intervention of the baseband module or the intervention of the external processing module, thereby improving the response efficiency of the power communication system and ensuring the efficient storage and update of feature information.

[0061] In the above-described embodiment, by introducing a synchronization strategy at the shadow register layer, selective retention and update control of continuous feature information is achieved, preventing feature loss due to burst coverage and improving the communication system's ability to cope with high-speed signal frame access scenarios. This synchronization strategy dynamically makes decisions based on the quality of feature information, not only improving the accuracy of frame data processing, but also enhancing the system's robustness to asynchronous frame structures or strong channel interference.

[0062] Among them, in some embodiments, the synchronization strategy includes: during the period when the data of the current signal frame stored in the memory module has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; when the overflow flag signal is in the set state, the baseband module performs a reset operation, and the shadow register latches the characteristic information corresponding to the current signal frame.

[0063] When the baseband module detects the frame synchronization signal for the next signal frame, if the current signal frame has not yet been read by the processing module, it automatically sets the overflow flag signal (overflow_flag). The overflow flag signal is a conflict indication signal used to indicate an abnormal state in which the previous frame has not yet been processed, but the next frame has begun to enter the receive path.

[0064] Under normal circumstances, when the baseband module receives the current signal frame (for example, frame 1), it calculates the feature information from the leading symbol and temporarily stores it in the baseband cache; after completing the frame synchronization of frame 1, the baseband module moves the feature information of frame 1 from the baseband cache to the shadow register to form a latch; at the same time, the baseband module continues to receive and process the FC field and PL field of frame 1, and writes them to the system memory; thereafter, the processing module (such as the CPU) reads the data of frame 1 from the memory, and synchronously reads the feature information of frame 1 in the shadow register to achieve a one-to-one correspondence between features and data.

[0065] When the overflow flag is set, it indicates a conflict scenario. For example, if the processing module fails to read frame 1 data from system memory in a timely manner, the baseband module detects that the synchronization process for frame 2 has completed. In this scenario, the baseband module performs a reset operation to abort the reception of the next signal frame. The shadow register then latches the feature information of the current signal frame, preventing it from being overwritten by the feature information of the next signal frame. This prevents it from being replaced by the next frame data before the processing module has read it. This ensures that the data (frame 1) read later by the processing module is consistent with the feature information (frame 1), avoiding data mismatches. This synchronization strategy effectively ensures that the processing module always obtains valid and consistent feature information.

[0066] In other words, after the reception of the current signal frame is completed, the baseband module transfers the data of the current signal frame to the memory module; and during the period when the current signal frame is completed and the baseband module transfers its data to the memory module, but has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; when the overflow flag signal is in the set state, the baseband module performs a reset operation to stop processing the next signal frame to keep the data of the current signal frame stored in the memory module; the shadow register latches and retains the characteristic information corresponding to the current signal frame, so that the processing module can perform subsequent processing based on the data of the current signal frame in the memory and the characteristic information corresponding to the current signal frame in the shadow register.

[0067] In the above embodiment, by setting an overflow flag signal and executing corresponding synchronization operations in the shadow register based on this signal, it is possible to effectively prevent the shadow register from being overwritten by the data of the next signal frame before the processing module has completed reading. This strategy ensures the consistency of feature information and improves the stability and reliability of frame data processing. It is particularly suitable for communication scenarios with short inter-frame intervals on high-speed receive links.

[0068] In other embodiments, the synchronization strategy also includes: during the period when the data of the current signal frame stored in the memory module has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; under the condition that the overflow flag signal is set, the shadow register writes the characteristic information corresponding to the next signal frame to overwrite the characteristic information corresponding to the current signal frame.

[0069] Normally, after receiving frame 1, the baseband module extracts feature information based on the preamble signal between its synchronization start and synchronization completion (i.e., the period between the frame synchronization start signal sync-begin and the frame synchronization completion signal frame-synced). This feature information is temporarily stored in the baseband buffer. Upon detecting the frame synchronization completion signal, the shadow register is triggered to write this feature information for latching, thereby moving the feature information of the current signal frame from the baseband buffer to the shadow register. The baseband module then transfers the payload (FC + PL) of frame 1 to system memory, awaiting retrieval by the CPU.

[0070] When the current signal frame has not been read and the next signal frame has completed frame synchronization, the baseband module detects a potential conflict scenario and sets the overflow flag signal. Subsequently, based on this set state, the baseband module triggers the shadow register to replace the feature information corresponding to the current signal frame with the feature information corresponding to the next signal frame. From the upper layer's perspective, it can be regarded as the feature information of the next signal frame being moved from the baseband cache to the shadow register, overwriting the feature information corresponding to the current signal frame in the shadow register. This mechanism can be used to meet the rapid response requirements of replacing the old with the new in some scenarios, taking into account both cache management efficiency and system timeliness.

[0071] For example, if the baseband module detects the frame synchronization completion signal for frame 2 before the CPU has read frame 1 from system memory, it deems a read delay and sets the overflow flag, indicating a reception conflict between the current and next frames. In this embodiment, the baseband module triggers the shadow register to no longer retain the signature information for frame 1 and instead write the signature information for frame 2, overwriting the original data for frame 1. This ensures that the frame data (frame 2) read later by the CPU matches the signature information (frame 2), preventing data mismatches.

[0072] In other words, after the reception of the current signal frame is completed, the baseband module transfers the data of the current signal frame to the memory module; and during the period when the current signal frame is completed and the baseband module transfers its data to the memory module, but has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; under the condition that the overflow flag signal is set, the baseband module abandons the data of the current signal frame and transfers the data of the next signal frame to the memory module; and the shadow register writes the characteristic information of the next signal frame to overwrite the characteristic information corresponding to the current signal frame for subsequent processing module to read, to ensure that when the processing module reads the next signal frame data in the memory, it is consistent with the characteristic information stored in the shadow register.

[0073] In the above embodiment, the ability to replace old frame features with new frame features under conflict conditions can significantly improve the system's response speed to burst data, avoid unexpected data overwriting, and improve the controllability and robustness of the frame feature synchronization process. It is suitable for application scenarios with higher priority requirements for information real-time performance.

[0074] In some high-speed power communication systems, signal frames are received continuously. Due to response delays, the processing module may not be able to complete the reading of the current signal frame in time, resulting in a conflict between the reception and processing of the next signal frame and the current frame. In this conflicting state, simply deciding which frame's feature information to retain based on timing priority or fixed rules may not be able to balance channel quality and system performance. For example, retaining frames with poor channel quality may lead to misjudgment in subsequent processing; discarding frames with higher quality will affect data reliability. Therefore, it is necessary to introduce a frame feature information selection mechanism based on channel quality to improve the overall processing effect and system robustness.

[0075] To this end, in some embodiments, the above-mentioned synchronization strategy also includes: the baseband module respectively determines the channel quality corresponding to the current signal frame and the next signal frame, and compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame to obtain a comparison result; based on the comparison result, the shadow register latches the characteristic information corresponding to the current signal frame, or writes the characteristic information corresponding to the next signal frame to overwrite the characteristic information corresponding to the current signal frame.

[0076] In this embodiment, the baseband module supports independent evaluation of the channel quality of the current signal frame and the next signal frame, and controls the feature information retained in the shadow register based on the evaluation results.

[0077] During the frame synchronization process, the baseband module estimates the channel characteristics of the current signal frame and the next signal frame respectively, and obtains channel quality indicators such as signal-to-noise ratio, received signal strength indication or channel estimation amplitude.

[0078] The baseband module compares the channel qualities corresponding to the current signal frame and the next signal frame to obtain a comparison result, which indicates which frame has a better channel quality.

[0079] Therefore, based on the result, the shadow register performs one of the following operations: if the channel quality of the current signal frame is better, no update is performed, and the characteristic information corresponding to the current signal frame remains unchanged; if the channel quality of the next signal frame is better, the characteristic information of the next signal frame is written to move the characteristic information of the next signal frame from the baseband cache to the shadow register to overwrite the original characteristic information of the current signal frame.

[0080] In the above embodiment, through the dynamic comparison mechanism based on channel quality, it is possible to adaptively select a synchronization strategy in the scenario of signal frame reception conflict. Compared with the method of fixedly retaining the first or last arriving frame, it has higher robustness and is particularly suitable for power line communication environments where channel conditions change rapidly and electromagnetic interference is severe.

[0081] In the receiving path, after a signal frame is received, its data needs to be written to the memory module for subsequent processing. However, in some high-frequency communication scenarios, the next frame may be synchronized and received before the previous frame is fully processed.

[0082] Figure 6 This is a schematic diagram of the principle of underlying data interaction provided in some embodiments of the present invention. Figure 6 As shown, the frame data (including the preamble, frame control data, and data payload) is first received by the baseband module, which then undergoes signal demodulation and field parsing. After processing the frame data, the baseband module writes the frame control data and data payload to the memory module (i.e., system memory). At time t1, its internal hardware logic asserts the receive completion flag (rx-end-flag), switching from its default low state to a high state, indicating that the reception and transmission of the frame data for that signal frame has been completed. After the processing module (i.e., the CPU) detects the high state of the receive completion flag, it begins reading the corresponding frame data from system memory. After reading is complete, the processing module resets the receive completion flag to zero at time t2, returning it from a high state to a low state, signaling completion. This establishes a handshake mechanism coordinated by the baseband and processing modules, ensuring reliable setting and release of the receive completion flag and improving the reliability of frame data reading.

[0083] The following further describes the normal timing process of the above handshake mechanism when frames arrive continuously. Figure 7 Schematic diagram of signals under normal conditions provided in some embodiments of the present invention. Figure 7As shown, in the context of a system continuously receiving multiple frames of data, after the baseband module completes reception and processing of frame 1, it writes the frame control data and data payload to the system memory at time t1 and sets the receive completion signal (rx-end-flag) to indicate that the data writing of frame 1 is complete. Subsequently, the processing module detects that the receive completion signal is in a high-level state, confirming that the current frame data is ready for reading and initiating the read operation. After the processing module completes reading frame 1 data, at time t2, the receive completion signal is reset to zero under software control, that is, it transitions from a high level to a low level, notifying the baseband module that processing of the current frame data has ended and that the next frame data reception process can begin.

[0084] exist Figure 7 In the normal data flow scenario shown, the timely setting and zeroing of the reception completion signal realizes the effective synchronization of the frame data reception status between the baseband module and the processing module, which helps to ensure the data integrity and reading timing of the system when continuously receiving multiple signal frames. However, in the actual operation process, the CPU often undertakes multiple parallel tasks at the same time, and there is a risk of response delay. Especially in scenarios with short frame intervals and high processing pressure, the zeroing operation of the reception completion signal may not be completed within the expected time window, thereby affecting the normal reception and storage of subsequent frames. In order to illustrate the potential data conflict problem caused by this type of response delay, the following shows the overwriting and misreading caused by the continuous reception of frame data when the CPU fails to promptly set the reception completion signal to zero.

[0085] Figure 8 Schematic diagram of signals under time delay provided in some embodiments of the present invention. Figure 8 As shown in the figure, at time t1, the baseband module transfers frame 1 data to system memory and sets the receive completion signal (rx-end-flag). Under normal circumstances, it should be reset to zero at time t2. However, because the CPU is currently processing other tasks and cannot respond in time, the receive completion signal is not reset to zero in time at time t2 and remains high. Assume that the receive completion signal is reset to zero at time t2', and the baseband module has already started receiving frame 2 data. In this case, the data extracted by the CPU between t1 and t2' contains a mixture of frame 1 and frame 2 data, which will cause errors in upper-layer application processing. Subsequent frame 2 data will also be missing, and subsequent processing will also cause errors.

[0086] It's important to note that while system designs typically reserve frame intervals for the CPU to complete read and flag zeroing operations, the CPU response process is software-controlled, subject to inevitable latency fluctuations. Any delay in response directly impacts the accuracy of cached data, making coverage conflicts more likely to occur, especially when receiving dense, continuous frames.

[0087] To this end, in some embodiments, the above method also includes: after the baseband module completes the reception of the current signal frame and transfers the data of the current signal frame to the memory module, it sets a reception completion signal for indicating the reception completion status; while the reception completion signal is in the set state, if the baseband module detects a frame synchronization completion signal, it sets an overflow flag signal; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame; according to the frame conflict processing strategy, the frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal.

[0088] The receive completion signal is a status indicator, set by the baseband module to indicate that the reception of the current signal frame has completed and that the next processing phase can begin. This signal helps coordinate read and write synchronization between the baseband and subsequent processing modules, preventing overlap between frames. The overflow flag signal serves as a trigger for conflict management, enabling the signal receiving device to promptly switch between normal processing and frame conflict handling to avoid data loss or status errors.

[0089] The baseband module receives the current signal frame (for example, frame 1) and completes data parsing and demodulation. After completing data processing, the baseband module writes the FC (Frame Control) and PL (Payload) fields of frame 1 to the memory module and asserts the receive completion signal, rx-end-flag. This signal defaults to a low level. When asserted, it indicates that the current frame has been transmitted and the system is ready for subsequent read operations.

[0090] The baseband module completes the process of receiving the current signal frame and transferring its data to the memory module. This process not only includes the direct transmission of the FC field (Frame Control Field) and PL field (Data Payload Field) in the signal frame, but also fully supports the initial receive processing flow. Specifically, when constructing a frame of power line carrier signal data, the signal transmitter typically first performs universal channel coding on the original byte data to be transmitted (for example, the hexadecimal number 0x12) to improve error resilience. The encoded result is then interleaved to mitigate the effects of burst interference or narrowband noise. The transmitter then inserts multiple preamble symbols before the encoded data. Preamble symbols typically consist of multiple synchronization training symbols or pilots, which are used by the receiver for frame synchronization and channel estimation. For example, the original data 0x12, after coding and interleaving, is mapped to "110011." A preamble sequence "010101" is then inserted, ultimately forming the complete transmitted bit string "010101110011" as a complete physical layer signal frame.

[0091] The baseband module of the signal receiving device first receives the bit stream (i.e., a composite frame consisting of the preamble, FC, and PL). Within the synchronization window, it synchronizes to the frame by detecting multiple consecutive synchronization peaks or matching the local frame preamble sequence. This triggers the generation of the corresponding frame synchronization start (sync-begin) and frame synchronization complete (frame-synced) signals. The baseband module also performs channel estimation and equalization, using the preamble symbols to calculate CE and estimate the channel response. The signal receiving device also performs deinterleaving and decoding, performing soft-decision decoding or maximum likelihood decoding on the payload portion of the FC and PL fields in the received bit stream to recover the original data bytes (e.g., 0x12). Furthermore, the receiving end performs checksums and field parsing, such as performing a CRC check on the frame control field and parsing the length / address fields. Finally, if the decoding result is valid, the baseband module writes the decoded result corresponding to the signal frame (i.e., 0x12) to the system memory module and simultaneously asserts the receive completion signal (Rx-end-flag) to notify the processing module (e.g., the CPU) that the data is readable.

[0092] The overflow flag is a conflict indicator, indicating an abnormal state where the previous frame has not yet been processed but the next frame has begun entering the receive path. This signal triggers conflict management, enabling the receiving device to promptly switch between normal processing and frame conflict handling to avoid data loss or status errors.

[0093] If the baseband module detects a frame synchronization completion signal while the receive completion signal rx-end-flag is still set (high), it indicates that frame synchronization processing for the next signal frame (for example, frame 2) has completed. In this case, the communication system faces a conflict scenario, that is, the previous frame has not yet been released, and the next frame has begun to be received. In this case, the baseband module generates the overflow flag signal overflow-flag to explicitly indicate that a new receive action has occurred while the current signal frame has not yet been processed, indicating a potential data conflict.

[0094] The frame collision handling strategy is a predefined conflict response plan for the signal receiving device to handle overlapping frames. This strategy includes strategies for retaining and discarding frames, along with corresponding behavior control logic, state setting and clearing sequences, and other parameters. Properly setting this strategy helps ensure system processing stability in scenarios with continuous frame reception, improving overall communication quality.

[0095] When a conflict is detected and an overflow flag is generated, the baseband module performs frame conflict handling according to a pre-set frame conflict handling strategy. This strategy determines whether to retain the previous frame or the current frame based on factors such as system load and processing priority.

[0096] For example, frame conflict handling strategies may include, but are not limited to, interrupting current reception, discarding new frames, latching old frames, enabling double buffering, and clearing the next frame. The baseband module will select differentiated conflict clearing actions for the current or next frame based on the state characteristics at the time of the conflict, thereby ensuring stable system operation.

[0097] For example, in a wireless communication system based on the OFDM (Orthogonal Frequency Division Multiplexing) signal structure, the baseband module asserts a receive completion signal after receiving all symbols of frame 1 and transferring them to memory via DMA. However, since the upper-layer CPU has not yet completed data reading, if frame 2 has already begun receiving after synchronization symbol detection, the baseband module generates an overflow flag and then handles the conflict according to a pre-set frame conflict handling strategy. For example, if the system prioritizes retaining frame 1 data, the reception process of frame 2 is discarded and its buffer area is cleared. If frame 2 must be retained, the reception status of frame 1 is cleared and its read path is released for the new frame, and so on.

[0098] In the above embodiment, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, the reception completion signal is set, thereby realizing a clear division of the state between the frame reception and the processing flow, and facilitating the processing module to judge the timing of data reading; while the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set, and the access behavior of the next frame can be detected in time, and a flag signal is generated for alarm, thereby realizing fast and automatic identification of the conflict state, without waiting for the processor to participate or polling judgment, and getting rid of the dependence on the interrupt response or software scheduling mechanism; furthermore, according to the frame conflict processing strategy, based on The overflow flag signal executes the frame conflict processing operation related to the current signal frame or the next signal frame. The baseband module automatically triggers the conflict strategy and supports automatic frame conflict processing within the hardware. There is no need for the processor to participate in the judgment and control signal initiation, which reduces the control path delay and improves the robustness and overall processing efficiency in high-speed reception scenarios. In addition, by introducing configurable or dynamically selected conflict handling strategies, it supports flexible response to conflicts in the current frame retention or the next frame reception according to application requirements, improves system adaptability and processing efficiency, effectively reduces the risk of data loss and state disorder caused by frame conflicts, and improves the reliability and processing efficiency of the system in high-density reception scenarios.

[0099] In the actual communication process, frames may arrive continuously. The signal receiving device needs to accurately determine when to enter the next frame reception process in order to realize the pre-triggering of frame conflict identification and control.

[0100] To this end, in some embodiments, the baseband module detects a frame synchronization completion signal, including: the baseband module monitors the synchronization sequence in the input signal, and when a synchronization sequence matching a preset frame format is detected, generates a frame synchronization start signal to indicate that the frame synchronization detection of the next signal frame has been started; after completing the confirmation of the frame synchronization position, the baseband module generates a frame synchronization completion signal, and the frame synchronization completion signal is used to indicate that the synchronization process of the next signal frame currently received has been completed.

[0101] Specifically, during signal reception, the baseband module first continuously monitors the synchronization sequence in the incoming signal. For example, a sliding window can be set to perform a matching operation on the leading region of the received signal to identify whether a sequence pattern matches a preset frame structure. If a continuous correlation peak or characteristic pattern that meets the requirements is detected, a frame synchronization start signal (sync-begin) is triggered, indicating that the synchronization detection phase of the next signal frame has begun.

[0102] The baseband module then performs frame synchronization on the input signal, such as locating the boundary between the synchronization symbols SYNCP (Synchronization Pattern) and SYNCM (Synchronization Channel Midpoint) or determining the frame header position using the maximum correlation value. Once the frame synchronization position is successfully confirmed, the baseband module generates a frame synchronization complete signal (frame-synced), indicating the end of the current synchronization process and allowing the reception process to proceed to the frame control segment and data payload segment.

[0103] Taking a typical OFDM frame structure as an example, its frame header typically contains multiple preamble symbols for frame synchronization, frequency offset estimation, and channel estimation. The communication system preconfigures a preset frame format and decision threshold. At time t0, the baseband module detects the presence of three or more similar synchronization peaks in the input signal and generates a frame synchronization start signal (sync-begin), indicating that synchronization detection for frame 2 has begun. Next, the baseband module confirms the synchronization position based on a sliding window matching mechanism, for example, determining the intersection of SYNCP and SYNCM, and generates a frame synchronization completion signal (frame-synced), indicating that synchronization for frame 2 is complete and that reception of its FC and PL fields can begin. If the previous frame, frame 1, has not yet been read, the baseband module combines this frame synchronization completion signal with the reception completion signal (Rx-end-flag) to trigger the subsequent frame conflict handling process.

[0104] In the above-described embodiment, by introducing a synchronization sequence matching and frame synchronization signal generation mechanism into the baseband module, the arrival of the next frame signal can be quickly and accurately identified without CPU involvement. This helps improve the accuracy of boundary detection during frame reception and ensures that the frame conflict handling process has an accurate basis for starting judgment. Furthermore, this mechanism effectively reduces system response latency, avoids data misreading or overwriting issues caused by hardware and software asynchrony, and enhances the robustness and real-time performance of the overall communication system.

[0105] It should be noted that the characteristic information synchronization method for power communication signal frames provided by the present invention can be applied to communication systems with a continuous frame structure. In such a communication system, one scenario is when multiple signal frames are arranged sequentially, and the interframe interval between adjacent signal frames is less than the shortest read cycle of the processing module. In other words, when the data extraction of the previous frame has not yet been completed, the next frame has already begun to arrive and enter the synchronization phase.

[0106] This type of system is common in high-density, high-speed data communication scenarios, such as power line carrier (HPLC), OFDM systems, or point-to-point communications between specific embedded devices. Because there is no buffering time between frames, the processing period of frame 1 can easily overlap with the reception period of frame 2, leading to frame collisions. In this context, the frame collision handling strategy proposed in this invention can significantly improve system stability.

[0107] The following will respectively describe the three frame conflict processing strategies proposed in the present invention to more clearly illustrate the specific coping methods under different conflict conditions.

[0108] It should be noted that the classification and implementation of the frame conflict handling strategies are merely exemplary descriptions and do not limit the scope of protection of the present invention. Without departing from the core concept of the present invention, the processing flow of the relevant strategies can be adapted and expanded according to the actual system design.

[0109] In some embodiments, according to the frame conflict processing strategy, a frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, including: when the overflow flag signal is in the set state, the baseband module generates an overflow reset signal for triggering an interrupt; in response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame data; the baseband module sets the reception completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0110] When the baseband module detects that the data of the current signal frame has been transmitted to the memory module and the reception completion signal is in the set state, and starts to receive the next frame of data, it will set the overflow flag signal (overflow-flag) to indicate the occurrence of a frame conflict.

[0111] Under the current frame collision handling strategy, if the overflow flag is set, the baseband module automatically generates an overflow reset signal (overflow-rst). This signal serves as a trigger, initiating a reset operation based on the signal. A reset operation means that, in the event of a frame collision, the baseband module actively suspends processing of the next frame. For example, this can reset modules such as the baseband deinterleaving and decoding modules. It should be noted that a reset does not terminate processing of the next signal frame; rather, it stops the current data write operation to avoid issues such as frame aliasing, frame header misalignment, or control signal lag caused by the writing of the next frame's data. After collision handling is complete, the baseband module simultaneously resets the previously asserted receive completion signal and the overflow reset signal to zero, clearly indicating the end of the collision and re-entering the synchronized receive state.

[0112] Figure 9 FIG. 1 is a signal diagram of a frame conflict handling strategy provided in some embodiments of the present invention. Figure 9 As shown, if the baseband module's receive completion signal (rx-end-flag) is not reset after processing frame 1, and during this time, the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame collision handling strategy, the baseband module also generates an overflow reset signal (overflow-rst). Furthermore, the baseband module performs a reset operation based on this overflow reset signal. Resetting refers to resetting modules such as the baseband deinterleaving and decoding modules. Therefore, after time t1', the baseband module will not perform decoding or other parsing processing on the frame 2 data, and will not transfer the frame 2 data to the memory module for writing to the system memory. The current frame collision handling strategy is to discard the frame 2 data. Therefore, based on the overflow flag and reset mechanism, the baseband module will not write the frame data to the system memory, thereby ensuring that the frame 1 data is not overwritten by the frame 2 data and maintaining the integrity of the frame 1 data.

[0113] It should be noted that when the baseband module performs frame synchronization detection, the frame 2 data consists of the frame preamble, FC field and PL field, and the frame synchronization position is in the preamble position. Therefore, when the baseband module detects the frame synchronization signal, it has not yet started to move the frame 2 data to the system memory, and there will be no data overwrite.

[0114] In the above embodiment, after a conflict is detected, the baseband module actively generates an overflow reset signal, and performs cache clearing and reception termination operations based on the signal, and then synchronizes the reception completion signal and the overflow reset signal to zero, thereby achieving rapid closed-loop processing of the frame conflict state, avoiding uncontrollable delays caused by relying on CPU response, ensuring timely handling of the conflict state, and avoiding overlapping or overwriting of consecutive frames by clearing the next frame data and terminating reception, thereby ensuring the integrity of each frame of data. In addition, the entire process is independently completed by the baseband module to complete the conflict detection and processing logic, without the need for CPU participation, without response delay, and completely avoiding the problem of conflict response lag caused by software busyness or scheduling delays. It not only ensures the real-time nature of the communication process, but also maintains the continuity and stability of the CPU software tasks. Even if consecutive frames arrive closely or the CPU is under high load, it can still ensure stable operation of the system, achieving efficient and reliable data protection in frame conflict scenarios.

[0115] In some other embodiments, the signal receiving device further includes a processing module. The following embodiments further propose a frame conflict handling strategy that is collaboratively processed by the processing module.

[0116] Accordingly, according to the frame conflict processing strategy, the frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, and also includes: when the overflow flag signal is detected, the processing module terminates the reading operation of the current signal frame; the processing module sets the receiving completion signal to zero to read the next signal frame.

[0117] When the processing module detects the overflow flag signal set by the baseband module, it determines that there is a read risk for the current signal frame and immediately terminates the reading operation of the current signal frame to prevent the data being extracted from being mixed with subsequent data. At the same time, the processing module can send a command to the baseband module to reset the reception completion signal to zero, thereby releasing the current frame state and entering the reading preparation process for the next signal frame.

[0118] For example, in a scenario where a set of consecutive OFDM signal frames is being received, the baseband module detects the start of frame 2 reception, but the receive completion signal for frame 1 has not yet been reset to zero. Therefore, the overflow flag is set. The CPU, acting as the processing module, then detects this overflow flag in an interrupt response and immediately stops fetching frame 1 data from system memory to prevent the reading of frame 2. The CPU then sends a reset command to the baseband module, instructing it to reset the receive completion signal (Rx-end-flag) to zero, allowing the system to quickly proceed with processing frame 2 data and avoiding communication backlogs.

[0119] Figure 10 FIG. 1 is a signal diagram of another frame conflict handling strategy provided in some embodiments of the present invention. Figure 10 As shown, if the baseband module's receive completion signal (rx-end-flag) is not reset to zero after processing frame 1, and during this time, the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame collision handling strategy, the processing module (e.g., the CPU) proactively terminates the read operation of frame 1 to avoid extracting invalid data that may have been partially overwritten. The processing module then resets the receive completion signal to zero, releasing the read flag for the current frame 1. The baseband module then continues receiving frame 2 and writes the data of frame 2 to the system memory. After the transmission of frame 2 is complete, the baseband module resets the receive completion signal at time t3 to indicate that the data for frame 2 is ready. Finally, after the CPU detects that the receive completion signal is high, it switches to reading the data for frame 2 from the system memory, completing data recovery and normal processing after the inter-frame collision. In other words, the current frame collision handling strategy discards the data of frame 1.

[0120] Compared with the baseband module handling conflicts completely, the processing module cooperates with the reading suspension and flag clearing mechanism to effectively solve the problem of misreading conflict data caused by inter-frame continuity, and enhances the accuracy and scalability of data reception while maintaining the original system architecture unchanged.

[0121] In the above embodiment, the processing module interrupts the continued reading of the current frame to avoid extracting invalid data after the frame data is partially overwritten, thereby improving the validity of the frame data; and by actively setting the reception completion signal to zero, it helps to shorten the conflict processing time, accelerate the processing preparation of the next frame data, and improve the overall system processing rhythm.

[0122] In order to further improve the signal reception reliability and data quality in the case of frame collision, based on the aforementioned frame collision processing strategy, the present invention also proposes a frame selection mechanism based on channel quality assessment, so that the signal receiving device can automatically judge and retain the frame with better quality between the two conflicting frame signals, avoid the misselection of low-quality data in the case of channel degradation, and improve the overall robustness of the system.

[0123] To this end, in some further embodiments, in accordance with the frame conflict processing strategy, frame conflict processing operations related to the current signal frame or the next signal frame are performed based on the overflow flag signal, and also include: the baseband module at least completes the reception of the leading symbol of the next signal frame to evaluate the channel quality corresponding to the next signal frame based on the leading symbol; the baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retains the signal frame with higher channel quality based on the comparison result, and discards the other signal frame.

[0124] Specifically, after detecting a subsequent signal frame that conflicts with the current signal frame, the baseband module in the signal receiving device first receives and interprets the preamble symbol in the subsequent signal frame. The preamble symbol, serving as a reference field for channel estimation, is highly stable and representative. The baseband module uses it to calculate channel characteristics for the corresponding frame, including but not limited to signal-to-noise ratio (SNR), received signal strength indicator (RSSI), and channel estimation (CE).

[0125] After obtaining the channel quality information for the next signal frame, the baseband module compares it with the channel quality of the current signal frame and determines which frame has better reception conditions based on preset criteria, such as maximum SNR priority and RSSI exceeding a threshold. Based on this judgment, the frame with higher channel quality is automatically retained for subsequent processing, while the frame with degraded channel quality is discarded to avoid invalid data interference and resource waste.

[0126] In the above embodiments, by introducing a channel quality assessment mechanism into the conflict handling strategy, the signal receiving device can effectively distinguish and prioritize frame data with better receiving conditions in high frame density or continuous communication scenarios, thereby avoiding data misuse due to fluctuations in channel conditions; at the same time, it reduces the resource burden brought by redundant data processing, thereby improving the communication reliability and robustness of the overall system.

[0127] In practical communication systems, the operational load of signal receiving devices is often affected by factors such as upper-layer processing tasks, system buffer occupancy, and external interrupt frequency. Using a fixed frame collision handling strategy under high load conditions can compromise both system real-time performance and data integrity. This paper further proposes a load-aware policy adaptation mechanism that enables signal receiving devices to dynamically adjust their frame collision handling logic, thereby flexibly balancing data retention and feature extraction strategies under varying operational loads.

[0128] To this end, in some embodiments, the above method also includes: detecting the load status; automatically selecting different frame conflict processing strategies based on the load status to retain the current signal frame or the next signal frame, and determining the reading strategy of the characteristic information of the current signal frame or the next signal frame based on the selected frame conflict processing strategy.

[0129] Specifically, the signal receiving device continuously monitors its load status during operation, and the load status may include indicators such as CPU processing occupancy, frame buffer queue depth, and task scheduling delay.

[0130] Based on these indicators, the signal receiving device determines whether the system is currently lightly loaded, medium loaded, or heavily loaded, and selects the most appropriate frame collision handling strategy from multiple preset strategies. For example, in a low-load state, the frame collision handling strategy of retaining the current signal frame and discarding the next one is preferred. In a high-load state, the frame collision handling strategy of retaining the next signal frame and discarding the current one is preferred to reduce congestion and improve processing throughput. If the load is critical or medium, a channel quality optimization strategy can be used to retain the current frame or the next frame.

[0131] In the above embodiments, by introducing a load state perception and processing strategy adaptive mechanism, the signal receiving device's ability to respond resiliently in complex operating environments is enhanced, and the overall processing efficiency and stability of the system can be improved while ensuring the integrity of frame data. It is particularly suitable for communication scenarios with dense frame arrival, high-frequency switching, or frequent interference.

[0132] Therefore, in combination with the above embodiments, Figure 11 This is a signal diagram of the feature information synchronization process provided in some embodiments of the present invention. Figure 11 As shown in the figure, based on the existing baseband cache structure, the present invention adds a shadow register (or shadow memory) to specifically store feature information to ensure the accuracy and readability of frame feature data in conflict states or software delay scenarios. Figure 3 As shown in Figure 2, the shadow register provides a stable copy of feature information for extraction and use by the CPU or upper-level processing modules.

[0133] refer to Figure 4 In the timing sequence shown, when the baseband module detects the sync-begin signal for frame 1 (time t0), that is, when multiple synchronization peaks are detected consecutively, the baseband module begins processing such as channel estimation, calculates the feature information of frame 1, and writes it to the baseband buffer. This process continues until the frame-synced signal for frame 1 is detected, that is, time t0'. When the baseband module detects the frame-synced signal for frame 1 at time t0', it immediately controls the shadow register to read the feature information of the current frame (frame 1) from the baseband buffer and latches it. At this point, the shadow register stores the same feature information that corresponds to the frame 1 data in the system memory.

[0134] When frame 1 data is transferred to system memory (at time t1), the baseband module asserts the receive completion signal (rx-end-flag) to notify the CPU that it can read the frame data. When the baseband detects the sync-begin signal for frame 2 at time T1, the baseband module begins recalculating and updating the feature information for frame 2. If the CPU has not yet finished extracting frame 1 data at this time, there is a risk that the frame feature data will be overwritten.

[0135] In combination with the above embodiments Figure 7 A frame collision handling strategy is provided. If the overflow flag (overflow_flag) is set at time t1' (i.e., when frame 2 synchronization is complete), the baseband module disables updates to the shadow register and retains the signature information of frame 1. In this case, even if the CPU delays data reading at time t2', the signature information obtained from the shadow register remains consistent with the data in frame 1.

[0136] In combination with the above embodiments Figure 8 A frame collision handling strategy is provided. If the overflow flag is set at time t1', a feature transfer operation is triggered. The baseband module controls the shadow register to update the feature information of frame 2, in accordance with the system's frame collision handling strategy of retaining frame 2 data. When the CPU subsequently completes the frame 2 data read (for example, at time t3), it can obtain the corresponding frame 2 feature information from the shadow register to ensure data consistency. This effectively solves the mismatch between frame data and feature information caused by software latency in traditional architectures, further improving data consistency and application reliability of signal receiving devices in high-concurrency scenarios.

[0137] Unlike related techniques where the CPU directly accesses the baseband cache, the CPU in this invention reads feature information from a shadow register. This ensures a one-to-one correspondence between the extracted frame data and the feature information, preventing data mismatches caused by cache overwriting. After the read is complete, the CPU or upper-layer application sets the receive completion signal (rx-end-flag) to zero, ending the current processing cycle.

[0138] The above mechanism is particularly suitable for scenarios requiring high communication reliability, complex meter networking, and large power line noise environment interference, such as the networking application of power line carrier communication chips.

[0139] In addition, the present invention further expands the shadow register mechanism and introduces a multi-shadow register structure to achieve parallel caching of multiple signal feature information.

[0140] To this end, in some embodiments, a plurality of shadow registers are configured for respectively latching characteristic information corresponding to a plurality of signal frames; the above method also includes: allocating unoccupied shadow registers in sequence for each signal frame that completes frame synchronization, and moving the characteristic information corresponding to each signal frame to the allocated shadow register; during the period when the data of the signal frame in which the characteristic information is earliest written is stored in the memory module and has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, then according to the synchronization strategy, one or more shadow registers latch the written characteristic information, or, one or more shadow registers write the characteristic information corresponding to the new signal frame to overwrite the characteristic information corresponding to the previous signal frame.

[0141] During the actual receiving process, after completing frame synchronization each time, the baseband module can search for an unoccupied shadow register from the shadow register through a polling mechanism, etc., to trigger the corresponding shadow register to perform the corresponding synchronization operation, thereby moving the characteristic information of the current signal frame to the selected shadow register.

[0142] If all shadow registers are currently occupied and the earliest written signal frame has not been read by the processing module, after detecting the frame synchronization signal of the next signal frame, the signal receiving device can perform one of the following operations based on the synchronization strategy: On the one hand, the shadow register that was first written with the characteristic information can be released, and the characteristic information corresponding to the new signal frame can be written into the register; On the other hand, according to priority or business requirements, the characteristic information of the new signal frame can be discarded and the original register content can be retained.

[0143] During this process, the baseband module can maintain the write order queue of the shadow register to ensure that the processing module can read according to the write order or priority rules during subsequent processing.

[0144] In the above embodiment, by setting multiple shadow registers and introducing a dynamic allocation and update mechanism, the characteristic information storage capacity in the multi-frame continuous reception scenario is improved, and the information loss problem caused by limited cache resources is effectively avoided, the receiving and processing capabilities of high-frequency signal frames are improved, and the robustness and scalability of the system are enhanced.

[0145] Based on this, the baseband module or signal receiving device can assign register identifiers to each shadow register and maintain a write order queue to record the order in which the shadow registers are written. This queue can be maintained in a first-in-first-out structure to ensure that the earliest written register can be clearly identified when resources are exhausted.

[0146] Correspondingly, the synchronization strategy also includes: when all shadow registers are occupied, releasing the shadow register at the head of the write order queue, removing the register identifier of the released shadow register from the head of the queue, and adding it back to the tail of the queue to store the characteristic information corresponding to the new signal frame moved from the baseband cache; or, discarding the characteristic information corresponding to the new signal frame to maintain the characteristic information latched in all current shadow registers unchanged.

[0147] When the baseband module detects that all shadow registers are occupied and a new signal frame has been synchronized, the baseband module can choose between the following two operations based on the synchronization strategy: First, the shadow register at the head of the write-order queue (i.e., the register written earliest) is released, its corresponding register identifier is removed from the head of the queue, and reinserted at the tail. Subsequently, the feature information corresponding to the new signal frame is moved from the baseband buffer to the register, achieving information update and resource reuse.

[0148] Second, the characteristic information of the new signal frame is discarded, and the data in all shadow registers is kept unchanged to avoid overwriting historical frame information that may not have been read.

[0149] The above synchronization strategy not only ensures the availability of shadow registers under resource-constrained conditions, but also provides the possibility of reserving space for specific key frame data.

[0150] In the above embodiment, by constructing a sequential write queue for shadow registers, an automatic recycling and updating mechanism is implemented when resources are full, significantly improving the reuse rate of feature information storage resources. Furthermore, the discard option in the policy flexibly responds to the need to prioritize the retention of key frames, thereby enhancing inter-frame data management capabilities and overall controllability, and reducing stability risks caused by processing delays and data conflicts.

[0151] The method for synchronizing characteristic information of a power communication signal frame provided in an embodiment of the present invention may be performed by a device for synchronizing characteristic information of a power communication signal frame. The device for synchronizing characteristic information of a power communication signal frame provided in an embodiment of the present invention is described by taking the device for synchronizing characteristic information of a power communication signal frame as an example of executing the method for synchronizing characteristic information of a power communication signal frame.

[0152] An embodiment of the present invention further provides a device for synchronizing characteristic information of a power communication signal frame, which is applied to a signal receiving device.

[0153] Figure 12 Schematic diagram of the structure of the characteristic information synchronization device of the power communication signal frame provided in some embodiments of the present invention. Figure 12 As shown, the characteristic information synchronization device of the power communication signal frame includes a calculation module 1201, a transfer module 1202 and a synchronization module 1203. The calculation module 1201 is configured to trigger calculation of corresponding feature information in response to a frame synchronization start signal of a current signal frame, and write the feature information into a baseband buffer.

[0154] The moving module 1202 is used to move the feature information from the baseband buffer to the shadow register after completing the frame synchronization, so as to provide the processing module with subsequent reading.

[0155] The synchronization module 1203 is used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected during the period when the data of the current signal frame stored in the memory module has not been read by the processing module.

[0156] The frame conflict processing device provided in the embodiment of the present invention can implement the various processes implemented in the various method embodiments and can achieve the same technical effects. To avoid repetition, it will not be described here.

[0157] The frame conflict processing apparatus in the embodiment of the present invention may be a signal receiving device, or a component in the signal receiving device, such as an integrated circuit or a chip. The signal receiving device is a computer device, such as a terminal device.

[0158] Figure 13 Schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. Figure 13 As shown, Figure 13 As shown, the signal receiving device 1300 includes a baseband 1301 and a central processing unit 1302. The baseband 1301 is configured with a shadow register. Baseband 1301 is used to trigger the calculation of corresponding feature information in response to the frame synchronization start signal of the current signal frame, and write the feature information into the baseband cache; after completing the frame synchronization, the feature information is moved from the baseband cache to the shadow register for subsequent reading by the central processing unit.

[0159] The baseband 1301 is also used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module.

[0160] The central processing unit 1302 is used to read feature information from the shadow register to perform upper-layer application processing.

[0161] The baseband 1301 corresponds to the baseband module in the aforementioned embodiment, and the central processing unit 1302 corresponds to the processing module in the aforementioned embodiment.

[0162] The signal receiving device 1300 provided in the embodiment of the present invention can implement each process implemented in each method embodiment, and will not be described again here to avoid repetition.

[0163] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the various processes of the above-mentioned embodiment of the characteristic information synchronization method of the power communication signal frame and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0164] The processor is the processor in the computer device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0165] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned method for synchronizing characteristic information of a power communication signal frame.

[0166] The processor is the processor in the computer device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0167] Another embodiment of the present invention provides a chip comprising a processor and a communication interface, the communication interface coupled to the processor, and the processor configured to execute a program or instruction to implement the various processes of the aforementioned embodiment of the method for synchronizing characteristic information of a power communication signal frame, thereby achieving the same technical effect. To avoid repetition, these processes are not described here. It should be understood that the chip described in the embodiment of the present invention may also be referred to as a system-on-chip, system-on-chip, system-on-chip, or system-on-chip chip.

[0168] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for synchronizing characteristic information of a power communication signal frame, characterized in that: The method comprises: In response to a frame synchronization start signal of a current signal frame, triggering calculation of corresponding feature information and writing the feature information into a baseband buffer; After completing frame synchronization, the feature information is moved from the baseband cache to the shadow register for subsequent reading by the processing module; During the period when the data of the current signal frame stored in the memory module has not been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the feature information stored in the shadow register is updated according to the synchronization strategy.

2. The method for synchronizing characteristic information of a power communication signal frame according to claim 1, characterized in that: Updating the feature information stored in the shadow register according to the synchronization strategy includes: The shadow register latches the characteristic information corresponding to the current signal frame; or The shadow register updates the characteristic information corresponding to the current signal frame to the characteristic information corresponding to the next signal frame.

3. The method for synchronizing characteristic information of a power communication signal frame according to claim 2, characterized in that: The synchronization strategy includes: During the period when the data of the current signal frame stored in the memory module has not been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; When the overflow flag signal is in the set state, the baseband module performs a reset operation, and the shadow register latches the feature information corresponding to the current signal frame.

4. The method for synchronizing characteristic information of a power communication signal frame according to claim 2, characterized in that: The synchronization strategy also includes: During the period when the data of the current signal frame stored in the memory module has not been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, the baseband module sets the overflow flag signal; Under the condition that the overflow flag signal is in the set state, the shadow register writes the characteristic information corresponding to the next signal frame to overwrite the characteristic information corresponding to the current signal frame.

5. The method for synchronizing characteristic information of a power communication signal frame according to claim 1, characterized in that: The synchronization strategy also includes: The baseband module determines the channel quality corresponding to the current signal frame and the next signal frame respectively, and compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame to obtain a comparison result; Based on the comparison result, the shadow register latches the characteristic information corresponding to the current signal frame, or writes the characteristic information corresponding to the next signal frame to overwrite the characteristic information corresponding to the current signal frame.

6. The method for synchronizing characteristic information of a power communication signal frame according to claim 1, characterized in that: The shadow register is configured with a plurality of registers for respectively latching feature information corresponding to a plurality of signal frames; the method further includes: Allocate unoccupied shadow registers in sequence for each signal frame that has completed frame synchronization, and move the feature information corresponding to each signal frame to the allocated shadow registers; During the period when the data of the signal frame in which the characteristic information is first written is stored in the memory module but has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, then according to the synchronization strategy, one or more shadow registers latch the written characteristic information, or, one or more shadow registers write the characteristic information corresponding to the new signal frame to overwrite the characteristic information corresponding to the previous signal frame.

7. The method for synchronizing characteristic information of a power communication signal frame according to claim 6, characterized in that: The method further comprises: assigning a register identifier to each shadow register, and maintaining a write sequence queue to record the write sequence of each shadow register; Accordingly, the synchronization strategy further includes: When all shadow registers are occupied, release the shadow register at the head of the write order queue, remove the register identifier of the released shadow register from the head of the queue, and add it to the tail of the queue for storing feature information corresponding to the new signal frame moved from the baseband cache; or The characteristic information corresponding to the new signal frame is discarded to maintain the characteristic information latched in all current shadow registers unchanged.

8. A characteristic information synchronization device for a power communication signal frame, characterized in that: The device comprises: a calculation module, configured to trigger calculation of corresponding feature information in response to a frame synchronization start signal of a current signal frame, and write the feature information into a baseband cache; A moving module, configured to move the feature information from the baseband cache to the shadow register after completing frame synchronization, so as to be subsequently read by the processing module; The synchronization module is used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected during the period when the data of the current signal frame stored in the memory module has not been read by the processing module.

9. A power communication system, characterized in that: The system comprises: A signal sending device, configured to send a power communication signal comprising continuous signal frames; A signal receiving device, configured to receive the power communication signal and execute the method for synchronizing characteristic information of a power communication signal frame according to any one of claims 1 to 6.

10. A signal receiving device, characterized in that: The signal receiving device includes a baseband and a central processing unit, wherein the baseband is configured with a shadow register; wherein: The baseband is configured to trigger calculation of corresponding feature information in response to a frame synchronization start signal of the current signal frame, and write the feature information into a baseband cache; after completing frame synchronization, move the feature information from the baseband cache to a shadow register for subsequent reading by a central processing unit; The baseband is further configured to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected during a period in which the data of the current signal frame stored in the memory module has not yet been read by the processing module; The central processing unit is used to read feature information from the shadow register to perform upper layer application processing.

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