Double-layer V-shaped nanowire structure, double-gate nanowire single electronic device and preparation method of double-layer V-shaped nanowire structure

Abstract

The invention relates to the technical field of microelectronic manufacturing. The invention discloses a double-layer V-shaped nanowire structure which comprises a base layer arranged on a substrate and further comprises an upper-layer nanowire and a lower-layer nanowire which spatially grow on the base layer in a staggered mode, the upper-layer nanowire and the lower-layer nanowire are broken line type nanowires, and horizontal projections of break points of the broken line type nanowires and horizontal projections of break points of the broken line type nanowires and the lower-layer nanowire coincide and are located on the same plumb line. And the broken line type nanowire on the upper layer is broken at the break point to form a gap. According to the invention, two spatially staggered nanowires are grown by using single IPSLS, the lower layer continuous silicon nanowire is used as a conductive channel, and the upper layer gap nanowire is used as an adjustable depletion gate, so that the preparation process flow of the double-layer V-shaped nanowire structure is greatly simplified, and multiple quantum islands can be integrated to construct a compact quantum bit chain.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics manufacturing technology. The present invention provides a dual-controllable depletion gate SET device having a double-layer V-shaped silicon nanowire structure. More specifically, the present invention provides a dual-controllable gate nanowire single-electron transistor device formed in a single growth step and a method for fabricating the device. Background Art

[0002] The single-electron transistor (SET), a quantum device based on the Coulomb blockade effect, holds revolutionary potential for next-generation quantum computing, high-precision sensing, and ultra-low-power electronics due to its ultra-low power consumption (single-electron manipulation) and ultra-high sensitivity (single-charge detection). The key challenge in realizing high-performance SET devices lies in the precise construction of a sub-10 nm "quantum island-tunneling junction" structure, requiring materials with atomically clean interfaces, excellent crystal quality, and uniform diameter. Silicon nanowires (SiNWs) are considered an ideal substrate for SET construction due to their inherent compatibility with mainstream silicon-based processes, strong quantum confinement, and controllable doping. However, SiNWs grown using traditional fabrication methods (such as vapor-phase deposition (VLS)) face the following bottlenecks: large diameter fluctuations (>20%) lead to discrete quantum island sizes; dense surface defect states induce random charge fluctuations; and positional disorder hinders high-density array integration.

[0003] The nanowires obtained by existing technologies based on the "planar solid-liquid-solid" growth method have the advantages of planar or three-dimensional positioning, programmable morphology, controllable diameter and high diameter consistency, low cost, single crystal quality, low-temperature growth (<400°C) and compatibility with back-end integration, which can easily meet the needs of quantum islands.

[0004] Based on the above research results, exploring a dual-controllable-gate silicon-based nanowire quantum island single-electron transistor with smaller size, lower cost, easier growth difficulty and higher integration density to better serve the next generation of quantum computing technology, high-precision sensing and ultra-low power electronics is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application solves the technical problem that silicon-based nanowire single-electron transistors in the prior art cannot be positioned and integrated by providing a double-layer V-shaped nanowire structure, a dual-gate nanowire single-electron device and a preparation method. It also solves the technical problem that the current IPSLS technology for growing nanowires to prepare SET devices requires multiple growth processes and a complex process flow, thereby achieving the technical effects of simple process, low cost, positionability and high integration density of silicon nanowire single-electron transistors.

[0006] The present application provides a double-layer V-shaped nanowire structure, including a base layer arranged on a substrate, characterized in that it also includes an upper nanowire and a lower nanowire grown on the base layer in a spatially dislocated manner, the upper nanowire and the lower nanowire being zigzag nanowires whose horizontal projections of inflection points coincide and are located on the same plumb line, and the zigzag nanowire of the upper layer is disconnected at the inflection point and has a gap.

[0007] Preferably, the base layer is a double-layer silicon oxide step structure etched in an upper and lower staggered cross pattern, and the upper and lower nanowires are respectively grown in the V-shaped guide channel of the double-layer silicon oxide step structure. The upper nanowire grows along the guide channel and breaks at the inflection point to form the gap.

[0008] The present invention also provides a dual-gate nanowire single-electron device, comprising the above-mentioned double-layer V-shaped nanowire structure, characterized in that: the active and drain electrode layers and the dielectric layer are deposited in sequence from the inside to the outside on the surfaces of the two ends of the lower nanowire and etched to form the source and drain electrode opening regions, and the gate electrode layer and the gate dielectric layer are deposited in sequence from the inside to the outside on the two ends of the upper nanowire and etched to form the gate electrode opening region.

[0009] Preferably, the step thickness of the double-layer silicon oxide step structure is greater than the sum of the diameters of the upper and lower nanowires and the thicknesses of the electrode layer and the dielectric layer deposited on the surface thereof.

[0010] Preferably, the thickness of the step is 100 nm, the diameters of the upper and lower nanowires are 50 nm, and the thickness of the dielectric layer is 25 nm.

[0011] The present invention also discloses a method for preparing the double-layer V-shaped nanowire structure, which is characterized by comprising the following steps: In the first step, the side structure of the silicon oxide base layer is exposed by photolithography and reactive coupled plasma etching technology to form the first step-shaped guide channel layer; In the second step, the side structure of the silicon oxide base layer is exposed by photolithography and reactive coupled plasma etching technology, forming a second stepped guide channel layer that intersects with the first stepped guide channel layer to obtain a double-layer V-shaped guide channel; In the third step, photolithography is used to locate the catalytic metal region at one end of the lower layer of the double-layer V-shaped guide channel, and thermal evaporation is used to deposit the metal film. Photolithography is then used to locate the catalytic metal region at the end of the upper layer of the double-layer V-shaped guide channel, which is farther away from the inflection point than the lower layer, and thermal evaporation is used to deposit the metal film. In the fourth step, a planar solid-liquid-solid growth method is used. Hydrogen plasma is used in the PECVD equipment to reduce the metal film into metal balls, which are then covered with precursors. In a vacuum and high-temperature environment of 300°C to 350°C, the metal balls absorb the precursors along the V-shaped guide channels on the etched silicon oxide substrate. When the upper metal balls move to the inflection point, the precursors at the inflection point have been absorbed by the lower metal balls and nanowires cannot be formed temporarily. Finally, a zigzag lower nanowire is formed that grows once along the lower V-shaped guide channel and an upper nanowire is formed that grows once along the upper V-shaped guide channel and is disconnected at the inflection point.

[0012] Preferably, the V-shaped guide channel has an angle ranging from 120° to 150°.

[0013] The present invention also discloses a method for preparing the dual-gate nanowire single-electron device, which is characterized by comprising the following steps: In the first step, photolithography was used to locate the nanowire electrode regions at the four ends of the double-layer V-shaped nanowire structure. The grown nanowire sample was passed through a silicon oxide etchant to remove the native oxide layer on the nanowire surface. Electron beam evaporation was then used to deposit nanowire electrodes to connect the four ends of the nanowire. In the second step, a gate dielectric layer is deposited on the surface of the double-layer V-shaped nanowire structure using ALD technology. The gate dielectric layer is not required to be positioned and is deposited on the entire surface to wrap around the double-layer V-shaped nanowire structure. The third step is to use photolithography and etching technology to locally etch the gate dielectric layer on the nanowire electrode to form an opening area of ​​the dual-adjustable gate SET device, so as to facilitate the application of voltage to the source, drain, and gate electrodes formed by the double-layer V-shaped nanowire connected by the nanowire electrode.

[0014] Preferably, source and drain electrode layers are deposited at both ends of the lower nanowire of the double-layer V-shaped nanowire structure, and gate electrode layers are deposited at both ends of the upper nanowire to form the gate of a dual-controllable depletion gate SET device.

[0015] The technical solution provided by this application has at least the following technical effects or advantages: 1. The present invention uses a single IPSLS to grow two spatially dislocated nanowires, in which the lower continuous silicon nanowire acts as a conductive channel and the upper nanowire with gaps acts as a controllable depletion gate. This greatly simplifies the preparation process of the double-layer V-shaped nanowire structure and can integrate multiple quantum islands to construct a compact quantum bit chain.

[0016] 2. The present invention solves the technical difficulty of obtaining a small-sized, positionable dual-adjustable depletion gate through single IPSLS growth, effectively improves the integration density of silicon nanowire dual-adjustable depletion gate SET, reduces the production cost, and is suitable for silicon-based quantum devices.

[0017] 3. This invention utilizes a double-layer V-shaped nanowire structure to fabricate a dual-tunable-gate SET device, where the lower nanowire grows to the inflection point earlier than the upper nanowire and pre-absorbs the amorphous silicon at the inflection point. When the upper nanowire grows to the inflection point, a gap is automatically created due to insufficient amorphous silicon supply. This avoids the high cost and large-scale integration limitations associated with the use of high-precision photolithography. The silicon nanowire dual-tunable-gate SET device avoids etching damage by forming quantum islands on unetched continuous nanowires through electric field depletion, resolving the fundamental contradictions between quantum island precision, noise suppression, and scalability in traditional SETs. This design provides one of the most promising technical paths for the practical application of silicon-based quantum devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart for preparing a double-layer V-shaped nanowire structure according to one embodiment of the present invention; Figure 2 1 is a schematic structural diagram of a dual-adjustable depletion gate SET fabricated using a double-layer V-shaped nanowire structure in one embodiment of the present invention; Figure 3 1 is a logic diagram of a dual-controllable depletion gate SET fabricated using a double-layer V-shaped nanowire structure in one embodiment of the present invention; Figure 4 1 is a schematic plan view of a dual-controllable depletion gate SET device fabricated using a double-layer V-shaped nanowire structure in one embodiment of the present invention; In the figure: 101, double-layer V-shaped steps; 102, lower nanowire; 103, upper nanowire; 104, step structure of silicon oxide base layer after the first etching; 105, step structure formed by silicon oxide base layer after the second etching; 106, upper guide channel metal indium film; 107, lower guide channel metal indium film; 108, upper guide channel indium ball; 109, lower guide channel indium ball; 110, amorphous silicon precursor; 111, lower nanowire grown to the inflection point in advance; 112, upper nanowire not yet grown to the inflection point; 201, dual-controllable depletion gate SET device; 202, gate dielectric layer; 203, source and drain electrode layer; 204, gate electrode layer; 301, source and drain electrode opening region; 401, gate electrode opening region. DETAILED DESCRIPTION

[0019] Based on a single-growth planar nanowire structure, this invention first uses two upper nanowires as gates to control the underlying continuous nanowire. Then, using ALD deposition technology, the gate dielectric and electrode layers are deposited using a double-layer V-shaped nanowire structure to create a high-performance dual-controllable depletion gate SET device. Leveraging the topography programming and three-dimensional positioning capabilities of the double-layer V-shaped nanowires, this invention achieves low cost, uniform dimensions, low defects, and high density.

[0020] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] Example 1: This example provides a double-layer V-shaped nanowire structure and a preparation method, such as Figure 1 As shown: it includes a silicon oxide base layer arranged on a silicon substrate, and also includes an upper nanowire 103 and a lower nanowire 102 that are spatially dislocated and grown on a double-layer V-shaped step 101 of the silicon oxide base layer. The upper nanowire 103 and the lower nanowire 102 are V-shaped nanowires whose horizontal projections of the inflection points coincide and are located on the same plumb line. The upper nanowire is disconnected at the inflection point and there is a gap.

[0022] As a preferred embodiment of this invention, a double-layer silicon oxide step structure is formed by staggered cross-etching of the upper and lower silicon oxide base layers, and the upper nanowires and the lower nanowires are respectively grown in the V-shaped guide channel of the double-layer silicon oxide step structure. The upper nanowire grows along the guide channel and breaks at the inflection point to form the gap.

[0023] This embodiment also discloses a method for preparing the double-layer V-shaped nanowire structure, which includes the following steps: In the first step, a silicon oxide layer is patterned on a single-sided polished substrate material having an upper silicon oxide layer having a thickness of more than 1 micron using photolithography technology, and then the silicon oxide layer is etched using inductively coupled plasma (ICP) etching technology to form a silicon oxide base layer step structure 104 after the first etching. In this embodiment, an etching depth of 100 nm is used as an example.

[0024] In the second step, the silicon oxide layer is patterned using photolithography, forming an angle with the pattern created in the first step. To ensure that the lower nanowires do not grow across the steps to the upper layer, the angle formed by the lower guide steps is controlled at 120 degrees. The silicon oxide layer is then etched using inductively coupled plasma (ICP) etching technology, forming a stepped structure 105 formed by the silicon oxide base layer after the second etching. In this embodiment, the etching depth is 100 nm.

[0025] In the third step, photolithography technology is used to locate the metal indium area at one end of the etched silicon oxide layer and the silicon oxide guide channel layer, and thermal evaporation deposition technology is used to position and deposit the upper guide channel metal indium film 106 at a position farther away from the intersection inflection point in the upper channel, and position and deposit the lower guide channel metal indium film 107 at a position closer to the intersection inflection point in the lower channel; using the "planar solid-liquid-solid" growth method, hydrogen plasma is used in the PECVD equipment to reduce the upper guide channel metal indium film 106 and the lower guide channel metal indium film 107 into upper guide channel indium balls 108 and lower guide channel indium balls 109, and then cover them with an amorphous silicon precursor 110 film.

[0026] Preferably, in this embodiment, the upper guide channel metal indium film is 45 microns away from the intersection inflection point, and the lower guide channel metal indium film is 40 microns away from the intersection inflection point.

[0027] In the fourth step, in a vacuum and high temperature environment of 300℃~350℃, the upper guide channel indium ball 108 absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow crystalline silicon nanowires at the rear end, and the lower guide channel indium ball 109 absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow crystalline silicon nanowires at the rear end. Compared with the upper guide channel indium ball, the lower guide channel indium ball moves to the guide channel inflection point first and absorbs the amorphous silicon precursor a-Si at the inflection point to form the lower layer nanowire 111 that grows to the inflection point first, and the upper guide channel indium ball has not yet grown to the inflection point, forming the upper layer nanowire 112 that has not yet grown to the inflection point.

[0028] In the fifth step, in a vacuum and high temperature environment of 300℃~350℃, the lower guide channel indium ball continues to absorb the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow crystalline silicon nanowires at the rear end to form the lower nanowire 102, and the upper guide channel indium ball absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow crystalline silicon nanowires at the rear end. When the upper guide channel indium ball moves to the inflection point, the amorphous silicon precursor a-Si at the inflection point has been absorbed by the lower guide channel indium ball and the nanowire cannot be formed temporarily, and finally the upper nanowire 103 is formed which is disconnected at the inflection point of the silicon oxide guide channel.

[0029] Embodiment 2: This embodiment provides a dual-controllable depletion gate SET device 201, such as Figure 2-Figure 4 As shown: it includes the double-layer V-shaped nanowire structure described in Example 1, the active and drain electrode layers 203 and the gate dielectric layer 202 are deposited on the surfaces of both ends of the lower nanowire from the inside out and are etched to form the source and drain electrode opening areas 301, and the gate electrode layer 204 and the gate dielectric layer 202 are deposited on both ends of the upper nanowire from the inside out and are etched to form the gate electrode opening area 401.

[0030] Preferably, in this embodiment, a gate dielectric layer 202 is deposited on the entire surface; the upper disconnected nanowires of the double-layer V-shaped nanowires constitute the gate of the dual-adjustable depletion gate SET device; the gate dielectric layer 202 is made of a high dielectric constant dielectric material, such as hafnium oxide, by ALD.

[0031] Preferably, the step thickness of the double-layer silicon oxide step structure in this embodiment is greater than the diameter of the upper and lower nanowires, plus the thickness of the electrode layer and dielectric layer deposited on their surfaces. More specifically, to ensure that the nanowires grow along the edge of the silicon oxide step layer without crossing the step, the step thickness is 100 nm, the diameters of the upper and lower nanowires are 50 nm, the dielectric layer thickness is 25 nm, and the distance between the fracture of the upper nanowire and the lower nanowire is 50 nm. Therefore, the high-k gate dielectric layer 202 deposited using ALD technology can ensure complete encapsulation of the nanowires, and the high-k gate dielectric layer can achieve good gate control of the silicon nanowires.

[0032] This embodiment also discloses a method for preparing the dual-controllable depletion gate SET device. First, the double-layer V-shaped nanowire structure in Example 1 is prepared by a planar solid-liquid-solid growth method. Then, the method further includes the following steps: In the first step, near the four ends of the double-layer V-shaped nanowire, Figure 2 In the device structure shown, the source, drain, and gate electrode regions are first positioned using photolithography, and the areas outside the regions are covered with photoresist. The source, drain, and gate electrode layers are deposited using EBE technology, and then the metal layer outside the positioning areas is lift-off to obtain patterned source and drain electrode layers 203 and gate electrode layer 204. In the second step, a gate dielectric layer 202 is deposited on the entire surface of the double-layer V-shaped nanowire structure and the source, drain, and gate electrode layers using ALD technology. The gate dielectric layer is deposited on the entire surface and wraps around the double-layer V-shaped nanowire structure and the source, drain, and gate electrode layers. In the third step, the gate dielectric layer on the nanowire source, drain and gate electrodes is partially etched using photolithography and etching techniques to form the source and drain electrode opening regions 301 and the gate electrode opening region 401 in the dual-adjustable depletion gate SET device, so as to facilitate the application of source and drain voltages to the source and drain electrodes and the application of gate voltage to the gate electrode.

[0033] This application is based on the self-organized catalytic growth strategy induced by metal nanodroplets. It does not rely on the "top-down" etching method of high-precision lithography technology, but can directly grow and prepare single-crystal nanowire structures with fine diameters in batches. Through the new "planar solid-liquid-solid" nanowire growth mode, the growth of nanowires is completely restricted and positioned to grow on the edge of the planar step. By cleverly forming a double-layer dislocated step with an angle, a nanowire structure that can be precisely disconnected is formed, which provides a convenient and reliable high-integration structure for using nanowires as depletion gates to form small-sized quantum islands. The structure or device of preparing a dual-adjustable depletion gate SET using nanowires proposed in this application effectively solves the problems of troublesome production of silicon nanowire quantum islands, inability to locate, and difficulty in large-scale production, greatly enhancing the application potential of silicon nanowires in the future development of quantum computing.

[0034] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements can be made without departing from the principles of the present invention. These improvements should also be regarded as the scope of protection of the present invention.

Claims

1. A double-layer V-shaped nanowire structure, comprising a base layer disposed on a substrate, characterized in that: It also includes upper nanowires and lower nanowires that are spatially dislocated and grown on the base layer. The upper nanowires and lower nanowires are zigzag nanowires whose horizontal projections of inflection points coincide and are located on the same plumb line. The zigzag nanowires of the upper layer are disconnected at the inflection points and have gaps.

2. The double-layer V-shaped nanowire structure according to claim 1, wherein: The base layer is a double-layer silicon oxide step structure with upper and lower staggered cross-etching. The upper nanowire and the lower nanowire are respectively grown in the V-shaped guide channel of the double-layer silicon oxide step structure. The upper nanowire grows along the guide channel and breaks at the inflection point to form the gap.

3. A dual-gate nanowire single-electron device comprising the double-layer V-shaped nanowire structure according to claim 1 or 2, characterized in that: The surfaces of both ends of the lower nanowire are sequentially deposited with source and drain electrode layers and dielectric layers from the inside out and etched to form source and drain electrode opening areas. The surfaces of both ends of the upper nanowire are sequentially deposited with gate electrode layers and dielectric layers from the inside out and etched to form gate electrode opening areas.

4. The dual-gate nanowire single-electron device according to claim 3, wherein: The step thickness of the double-layer silicon oxide step structure is greater than the sum of the diameters of the upper and lower nanowires and the thicknesses of the electrode layer and the dielectric layer deposited on the surface thereof.

5. The dual-gate nanowire single-electron device according to claim 4, characterized in that: The thickness of the step is 100 nm, the diameters of the upper and lower nanowires are 50 nm, and the thickness of the dielectric layer is 25 nm.

6. A method for preparing a double-layer V-shaped nanowire structure, characterized in that: It includes the following steps: In the first step, the side structure of the silicon oxide base layer is exposed by photolithography and reactive coupled plasma etching technology to form the first step-shaped guide channel layer; In the second step, the side structure of the silicon oxide base layer is exposed by photolithography and reactive coupled plasma etching technology, forming a second stepped guide channel layer that intersects with the first stepped guide channel layer to obtain a double-layer V-shaped guide channel; In the third step, photolithography is used to locate the catalytic metal region at one end of the lower layer of the double-layer V-shaped guide channel, and thermal evaporation is used to deposit the metal film. Photolithography is then used to locate the catalytic metal region at the end of the upper layer of the double-layer V-shaped guide channel, which is farther away from the inflection point than the lower layer, and thermal evaporation is used to deposit the metal film. In the fourth step, a planar solid-liquid-solid growth method is used. Hydrogen plasma is used in the PECVD equipment to reduce the metal film into metal balls, which are then covered with precursors. In a vacuum and high-temperature environment of 300°C to 350°C, the metal balls absorb the precursors along the V-shaped guide channels on the etched silicon oxide substrate. When the upper metal balls move to the inflection point, the precursors at the inflection point have been absorbed by the lower metal balls and nanowires cannot be formed temporarily. Finally, a zigzag lower nanowire is formed that grows once along the lower V-shaped guide channel and an upper nanowire is formed that grows once along the upper V-shaped guide channel and is disconnected at the inflection point.

7. The method for preparing a double-layer V-shaped nanowire structure according to claim 6, characterized in that: The V-shaped guide channel has an included angle range of 120° to 150°.

8. A method for preparing a dual-gate nanowire single-electron device, applicable to the dual-gate nanowire single-electron device according to claim 3, characterized in that: It includes the following steps: In the first step, photolithography was used to locate the nanowire electrode regions at the four ends of the double-layer V-shaped nanowire structure. The grown nanowire sample was passed through a silicon oxide etchant to remove the native oxide layer on the nanowire surface. Electron beam evaporation was then used to deposit nanowire electrodes to connect the four ends of the nanowire. In the second step, a gate dielectric layer is deposited on the surface of the double-layer V-shaped nanowire structure using ALD technology. The gate dielectric layer is not required to be positioned and is deposited on the entire surface to wrap around the double-layer V-shaped nanowire structure. The third step is to use photolithography and etching technology to locally etch the gate dielectric layer on the nanowire electrode to form an opening area of ​​the dual-adjustable gate SET device, so as to facilitate the application of voltage to the source, drain, and gate electrodes formed by the double-layer V-shaped nanowire connected by the nanowire electrode.

9. The method for preparing a dual-gate nanowire single-electron device according to claim 8, characterized in that: The two ends of the lower nanowire of the double-layer V-shaped nanowire structure are respectively positioned to deposit source and drain electrode layers, and the two ends of the upper nanowire are both positioned to deposit gate electrode layers to form the gate of a dual-adjustable depletion gate SET device.

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