Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, relates to the technical field of photovoltaic, and is used for reducing the risk that the surface of a semiconductor substrate and a surface passivation layer are scratched, facilitating the improvement of the passivation effect of the surface passivation layer on the semiconductor substrate, and further facilitating the improvement of the conversion efficiency of the solar cell. The solar cell comprises a semiconductor substrate and a surface passivation layer. The semiconductor substrate includes a textured topography region. Suede structures are densely distributed in the suede morphology area. And the surface passivation layer is directly arranged on the suede morphology area. Wherein the suede morphology area comprises a non-plaque area and a plurality of plaque areas dispersed in the non-plaque area. In the thickness direction of the semiconductor substrate, the height of the plaque region is smaller than that of the non-plaque region. The photovoltaic module comprises the solar cell. The manufacturing method of the solar cell is used for manufacturing the solar cell.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the solar cell's semiconductor pn junction, forming new hole-electron pairs. Under the action of the pn junction's built-in electric field, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. Once the circuit is connected, current is generated. A doped semiconductor layer and a surface passivation layer with a chemical passivation function can be formed on the surface of the solar cell's semiconductor substrate to reduce the number of surface defects and lower the carrier recombination rate on the semiconductor substrate's surface, thereby improving the efficiency of the solar cell. Furthermore, to improve light absorption and utilization, the surface of the semiconductor substrate is generally designed with a suede morphology. Furthermore, because doped semiconductor layers generally have strong parasitic absorption, the doped semiconductor layer is eliminated and the surface passivation layer is directly used to passivate the semiconductor substrate.

[0003] However, existing solar cells have a problem of low conversion efficiency during mass production. Summary of the Invention

[0004] The object of the present invention is to provide a solar cell and its manufacturing method, and a photovoltaic module, which are used to reduce the risk of scratching the suede morphology area and surface passivation layer included in the semiconductor substrate, thereby improving the passivation effect of the surface passivation layer on the semiconductor substrate, and further improving the conversion efficiency of the solar cell.

[0005] To achieve the above objectives, the present invention provides a solar cell comprising: a semiconductor substrate and a surface passivation layer. The semiconductor substrate includes a suede topography region. The suede topography region is densely covered with a suede structure. The surface passivation layer is directly disposed on the suede topography region. The suede topography region includes a non-patch region and a plurality of patch regions dispersed within the non-patch region. Along the thickness direction of the semiconductor substrate, the patch region is less in height than the non-patch region.

[0006] When the above technical solution is adopted, in the solar cell provided by the present invention, the semiconductor substrate includes a velvet morphology area, and the velvet morphology area is densely covered with velvet structures, so that the velvet morphology area has a larger specific surface area. While having a higher light trapping effect, it can also increase the contact area between the surface passivation layer and the velvet morphology area, which is conducive to the stable deposition of the surface passivation layer on the velvet morphology area and enhances the binding force of the surface passivation layer on the velvet morphology area. In addition, the velvet morphology area includes a non-patch area and several patch areas scattered in the non-patch area. Among them, the patch area refers to a patch area with a tower base morphology presented by a plurality of velvet structures included in the velvet morphology area. The patch area is a closed figure with a clear boundary between the patch area and the non-patch area. In the above case, when the height of the patch area in the velvet morphology area is smaller, the patch area is moved closer to the inside, while the non-patch area with a larger height in the velvet morphology area is moved closer to the outside; compared with the previous situation where the entire velvet morphology area is in contact with the manufacturing equipment and / or transfer equipment, the area of ​​contact between the velvet morphology area and the manufacturing equipment and / or transfer equipment is reduced, thereby reducing the probability of the surface passivation layer being scratched. Based on this, the presence of the patch area with a smaller height can reduce the risk of part of the velvet structure (i.e., the velvet structure located in the patch area) being scratched during other operations and / or transfers after the velvet treatment and before the surface passivation treatment is performed on at least the velvet morphology area of ​​the semiconductor substrate to form a surface passivation layer, thereby reducing damage to the velvet structure, reducing the number of defects in the velvet morphology area, and improving the yield of battery production. In particular, for high-efficiency batteries, it is more helpful to improve the yield of battery production.

[0007] As a possible implementation solution, at least one patch area is in the shape of a polygon or a strip.

[0008] When the above technical solution is adopted, the shape of at least one patch area can be a polygonal morphology such as a quadrilateral, pentagon or hexagon. In this case, the patch area presents a patch area with a discretely distributed tower base morphology. Alternatively, the shape of at least one patch area can also be a long strip. In this case, the patch area presents a patch area composed of multiple tower base morphologies overlapping each other in roughly the same direction. It can be seen that the patch area can have a variety of morphologies, which can reduce the difficulty of manufacturing; at the same time, different patch areas have different ranges, and the morphology of the patch area can be set according to actual needs, thereby regulating the distribution of patch areas with smaller heights in the suede morphology area. This is beneficial to prevent the suede morphology area included in the semiconductor substrate and the part of the surface passivation layer located on the patch area from coming into contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process, thereby greatly reducing the risk of scratching the suede morphology area and the surface passivation layer included in the semiconductor substrate, and improving the passivation effect of the surface passivation layer on the semiconductor substrate.

[0009] As a possible implementation scheme, a plurality of patch areas arranged at intervals along a first direction form a patch column. A plurality of patch columns are provided in the suede morphology area, and different patch columns are spaced apart along a second direction. The second direction intersects with the first direction. In this case, the distribution of different patch areas is relatively regular, which prevents the excessive concentration of patch areas in a certain area of ​​the suede morphology area, making it difficult for the surface of the semiconductor substrate and the surface passivation layer corresponding to this area to be separated from the contact surface of the manufacturing equipment and / or transfer equipment through the non-patch area with a larger height during the corresponding manufacturing process, thereby effectively reducing the risk of scratches on the suede morphology area and the surface passivation layer included in the semiconductor substrate. In addition, the distribution of different patch areas is relatively regular, which is also conducive to improving the macroscopic flatness of different areas of the suede morphology area, effectively improving the uniform deposition of the surface passivation layer on the suede morphology area, and improving the passivation effect.

[0010] As a possible implementation solution, a one-dimensional size of at least one patch area is greater than or equal to 15 μm and less than or equal to 50 μm.

[0011] When the above technical solution is adopted, the one-dimensional size of at least one patch area is within the above range, which is beneficial to prevent the one-dimensional size of the patch area from being too small, resulting in the patch area with a smaller height in the velvet morphology area accounting for a smaller area, causing the velvet morphology area and the surface passivation layer to have a higher height on one side of the surface corresponding to the velvet morphology area, making it easier for them to contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process, reducing the risk of scratches on the velvet morphology area and the surface passivation layer included in the semiconductor substrate; and it can also prevent the one-dimensional size of the patch area from being too small, resulting in a smaller degree of flattening of the part of the surface of the semiconductor substrate corresponding to the velvet morphology area before the velvet treatment is performed, which is beneficial to make the part of the surface have a certain macroscopic flatness, so that the size uniformity of the velvet structure obtained after the velvet treatment of this part of the surface is higher, which is beneficial to improving the deposition quality of the surface passivation layer on the velvet morphology area and improving the passivation effect of the surface passivation layer. In addition, it can also prevent the one-dimensional size of the patch area from being too large, resulting in the patch area occupying a large area in the suede morphology area and / or the patch area occupying too large an area in a certain area in the suede morphology area, making it difficult for most of the surfaces of the semiconductor substrate and the surface passivation layer corresponding to the patch area to be isolated from the manufacturing equipment and / or transfer equipment through the non-patch area with a larger height during the corresponding manufacturing process, effectively reducing the risk of scratches on the suede morphology area and the surface passivation layer included in the semiconductor substrate; and because the non-patch area with a larger height is located on the outside, it is easier for it to come into contact with the manufacturing equipment and / or transfer equipment. Therefore, it can also prevent the one-dimensional size of the patch area from being too large, which makes the area of ​​the non-patch area smaller, resulting in a larger contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment comes into contact at the non-patch area, thereby reducing the risk of scratches on the non-patch area corresponding to the semiconductor substrate and the surface passivation layer; at the same time, it can also prevent the one-dimensional size of the patch area from being too large, which makes the degree of flattening of the part of the surface of the semiconductor substrate corresponding to the suede morphology area too large, which is beneficial for the part of the semiconductor substrate corresponding to the suede morphology area to have a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate.

[0012] As a possible implementation solution, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure is greater than or equal to 4 and less than or equal to 60.

[0013] When the above technical solution is adopted, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure is within the above range, which can prevent the one-dimensional size of the patch area from being too small and / or the one-dimensional size of the velvet structure from being too large due to the ratio being too small. At this time, the size of the velvet structure is relatively small, which can reduce the surface roughness of the velvet morphology area, improve the conformality difference of the surface passivation layer on the top and base of the velvet structure, and further improve the passivation effect of the surface passivation layer on the semiconductor substrate. In addition, it can also prevent the one-dimensional size of the patch area from being too large and / or the one-dimensional size of the velvet structure from being too small due to the ratio being too large, which is beneficial to reducing the light reflectivity of the portion corresponding to the velvet morphology area and improving the light absorptivity of the semiconductor substrate corresponding to the velvet morphology area. As for the beneficial effect of preventing the one-dimensional size of the patch area from being too large or too small, please refer to the previous text and will not be repeated here.

[0014] As a possible implementation solution, within the suede morphology area and in a unit area of ​​300 μm×300 μm, the number of patch areas distributed is greater than or equal to 6 and less than or equal to 25.

[0015] When adopting the above technical solution, the distribution number of patch areas per unit area is within the above range, which is conducive to preventing the patch areas from being too concentrated in a certain area of ​​the surface of the suede morphology area due to the distribution number of patch areas being too large and / or the patch areas accounting for a large proportion of the area in the suede morphology area, resulting in the suede morphology area and the surface passivation layer corresponding to the surface of the area being difficult to be separated from the contact surface of the manufacturing equipment and / or transfer equipment through the non-patch area with a larger height, thereby reducing the risk of the suede morphology area and the surface passivation layer being scratched; at the same time, it can also reduce the contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment comes into contact at the non-patch area, thereby reducing the risk of the semiconductor substrate and the surface passivation layer corresponding to the non-patch area being scratched. In addition, it can also prevent the area of ​​the surface of the semiconductor substrate and the surface passivation layer that is separated from the contact surface of the manufacturing equipment and / or transfer equipment by the patch area from being small due to the small number of patch areas, thereby reducing the risk of the semiconductor substrate and the surface passivation layer being scratched; at the same time, it can also prevent the degree of flattening of the part of the surface corresponding to the suede morphology area of ​​the semiconductor substrate from being too large due to the high number of patch areas, which is beneficial for the part of the semiconductor substrate corresponding to the suede morphology area to have a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate.

[0016] As a possible implementation solution, the velvet structure is a pyramid structure. In this case, the pyramid structure has a good light trapping effect, which is beneficial to improving the conversion efficiency of the solar cell.

[0017] As a possible implementation solution, a one-dimensional size of at least one texture structure is greater than or equal to 0.1 μm and less than or equal to 4 μm.

[0018] When the above technical solution is used, the one-dimensional size of the velvet structure is within the above range, which helps prevent the specific surface area of ​​the velvet morphology region from being too small due to the one-dimensional size of the velvet structure being too small, thereby ensuring that the velvet morphology region has a higher light trapping effect. In addition, it can also prevent the large degree of undulation in the velvet morphology region caused by the one-dimensional size of the velvet structure being too large, reduce the difference in the deposition quality of the surface passivation layer in different areas of the velvet structure, and improve the passivation effect of the surface passivation layer.

[0019] As a possible implementation solution, a height difference between at least one patch area and a non-plaque area is less than 4 μm.

[0020] When adopting the above-mentioned technical solution, the height difference between the patch area and the non-patch area is relatively small, which is beneficial to improving the flatness of the partial surface of the semiconductor substrate corresponding to the velvet morphology area within the scale standard range of the film layer conformality, thereby helping to improve the one-dimensional size uniformity of the velvet structure in different parts of the velvet morphology area after the velvet treatment, thereby improving the deposition uniformity of the surface passivation layer on the velvet morphology area and improving the passivation effect of the surface passivation layer.

[0021] As a possible implementation scheme, in the velvet morphology area, the velvet structure located in the patch area is defined as the first velvet structure, and the velvet structure located at the junction of the patch area and the non-patch area is defined as the junction velvet structure. The velvet structure located in the non-patch area is the second velvet structure. Among them, the one-dimensional size of at least one junction velvet structure is greater than the one-dimensional size of the first velvet structure and the second velvet structure; and / or, the one-dimensional size of at least one junction velvet structure is greater than or equal to 1.8μm and less than or equal to 2.5μm; and / or, the one-dimensional size of at least one first velvet structure and / or the second velvet structure is greater than or equal to 0.9μm and less than or equal to 1.5μm.

[0022] When adopting the above technical solution, the size of the one-dimensional size of the velvet structure itself and its corresponding light-trapping wavelength have a certain matching property. When the one-dimensional size of the boundary velvet structure is different from the one-dimensional size of the first velvet structure and the second velvet structure, it is beneficial for the velvet morphology area to have a higher light-trapping effect for light of different wavelengths, thereby improving the light absorption rate of the semiconductor substrate.

[0023] As a possible implementation solution, in the velvet morphology area, the velvet structure located at the junction of the patch area and the non-patch area is defined as the junction velvet structure. In addition, the junction velvet structure is a pyramid-shaped structure, and the length of the side edge of the junction velvet structure facing the non-patch area is shorter than the length of the side edge facing the patch area.

[0024] When adopting the above technical solution, since the top of the pyramid-shaped structure is sharper than its own side surface, compared with setting the junction velvet structure at the junction of the patch area and the non-patch area as a multi-layer pyramid-shaped structure with sharp apex angles, when the length of the side edge of the junction velvet structure facing the non-patch area is less than the length of the side edge of the structure facing the patch area itself, the number of sharp apex angles at the junction of the patch area and the non-patch area can be reduced, which is beneficial to reducing the degree of undulation at the junction and improving the coating of the surface passivation layer at the junction of the patch area and the non-patch area. It solves the problem in the prior art that the surface passivation layer has high requirements on the flatness of the deposited surface when forming the surface passivation layer by atomic layer deposition process, and the specific surface area at the junction is too large, resulting in poor deposition uniformity of the surface passivation layer at the junction, and improves the passivation effect of the surface passivation layer at the junction.

[0025] As a possible implementation scheme, the surface passivation layer includes at least one of an oxide layer, a nitride layer, a nitride oxide layer and a carbide layer. In this case, the material of the surface passivation layer has a variety of optional examples, which is conducive to improving the applicability of the solar cell provided by the present invention in different application scenarios. In addition, the surface passivation layer deposited by atomic layer deposition such as aluminum oxide layer or molybdenum oxide layer has high requirements on the flatness of the deposited surface. Due to the presence of the patch area, the height consistency of the adjacent velvet structure is higher, and the junction of the patch area and the non-patch area is transitioned through the side of the longer pyramid structure, which reduces the number of sharp corners and reduces the degree of undulation of the surface at the junction, which is conducive to improving the deposition uniformity of the surface passivation layer deposited by atomic layer deposition such as aluminum oxide layer or molybdenum oxide layer, and improving the passivation effect of the surface passivation layer.

[0026] As one possible implementation, the semiconductor substrate includes a first surface and a second surface facing each other. The textured topography region is located at least on the first surface. Furthermore, the solar cell further includes a doped semiconductor layer. The doped semiconductor layer is disposed on a surface of the first surface excluding the textured topography region, and / or the doped semiconductor layer is disposed on the second surface.

[0027] As a possible implementation, the surface of the semiconductor substrate where the doped semiconductor layer is provided is a polished topography region, and the polished topography region is provided with a tower-like structure. Furthermore, when both the polished topography region and the suede topography region are located on the first surface, the one-dimensional dimension of the tower-like structure is smaller than the one-dimensional dimension of the patch region.

[0028] When the above-mentioned technical solution is adopted, when the one-dimensional size of the tower base structure is smaller than the one-dimensional size of the patch area, it indicates that after the doped semiconductor layer is formed on a partial area of ​​the semiconductor substrate, and before the partial surface of the semiconductor substrate corresponding to the velvet morphology area is subjected to texturing treatment, the partial surface of the semiconductor substrate corresponding to the velvet morphology area is further flattened. This not only removes the damaged part of the semiconductor substrate corresponding to the velvet morphology area and reduces the carrier recombination rate; it also helps to improve the dimensional uniformity of the velvet structure after the texturing treatment and improve the deposition uniformity of the surface passivation layer in the velvet morphology area.

[0029] As a possible implementation scheme, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion that are alternately distributed along a plane parallel to the first surface and have opposite doping types. In the polishing topography area, the surface of the region where the first doped semiconductor portion is provided is the first region, and the surface of the region where the second doped semiconductor portion is provided is the second region. Along the direction from the second surface to the first surface, the height of the first region is greater than the height of the second region. The one-dimensional size of the tower-shaped structure located in the first region is smaller than the one-dimensional size of the tower-shaped structure located in the second region; and / or the ratio of the one-dimensional size of the tower-shaped structure located in the second region to the one-dimensional size of the tower-shaped structure located in the first region is greater than 1 and less than or equal to 3.

[0030] When the above technical solution is adopted, when the height of the first zone is greater than the height of the second zone; and the one-dimensional size of the tower-shaped structure located in the first zone is smaller than the one-dimensional size of the tower-shaped structure located in the second zone, it indicates that after the first doped semiconductor portion is formed on a partial area of ​​the semiconductor substrate, and before the second doped semiconductor portion is formed on the partial surface of the semiconductor substrate corresponding to the second zone, the partial surface of the semiconductor substrate corresponding to the second zone is further planarized. This not only removes the damaged portion of the semiconductor substrate corresponding to the second zone caused by the patterning of the first doped semiconductor portion, reduces the carrier recombination rate, but also helps to improve the carrier collection efficiency of the second doped semiconductor portion and improve the conversion efficiency of the solar cell.

[0031] In addition, the ratio of the one-dimensional size of the tower-shaped structure located in the first zone to the one-dimensional size of the tower-shaped structure located in the second zone is within the above range, which is beneficial to prevent the surface of the semiconductor substrate corresponding to the second zone from being flattened to a low degree or even not being flattened due to the ratio being too small, which is beneficial to reducing the carrier recombination rate in the second zone and improving the carrier collection efficiency of the second doped semiconductor part; it can also prevent the flattening degree of the part of the second zone from being too high due to the ratio being too large, so that the semiconductor substrate corresponding to the second zone and the suede morphology zone has a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate.

[0032] As a possible implementation, the solar cell is a back-contact cell. A textured morphology region is located in a portion of the first surface and the second surface of the semiconductor substrate. Furthermore, the doped semiconductor layer includes first and second doped semiconductor portions, which are alternately spaced and parallel to the first surface and have opposite doping types. The textured morphology region located on the first surface is disposed between the first and second doped semiconductor portions.

[0033] When the above technical solution is adopted, the solar cell is a back-contact cell, which can reduce the light utilization rate on the front side of the cell and improve the conversion efficiency of the solar cell. In addition, the suede morphology area can not only be located on the second surface of the semiconductor substrate to improve the light trapping effect on the front side of the cell and the passivation effect of the surface passivation layer on the front side of the cell, preventing the surface passivation layer from being scratched, but the suede morphology area can also be arranged between the first doped semiconductor part and the second doped semiconductor part, thereby improving the bifaciality of the back-contact cell and improving the deposition quality of the surface passivation layer between the first doped semiconductor part and the second doped semiconductor part. It can also enhance the resistivity of the surface passivation layer between the first doped semiconductor part and the second doped semiconductor part, effectively preventing charge from being lost from the back side of the cell, and improving the conversion efficiency of the solar cell.

[0034] In a second aspect, the present invention provides a photovoltaic module comprising: a cell string formed by electrically connecting a plurality of solar cells provided in the first aspect and various implementations thereof; and an encapsulation layer covering a surface of the cell string.

[0035] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0036] In a third aspect, the present invention provides a method for manufacturing a solar cell, comprising: first, providing a semiconductor substrate; then, sequentially performing a first planarization process and a texturing process on a portion of the surface of the semiconductor substrate to form a textured topography region on the semiconductor substrate; the textured topography region includes a non-patch region and a plurality of patch regions dispersed within the non-patch region; along the thickness direction of the semiconductor substrate, the patch regions are shorter than the non-patch regions; and finally, forming a surface passivation layer directly on the textured topography region.

[0037] As a possible implementation solution, at least an atomic layer deposition process is used to form a surface passivation layer on the textured morphology area.

[0038] As one possible implementation, a semiconductor substrate includes a first surface and a second surface facing each other. The textured morphology region is located at least on the first surface. Furthermore, after providing the semiconductor substrate, the solar cell manufacturing method further includes: forming a doped semiconductor layer on the second surface and / or on a surface of a region of the first surface excluding the textured morphology region.

[0039] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 A schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention; Figure 2 A schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention; Figure 3 A schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention; Figure 4 A schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention; Figure 5 A schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided by an embodiment of the present invention; Figure 6 A schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided by an embodiment of the present invention; Figure 7 A schematic longitudinal cross-sectional view of a seventh structure of a solar cell provided by an embodiment of the present invention; Figure 8 A schematic longitudinal cross-sectional view of an eighth structure of a solar cell provided by an embodiment of the present invention; Figure 9 A schematic longitudinal cross-sectional view of a ninth structure of a solar cell provided by an embodiment of the present invention; Figure 10 A schematic longitudinal cross-sectional view of a tenth structure of a solar cell provided by an embodiment of the present invention; Figure 11 A SEM image of the structure of a solar cell in a patch area provided by an embodiment of the present invention; Figure 12 A 3D microscope image of the structure of a solar cell in a patch area provided by an embodiment of the present invention; Figure 13A 3D microscope image of the structure of a solar cell provided by an embodiment of the present invention at a partial textured morphology area.

[0041] Figure numerals: 11 is a semiconductor substrate, 12 is a surface passivation layer, 13 is a velvet morphology area, 14 is a non-patch area, 15 is a patch area, 16 is a first velvet structure, 17 is a junction velvet structure, 18 is a second velvet structure, 19 is a doped semiconductor layer, 20 is a first doped semiconductor part, 21 is a second doped semiconductor part, 22 is a first area, 23 is a second area, and 24 is an interface passivation layer. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0043] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0044] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0046] In a first aspect, the present invention provides a solar cell. The solar cell may be a double-sided contact cell or a back-contact cell. The embodiments of the present invention do not specifically limit the type of solar cell.

[0047] like Figures 1 to 5 As shown, the solar cell provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a surface passivation layer 12. The semiconductor substrate 11 includes a suede morphology area 13. Figure 5 As shown, the velvet morphology area 13 is densely covered with velvet structures. Figures 1 to 5 As shown, the surface passivation layer 12 is directly disposed on the textured topography region 13 .

[0048] The surface passivation layer is used to passivate defects, dangling bonds, and the like on the surface of the semiconductor substrate. The surface passivation layer can be, but is not limited to, a chemical passivation layer. The surface passivation layer can also have a fixed charge. In some embodiments, the surface passivation layer can also have an anti-reflection effect.

[0049] like Figures 1 to 5 As shown, the textured morphology area 13 includes a non-plaque area 14 and a plurality of patch areas 15 dispersed within the non-plaque area 14. Along the thickness direction of the semiconductor substrate 11, the height of the patch area 15 is less than the height of the non-plaque area 14. It can be understood that for the convenience of illustration, Figures 1 to 5 Only one patch area is shown, but it is not limited to this.

[0050] The patch area is formed by a plurality of velvet structures included in the velvet morphology area. Specifically, the patch area is generally distinguished by its lower height than other areas (i.e., non-patch areas) in microscopic images such as 3D or SEM, and thus presents a pattern. Figure 11 The quadrilateral block pattern in the SEM image shown. Figure 12 and Figure 13 The blue block pattern in the 3D plot is shown.

[0051] The inventors of this application discovered that high-efficiency batteries have become more sensitive to scratches on the battery surface due to the elimination of the doped semiconductor layer under the surface passivation layer. Previously, due to the presence of the doped semiconductor layer, even if there were some scratches, the doped semiconductor layer could still have a certain passivation effect, and the battery efficiency reduction was not very severe. For high-efficiency batteries that have eliminated the doped semiconductor layer, if the surface passivation layer is scratched, the semiconductor substrate will be directly exposed, forming serious recombination centers. This recombination center may not be the main factor in low-efficiency batteries, but in high-efficiency batteries, this recombination center is the shortest board that restricts battery efficiency. In other words, the more efficient the battery, the greater the impact of this recombination center on battery efficiency.

[0052] The inventors of the present application further discovered that when a patch area with a smaller height is provided in the velvet morphology area, that is, the patch area is a pit, the surface of the patch area in the velvet morphology area is closer to the inside, and the surface of the non-patch area in the velvet morphology area is closer to the outside; compared with the previous velvet morphology area that is in contact with the manufacturing equipment and / or transfer equipment, the area of ​​contact between the velvet morphology area and the manufacturing equipment and / or transfer equipment is reduced, reducing the probability of the surface passivation layer being scratched. Based on this, the presence of a patch area with a smaller height can reduce the risk of part of the velvet structure (that is, the velvet structure located in the patch area) being scratched during other operations and / or transfers after the velvet treatment and before at least the velvet morphology area of ​​the semiconductor substrate is subjected to surface passivation treatment to form a surface passivation layer, reduce damage to the velvet structure, reduce the number of defects in the velvet morphology area, and improve the yield of battery production. Especially for high-efficiency batteries, it is more helpful to improve the yield of battery production.

[0053] In the actual manufacturing process, before forming the surface passivation layer, at least part of the surface of the semiconductor substrate corresponding to the velvet morphology area is first flattened, and then the surface of this part is subjected to a texturing process to obtain a patch area and a non-patch area. Among them, after the flattening process, the deep line marks of the original semiconductor substrate leave a patch prototype area with a flat interior but lower height than other areas. In the subsequent texturing process, by controlling the size of the formed velvet structure and the texturing time, a dense small velvet structure is formed, and the flattening marks are not completely destroyed, so that the patch prototype area forms a patch area. It can be understood that the one-dimensional size of the texture structure formed by the flattening treatment cannot be too small, and the one-dimensional size of the velvet structure during texturing cannot be too large, otherwise it will be difficult to form a patch area.

[0054] The one-dimensional size of the patch area, the depth and distribution density of the deep line marks in the original semiconductor substrate, the polishing morphology control, and the velvet structure control-related parameters can be adjusted by those skilled in the art according to actual conditions.

[0055] This ensures that the patch area has a certain area ratio within the velvet morphology area, and the velvet morphology area has a certain degree of flatness. At the same time, damage and defects to the original semiconductor substrate are relatively completely removed while ensuring low weight loss. This is conducive to ensuring that the velvet structure on the surface of the non-patch area and on the surface of the patch area has a high degree of dimensional uniformity and higher height consistency. After the flattening treatment, the larger texture structure is retained, which can further ensure that damage and defects to the original semiconductor substrate are relatively completely removed while ensuring low weight loss. In addition, the smaller one-dimensional velvet structure formed after the texturing treatment can further improve the deposition uniformity of the surface passivation layer.

[0056] In actual application, the embodiment of the present invention does not specifically limit the distribution range of the suede morphology area on the semiconductor substrate. It can be determined based on the type of solar cell, the formation range of the doped semiconductor layer for collecting carriers in the solar cell, and the requirements for the formation range of the surface passivation layer on the semiconductor substrate in the actual application scenario. No specific limitation is made here.

[0057] For example, Figures 1 to 4 As shown, the semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The textured morphology region 13 is located at least on the first surface. In addition, the solar cell further includes a doped semiconductor layer 19. The doped semiconductor layer 19 is disposed on the surface of the first surface excluding the textured morphology region 13, and / or the doped semiconductor layer 19 is disposed on the second surface.

[0058] The first surface of the semiconductor substrate may correspond to the front surface of the solar cell (the surface directly exposed to light), in which case the second surface of the semiconductor substrate corresponds to the back surface of the solar cell. Alternatively, the first surface of the semiconductor substrate may correspond to the back surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the front surface of the solar cell. The correspondence between the first and second surfaces of the semiconductor substrate and the front and back surfaces of the solar cell, respectively, as well as the location of the doped semiconductor layer on the semiconductor substrate, may be determined according to the type of solar cell.

[0059] In the case of a double-sided contact solar cell, the first surface of the semiconductor substrate may correspond to the front side of the solar cell or the back side of the solar cell. Figure 2 As shown, the doped semiconductor layer 19 can be provided only on the surface of the first surface except the textured topography area 13. Alternatively, as shown in FIG. Figure 1 As shown, the doped semiconductor layer 19 may also be provided only on the second surface. Figure 6 As shown, the doped semiconductor layer 19 can also be arranged on the surface of the area other than the textured morphology area 13 in the first surface, and also on the second surface. Figure 1 As shown, the doped semiconductor layer 19 can be disposed on the second surface as a whole layer, or as shown in FIG. Figure 4 and Figure 6 As shown, it can also be set on a local area of ​​the second surface (in this case, the doping types of the doped semiconductor layer 19 on the first surface and the doped semiconductor layer 19 on the second surface are opposite. Secondly, as Figure 4 As shown, the textured morphology region 13 may also be located on the surface of the second surface except for the area where the doped semiconductor layer 19 is provided, or the textured morphology region 13 may also be located only on the first surface).

[0060] In the case of a back-contact solar cell, the first surface of the semiconductor substrate may correspond to the front surface of the solar cell or the back surface of the solar cell. Figures 7 to 9 As shown, the doped semiconductor layer 19 is disposed on one side of the first and second sides of the semiconductor substrate 11 corresponding to the back side of the solar cell. Furthermore, the doped semiconductor layer 19 includes first doped semiconductor portions 20 and second doped semiconductor portions 21 that are alternately spaced and distributed in a direction parallel to the back side of the solar cell and have opposite doping types. In this case, Figure 9 As shown, the textured morphology area 13 can be provided only on one side of the semiconductor substrate 11 corresponding to the front side of the battery. Figure 7 As shown, the textured morphology region 13 can also be provided only in one side of the semiconductor substrate 11 corresponding to the back side of the battery, and between the first doped semiconductor portion 20 and the second doped semiconductor portion 21. Alternatively, as Figure 8 As shown, the suede morphology region 13 is located both within the side of the semiconductor substrate 11 corresponding to the front side of the battery and within the side of the semiconductor substrate 11 corresponding to the back side of the battery, and the suede morphology region 13 located on the back side of the battery is arranged between the first doped semiconductor portion 20 and the second doped semiconductor portion 21.

[0061] It is worth noting that Figure 8 As shown, in the case where the solar cell is a back-contact cell, when the velvet morphology area 13 is located on both the side of the first and second surfaces of the semiconductor substrate 11 corresponding to the front of the cell and the side of the first and second surfaces corresponding to the back of the cell, the light utilization rate on the front side of the cell can be reduced, thereby improving the conversion efficiency of the solar cell. In addition, the velvet morphology area 13 can not only be located on the side of the semiconductor substrate 11 corresponding to the front of the cell, thereby improving the light trapping effect on the front of the cell and the passivation effect of the surface passivation layer 12 on the front of the cell, thereby preventing the surface passivation layer 12 from being scratched, but also can be arranged between the first doped semiconductor portion 20 and the second doped semiconductor portion 21, thereby improving the bifaciality of the back-contact cell and improving the deposition quality of the surface passivation layer 12 between the first doped semiconductor portion 20 and the second doped semiconductor portion, thereby enhancing the resistivity of the surface passivation layer 12 between the first doped semiconductor portion 20 and the second doped semiconductor portion, thereby effectively preventing charge from being lost from the back of the cell, thereby improving the conversion efficiency of the solar cell.

[0062] As for the doped semiconductor layer, the material of the doped semiconductor layer can include any semiconductor material such as silicon, silicon germanium, or germanium. Exemplarily, the doped semiconductor layer can include a doped crystalline silicon layer (such as at least one of a polycrystalline silicon layer, a single crystal silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer). When the solar cell is a double-sided contact cell, the materials of the two doped semiconductor layers located on the front and back sides of the cell can be the same or different. Furthermore, when the solar cell is a back-contact cell, the materials of the first doped semiconductor portion and the second doped semiconductor portion included in the doped semiconductor layer can be the same or different.

[0063] like Figures 7 to 9 As shown, the doped semiconductor layer 19 can be directly disposed on the semiconductor substrate 11. Alternatively, as shown in FIG. Figure 10 As shown, the solar cell may further include an interface passivation layer 24 located between the doped semiconductor layer 19 and the semiconductor substrate 11. The material and thickness of the interface passivation layer 24 may be set according to the material of the doped semiconductor layer 19 and actual needs. For example: when the doped semiconductor layer is a doped polycrystalline silicon layer, the interface passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include materials such as silicon oxide, aluminum oxide or titanium oxide. For another example: when the material of the doped semiconductor layer may include at least one of a doped amorphous silicon layer, a doped nanocrystalline silicon and a doped microcrystalline silicon, the interface passivation layer may be at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon and intrinsic microcrystalline silicon.

[0064] For example, the solar cell is a double-sided contact cell, wherein the doped semiconductor layer disposed on the surface of the first surface of the semiconductor substrate excluding the textured morphology region and / or on the second surface is a doped crystalline silicon layer. The solar cell further includes a tunneling passivation layer located between the doped semiconductor layer and the semiconductor substrate.

[0065] For example, the solar cell is a back-contact cell, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion, both of which are doped crystalline silicon layers, and the solar cell further includes a tunneling passivation layer located between the doped crystalline silicon layer and the semiconductor substrate.

[0066] As for the height difference between the patch area and the non-patch area in the suede morphology area, it can be set according to the requirements of the actual application scenario for the scratch resistance and deposition uniformity of the surface passivation layer, the light trapping requirements of the suede morphology area, and the thickness requirements of different areas of the semiconductor substrate.

[0067] Exemplarily, the height difference between at least one patch area and the non-patch area is less than 4μm. For example, the height difference between at least one patch area and the non-patch area can be 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm, 3.5μm or 4μm, etc. In this case, the height difference between the patch area and the non-patch area is relatively small, which is beneficial to improving the flatness of the surface of the semiconductor substrate corresponding to the suede morphology area within the scale standard range of the film layer conformal, thereby improving the one-dimensional size uniformity of the suede structure of different parts of the suede morphology area after the suede treatment, thereby improving the deposition uniformity of the surface passivation layer on the suede morphology area and improving the passivation effect of the surface passivation layer.

[0068] As for the morphology and size of the velvet structure of the velvet morphology area, the morphology and size of the patch area, and the distribution of different patch areas, they can be set according to actual needs.

[0069] For example, Figure 5 As shown, the velvet structure is a pyramid structure. In this case, the pyramid structure has a good light trapping effect, which is beneficial to improving the conversion efficiency of the solar cell. In addition, when the velvet structure of the velvet morphology area 13 is a pyramid structure, the one-dimensional dimension of the velvet structure can refer to the bottom side length, bottom diagonal length, side edge length, or the height of the pyramid structure.

[0070] Exemplarily, when the velvet structure of the velvet morphology area is a pyramid structure, the one-dimensional size of at least one velvet structure can be greater than or equal to 0.1μm and less than or equal to 4μm. For example, the one-dimensional size of the velvet structure can be 0.1μm, 0.5μm, 0.9μm, 1μm, 1.2μm, 1.4μm, 1.5μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 3μm, 3.5μm or 4μm, etc. In this case, the one-dimensional size of the velvet structure is within the above range, which is conducive to preventing the specific surface area of ​​the velvet morphology area from being too small due to the one-dimensional size of the velvet structure being too small, so that the velvet morphology area has a higher light trapping effect. In addition, it can also prevent the velvet morphology area from having a large degree of undulation due to the one-dimensional size of the velvet structure being too large, reduce the difference in deposition quality of the surface passivation layer on different areas of the velvet structure, and improve the passivation effect of the surface passivation layer.

[0071] The suede structures on different portions of the surface of the suede topography region can be roughly the same size. In this case, the suede structures have a high degree of dimensional uniformity, which can improve the deposition quality of the surface passivation layer on the suede topography region. Alternatively, because the one-dimensional size of the suede structure itself matches the wavelength of light it traps, the one-dimensional size of at least some of the suede structures can be different from the one-dimensional size of the remaining suede structures. This helps ensure that the suede topography region has a high light trapping effect for light of different wavelengths, thereby improving the light absorption rate of the semiconductor substrate. The distribution of suede structures of varying one-dimensional size can be determined based on actual needs.

[0072] In actual application, since the height of the patch area is smaller than that of the non-plaque area, the interface between the two areas has a certain angle relative to the surface of the non-plaque area. At this time, by adjusting the inclination angle of the interface between the patch area and the non-plaque area, as well as the height difference between the patch area and the non-plaque area, the relationship between the one-dimensional size of the velvet structure on the interface and the one-dimensional size of the velvet structure on the surface of the rest of the velvet topography area can be regulated. Figure 11 As shown, in the velvet morphology area, the velvet structure located in the patch area is defined as the first velvet structure 16, the velvet structure located at the junction of the patch area and the non-plaque area is defined as the junction velvet structure 17; the velvet structure located in the non-plaque area is the second velvet structure 18. In this case, for example, Figure 11 As shown, in the velvet structure of the velvet morphology area 13 , the one-dimensional size of the boundary velvet structure 17 can be larger than the one-dimensional size of the first velvet structure 16 and the second velvet structure 18 .

[0073] As for the difference in one-dimensional size of the velvet structure on the surface of different areas, it can be determined according to the angle between the interface and the surface of the non-plaque area, the height difference between the patch area and the non-plaque area, and the morphology of the velvet structure, which is not specifically limited here.

[0074] For example, the one-dimensional size of at least one boundary velvet structure may be greater than or equal to 1.8 μm and less than or equal to 2.5 μm. For example, the one-dimensional size of at least one boundary velvet structure may be 1.8 μm, 1.85 μm, 1.9 μm, 2 μm, 2.05 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0075] Exemplarily, a one-dimensional size of at least one of the first velvet structure and / or the second velvet structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm. For example, a one-dimensional size of at least one of the first velvet structure and / or the second velvet structure may be 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.25 μm, 1.3 μm, 1.35 μm, 1.4 μm, 1.45 μm, or 1.5 μm, etc.

[0076] In some cases, such as Figure 11 As shown, when the boundary velvet structure 17 is a pyramid-shaped structure, the length of the side edge of the boundary velvet structure 17 facing the non-plaque area 14 can be smaller than the length of the side edge of the boundary velvet structure 17 facing the plaque area 15. In this case, because the top of the pyramid structure is sharper than its own side surface, compared with setting the junction velvet structure 17 at the junction of the patch area 15 and the non-patch area 14 as a multi-layer pyramid structure with sharp apex angles, when the length of the side edge of the junction velvet structure 17 facing the non-patch area 14 is less than the length of the side edge of the junction velvet structure 17 facing the patch area 14, the number of sharp apex angles at the junction of the patch area 15 and the non-patch area 14 can be reduced, which is beneficial to reducing the degree of undulation at the junction and improving the coating of the surface passivation layer 12 at the junction of the patch area 15 and the non-patch area 14. It solves the problem in the prior art that the surface passivation layer 12 has high requirements on the flatness of the deposition surface when forming the surface passivation layer 12 by atomic layer deposition process and the specific surface area at the junction is too large, resulting in poor deposition uniformity of the surface passivation layer 12 at the junction, and improves the passivation effect of the surface passivation layer 12 at the junction.

[0077] Alternatively, in the pyramid structure located at the junction of the patch area and the non-plaque area, the side edge lengths of different suede structures are roughly the same, and the side surfaces and top of the suede structure at the junction together form the side surfaces of the patch area.

[0078] As for the morphology of the plaque area, for example, Figure 13As shown, the shape of at least one patch area 15 can be a polygon or a long strip. Among them, the polygon can be a quadrilateral, pentagon, hexagon or octagon with regular or irregular shapes. The corners of the polygon can be sharp corners, or they can be chamfered angles with smooth transitions. The long strip can be composed of a plurality of polygons overlapping each other in roughly the same direction. The shape of the long strip can be determined based on the shape, number, and overlap between the different polygons included, and is not specifically limited here. In this case, at least one patch area 15 can present a discretely distributed patch area 15 of a tower base morphology. Alternatively, the shape of at least one patch area 15 can also be a long strip, in which case the patch area 15 presents a patch area 15 composed of a plurality of tower base morphologies overlapping each other in roughly the same direction. It can be seen that the patch area 15 can have a variety of morphologies, which can reduce the manufacturing difficulty; at the same time, different patch areas 15 have different ranges, and the morphology of the patch area 15 can be set according to actual needs, thereby regulating the distribution of the patch areas 15 with smaller heights in the suede morphology area 13. This is beneficial to prevent the suede morphology area 13 and the surface passivation layer 12 included in the semiconductor substrate 11 from being located on the patch area 15. The risk of scratching the suede morphology area 13 and the surface passivation layer 12 included in the semiconductor substrate 11 is greatly reduced under the premise of preventing the suede morphology area 13 and the surface passivation layer 12 included in the semiconductor substrate 11 from contacting the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process, which is beneficial to improving the passivation effect of the surface passivation layer 12 on the semiconductor substrate 11.

[0079] The morphologies of different patch areas can be the same or different. In addition, different patch areas can be randomly distributed in the velvet morphology area; or, as Figure 13 As shown, a plurality of patch areas 15 arranged at intervals along the first direction form a patch column. A plurality of patch columns are provided in the velvet morphology area 13, and different patch columns are spaced apart along the second direction. The second direction intersects with the first direction. In this case, the distribution of different patch areas 15 is relatively regular, which prevents the patch areas 15 in a certain area of ​​the velvet morphology area 13 from being too concentrated, so that the surface of the semiconductor substrate 11 and the surface passivation layer 12 corresponding to this part of the area cannot be located on the inner side of the surface of the area through the non-patch area 14 with a smaller lateral spacing and a larger height, thereby making it difficult to be isolated from the contact surface of the manufacturing equipment and / or transfer equipment through the non-patch area 14 with a larger height during the corresponding manufacturing process, effectively reducing the risk of scratches on the velvet morphology area 13 and the surface passivation layer 12 included in the semiconductor substrate 11. In addition, the distribution of different patch areas 15 is relatively regular, which is also conducive to improving the macroscopic flatness of different areas of the velvet morphology area 13, effectively improving the uniform deposition of the surface passivation layer 12 on the velvet morphology area 13, and improving the passivation effect. In addition, the embodiment of the present invention does not specifically limit the directions indicated by the second direction and the first direction, and can be set according to actual needs. For example, the second direction and the first direction can be perpendicular.

[0080] For example, within the suede morphology region, and within a unit area of ​​300 μm×300 μm, the number of patch regions distributed per unit area may be greater than or equal to 6 and less than or equal to 25. For example, within the suede morphology region, the number of patch regions distributed per unit area may be 6, 8, 10, 12, 15, 18, 20, 22, or 25, etc. In this case, the number of patch areas distributed per unit area is within the above range, which helps prevent the patch areas from being too concentrated in a certain area of ​​the suede morphology area due to the distribution of too many patch areas and / or the patch areas accounting for a large proportion of the area in the suede morphology area, resulting in the suede morphology area and the surface passivation layer corresponding to the surface of the area being difficult to be separated from the contact surface of the manufacturing equipment and / or transfer equipment through the non-patch area with a larger height, thereby reducing the risk of the suede morphology area and the surface passivation layer being scratched; at the same time, it can also reduce the contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment comes into contact at the non-patch area, thereby reducing the risk of the semiconductor substrate and the surface passivation layer corresponding to the non-patch area being scratched. In addition, it can also prevent the area of ​​the surface of the semiconductor substrate and the surface passivation layer that is separated from the contact surface of the manufacturing equipment and / or transfer equipment by the patch area from being small due to the small number of patch areas, thereby reducing the risk of the semiconductor substrate and the surface passivation layer being scratched; at the same time, it can also prevent the degree of flattening of the part of the surface corresponding to the suede morphology area of ​​the semiconductor substrate from being too large due to the high number of patch areas, which is beneficial for the part of the semiconductor substrate corresponding to the suede morphology area to have a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate.

[0081] Illustratively, the one-dimensional size of at least one patch area may be greater than or equal to 15 μm and less than or equal to 50 μm. For example, the one-dimensional size of at least one patch area may be 15 μm, 20 μm, 25 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 42 μm, 45 μm, 48 μm, or 50 μm. In this case, the one-dimensional size of at least one patch area is within the above range, which is beneficial to prevent the one-dimensional size of the patch area from being too small, resulting in the patch area with a smaller height in the velvet morphology area accounting for a smaller area, resulting in the velvet morphology area and the surface passivation layer corresponding to the velvet morphology area having a higher height on one side of the surface. This makes it easier for them to contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process, reducing the risk of scratches on the velvet morphology area and the surface passivation layer included in the semiconductor substrate; and it can also prevent the one-dimensional size of the patch area from being too small, resulting in a smaller degree of flattening of the part of the surface of the semiconductor substrate corresponding to the velvet morphology area before the velvet treatment is performed on the part of the surface of the semiconductor substrate corresponding to the velvet morphology area, which is beneficial to make the part of the surface have a certain macroscopic flatness, so that the size uniformity of the velvet structure obtained after the velvet treatment of this part of the surface is higher, which is beneficial to improving the deposition quality of the surface passivation layer on the velvet morphology area and improving the passivation effect of the surface passivation layer. In addition, it can also prevent the one-dimensional size of the patch area from being too large, resulting in the patch area occupying a large area in the suede morphology area and / or the patch area occupying too large an area in a certain area in the suede morphology area, making it difficult for most of the surfaces of the semiconductor substrate and the surface passivation layer corresponding to the patch area to be isolated from the manufacturing equipment and / or transfer equipment through the non-patch area with a larger height during the corresponding manufacturing process, effectively reducing the risk of scratches on the suede morphology area and the surface passivation layer included in the semiconductor substrate; and because the non-patch area with a larger height is located on the outside, it is easier for it to come into contact with the manufacturing equipment and / or transfer equipment. Therefore, it can also prevent the one-dimensional size of the patch area from being too large, which makes the area of ​​the non-patch area smaller, resulting in a larger contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment comes into contact at the non-patch area, thereby reducing the risk of scratches on the non-patch area corresponding to the semiconductor substrate and the surface passivation layer; at the same time, it can also prevent the one-dimensional size of the patch area from being too large, which makes the degree of flattening of the part of the surface of the semiconductor substrate corresponding to the suede morphology area too large, which is beneficial for the part of the semiconductor substrate corresponding to the suede morphology area to have a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate.

[0082] It should be noted that the one-dimensional size of a patch area can be determined based on its shape. For example, the one-dimensional size of a patch area can be the side length or diagonal length of a polygon. In addition, when at least one patch area is in the shape of a long strip, the one-dimensional size of the patch area can refer to the side lengths at both ends of the strip along the length direction, or it can also refer to the width of the strip. Alternatively, when the strip is composed of multiple polygons overlapping each other in roughly the same direction, the one-dimensional size of the patch area can also be the side length or diagonal length of a single polygon after the strip is disassembled into multiple polygons.

[0083] Exemplarily, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure may be greater than or equal to 4 and less than or equal to 60. For example, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure may be 4, 6, 8, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60. In this case, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure is within the above range, which can prevent the one-dimensional size of the patch area from being too small and / or the one-dimensional size of the velvet structure from being too large due to the ratio being too small. At this time, the size of the velvet structure is relatively small, which can reduce the surface roughness of the velvet morphology area, improve the difference in conformality of the surface passivation layer on the top and base of the velvet structure, and further enhance the passivation effect of the surface passivation layer on the semiconductor substrate. Furthermore, this can prevent the one-dimensional size of the patch region from being too large and / or the one-dimensional size of the suede structure from being too small due to an excessively large ratio, thereby reducing the light reflectivity of the portion corresponding to the suede topography region and increasing the light absorptivity of the semiconductor substrate corresponding to the suede topography region. The beneficial effects of preventing the one-dimensional size of the patch region from being too large or too small can be found in the previous text and will not be elaborated on here.

[0084] As for the surface passivation layer, the embodiment of the present invention does not specifically limit the material and thickness of the surface passivation layer.

[0085] Exemplarily, the surface passivation layer may include at least one of an oxide layer, a nitride layer, an oxynitride layer, and a carbide layer. In this case, the material of the surface passivation layer has a variety of optional examples, which is conducive to improving the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. In addition, the surface passivation layer deposited by atomic layer deposition, such as the aluminum oxide layer or the molybdenum oxide layer, has high requirements on the flatness of the deposited surface. Due to the presence of the patch area, the height consistency of the adjacent velvet structure is higher, and the junction of the patch area and the non-patch area is transitioned through the side of the longer pyramid structure, which reduces the number of sharp corners and reduces the degree of undulation of the surface at the junction, which is conducive to improving the deposition uniformity of the surface passivation layer deposited by atomic layer deposition, such as the aluminum oxide layer or the molybdenum oxide layer, and improving the passivation effect of the surface passivation layer.

[0086] Optionally, the material of the surface passivation layer may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride and molybdenum oxide.

[0087] In addition, the surface passivation layer is in direct contact with the suede morphology area, and there is no other film layer such as a doped semiconductor layer or an intrinsic semiconductor layer between the two. In addition, on the surface of the semiconductor substrate with the suede morphology area, there is no other film layer such as a doped semiconductor layer or an intrinsic passivation layer on the side of the surface passivation layer facing away from the semiconductor substrate; in terms of the battery end, the surface passivation layer is the outermost film layer on the side of the semiconductor substrate with the suede morphology area. Secondly, the surface passivation layer can be located only on the suede morphology area; or, when a doped semiconductor layer is also formed on the surface of the semiconductor substrate with the suede morphology area, the surface passivation layer can also extend to cover the side of the doped semiconductor layer facing away from the semiconductor substrate.

[0088] As for the surface morphology of the area where the doped semiconductor layer is provided on the semiconductor substrate, it can be set according to actual needs. For example, the surface of the area where the doped semiconductor layer is provided on the semiconductor substrate can be a velvet surface to increase the contact area between the doped semiconductor layer and the electrode material and reduce the contact resistance. For example, Figures 1 to 4 ,as well as Figures 6 to 10 As shown, the surface of the semiconductor substrate 11 in the region where the doped semiconductor layer is disposed is a polished region, and the polished region is provided with a tower-shaped structure. This configuration can make the surface of the semiconductor substrate 11 in the region where the doped semiconductor layer 19 is disposed relatively flat, which is beneficial for improving the deposition quality of the doped semiconductor layer 19 on the surface of this region and improving the passivation effect of the doped semiconductor layer.

[0089] For example, when both the polished morphology area and the velvet morphology area are located on the first surface, the one-dimensional size of the tower base structure can be smaller than the one-dimensional size of the patch area. In this case, when the one-dimensional size of the tower base structure is smaller than the one-dimensional size of the patch area, it indicates that after the doped semiconductor layer is formed on a partial area of ​​the semiconductor substrate, and before the partial surface of the semiconductor substrate corresponding to the velvet morphology area is subjected to a velvet treatment, the partial surface of the semiconductor substrate corresponding to the velvet morphology area is further subjected to a flattening treatment, which not only removes the damaged portion of the semiconductor substrate corresponding to the velvet morphology area and reduces the carrier recombination rate, but also helps to improve the dimensional uniformity of the velvet structure after the velvet treatment and improves the deposition uniformity of the surface passivation layer in the velvet morphology area.

[0090] The one-dimensional dimensions of the tower-like structures in the polished topography area, as well as the size difference between the tower-like structures in the polished topography area and the patchy areas in the velvet topography area, can be determined based on the deposition requirements for the doped semiconductor layer, the deposition quality requirements for the surface passivation layer, and the thickness requirements for the corresponding velvet topography area of ​​the semiconductor substrate in the actual application scenario. Furthermore, the size relationship between the one-dimensional dimensions of the different tower-like structures in the polished topography area can be set based on the structure of the doped semiconductor layer and actual needs, and is not specifically limited here.

[0091] In the case where the doped semiconductor layer includes the first doped semiconductor portion and the second doped semiconductor portion, as described above, Figure 10 As shown, in the polished topography region, the surface of the region where the first doped semiconductor portion is provided is defined as the first region 22, and the surface of the region where the second doped semiconductor portion is provided is defined as the second region 23. Based on this, along the direction from the second surface to the first surface, the height of the first region 22 can be greater than or equal to the height of the second region 23. When the height of the first region 22 is greater than the height of the second region 23, the carrier recombination rate at the surface of the second region 23 can be reduced, thereby improving the carrier collection efficiency of the second doped semiconductor portion.

[0092] In addition, illustratively, when the height of the first region is greater than the height of the second region, the one-dimensional size of the tower-shaped structure located in the first region can be smaller than the one-dimensional size of the tower-shaped structure located in the second region. In this case, after forming the first doped semiconductor portion on a portion of the semiconductor substrate, and before forming the second doped semiconductor portion on the portion of the semiconductor substrate corresponding to the second region, further planarizing the portion of the semiconductor substrate corresponding to the second region can not only remove the damaged portion of the semiconductor substrate corresponding to the second region caused by the patterning of the first doped semiconductor portion, thereby reducing the carrier recombination rate, but also help improve the carrier collection efficiency of the second doped semiconductor portion, thereby improving the conversion efficiency of the solar cell.

[0093] Exemplarily, the ratio of the one-dimensional size of the tower-like structure in the second region to the one-dimensional size of the tower-like structure in the first region is greater than 1 and less than or equal to 3. For example, the ratio of the one-dimensional size of the tower-like structure in the second region to the one-dimensional size of the tower-like structure in the first region can be 1.2, 1.5, 1.8, 2, 2.2, 2.5, 2.8, or 3. In this case, the ratio of the one-dimensional size of the tower-like structure in the first region to the one-dimensional size of the tower-like structure in the second region is within the above range. This helps prevent the surface of the portion of the semiconductor substrate corresponding to the second region from being planarized to a low degree, or even not planarized, due to the ratio being too small, thereby reducing the carrier recombination rate in the second region and improving the carrier collection efficiency of the second doped semiconductor portion. It also helps prevent the surface of the portion of the second region from being planarized to an excessive degree due to the ratio being too large, thereby ensuring that the semiconductor substrate has a greater light absorption depth corresponding to the second region and the textured morphology region, thereby improving the light utilization efficiency of the semiconductor substrate.

[0094] In a second aspect, an embodiment of the present invention provides a photovoltaic module comprising: a cell string formed by electrically connecting a plurality of solar cells as provided in the first aspect and various implementations thereof; and an encapsulation layer covering a surface of the cell string.

[0095] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0096] In a third aspect, embodiments of the present invention provide a method for manufacturing a solar cell, comprising: first, providing a semiconductor substrate. Next, sequentially performing a first planarization process and a texturing process on a portion of the surface of the semiconductor substrate to form a textured topography region on the semiconductor substrate; the textured topography region includes a non-patch region and a plurality of patch regions dispersed within the non-patch region; along the thickness direction of the semiconductor substrate, the patch regions are shorter than the non-patch regions. Next, forming a surface passivation layer directly on the textured topography region.

[0097] It should be noted that the structure and materials of the solar cell manufactured by the manufacturing method provided by the embodiment of the present invention can refer to the description of the structure and materials of the solar cell provided in the first aspect above, and will not be repeated here.

[0098] For example, when forming a semiconductor substrate, the process may include: slicing a semiconductor rod using a cutting process (e.g., a diamond wire cutting process) to form a semiconductor substrate; and distributing a plurality of cutting lines on the surface of the semiconductor substrate. In this case, before performing a first planarization and texturing process on a portion of the surface of the semiconductor substrate corresponding to the textured morphology region, the approximate position of a patch region that is recessed into the semiconductor substrate relative to the surface of the non-patch region can be pre-set by forming recessed cutting lines on the surface of the semiconductor substrate. In other words, by adjusting parameters such as the recessed depth and length of the cutting lines during the formation of the semiconductor substrate, the spacing between adjacent cutting lines, and the processing parameters of the first planarization and texturing process performed after the formation of the semiconductor substrate, it is easy to form a patch region at the position of the cutting lines after the first planarization and texturing process, thereby improving the dimensional uniformity of the textured structure while reducing the difficulty of manufacturing the solar cell.

[0099] In an actual manufacturing process, the semiconductor substrate can be defined as comprising a first surface and a second surface that are opposite to each other. For example, the textured topography region is located at least on the first surface of the semiconductor substrate; and after providing the semiconductor substrate, the solar cell manufacturing method further includes: forming a doped semiconductor layer on the second surface and / or on a surface of an area of ​​the first surface excluding the textured topography region. Based on this, the manufacturing sequence and manufacturing process of the textured topography region can be determined based on the type of solar cell and the formation range of the textured topography region and the doped semiconductor layer on the semiconductor substrate.

[0100] For example, if the solar cell being manufactured is a double-sided contact cell, a doped semiconductor layer can be formed entirely on the first side of the semiconductor substrate using deposition and doping processes. Subsequently, the doped semiconductor layer can be patterned using processes such as laser etching and / or wet etching, under the protection of a corresponding mask. Subsequently, a first planarization process and a texturing process are sequentially performed on the first side of the semiconductor substrate using processes such as wet etching, under the protection of a corresponding mask, to obtain a textured morphology region. On the second side of the semiconductor substrate, another doped semiconductor layer can be provided entirely (in this case, the other doped semiconductor layer can be formed using deposition and doping processes), or the other doped semiconductor layer can be provided on a localized area of ​​the second side (the formation process of the other doped semiconductor layer can refer to the fabrication process of the doped semiconductor layer on the first side; if the second side also includes a textured morphology region, after forming the other doped semiconductor layer, a first planarization process and a texturing process are performed on the surface of the second side exposed outside the other doped semiconductor layer using processes such as wet etching, under the protection of a corresponding mask, to obtain a textured morphology region).

[0101] For another example: in the case where the solar cell being manufactured is a back-contact cell, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion spaced apart in a direction parallel to the back of the solar cell. Based on this, the first doped semiconductor portion and the second doped semiconductor portion can be respectively formed on the side of the semiconductor substrate corresponding to the back of the cell in accordance with the aforementioned method of forming the doped semiconductor layer on a local area of ​​the first side of the semiconductor substrate. Then, according to the formation range of the velvet morphology region on the semiconductor substrate, a wet etching process or the like is used to perform a first flattening treatment and a texturing treatment only on the side of the semiconductor substrate corresponding to the front of the cell, or only on the surface of the region between the first doped semiconductor portion and the second doped semiconductor portion on the side of the semiconductor substrate corresponding to the back of the cell, or both on the side of the semiconductor substrate corresponding to the front of the cell and on the surface of the region between the first doped semiconductor portion and the second doped semiconductor portion on the side of the semiconductor substrate corresponding to the back of the cell, to obtain a velvet morphology region.

[0102] Next, after the textured morphology region is formed, an atomic layer deposition process may be used to form a surface passivation layer on the textured morphology region.

[0103] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0104] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0105] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, comprising a suede morphology region; the suede morphology region is densely covered with suede structures; A surface passivation layer is directly disposed on the suede topography area; The textured morphology area includes a non-patch area and a plurality of patch areas dispersed in the non-patch area; along the thickness direction of the semiconductor substrate, the height of the patch area is smaller than the height of the non-patch area.

2. The solar cell according to claim 1, wherein At least one of the patch areas is in the shape of a polygon or a long strip.

3. The solar cell according to claim 1, wherein A plurality of the patch areas spaced apart along the first direction form a patch column; a plurality of the patch columns are arranged in the velvet morphology area, and the patch columns in different columns are spaced apart along the second direction; the second direction intersects the first direction.

4. The solar cell according to claim 1, wherein A one-dimensional size of at least one of the patch regions is greater than or equal to 15 μm and less than or equal to 50 μm; And / or, the ratio of the one-dimensional size of the patch area to the one-dimensional size of the velvet structure is greater than or equal to 4 and less than or equal to 60; And / or, within the suede morphology area, and in a unit area of ​​300 μm×300 μm, the number of the patch areas distributed is greater than or equal to 6 and less than or equal to 25.

5. The solar cell according to claim 1, wherein The velvet structure is a pyramid structure; And / or, at least one one-dimensional size of the textured structure is greater than or equal to 0.1 μm and less than or equal to 4 μm.

6. The solar cell according to claim 1, wherein A height difference between at least one of the patch areas and the non-plaque area is less than 4 μm.

7. The solar cell according to claim 1, wherein In the velvet morphology area, the velvet structure located in the patch area is defined as a first velvet structure, the velvet structure located at the junction of the patch area and the non-plaque area is defined as a junction velvet structure; the velvet structure located in the non-plaque area is defined as a second velvet structure; Wherein, a one-dimensional dimension of at least one of the boundary velvet structures is larger than a one-dimensional dimension of the first velvet structure and the second velvet structure; And / or, a one-dimensional size of at least one of the boundary texture structures is greater than or equal to 1.8 μm and less than or equal to 2.5 μm; And / or, a one-dimensional size of at least one of the first textured structure and / or the second textured structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm.

8. The solar cell according to claim 1, wherein In the velvet morphology area, the velvet structure located at the junction of the patch area and the non-plaque area is defined as a junction velvet structure; The junction velvet structure is a pyramid-shaped structure, and the length of the side edge of the junction velvet structure facing the non-plaque area is shorter than the length of the side edge of the junction velvet structure facing the plaque area.

9. The solar cell according to any one of claims 1 to 8, characterized in that: The surface passivation layer includes at least one of an oxide layer, a nitride layer, an oxynitride layer, and a carbide layer.

10. The solar cell according to any one of claims 1 to 8, characterized in that The semiconductor substrate comprises a first surface and a second surface opposite to each other; the textured topography region is at least located on the first surface; The solar cell further includes a doped semiconductor layer; the doped semiconductor layer is arranged on the surface of a region of the first surface excluding the textured morphology region, and / or the doped semiconductor layer is arranged on the second surface.

11. The solar cell according to claim 10, characterized in that The surface of the semiconductor substrate where the doped semiconductor layer is provided is a polished morphology area, and the polished morphology area is provided with a tower base structure; When the polishing morphology area and the velvet morphology area are both located on the first surface, the one-dimensional size of the tower base-shaped structure is smaller than the one-dimensional size of the patch area.

12. The solar cell according to claim 11, characterized in that The doped semiconductor layer includes first doped semiconductor portions and second doped semiconductor portions that are alternately distributed along a plane parallel to the first surface and have opposite doping types; In the polishing topography region, the surface of the region where the first doped semiconductor portion is provided is a first region, and the surface of the region where the second doped semiconductor portion is provided is a second region; along the direction from the second surface to the first surface, the height of the first region is greater than the height of the second region; wherein one dimension of the tower base-shaped structure located in the first area is smaller than one dimension of the tower base-shaped structure located in the second area; And / or, a ratio of a one-dimensional dimension of the tower base-like structure located in the second area to a one-dimensional dimension of the tower base-like structure located in the first area is greater than 1 and less than or equal to 3.

13. The solar cell according to claim 10, characterized in that The solar cell is a back contact cell; the textured morphology region is located on a partial area of ​​the first surface and the second surface of the semiconductor substrate; The doped semiconductor layer includes first doped semiconductor portions and second doped semiconductor portions that are alternately distributed parallel to a first surface and have opposite doping types; the suede topography region located on the first surface is arranged between the first doped semiconductor portion and the second doped semiconductor portion.

14. A photovoltaic module, characterized in that: include: A battery string, wherein the battery string is formed by electrically connecting a plurality of solar cells according to any one of claims 1 to 13; and an encapsulation layer covering a surface of the battery string.

15. A method for manufacturing a solar cell, characterized in that: include: providing a semiconductor substrate; A first planarization process and a texturing process are sequentially performed on a portion of the surface of the semiconductor substrate to form a textured morphology region on the semiconductor substrate; the textured morphology region includes a non-patch region and a plurality of patch regions dispersed within the non-patch region; along the thickness direction of the semiconductor substrate, the height of the patch region is smaller than the height of the non-patch region; A surface passivation layer is formed directly on the textured topography area.

16. The method for manufacturing a solar cell according to claim 15, wherein: The surface passivation layer is formed on the textured morphology area by at least an atomic layer deposition process.

17. The method for manufacturing a solar cell according to claim 15, wherein: The semiconductor substrate comprises a first surface and a second surface opposite to each other; the textured topography region is at least located on the first surface; After providing the semiconductor substrate, the method for manufacturing a solar cell further includes: forming a doped semiconductor layer on the second surface and / or on the surface of a region of the first surface excluding the textured morphology region.

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