Memory system, memory controller, garbage collection method, and storage medium

Abstract

The embodiment of the invention provides a memory system, a memory controller, a garbage collection method and a storage medium. The method comprises the following steps: acquiring a first bitmap corresponding to a first source data block to an Nth bitmap corresponding to an Nth source data block; n is an integer greater than or equal to 2; obtaining a combined bitmap based on the first bitmap to the Nth bitmap; reading a page table item table according to the combined bitmap; and writing the effective data corresponding to the first source data block to the Nth source data block in the page table entry table into the target data block. According to the garbage collection method, garbage collection operation can be performed on a plurality of source data blocks. And merging the bitmaps corresponding to the plurality of source data blocks to obtain a merged bitmap. And the corresponding page table item table is read through the merged bitmap, so that response delay caused by repeatedly reading the page table item table among the source data blocks is avoided, and the processing efficiency of the whole garbage collection process is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory system, a storage controller, a garbage collection method, a computer program product, and a storage medium. Background Art

[0002] In memory technology, garbage collection (GC) is a fundamental function of many storage products, such as solid-state drives (SSDs) and embedded storage devices. Its primary purpose is to move valid data from a source data block to a target data block, allowing the source data block to be reused. However, there is room for further improvement in the efficiency of GC. Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory system, a storage controller, a garbage collection method, a computer program product, and a storage medium.

[0004] According to one aspect of an embodiment of the present disclosure, a memory system is provided, comprising: a storage device; and a storage controller coupled to the storage device, wherein the storage controller is configured to: obtain a first bitmap corresponding to a first source data block to an Nth bitmap corresponding to an Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier of a page table entry table pointing to the corresponding data block; based on the first bitmap to the Nth bitmap, a merged bitmap is obtained; the page table entry table is read according to the merged bitmap; and valid data in the page table entry table corresponding to the first source data block to the Nth source data block is written into a target data block.

[0005] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: search for valid data in the page table entry table whose physical addresses are located between the first source data block and the Nth source data block; and write the valid data corresponding to the physical addresses in the page table entry table that are located between the first source data block and the Nth source data block into the target data block.

[0006] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: update a logical address to physical address mapping table in response to the valid data being written into the target data block; and release the first source data block to the Nth source data block.

[0007] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: perform an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

[0008] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: match the data block bits of the physical address corresponding to the valid data in the page table entry table with the data block index values ​​of the first source data block to the Nth source data block, respectively, to determine the valid data located from the first source data block to the Nth source data block.

[0009] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: obtain valid page counts of multiple data blocks; and select the first source data block to the Nth source data block according to the valid page counts of the multiple data blocks.

[0010] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: obtain the effective capacity of the target data block; and select the first source data block to the Nth source data block based on the effective page counts of the multiple data blocks and the effective capacity of the target data block.

[0011] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: select multiple first data blocks; accumulate valid page counts of the multiple first data blocks; in response to the accumulated value of the valid page count being not greater than the effective capacity of the target data block, the accumulated first data blocks are selected as the first source data block to the Nth source data block.

[0012] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: select a plurality of first data blocks, including selecting a preset number of first data blocks.

[0013] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: in response to the target data block being not full, obtain the N+1th source data block; read the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; and write at least part of the valid data corresponding to the N+1th source data block in the page table entry table into the target data block until the target data block is full.

[0014] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: in response to the target data block being not full, write dummy data to the target data block until the target data block is full.

[0015] In some exemplary embodiments of the present disclosure, the storage controller is further configured to: determine the valid data ratio of each data block in the multiple data blocks based on the valid page count; and select the first source data block to the Nth source data block from the multiple data blocks whose valid data ratio is lower than a preset threshold.

[0016] According to another aspect of an embodiment of the present disclosure, a storage controller is provided, comprising: a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform processing, wherein the processing comprises: obtaining a first bitmap corresponding to a first source data block to an Nth bitmap corresponding to an Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier of a page table entry table pointing to the corresponding data block; based on the first bitmap to the Nth bitmap, a merged bitmap is obtained; the page table entry table is read according to the merged bitmap; and valid data in the page table entry table corresponding to the first source data block to the Nth source data block is written into a target data block.

[0017] In some exemplary embodiments of the present disclosure, the processing also includes: searching for valid data in the page table entry table whose physical addresses are located between the first source data block and the Nth source data block; and writing the valid data corresponding to the physical addresses in the page table entry table that are located between the first source data block and the Nth source data block into the target data block.

[0018] In some exemplary embodiments of the present disclosure, the processing further includes: updating a logical address to physical address mapping table in response to the valid data being written into the target data block; and releasing the first source data block to the Nth source data block.

[0019] In some exemplary embodiments of the present disclosure, the processing further includes: performing an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

[0020] In some exemplary embodiments of the present disclosure, the processing also includes: matching the data block bits of the physical address corresponding to the valid data in the page table entry table with the data block index values ​​of the first source data block to the Nth source data block, respectively, to determine the valid data located from the first source data block to the Nth source data block.

[0021] In some exemplary embodiments of the present disclosure, the processing further includes: obtaining valid page counts of multiple data blocks; and selecting the first source data block to the Nth source data block according to the valid page counts of the multiple data blocks.

[0022] In some exemplary embodiments of the present disclosure, the processing further includes: obtaining the effective capacity of the target data block; and selecting the first source data block to the Nth source data block based on the effective page counts of the multiple data blocks and the effective capacity of the target data block.

[0023] In some exemplary embodiments of the present disclosure, the processing also includes: selecting multiple first data blocks; accumulating valid page counts of the multiple first data blocks; in response to the accumulated value of the valid page count being not greater than the effective capacity of the target data block, the accumulated first data blocks are selected as the first source data block to the Nth source data block.

[0024] In some exemplary embodiments of the present disclosure, the processing further includes: the selecting of multiple first data blocks includes selecting a preset number of first data blocks.

[0025] In some exemplary embodiments of the present disclosure, the processing also includes: in response to the target data block being not full, obtaining the N+1th source data block; reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; and writing at least part of the valid data corresponding to the N+1th source data block in the page table entry table into the target data block until the target data block is full.

[0026] In some exemplary embodiments of the present disclosure, the processing further includes: in response to the target data block being not full, writing dummy data into the target data block until the target data block is full.

[0027] In some exemplary embodiments of the present disclosure, the processing also includes: determining the valid data ratio of each data block in the multiple data blocks based on the valid page count; and selecting the first source data block to the Nth source data block from the multiple data blocks whose valid data ratio is lower than a preset threshold.

[0028] According to another aspect of the embodiments of the present disclosure, a garbage collection method is provided, including: obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier of a page table entry table pointing to the corresponding data block; based on the first bitmap to the Nth bitmap, a merged bitmap is obtained; the page table entry table is read according to the merged bitmap; and valid data in the page table entry table corresponding to the first source data block to the Nth source data block is written into a target data block.

[0029] In some exemplary embodiments of the present disclosure, writing the valid data corresponding to the first source data block to the Nth source data block in the page table entry table into the target data block includes: searching the page table entry table for valid data whose physical addresses are located from the first source data block to the Nth source data block; and writing the valid data located from the first source data block to the Nth source data block into the target data block.

[0030] In some exemplary embodiments of the present disclosure, the method further includes: writing the target data block according to the valid data, updating the logical address to physical address mapping table; and releasing the first source data block to the Nth source data block.

[0031] In some exemplary embodiments of the present disclosure, obtaining a merged bitmap based on the first bitmap to the Nth bitmap includes: performing an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

[0032] In some exemplary embodiments of the present disclosure, searching for valid data whose physical addresses in the page table entry table are located from the first source data block to the Nth source data block includes: matching the data block bits of the physical addresses corresponding to the valid data in the page table entry table with the data block index values ​​of the first source data block to the Nth source data block, respectively, to determine the valid data located from the first source data block to the Nth source data block.

[0033] In some exemplary embodiments of the present disclosure, the method further includes: acquiring valid page counts of a plurality of data blocks; and selecting the first source data block to the Nth source data block according to the valid page counts of the plurality of data blocks.

[0034] In some exemplary embodiments of the present disclosure, selecting the first source data block to the Nth source data block based on the valid page counts of the multiple data blocks includes: obtaining the valid capacity of the target data block; and selecting the first source data block to the Nth source data block based on the valid page counts of the multiple data blocks and the valid capacity of the target data block.

[0035] In some exemplary embodiments of the present disclosure, selecting the first source data block to the Nth source data block based on the valid page counts of the multiple data blocks and the valid capacity of the target data block includes: selecting multiple first data blocks; accumulating the valid page counts of the multiple first data blocks; in response to the accumulated value of the valid page count being not greater than the valid capacity of the target data block, the accumulated first data blocks are selected as the first source data block to the Nth source data block.

[0036] In some exemplary embodiments of the present disclosure, the selecting of the plurality of first data blocks includes: the selecting of the plurality of first data blocks is selecting a preset number of first data blocks.

[0037] In some exemplary embodiments of the present disclosure, the method further includes: in response to the target data block being not full, obtaining the N+1th source data block; reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; and writing at least part of the valid data corresponding to the N+1th source data block in the page table entry table into the target data block until the target data block is full.

[0038] In some exemplary embodiments of the present disclosure, the method further includes: in response to the target data block being not full, writing dummy data into the target data block until the target data block is full.

[0039] In some exemplary embodiments of the present disclosure, selecting the first source data block to the Nth source data block based on the valid page counts of the multiple data blocks includes: determining the valid data ratio of each data block in the multiple data blocks based on the valid page counts; and selecting the first source data block to the Nth source data block from the multiple data blocks whose valid data ratio is lower than a preset threshold.

[0040] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided. When control instructions in the computer-readable storage medium are executed by a controller processor, the controller processor is enabled to execute any one of the memory garbage collection methods described above.

[0041] According to another aspect of the embodiments of the present disclosure, a computer program product is provided, including a computer program / instruction, which implements the garbage collection method mentioned in any of the above embodiments when executed by a processor.

[0042] The memory system, storage controller and garbage collection method provided by the embodiments of the present disclosure perform garbage collection operations on multiple source data blocks by merging the bitmaps corresponding to the multiple source data blocks to obtain a merged bitmap, and then reading the corresponding page table entry table based on the merged bitmap, thereby avoiding the response delay caused by repeated reading of the page table entry table between the various source data blocks, and improving the processing efficiency of the overall garbage collection process.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] Figure 1A A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure is provided;

[0046] Figure 1B A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0047] Figure 1C A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2 A schematic diagram of an exemplary memory controller having a memory system according to an embodiment of the present disclosure is provided;

[0049] Figure 3 A flowchart of a memory garbage collection method according to an embodiment of the present disclosure is shown;

[0050] Figure 4 A schematic diagram of the structure of a memory effective data address mapping table according to an embodiment of the present disclosure;

[0051] Figure 5 A schematic diagram of a memory garbage collection process according to an embodiment of the present disclosure;

[0052] Figure 6 Schematic diagram 1 of a flow chart of a memory garbage collection method according to an embodiment of the present disclosure;

[0053] Figure 7 A schematic diagram of a flow chart of valid data address matching according to an embodiment of the present disclosure;

[0054] Figure 8 Schematic diagram 1 of a process for selecting a source data block according to an embodiment of the present disclosure;

[0055] Figure 9 Schematic diagram of the process of selecting source data blocks according to an embodiment of the present disclosure Figure 2 ;

[0056] Figure 10 Schematic diagram 1 of a process for effective data migration according to an embodiment of the present disclosure;

[0057] Figure 11 A schematic diagram of an effective data migration process according to an embodiment of the present disclosure;

[0058] Figure 12 Schematic diagram of the process of effective data migration according to an embodiment of the present disclosure Figure 2 ;and

[0059] Figure 13 Schematic diagram of the process of selecting source data blocks according to an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0061] The features, structures or characteristics described in the present disclosure may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0062] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in at least one hardware module or integrated circuit, or in different networks and / or processor devices and / or microcontroller devices.

[0063] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all content and steps, nor must they be executed in the order described. For example, some steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0064] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of at least one element / component / etc.; the terms "comprising", "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0065] One implementation of garbage collection is to move data block by block, moving one block at a time. This approach requires multiple reads of the data mapping table, which consumes considerable time. Garbage collection typically involves processing multiple blocks, making it inefficient.

[0066] Figure 1A 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. System 100 may be a mobile phone, a desktop computer, a portable computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1A As shown in , system 100 may include a host 108 and a memory system 102 having one or more storage devices 104 and a storage controller 106 .

[0067] The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be coupled to the memory controller 106 and configured to send data to or receive data from the memory device 104 through the memory controller 106. For example, the host 108 may send program data in a programming operation or receive read data in a read operation. The host 108 is configured to receive instructions and commands from and send instructions and commands to the memory controller 106 of the memory system 102, and to perform or implement a plurality of functions and operations provided in the present disclosure, which will be described below.

[0068] The storage device 104 may be any storage device disclosed in the present disclosure, for example, a NAND flash memory device including a page buffer having multiple sections. Note that for illustrative purposes, NAND flash memory is only one example of a storage device. The storage device 104 may include any suitable solid-state non-volatile memory, for example, NOR flash memory, ferroelectric random access memory (FeRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), spin-transfer torque random access memory (STT-RAM), or resistive random access memory (RRAM). In some implementations, the storage device 104 includes a three-dimensional (3D) NAND flash memory.

[0069] The storage controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gating logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0070] According to some implementations, the storage controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The storage controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some implementations, the storage controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the storage controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded MultiMedia Card (eMMC) used as a data storage device for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The storage controller 106 can be configured to control the operations of the storage device 104, such as read, erase, and program operations, by providing instructions, such as read instructions, to the storage device 104. For example, the storage controller 106 can be configured to provide read instructions to the peripheral circuits of the storage device 104 to control read operations. The storage controller 106 can also be configured to manage various functions related to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection (GC), logical to physical address translation, wear leveling, etc. In some implementations, the storage controller 106 is also configured to process error correction codes (ECC) on data read from or written to the storage device 104. The storage controller 106 can also perform any other suitable functions, such as formatting the storage device 104.

[0071] The storage controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the storage controller 106 can communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC (Multi Media Card) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Drive Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, and the like.

[0072] The storage controller 106 and the one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0073] In such Figure 1B In one example shown in FIG, the storage controller 106 and the storage device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA (Personal Computer Memory Card International Association) card), a CF card, a Smart Media (SM) card, a memory stick, a MultiMediaCard (MMC), an SD card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card to a host (e.g., the host 108 in FIG. 1 ).

[0074] In such Figure 1CIn another example shown in FIG, the storage controller 106 and the plurality of storage devices 104 can be integrated into a solid-state drive 206. The solid-state drive 206 can also include a solid-state drive connector 208 that couples the solid-state drive 206 to a host (e.g., the host 108 in FIG. 1 ). In some implementations, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0075] Figure 2 FIG. 1 is a schematic diagram of an exemplary memory controller having a memory system according to an embodiment of the present disclosure. Figure 2 As shown, the storage controller 106 is coupled to the host 108 and one or more storage devices 104, respectively, and is used to control the host 108 to send data to the storage device 104 or read data from the storage device 104 and return it to the host 108. The storage controller 106 includes at least: a controller processor 210, a host interface controller 211, a storage device interface controller 212, a controller memory 213, a hardware accelerator 214, and a buffer memory 215.

[0076] The controller processor 210 is the core of the storage controller, used to execute the control logic and algorithms of the storage controller, and is responsible for processing functions such as command queue, address mapping, garbage collection, data compression, input and output control, etc. The controller processor 210 can be implemented by an embedded processor or FPGA.

[0077] The host interface controller 211, coupled to the host 108 and the controller processor 210, is the communication interface component between the host and the storage controller. It is responsible for data transmission between the host and the storage controller, including reading and writing data, and receiving and sending commands. It generally supports various interfaces (such as SATA (Serial Advanced Technology Attachment) and PCIe) and protocols (such as AHCI (Advanced Host Controller Interface) and NVMe (Non-Volatile Memory Express)) and provides data transmission functions.

[0078] The storage device interface controller 212 is coupled to the storage device 104 and the controller processor 210 respectively, and is a communication interface component between the storage device and the storage controller, responsible for implementing functions such as data reading, writing, erasing, and address mapping.

[0079] The controller memory 213 is coupled to the controller processor 210 and is a storage area for storing controller instructions and data, providing fast read and write operations and real-time control functions. The controller memory is usually a storage medium such as NOR flash, NAND flash or RAM.

[0080] The hardware accelerator 214, coupled to the controller processor 210, is a component that optimizes specific operations. It uses hardware logic to optimize the performance of specific operations, thereby improving the performance and data security of the storage device. For example, the hardware accelerator may be used to handle tasks such as encryption, decryption, compression, decompression, and error correction codecs. It can also be used to improve operations such as data searching and sorting.

[0081] Buffer memory 215, coupled to controller processor 210, is used to temporarily store data and can also cache instructions and data. It typically uses high-speed storage devices such as DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) to improve the read and write performance of the storage controller and reduce latency.

[0082] The storage controller 106 is configured to receive commands from and send commands to the host 108 , and to perform or implement a number of functions and operations provided in the present disclosure, which will be described below.

[0083] Figure 3 FIG. 1 is a flow chart of a garbage collection method according to an embodiment of the present disclosure. Figure 3 As shown, the garbage collection method provided in the embodiment of the present disclosure can be applied to Figure 2 The storage controller is shown.

[0084] The garbage collection method of an embodiment of the present disclosure may include S310, in which the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block are obtained; N is an integer greater than or equal to 2; the bitmap records an identifier of a page table entry (PTE) table pointing to the corresponding data block.

[0085] In the disclosed embodiment, the garbage collection process involves copying valid data stored in a data block to be recycled to other data blocks, and then performing garbage collection on the data block to be recycled so that it can be reused. In the garbage collection process, the data block to be recycled is the source data block, and the data block to which its valid data is copied is the target data block. Valid data

[0086] In some embodiments, an important function of the storage controller 106 includes completing the conversion of the logical address space of the host 108 (e.g., the logical block address, LBA) to the physical address space of the storage device 104 (e.g., the physical cluster address, PCA). When the storage controller 106 writes a piece of user data to the storage device 104, the storage controller 106 calculates the logical block address LBA involved in the write request sent by the host 108, obtains the corresponding logical cluster address (LCA), and then allocates a physical address space such as the physical cluster address PCA for the user data, stores the user data in the corresponding physical cluster address PCA, and records the mapping of the logical cluster address LCA of the user data to the physical cluster address PCA, that is, the mapping relationship between the logical cluster address and the physical cluster address. When the host 108 reads the data, the memory system 102 reads the data from the storage device 104 according to this mapping relationship and returns it to the host 108.

[0087] When managing the physical storage space of the storage device 104, the storage controller 106 may evenly divide the entire physical storage space of the storage device 104 into multiple logical storage spaces for overlay representation. The multiple logical storage spaces may cover the entire physical storage space of the storage device 104. Each logical storage space has a corresponding logical cluster address (LCA). In some embodiments, each logical storage space may correspond to a 4K storage space.

[0088] The storage controller 106 can maintain a logical-to-physical mapping table (L2P mapping table) to convert the logical block address identified by the host 108 to the physical cluster address of the storage device, wherein the L2P mapping table includes all the mapping relationships between the logical cluster address and the physical cluster address. Figure 4 As shown, the logical cluster address can be mapped to the physical cluster address PCA of the storage device 104 in combination with the L2P mapping table. In order to shorten the host's read latency, the L2P mapping table is preferably placed in the memory of the storage controller (e.g. Figure 2The memory of the storage controller or the cache communicating with the memory controller may include a volatile memory device, such as, but not limited to, a static random access memory (SRAM) and a dynamic random access memory (DRAM).

[0089] Several schemes can be used to store and maintain the L2P mapping table. One scheme is a single-level direct L2P mapping scheme, which can contain mapping information for data in the entire storage device. Therefore, the single-level direct page mapping scheme requires a large amount of storage space (on the order of 1-2MB of L2P mapping table for 1GB of data) to store the L2P mapping table, which is challenging for large-capacity storage devices, especially for DRAM-less memory systems, such as DRAM-less SSDs. The mapping table corresponding to the single-level direct L2P mapping scheme can be called a Page Table Entry (PTE) table, which stores the physical address of the data (for example, the physical cluster address PCA).

[0090] Another solution for storing and maintaining the L2P mapping table is a multi-level mapping solution. Here, a three-level mapping solution is used as an example. Figure 4 As shown, the first-level mapping table can be called a page global directory or page directory (PGD) table, which stores the physical address of the second-level mapping table (e.g., physical cluster address PCA), and each mapping in the first-level mapping table points to a second-level mapping table; the second-level mapping table can be called a page middle directory (PMD) table, which stores the physical address of the third-level mapping table (e.g., physical cluster address PCA), and each mapping in the second-level mapping table points to a third-level mapping table; the third-level mapping table page can be called a page table entry (PTE) table, which stores the physical address of the data (e.g., physical cluster address PCA). It should be clear that no matter how many levels of mapping scheme are used, the last-level mapping table can be used as a page table entry (PTE) table, which stores the physical address of the data (e.g., physical cluster address PCA).

[0091] The storage controller 106 divides the entire physical storage space of the storage device 104 into multiple logical storage spaces for overlay expression, and allocates a logical cluster address LCA to each logical storage space. The storage controller 106 may number the multiple logical cluster addresses LCA starting from 0 (LCA0) and sort them starting from LCA0 in the page table entry table. Each logical cluster address LCA has a fixed position in the page table entry table. For example, see Figure 4 Each page table entry table includes 1024 entries, each entry can include a physical cluster address PCA mapped to the logical cluster address LCA, and corresponds to 4K of storage space, so each page table entry table can correspond to 4M of user data.

[0092] In the multi-level mapping scheme, the first-level mapping table can be stored in the memory of the storage controller 106, that is, the first-level mapping table resides in the memory of the storage controller 106, and some mapping tables of other levels are stored in the memory of the storage controller 106. When the L2P mapping relationship corresponding to the logical block address involved in the host's read request is not in the memory of the storage controller 106, the storage controller needs to first read the corresponding L2P mapping relationship from the storage device 104 to the memory of the storage controller 106, and then execute the read operation corresponding to the host's read request.

[0093] In an exemplary embodiment, as Figure 4 As shown, PMD index0 in PGD table 410 is mapped to a PMD table 420. The PMD table 420 contains PTE index0 to PTE index1023. And PTE index0 in the PMD table 420 is mapped to a PTE table 430. The PTE table 430 contains logical cluster addresses LCA0 to LCA1023. As shown in the figure, the physical cluster address PCA corresponding to LCA0 points to data in a physical space in data block 1, the physical cluster address PCA corresponding to LCA1 points to data in a physical space in data block 2, and the physical cluster address PCA corresponding to LCA1023 points to data in a physical space in data block N. In the storage system, each data block corresponds to a bitmap. A bitmap is a data structure, which is usually composed of consecutive binary bits, each bit representing a specific state or referring to some information. Each bit in the bitmap can take the value 0 or 1, corresponding to a PTE table. For example, when a bit in the bitmap is set to 0, it indicates that there is no L2P mapping relationship pointing to the valid data in the data block in the corresponding PTE table; when a bit in the bitmap is set to 1, it indicates that there is an L2P mapping relationship pointing to the valid data in the data block in the corresponding PTE table.

[0094] During the garbage collection process, valid data in the source data block is moved to the target data block to perform garbage collection on the source data block. Therefore, in S310, the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block are obtained, where N is an integer greater than or equal to 2. Each bitmap contains the PTE table containing the L2P mapping relationship corresponding to the valid data in the corresponding data block.

[0095] For example, during the garbage collection process, six source data blocks are selected for garbage collection, that is, N=6. The six source data blocks are respectively the first source data block, the second source data block, the third source data block, the fourth source data block, the fifth source data block, and the sixth source data block. As mentioned above, each data block corresponds to a bitmap. The above six source data blocks correspond to the first bitmap, the second bitmap, the third bitmap, the fourth bitmap, the fifth bitmap, and the sixth bitmap, respectively. It should be noted that the above N is used to represent the number of selected source data blocks. Among them, "first", "second", "third" ... "Nth", etc. are only used as labels to distinguish different source data blocks and bitmaps, and do not constitute a restriction on their number or order.

[0096] In an exemplary embodiment, as Figure 5 As shown, each data block corresponds to a bitmap, and each bit in the bitmap corresponds to a different PTE table from left to right: PTE0, PTE1, PTE2, ..., and PTE N. As shown in the figure, Bitmap1 corresponding to source data block 1 is "000001000000000001...", indicating that PTE5 and PTE17 have an L2P mapping relationship corresponding to the valid data of source data block 1; Bitmap2 corresponding to source data block 2 is "00010000000000001...", indicating that PTE3 and PTE17 have an L2P mapping relationship corresponding to the valid data of source data block 2; Bitmap N corresponding to source data block N is "000100000010000000...", indicating that PTE3 and PTE10 have an L2P mapping relationship corresponding to the valid data of source data block N.

[0097] In an exemplary embodiment, the bitmaps corresponding to the acquired source data blocks may be temporarily stored in a buffer memory of the storage controller.

[0098] Continue to see Figure 3 The garbage collection method of an embodiment of the present disclosure may include S320. In S320, a merge bitmap (Merge Bitmap) is obtained based on the first bitmap to the Nth bitmap.

[0099] After obtaining the bitmap corresponding to the source data block, the corresponding PTE table can be read according to the identification bit of the bitmap. For example, valid data can be moved one by one according to the identification bit of the bitmap of each source data block, and the possibility of repeatedly reading the same PTE table increases. For example, see Figure 5 When moving valid data of source data block 1, PTE17 needs to be read. When moving valid data of source data block 2, PTE17 needs to be read again, resulting in a high overall response delay.

[0100] In the disclosed embodiment, in S310, the first through Nth bitmaps corresponding to the first through Nth source data blocks are obtained, respectively. The first through Nth bitmaps are then merged to obtain a merged bitmap. The merging of the multiple bitmaps involves performing an OR operation on corresponding bits of the multiple bitmaps to obtain the merged bitmap.

[0101] In an exemplary embodiment, as Figure 5 As shown in the figure, Bitmap1 corresponding to source data block 1 is "000001000000000001...", Bitmap2 corresponding to source data block 2 is "00010000000000001...", and Bitmap N corresponding to source data block N is "000100000010000000...". Therefore, the merged bitmap (MergeBitmap) is obtained based on the following calculation:

[0102] Merge Bitmap=Bitmap1|Bitmap2|……|Bitmap N=000101000010000001...

[0103] In an exemplary embodiment, the controller processor reads the acquired bitmaps from the buffer memory, performs the merging process of S320 on the bitmaps in the controller processor, and temporarily stores the obtained merged bitmap in the buffer memory of the storage controller.

[0104] In step S330, the page table entry table is read according to the merge bitmap.

[0105] In the embodiment of the present disclosure, the corresponding PTE table is read according to each identification bit in the merge bitmap.

[0106] In an exemplary embodiment, as Figure 5As shown in the figure, the merged bitmap obtained based on the above merge calculation is "000101000010000001...", which corresponds to PTE3, PTE5, PTE10, and PTE17. Based on this merged bitmap, the corresponding PTE3, PTE5, PTE10, and PTE17 are read. It can be seen that reading the PTE table based on this merged bitmap can avoid repeatedly reading PTE17 based on Bitmap1 and Bitmap2, and also avoid repeatedly reading PTE3 based on Bitmap2 and BitmapN, saving the response time cost consumed by repeatedly reading the relevant PTE tables.

[0107] In step S340 , valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into a target data block.

[0108] The mapping relationship between the logical address and the physical address of each data is stored in the PTE table. At least one PTE table corresponding to the merge bitmap is read in step S330. The relevant at least one PTE table corresponds to at least one source data block from the first source data block to the Nth source data block. The mapping relationship between the logical address and the physical address corresponding to the first source data block to the Nth source data block is read according to the at least one PTE table, and the logical address and the physical address of the relevant valid data are pushed to the retrieval queue. The relevant valid data is read by reading the logical address and the physical address of the valid data in the retrieval queue, and the relevant valid data is written to a pre-set target data block.

[0109] In an exemplary embodiment, as Figure 5 As shown, the logical addresses / physical addresses of the valid data corresponding to the first source data block through the Nth source data block are read from the PTE table through the merge bitmap and pushed to the search queue. The search queue includes the logical address / physical address pairs: LCA0 / PCA0, LCA1 / PCA1, ..., LCAn / PCAn. The relevant valid data is read based on the logical address / physical address pairs and written to the target data block.

[0110] In an exemplary embodiment, the memory garbage collection method can be implemented by a computer program / instruction executed by a processor. The computer program / instruction can be stored in a controller memory in a storage controller or in a hardware accelerator. When the memory system needs to perform garbage collection, the controller processor calls and executes the computer program / instruction. Data generated during the execution of the computer program / instruction can be temporarily stored in a buffer memory.

[0111] The garbage collection method provided by the disclosed embodiments performs garbage collection on multiple source data blocks by merging the bitmaps corresponding to the multiple source data blocks to generate a merged bitmap. The merged bitmap is then used to read the corresponding page table entries, thereby avoiding response delays caused by repeated page table entry reading between source data blocks and improving the overall efficiency of the garbage collection process.

[0112] Figure 6 FIG1 is a flow chart of a memory garbage collection method according to an embodiment of the present disclosure. Figure 6 In the garbage collection method shown, steps S610, S620, S630, and S640 are respectively Figure 3 Steps S310, S320, S330, and S340 in the garbage collection method shown correspond to each other and are not described in detail for the sake of brevity. Based on the aforementioned memory garbage collection method, the method may further include the following steps. The method may be applied to Figure 2 The storage controller is shown.

[0113] In step S650, a logical address to physical address mapping table (Logical address to physical address, L2P) is updated according to writing the valid data into the target data block.

[0114] The PTE table stores the mapping relationship between the logical address and the physical address of each data, i.e., the logical address to physical address mapping table (Logical Address To Physical Address, L2P). In step S340, the PTE table determines the address mapping relationship LCA / PCA of the valid data, and then writes the relevant valid data into the target data block. In the process of writing the valid data into the target data block, the new physical address PCA' of the valid data in the target data block is obtained. Based on the new physical address PCA', the original address mapping relationship LCA / PCA in the PTE table is updated to obtain the updated address mapping relationship LCA / PCA'.

[0115] By updating the address mapping relationship in the PTE table, when a subsequent program accesses the valid data based on the logical address LCA, the valid data can be accessed at the corresponding physical address in the target data block based on the updated address mapping relationship LCA / PCA'.

[0116] In memory systems, the address mapping relationship between logical addresses and physical addresses is usually managed through multi-level mapping tables. Depending on the requirements of the memory system address mapping relationship management, in addition to the above-mentioned update of the PTE table, it may also involve synchronous updates to the PGD table and PMD table.

[0117] In addition, as the valid data is moved from the source data block to the target data block, the above-mentioned PTE table is updated, and the bitmaps corresponding to the first source data block to the Nth source data block and the target data block are synchronously updated, and the bitmap bit value corresponding to the moved valid data is changed from 1 to 0.

[0118] In step S660 , the first source data block is released to the Nth source data block.

[0119] In the disclosed embodiment, after the relevant valid data in the first to Nth source data blocks are moved, the original physical addresses PCA of the relevant valid data can be marked as free or invalid to release the data in the source data blocks. After the valid data in the relevant source data blocks is released, a garbage collection operation can be performed on the source data blocks, so that the storage space of the source data blocks is freed up and can be used for data writing again.

[0120] The garbage collection method provided by the embodiments of the present disclosure simultaneously updates the address mapping relationship of the relevant valid data in the PTE table during the process of moving valid data from the source data block to the target data block, and releases the storage space of the valid data in the first to Nth source data blocks. This ensures that the valid data can be read normally by the host side and that the first to Nth source data blocks can be garbage collected.

[0121] In the embodiment of the present disclosure, Figure 4 As shown, the PTE table includes multiple sets of address mapping relationships LCA / PCA. Among them, some address mapping relationships LCA / PCA may correspond to valid data in the first source data block to the Nth source data block. Based on this, the step S340 may include the following steps.

[0122] Step S340A: searching the page table entry for valid data whose physical addresses are located between the first source data block and the Nth source data block.

[0123] In the embodiment of the present disclosure, multiple groups of physical addresses in the PTE table are matched with the physical addresses of the first to Nth source data blocks to find valid data whose physical addresses are located in the first to Nth source data blocks. Figure 7 The figure is a flow chart of valid data address matching according to an embodiment of the present disclosure. As shown in the figure, the valid data address matching process may include the following steps.

[0124] In step S710 , the physical address of valid data in the page table entry table is read.

[0125] In the embodiment of the present disclosure, based on the aforementioned step S330, the PTE table corresponding to the merge bitmap is read, and the physical address of the address mapping relationship of each valid data in the PTE table is further read. Here, reading the physical address of each valid data in the PTE table can be implemented by hardware or software. This disclosure does not specifically limit this.

[0126] In step S720 , the physical addresses corresponding to the valid data in the page table entry are matched with the first source data block to the Nth source data block respectively.

[0127] In the disclosed embodiment, the physical address is typically a binary data structure including data block bits corresponding to the index value of the data block. The data block bits are partial fields in the physical address and are used to identify the data block corresponding to the physical address. The index value of the data block refers to a numerical value used to uniquely identify the position of the data block in the physical address space. The relevant fields in the physical address of each valid data in the PTE table are matched with the index values ​​of the first to Nth source data blocks to determine which valid data in the PTE table is located in the first to Nth source data blocks.

[0128] In an exemplary embodiment, the physical address is a 32-bit binary number, where a data block bit (denoted as VB_bit) corresponds to a data block index value (denoted as VB_index). The physical address of the valid data in the PTE table is matched with the data block index value, that is, the VB_bit and the VB_index are "exclusive-ored" bit by bit. If the exclusive-or result is 0, it indicates that the VB_bit and the VB_index match. Otherwise, it indicates a mismatch.

[0129] In step S730, it is determined whether the physical address matches.

[0130] In step S740 , valid data located in the first source data block to the Nth source data block is determined.

[0131] In the disclosed embodiment, the matching results are used to determine which valid data in the PTE table is located in the first through Nth source data blocks. Furthermore, the source data blocks corresponding to each valid data item can be determined. Furthermore, the address mapping relationship LCA / PCA stored in the PTE table for the determined valid data item is read.

[0132] Step S340B: writing the valid data located from the first source data block to the Nth source data block into the target data block.

[0133] In the disclosed embodiment, the determined valid data is pushed to the search queue corresponding to the address mapping relationship LCA / PCA stored in the PTE table. The relevant valid data is read by reading the address mapping relationship LCA / PCA of the valid data in the search queue, and the relevant valid data is written to a pre-set target data block.

[0134] The garbage collection method provided by the disclosed embodiments rapidly locates the valid data in the page table entry corresponding to the merged bitmap by matching the physical addresses of the valid data in the page table entry corresponding to the merged bitmap with the index values ​​of the first through Nth source data blocks, thereby writing the relevant valid data into the target data block. Furthermore, by reading the corresponding page table entry based on the merged bitmap, the response delay caused by reading the page table entry for each source data block separately is avoided.

[0135] As previously described, the disclosed embodiments perform parallel garbage collection on multiple source data blocks, thereby reducing the response delay caused by repeated reading of the PTE table between each source data block and improving the overall response efficiency of the garbage collection process. The disclosed embodiments can select multiple source data blocks from multiple data blocks for garbage collection. The selection process of these multiple source data blocks can be performed through the following various implementations.

[0136] Figure 8 This is a flow chart of selecting source data blocks according to an embodiment of the present disclosure. As shown in the figure, the process of selecting source data blocks can be applied to Figure 2 The storage controller shown may include the following steps.

[0137] In step S810 , valid page counts of multiple data blocks are obtained.

[0138] In the disclosed embodiment, the multiple data blocks are data blocks to be selected for garbage collection. The multiple data blocks can be all data blocks in the storage device or data blocks in a certain area to be garbage collected. The valid page count (VPC) is the amount of valid data stored in each data block, where the valid data can be counted in units of pages.

[0139] It should be noted that storage devices contain used data blocks (used VBs) and unused data blocks. Garbage collection is the process of recovering and reusing data blocks that have already been written. In step S810, the multiple data blocks described can be further defined as used data blocks (used VBs), while unused data blocks are not processed, thereby reducing processing complexity.

[0140] In step S820 , the first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks.

[0141] In the disclosed embodiments, the lower the valid page count in a data block, the shorter the time it takes to move the valid data in that data block to the target data block, thereby completing garbage collection for that data block. Therefore, by selecting the first through Nth source data blocks based on the valid page counts of multiple data blocks through a reasonable selection strategy, the overall efficiency of the garbage collection process can be improved.

[0142] It should be noted that, depending on the requirements of actual application scenarios, there can be many different selection strategies for selecting multiple source data blocks based on the valid page counts of multiple data blocks. Any feasible selection strategy should be considered within the scope of protection of this disclosure. Based on this, this disclosure illustratively provides several feasible selection strategies.

[0143] Figure 13 Schematic diagram of the process of selecting source data blocks according to an embodiment of the present disclosure Figure 3 In the embodiments of the present disclosure, Figure 13 In the process of selecting source data block, step S1310 and Figure 3 The process of selecting source data blocks shown in FIG8 corresponds to step S810, which will not be repeated here. Based on the above process of selecting source data blocks, the method may further include the following steps. Figure 2 The storage controller is shown.

[0144] In step S1320, it is determined whether the valid data ratio of each data block in the plurality of data blocks is lower than a preset threshold value according to the valid page count.

[0145] In the embodiment of the present disclosure, the valid data ratio is the ratio of the valid page count in the data block to the total data storage space in the data block. A threshold value is set in advance for the valid data ratio to perform a preliminary screening of the data blocks.

[0146] In step S1330 , the first source data block to the Nth source data block are selected from the plurality of data blocks whose valid data proportion is lower than a preset threshold.

[0147] In the disclosed embodiment, due to the large number of data blocks in the storage device, if each data block participates in the selection of the source data block, it may affect the efficiency of the selection decision. Therefore, the disclosed embodiment presets the threshold value to perform an initial screening of the data blocks. Only when the valid data ratio of the data block is lower than the preset threshold value, the data block participates in the selection of multiple source data blocks. In an exemplary embodiment, the valid data ratio can be set to 60%. When the valid data ratio of the data block is higher than 60%, it does not participate in the selection of the source data block.

[0148] The selection strategy provided by the embodiment of the present disclosure can be combined with other selection strategies as a preliminary screening link of other selection strategies, and can also be used as a complete selection strategy for source data block selection.

[0149] In the embodiment of the present disclosure, the process of selecting a source data block may include the following steps.

[0150] In step 1, the multiple data blocks are sorted based on the valid page count according to the valid page count.

[0151] In an embodiment of the present disclosure, multiple data blocks are sorted according to valid page counts of each data block. In an exemplary embodiment, multiple data blocks are sorted from small to large based on valid page counts.

[0152] In step 2, according to the data block sorting, a preset number of the data blocks are selected as the first source data block to the Nth source data block.

[0153] In the disclosed embodiment, a predetermined number of source data blocks are selected, and this predetermined number of data blocks are selected from smallest to largest based on the order of the aforementioned data blocks as the first to Nth source data blocks. As previously mentioned, the lower the valid page count in a data block, the more efficient the garbage collection process. Therefore, selecting multiple source data blocks based on the valid page count order can improve the overall efficiency of the garbage collection process.

[0154] In addition to selecting multiple source data blocks according to the selection strategy provided above, the embodiment of the present disclosure may also combine the above selection strategy with other selection strategies to select multiple source data blocks.

[0155] In the disclosed embodiments, in addition to using the valid page counts of multiple data blocks as a reference factor for selecting multiple source data blocks, the effective capacity of the target data block is also used as a reference factor. Effective capacity refers to the remaining capacity in a data block available for storing data. The process of selecting a source data block may include the following steps.

[0156] Gets the valid page count for multiple data blocks.

[0157] Obtain the effective capacity of the target data block.

[0158] The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks and the valid capacity of the target data block.

[0159] Based on the valid page counts of multiple data blocks and the valid capacity of the target data block, the current data storage conditions of the data block and the target data block can be taken into account, so as to better select the source data block and achieve higher garbage collection processing efficiency.

[0160] Figure 9 Schematic diagram of the process of selecting source data blocks according to an embodiment of the present disclosure Figure 2 As shown in the figure, the process of selecting the first source data block to the Nth source data block according to the valid page counts of the plurality of data blocks and the valid capacity of the target data block may include the following steps. Figure 2 The storage controller is shown.

[0161] In step S910 , a plurality of first data blocks are selected.

[0162] In the embodiment of the present disclosure, a plurality of first data blocks are selected from the plurality of data blocks. The plurality of first data blocks may be selected based on a preset rule or randomly selected from the plurality of data blocks.

[0163] In an exemplary embodiment, selecting the plurality of first data blocks is selecting a preset number of first data blocks, for example, the preset number is 12.

[0164] In an exemplary embodiment, the plurality of data blocks may be sorted based on the valid page counts, and then a preset number of first data blocks may be selected from the plurality of data blocks based on the sorting of the data blocks.

[0165] In step S920 , valid page counts of the plurality of first data blocks are accumulated.

[0166] In the embodiment of the present disclosure, valid page counts of the plurality of first data blocks selected in step S910 are accumulated to obtain an accumulated value, which represents the storage space in the target data block required for moving valid data in the plurality of first data blocks.

[0167] In step S930 , it is determined whether the accumulated value of the valid page count is greater than the valid capacity.

[0168] In the embodiment of the present disclosure, it is determined whether the accumulated value is greater than the effective capacity of the target data block. If the accumulated value is not greater than the effective capacity of the target data block, it means that the target data block can accommodate the effective data in the accumulated first data block.

[0169] In an exemplary embodiment, if the accumulated value is not greater than the effective capacity of the target data block, the process returns to step S910 to select more first data blocks to fully utilize the effective capacity of the target data block. Conversely, if the accumulated value is greater than the effective capacity of the target data block, it indicates that the effective capacity of the target data block is saturated, and no further first data blocks need to be selected.

[0170] In step S940 , in response to the accumulated value of the valid page count being no greater than the valid capacity of the target data block, the accumulated first data block is selected as the first to Nth source data blocks.

[0171] In the disclosed embodiment, if the accumulated value is not greater than the valid capacity of the target data block, it indicates that the target data block can accommodate the valid data in the accumulated first data block. Therefore, the accumulated first data block is selected as the first to Nth source data blocks, i.e., is determined to be a source data block participating in garbage collection.

[0172] In the disclosed embodiment, the selected first data block is continuously accumulated through steps S910 to S930. As long as the accumulated value is not greater than the effective capacity of the target data block, it indicates that the target data block can accommodate the valid data in the accumulated first data block. When the accumulated value exceeds the effective capacity of the target data block, it indicates that the effective capacity of the target data block has been saturated, and the accumulation process is stopped. Before the accumulated value exceeds the effective capacity, the accumulated first data block is selected as the first source data block to the Nth source data block.

[0173] The garbage collection method provided in the embodiments of the present disclosure provides various implementation methods for source data block selection strategies. These selection strategies can be flexibly combined to form a suitable source data block selection strategy based on parameters such as the valid page count of the data block, the valid capacity of the target data block, the preset number, and the valid data percentage of the data block, depending on the needs of the actual application scenario. By selecting the first through Nth source data blocks through a reasonable selection strategy, the overall efficiency of the garbage collection process can be improved.

[0174] Due to physical characteristics, storage devices have a certain limit on the number of erase and write operations they can perform. Frequent write operations will accelerate the aging of the storage device. Filling the storage space of a data block completely can reduce the number of data writes, thereby extending the lifespan of the data block. Therefore, it is desirable for a storage device to fill the storage space of a data block as completely as possible to reduce the number of data writes. Based on this, the garbage collection method of the embodiment of the present disclosure further includes the following implementation method to fill the target data block.

[0175] Figure 10 FIG1 is a flowchart of an effective data migration process according to an embodiment of the present disclosure. Figure 11 This is a schematic diagram of an effective data migration process according to an embodiment of the present disclosure. As shown in the figure, the effective data migration process can be applied to Figure 2 The storage controller shown may include the following steps.

[0176] In step S1010, it is determined whether the target data block is full.

[0177] In the embodiment of the present disclosure, after writing valid data from the first source data block to the Nth source data block into the target data block as described above in the garbage collection method, it is determined whether the target data block is full. If the target data block is not full, the following step S1020 is executed. If the target data block is full, the following step S1050 is executed.

[0178] In step S1020, in response to the target data block being not full, the (N+1)th source data block is obtained.

[0179] In the embodiment of the present disclosure, when the target data block is not full, in order to fully utilize the storage space of the target data block, the target data block is filled as much as possible, and the N+1th source data block is further obtained. The selection strategy for the N+1th source data block can be based on any of the aforementioned source data block selection strategies, which will not be repeated here.

[0180] In step S1030 , the corresponding page table entry table is read according to the N+1th bitmap corresponding to the N+1th source data block.

[0181] In the embodiment of the present disclosure, the corresponding PTE table is read according to the N+1th bitmap corresponding to the N+1th source data block. The relevant process has been detailed in the above step S330 and will not be repeated here.

[0182] In step S1040, at least part of the valid data corresponding to the (N+1)th source data block in the page table entry table is written into the target data block.

[0183] In the embodiment of the present disclosure, at least part of the valid data corresponding to the N+1th source data block in the PTE table is written into the target data block. The relevant process has been described in detail in the aforementioned step S340 and will not be repeated here.

[0184] It should be noted that during the process of migrating valid data from the (N+1)th source data block, the target data block may be filled. Therefore, the migration operation may only be performed on at least a portion of the valid data in the (N+1)th source data block. After the target data block is filled, the remaining valid data will no longer be migrated. The order in which the valid data in the (N+1)th source data block is moved can be randomly selected or can be moved according to pre-set rules, and is not particularly limited here.

[0185] In step S1050 , in response to the target data block being full, writing valid data into the target data block is stopped.

[0186] In the embodiment of the present disclosure, when the target data block is full, writing of valid data into the target data block is stopped.

[0187] Figure 12 Schematic diagram of the process of effective data migration according to an embodiment of the present disclosure Figure 2 As shown in the figure, the effective data migration process can be applied to Figure 2 The storage controller shown may include the following steps.

[0188] In step S1210, it is determined whether the target data block is full.

[0189] In the embodiment of the present disclosure, after writing valid data from the first source data block to the Nth source data block into the target data block as described above in the garbage collection method, it is determined whether the target data block is full. If the target data block is not full, the following step S1220 is executed. If the target data block is full, the following step S1230 is executed.

[0190] In step S1220 , in response to the target data block being not full, dummy data is written into the target data block.

[0191] In the disclosed embodiments, when the target data block is not fully written, dummy data is further written to the target data block to fully utilize the target data block's storage space. Dummy data is a data structure used to simulate actual storage space usage. By writing this dummy data into the remaining storage space in the target data block, the target data block can be fully written, thereby reducing the number of writes to the target data block.

[0192] After the dummy data is written to the target data block, the process returns to step S1210 to determine whether the target data block is full. If the target data block is not full, the process continues to write dummy data to the target data block until the target data block is full.

[0193] In step S1030 , in response to the target data block being full, writing valid data into the target data block is stopped.

[0194] In the embodiment of the present disclosure, when the target data block is full, writing of valid data into the target data block is stopped.

[0195] The garbage collection method provided by the embodiment of the present disclosure provides multiple ways to fill the target data block. By filling the target data block, the number of times data is written to the target data block can be reduced, thereby extending the service life of the data block.

[0196] Based on the same inventive concept, the present disclosure also provides a memory system, as described in the following embodiments. Since the principles of the memory system embodiments are similar to those of the garbage collection method embodiments described above, the implementation of the memory system embodiments can refer to the implementation of the method embodiments described above, and the repetitive parts will not be repeated.

[0197] Figure 1A 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. The memory system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1A As shown, the memory system 100 includes: one or more storage devices 104 as described in the above embodiments; and a storage controller 106 coupled to the storage devices 104, wherein the storage controller 106 is configured to:

[0198] Obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier pointing to a page table entry table of the corresponding data block;

[0199] Obtaining a merged bitmap based on the first bitmap to the Nth bitmap;

[0200] Reading the page table entry table according to the merge bitmap;

[0201] The valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into the target data block.

[0202] In an embodiment of the present disclosure, the storage controller 106 is also configured to: search for valid data in the page table entry table whose physical addresses are located between the first source data block and the Nth source data block; and write valid data corresponding to physical addresses in the page table entry table that are located between the first source data block and the Nth source data block into the target data block.

[0203] In an embodiment of the present disclosure, the storage controller 106 is further configured to: update the logical address to physical address mapping table in response to the valid data being written into the target data block; and release the first source data block to the Nth source data block.

[0204] In an embodiment of the present disclosure, the storage controller 106 is further configured to perform an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

[0205] In an embodiment of the present disclosure, the storage controller 106 is also configured to: match the data block bits of the physical address corresponding to the valid data in the page table entry table with the data block index values ​​of the first source data block to the Nth source data block, respectively, to determine the valid data located from the first source data block to the Nth source data block.

[0206] In an embodiment of the present disclosure, the storage controller 106 is further configured to: obtain valid page counts of multiple data blocks; and select the first source data block to the Nth source data block according to the valid page counts of the multiple data blocks.

[0207] In an embodiment of the present disclosure, the storage controller 106 is further configured to: obtain the effective capacity of the target data block; and select the first source data block to the Nth source data block based on the effective page counts of the multiple data blocks and the effective capacity of the target data block.

[0208] In an embodiment of the present disclosure, the storage controller 106 is further configured to: select multiple first data blocks according to the valid page counts of the multiple data blocks from small to large; and select N first data blocks whose cumulative valid page count value is not greater than the valid capacity of the target data block as the first source data block to the Nth source data block according to the valid page counts of the multiple first data blocks from small to large.

[0209] In an embodiment of the present disclosure, the storage controller 106 is further configured to: select a plurality of first data blocks, including selecting a preset number of first data blocks.

[0210] In an embodiment of the present disclosure, the storage controller 106 is further configured to: in response to the target data block being not full, obtain the N+1th source data block; read the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; and write at least part of the valid data corresponding to the N+1th source data block in the page table entry table into the target data block until the target data block is full.

[0211] In an embodiment of the present disclosure, the storage controller 106 is further configured to: in response to the target data block being not full, write dummy data into the target data block until the target data block is full.

[0212] In an embodiment of the present disclosure, the storage controller 106 is further configured to: determine the valid data ratio of each data block in the multiple data blocks based on the valid page count; and select the first source data block to the Nth source data block from the multiple data blocks whose valid data ratio is lower than a preset threshold.

[0213] Based on the same inventive concept, the present disclosure also provides a storage controller, as described in the following embodiments. Because the principles of this storage controller embodiment are similar to those of the aforementioned garbage collection method embodiment, the implementation of this storage controller embodiment can refer to the implementation of the aforementioned method embodiment, and any repetitions will not be repeated.

[0214] Figure 2 FIG. 1 is a schematic diagram of an exemplary memory controller having a memory system according to an embodiment of the present disclosure. Figure 2 As shown, the storage controller 106 includes: a controller memory 213 configured to store control instructions; and a controller processor 210 coupled to the controller memory 213 and configured to execute the control instructions to perform a process, wherein the process includes:

[0215] Obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier pointing to a page table entry table of the corresponding data block;

[0216] Obtaining a merged bitmap based on the first bitmap to the Nth bitmap;

[0217] Reading the page table entry table according to the merge bitmap;

[0218] The valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into the target data block.

[0219] In an embodiment of the present disclosure, the processing also includes: searching for valid data whose physical addresses are located from the first source data block to the Nth source data block in the page table entry table; and writing the valid data located from the first source data block to the Nth source data block into the target data block.

[0220] In an embodiment of the present disclosure, the processing further includes: writing the target data block according to the valid data, updating the logical address to physical address mapping table; and releasing the first source data block to the Nth source data block.

[0221] In an embodiment of the present disclosure, the processing further includes: performing an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

[0222] In an embodiment of the present disclosure, the processing also includes: matching the data block bits of the physical address corresponding to the valid data in the page table entry table with the data block index values ​​of the first source data block to the Nth source data block, respectively, to determine the valid data located from the first source data block to the Nth source data block.

[0223] In an embodiment of the present disclosure, the processing further includes: obtaining valid page counts of multiple data blocks; and selecting the first source data block to the Nth source data block according to the valid page counts of the multiple data blocks.

[0224] In an embodiment of the present disclosure, the processing further includes: obtaining the effective capacity of the target data block; and selecting the first source data block to the Nth source data block based on the effective page counts of the multiple data blocks and the effective capacity of the target data block.

[0225] In an embodiment of the present disclosure, the processing also includes: selecting multiple first data blocks; accumulating the valid page counts of the multiple first data blocks; in response to the accumulated value of the valid page count being not greater than the effective capacity of the target data block, the accumulated first data blocks are selected as the first source data block to the Nth source data block.

[0226] In an embodiment of the present disclosure, the processing further includes: selecting multiple first data blocks, which is selecting a preset number of first data blocks.

[0227] In an embodiment of the present disclosure, the processing also includes: in response to the target data block being not full, obtaining the N+1th source data block; reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; writing at least part of the valid data corresponding to the N+1th source data block in the page table entry table into the target data block until the target data block is full.

[0228] In an embodiment of the present disclosure, the processing further includes: in response to the target data block being not full, writing virtual data into the target data block until the target data block is full.

[0229] In an embodiment of the present disclosure, the processing also includes: determining the valid data ratio of each data block in the multiple data blocks based on the valid page count; and selecting the first source data block to the Nth source data block from the multiple data blocks whose valid data ratio is lower than a preset threshold.

[0230] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a controller memory including instructions. The instructions are executable by a controller processor of a storage controller to perform the above method. Alternatively, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, or the like.

[0231] In an exemplary embodiment, a computer program product is further provided, including a computer program / instruction. When the computer program / instruction is executed by a processor, the method in the above embodiment is implemented.

[0232] It should be understood that the “some embodiments” mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in other embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0233] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0234] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0235] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0236] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0237] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system comprising: Storage devices; as well as a storage controller coupled to the storage device, wherein the storage controller is configured to: Obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier pointing to a page table entry table of the corresponding data block; Obtaining a merged bitmap based on the first bitmap to the Nth bitmap; Reading the page table entry table according to the merge bitmap; The valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into the target data block.

2. The memory system according to claim 1, wherein: The storage controller is further configured to: Searching for valid data in the page table entry table whose physical addresses are between the first source data block and the Nth source data block; The valid data corresponding to the physical addresses in the page table entry table from the first source data block to the Nth source data block are written into the target data block.

3. The memory system according to claim 1 or 2, characterized in that: The storage controller is further configured to: In response to the valid data being written into the target data block, updating the logical address to physical address mapping table; Release the first source data block to the Nth source data block.

4. The memory system according to claim 1 or 2, characterized in that: The storage controller is further configured to: Perform an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

5. The memory system according to claim 2, wherein: The storage controller is further configured to: The data block bits of the physical address corresponding to the valid data in the page table entry table are matched with the data block index values ​​of the first source data block to the Nth source data block respectively to determine the valid data located from the first source data block to the Nth source data block.

6. The memory system according to claim 1 or 2, characterized in that: The storage controller is further configured to: Get valid page counts for multiple data blocks; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks.

7. The memory system according to claim 6, wherein: The storage controller is further configured to: Obtaining the effective capacity of the target data block; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks and the valid capacity of the target data block.

8. The memory system according to claim 7, wherein: The storage controller is further configured to: selecting a plurality of first data blocks; Accumulating valid page counts of the plurality of first data blocks; In response to the accumulated value of the valid page count being no greater than the valid capacity of the target data block, the accumulated first data block is selected as the first to Nth source data blocks.

9. The memory system according to claim 8, wherein: The storage controller is further configured to: The selecting of the plurality of first data blocks includes selecting a preset number of first data blocks.

10. The memory system according to claim 1, wherein: The storage controller is further configured to: In response to the target data block being not full, obtaining the (N+1)th source data block; Reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; At least part of the valid data corresponding to the (N+1)th source data block in the page table entry table is written into the target data block until the target data block is full.

11. The memory system according to claim 1 or 2, characterized in that: The storage controller is further configured to: In response to the target data block being not full, dummy data is written into the target data block until the target data block is full.

12. The memory system according to claim 6, wherein: The storage controller is further configured to: Determining a valid data ratio of each data block in the plurality of data blocks according to the valid page count; The first source data block to the Nth source data block are selected from the multiple data blocks whose valid data proportion is lower than a preset threshold.

13. A storage controller comprising: a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform a process comprising: Obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; the bitmap records an identifier pointing to a page table entry table of the corresponding data block; Obtaining a merged bitmap based on the first bitmap to the Nth bitmap; Reading the page table entry table according to the merge bitmap; The valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into the target data block.

14. The storage controller according to claim 13, wherein: The processing also includes: Searching for valid data in the page table entry table whose physical addresses are between the first source data block and the Nth source data block; The valid data located in the first source data block to the Nth source data block is written into the target data block.

15. The storage controller according to claim 13 or 14, characterized in that: The processing also includes: Writing the valid data into the target data block, updating the logical address to physical address mapping table; Release the first source data block to the Nth source data block.

16. The storage controller according to claim 13 or 14, characterized in that: The processing also includes: Perform an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

17. The storage controller according to claim 14, wherein: The processing also includes: The data block bits of the physical address corresponding to the valid data in the page table entry table are matched with the data block index values ​​of the first source data block to the Nth source data block respectively to determine the valid data located from the first source data block to the Nth source data block.

18. The storage controller according to claim 13 or 14, characterized in that: The processing also includes: Get valid page counts for multiple data blocks; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks.

19. The storage controller according to claim 18, wherein: The processing also includes: Obtaining the effective capacity of the target data block; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks and the valid capacity of the target data block.

20. The storage controller according to claim 19, wherein: The processing also includes: selecting a plurality of first data blocks; Accumulating valid page counts of the plurality of first data blocks; In response to the accumulated value of the valid page count being no greater than the valid capacity of the target data block, the accumulated first data block is selected as the first to Nth source data blocks.

21. The storage controller according to claim 20, wherein: The processing also includes: The selecting of multiple first data blocks is selecting a preset number of first data blocks.

22. The storage controller according to claim 18, wherein: The processing also includes: In response to the target data block being not full, obtaining the (N+1)th source data block; Reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; At least part of the valid data corresponding to the (N+1)th source data block in the page table entry table is written into the target data block until the target data block is full.

23. The storage controller according to claim 13 or 14, characterized in that: The processing also includes: In response to the target data block being not full, dummy data is written into the target data block until the target data block is full.

24. The storage controller according to claim 18, wherein: The processing also includes: Determining a valid data ratio of each data block in the plurality of data blocks according to the valid page count; The first source data block to the Nth source data block are selected from the multiple data blocks whose valid data proportion is lower than a preset threshold.

25. A garbage collection method, characterized in that: include: Obtaining the first bitmap corresponding to the first source data block to the Nth bitmap corresponding to the Nth source data block; N is an integer greater than or equal to 2; The bitmap records the identifier of the page table entry table pointing to the corresponding data block; Obtaining a merged bitmap based on the first bitmap to the Nth bitmap; Reading the page table entry table according to the merge bitmap; The valid data corresponding to the first source data block to the Nth source data block in the page table entry table is written into the target data block.

26. The memory garbage collection method according to claim 25, characterized in that: Writing the valid data corresponding to the first source data block to the Nth source data block in the page table entry table into the target data block includes: Searching for valid data in the page table entry table whose physical addresses are between the first source data block and the Nth source data block; The valid data located in the first source data block to the Nth source data block is written into the target data block.

27. The memory garbage collection method according to claim 25 or 26, characterized in that: Also includes: Writing the valid data into the target data block, updating the logical address to physical address mapping table; Release the first source data block to the Nth source data block.

28. The memory garbage collection method according to claim 25 or 26, characterized in that: The obtaining a merged bitmap based on the first bitmap to the Nth bitmap includes: Perform an OR operation on corresponding bits of the first bitmap to the Nth bitmap to obtain the merged bitmap.

29. The memory garbage collection method according to claim 26, wherein: The step of searching the page table entry table for valid data whose physical addresses are located between the first source data block and the Nth source data block includes: The data block bits of the physical address corresponding to the valid data in the page table entry table are matched with the data block index values ​​of the first source data block to the Nth source data block respectively to determine the valid data located from the first source data block to the Nth source data block.

30. The memory garbage collection method according to claim 25 or 26, characterized in that: Also includes: Get valid page counts for multiple data blocks; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks.

31. The memory garbage collection method according to claim 30, characterized in that: The selecting, based on valid page counts of the plurality of data blocks, the first source data block to the Nth source data block comprises: Obtaining the effective capacity of the target data block; The first source data block to the Nth source data block are selected according to the valid page counts of the plurality of data blocks and the valid capacity of the target data block.

32. The memory garbage collection method according to claim 31, wherein: The selecting, based on the valid page counts of the plurality of data blocks and the valid capacity of the target data block, the first source data block to the Nth source data block comprises: selecting a plurality of first data blocks; Accumulating valid page counts of the plurality of first data blocks; In response to the accumulated value of the valid page count being no greater than the valid capacity of the target data block, the accumulated first data block is selected as the first to Nth source data blocks.

33. The memory garbage collection method according to claim 32, characterized in that: The selecting of the plurality of first data blocks comprises: The selecting of multiple first data blocks is selecting a preset number of first data blocks.

34. The memory garbage collection method according to claim 30, wherein: Also includes: In response to the target data block being not full, obtaining the (N+1)th source data block; Reading the corresponding page table entry table according to the N+1th bitmap corresponding to the N+1th source data block; At least part of the valid data corresponding to the (N+1)th source data block in the page table entry table is written into the target data block until the target data block is full.

35. The memory garbage collection method according to claim 25 or 26, characterized in that: Also includes: In response to the target data block being not full, dummy data is written into the target data block until the target data block is full.

36. The memory garbage collection method according to claim 30, characterized in that: The selecting, based on valid page counts of the plurality of data blocks, the first source data block to the Nth source data block comprises: Determining a valid data ratio of each data block in the plurality of data blocks according to the valid page count; The first source data block to the Nth source data block are selected from the multiple data blocks whose valid data proportion is lower than a preset threshold. 37 . A computer-readable storage medium, when control instructions in the computer-readable storage medium are executed by a controller processor, enables the controller processor to execute the memory garbage collection method according to any one of claims 25 to 36.

38. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the memory garbage collection method according to any one of claims 25 to 36 is implemented.

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