Memory access device, processor and memory access method

Abstract

The invention discloses a memory access device, a processor and a memory access method, and belongs to the technical field of computers. The memory access device comprises a scheduling module which is configured to distribute memory access instructions in an instruction queue to a plurality of assembly lines of the memory access device; the first cache module is configured to cache the first mapping relation; the control module is configured to query the page table and update the second mapping relation in the second cache module according to the memory access instruction of the virtual machine monitor if the memory access instruction currently processed by the plurality of assembly lines does not hit the first mapping relation and the memory access instruction is the memory access instruction of the virtual machine monitor; and the second cache module is configured to cache the second mapping relation. On the basis of not increasing the complexity of hardware design, the resource utilization rate in the execution process of the memory access instruction of the virtual machine monitor can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory access device, a processor, and a method for accessing a memory. Background Art

[0002] Virtualization mode refers to a technology that abstracts and logicalizes physical resources (such as servers, storage devices, and network equipment), allowing multiple virtual machines to run on a single physical platform (an integration of physical resources) and be managed by a virtual machine monitor (VMM). In virtualization mode, when the context of a virtual machine and a VMM switches, due to the different contexts of the virtual machine and the VMM corresponding to different context identifiers, memory access instructions with different context identifiers may currently exist in multiple pipelines of the memory access device.

[0003] In related technologies, in order to ensure that virtual machines and virtual machine monitors can correctly perform memory access operations, the processor needs to manage and maintain memory access instructions corresponding to different context identifiers in multiple pipelines, such as updating the page table cache according to different context identifiers, and configuring the corresponding registers to query the page table cache in sequence, etc.

[0004] However, the above method not only increases the complexity of hardware design, but also increases the risk of bugs. In addition, since the memory access instructions of the virtual machine monitor account for a relatively low proportion of all memory access instructions, the cost-effectiveness of this method is also low. Summary of the Invention

[0005] The present application provides a memory access device, a processor, and a method for accessing memory to solve the technical problems existing in the related art. Specifically, the present application includes the following technical solutions.

[0006] In a first aspect, the present application provides a memory access device, which includes a scheduling module, a control module, a first cache module and a second cache module; the scheduling module is configured to distribute memory access instructions in an instruction queue to multiple pipelines of the memory access device; the first cache module is configured to cache a first mapping relationship, which is a mapping relationship between a virtual address and a physical address carried by the memory access instruction; the control module is configured to query a page table and update a second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor if the memory access instruction currently processed by the multiple pipelines does not hit the first mapping relationship and the memory access instruction is a memory access instruction of a virtual machine monitor; the second cache module is configured to cache the second mapping relationship, which is a mapping relationship between the virtual address and the physical address carried by the memory access instruction of the virtual machine monitor that does not hit the first mapping relationship.

[0007] In some possible implementations, the context identifiers carried by the memory access instructions of the virtual machine monitor currently processed by the multiple pipelines are different; when the control module queries the page table according to the memory access instruction of the virtual machine monitor and updates the second mapping relationship in the second cache module, it is configured to: query the page table according to the virtual address carried by the memory access instruction of the virtual machine monitor; update the second mapping relationship according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and the context identifier carried by the memory access instruction of the virtual machine monitor.

[0008] In some possible implementations, the control module is further configured to: resend the memory access instructions of the virtual machine monitor that miss the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, query the updated second mapping relationship based on the virtual address and context identifier carried by the memory access instructions of the virtual machine monitor resent to the instruction queue.

[0009] In some possible implementations, the context identifiers carried by the memory access instructions of the virtual machine monitor currently processed by the multiple pipelines are the same; when the control module queries the page table according to the memory access instruction of the virtual machine monitor and updates the second mapping relationship in the second cache module, it is configured to: query the page table according to the virtual address carried by the memory access instruction of the virtual machine monitor; and update the second mapping relationship according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor.

[0010] In some possible implementations, the control module is further configured to: resend the memory access instructions of the virtual machine monitor that miss the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, query the updated second mapping relationship based on the virtual address carried by the memory access instructions of the virtual machine monitor resent to the instruction queue.

[0011] In some possible implementations, the memory access instruction of the virtual machine monitor currently processed by the multiple pipelines includes the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor.

[0012] In some possible implementations, the control module is further configured to: resend the memory access instruction of the virtual machine monitor to the instruction queue if the memory access instruction of the virtual machine monitor assigned to the multiple pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor.

[0013] In some possible implementations, the control module is further configured to: clear the updated second mapping relationship when the updated second mapping relationship hits.

[0014] In a second aspect, a processor is provided, comprising an instruction fetch unit and a memory access device as described in any one of the first aspects of the present application, wherein the instruction fetch unit is configured to obtain a memory access instruction and send the memory access instruction to the memory access device.

[0015] According to a third aspect, a method for accessing memory is provided, the method comprising: allocating memory access instructions in an instruction queue to multiple pipelines of the memory access device; if the memory access instruction currently processed by the multiple pipelines misses a first mapping relationship in a first cache module and the memory access instruction is a memory access instruction of a virtual machine monitor, querying a page table according to the memory access instruction of the virtual machine monitor and updating a second mapping relationship in the second cache module; wherein the first mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction, and the second mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction of the virtual machine monitor that misses the first mapping relationship.

[0016] In some possible implementations, the context identifiers carried by the memory access instructions of the virtual machine monitor currently processed by the multiple pipelines are different; querying the page table according to the memory access instructions of the virtual machine monitor and updating the second mapping relationship in the second cache module include: querying the page table according to the virtual address carried by the memory access instruction of the virtual machine monitor; updating the second mapping relationship according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and the context identifier carried by the memory access instruction of the virtual machine monitor.

[0017] In some possible implementations, the method further includes: resending the memory access instructions of the virtual machine monitor that miss the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, querying the updated second mapping relationship based on the virtual address and context identifier carried by the memory access instructions of the virtual machine monitor resent to the instruction queue.

[0018] In some possible implementations, the context identifiers carried by the memory access instructions of the virtual machine monitor currently processed by the multiple pipelines are the same; querying the page table according to the memory access instructions of the virtual machine monitor and updating the second mapping relationship in the second cache module include: querying the page table according to the virtual address carried by the memory access instructions of the virtual machine monitor; updating the second mapping relationship according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor.

[0019] In some possible implementations, the method further includes: resending the memory access instructions of the virtual machine monitor that miss the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, querying the updated second mapping relationship based on the virtual address carried by the memory access instructions of the virtual machine monitor resent to the instruction queue.

[0020] In some possible implementations, the memory access instruction of the virtual machine monitor currently processed by the multiple pipelines includes the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor.

[0021] In some possible implementations, the method further includes: if the memory access instruction of the virtual machine monitor assigned to the multiple pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor, resending the memory access instruction of the virtual machine monitor to the instruction queue.

[0022] In some possible implementations, the method further includes: when the updated second mapping relationship is hit, clearing the updated second mapping relationship.

[0023] In a fourth aspect, the present application provides a computer-readable storage medium on which program instructions for accessing memory are stored. When the program instructions are executed by one or more processors, the processors implement the method for accessing memory described in any one of the third aspects of the present application.

[0024] In a fifth aspect, the present application provides a computer program product, which includes a computer program. The computer program is executed by a processor to enable a computer to implement the method for accessing memory described in any one of the third aspects.

[0025] The beneficial effects of the technical solution provided by this application include at least:

[0026] The technical solution provided in the present application sets a second cache module to cache the second mapping relationship, and diverts the mapping relationship corresponding to the memory access instruction of the virtual machine monitor that misses the first mapping relationship and the first mapping relationship, so that when the memory access instruction of the virtual machine monitor accounts for a low proportion of all memory access instructions, the second mapping relationship corresponding to the memory access instruction of the virtual machine monitor that misses the first mapping relationship can be cached in the second cache module, thereby reducing the resource overhead of maintaining the first cache module and helping to improve resource utilization and device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 is a structural diagram of a memory access device provided in an embodiment of the present application;

[0029] Figure 2 is a flowchart of a method for accessing memory provided by an embodiment of the present application;

[0030] Figure 3 is a schematic diagram of the structure of the processor provided in an embodiment of the present application;

[0031] Figure 4 This is a schematic diagram of the architecture of the processor core provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0034] In virtualization mode, by virtualizing the device's memory and other storage resources and mapping the physical address space of the storage resources to a virtual address space, a separate virtual address space can be allocated to each memory access subject (such as a virtual machine program or a virtual machine monitor) running on the device that needs to access memory, thereby achieving expansion of storage resources and isolation of address spaces. When a memory access subject needs to access memory, the virtual address carried in the memory access instruction is converted into a physical address, and then the memory is accessed based on the physical address.

[0035] In related technologies, when a device currently executes memory access instructions from multiple memory access entities, to ensure that the memory access instructions from different memory access entities can correctly execute the memory access operations, the memory access operations and address spaces of different memory access entities are usually distinguished by the memory access entity's context identifier (Context ID) (a unique identifier used to distinguish different memory access entities). For example, different registers are configured for different context identifiers, and the address translation lookaside buffer (TLB) is maintained based on different context identifiers.

[0036] On this basis, when the memory access instructions of the virtual machine and the memory access instructions of the virtual machine monitor exist simultaneously in multiple pipelines of the memory access device, and the memory access instructions of the virtual machine monitor account for a low proportion of all memory access instructions, the method of distinguishing the memory access operations and address spaces of different memory access subjects through the context identifier of the memory access subject is less efficient.

[0037] For example, when a TLB is queried based on a memory access instruction from a virtual machine monitor and a cached entry in the TLB misses, it is typically necessary to query a page table entry and update the cached entry in the TLB based on the page table entry corresponding to the memory access instruction from the virtual machine monitor. However, since memory access instructions from the virtual machine monitor account for a relatively low proportion of all memory access instructions, updating the cached entry in the TLB based on the page table entry corresponding to the memory access instruction from the virtual machine monitor is not cost-effective, thus affecting device performance.

[0038] In view of this, the present application provides a memory access device, which can cache the mapping relationship between the virtual address and the physical address carried by the memory access instruction of the virtual machine monitor that missed the first mapping relationship through a separately set second cache module when the memory access instruction of the virtual machine monitor misses the first mapping relationship in the first cache module, thereby reducing the resource overhead of maintaining the first mapping relationship in the first cache module and helping to improve resource utilization.

[0039] Figure 1 This is a schematic diagram of the structure of the memory access device provided in the embodiment of the present application. Figure 1 The memory access device provided in the embodiment of the present application includes a scheduling module 110 , a control module 120 , a first cache module 130 and a second cache module 140 .

[0040] The first cache module 130 is configured to cache a first mapping relationship, where the first mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction.

[0041] Exemplarily, the memory access instruction is a program code generated by the memory access subject for accessing memory, which can be used for, but not limited to, carrying the context identifier and virtual address of the memory access subject. The first mapping relationship can be used for, but not limited to, converting the virtual address carried by the memory access instruction of the memory access subject into a physical address, so that the memory can be accessed according to the physical address. Wherein, the memory access subject includes, for example, a virtual machine and a virtual machine monitor, the memory access instruction includes, for example, the memory access instruction of the virtual machine monitor and the memory access instruction of the virtual machine, the first mapping relationship includes, for example, the mapping relationship between the virtual address carried by the memory access instruction of the virtual machine monitor and the physical address and the mapping relationship between the virtual machine address carried by the memory access instruction of the virtual machine and the physical address, and the same will be omitted below.

[0042] In some embodiments, the first cache module 130 is a TLB implemented based on hardware for accelerating address translation, or other buffers that can be used to cache the first mapping relationship.

[0043] The scheduling module 110 is configured to distribute the memory access instructions in the instruction queue to multiple pipelines of the memory access device.

[0044] Exemplarily, the instruction queue can be used for, but not limited to, temporarily storing memory access instructions of memory access subjects that are not assigned to multiple pipelines of the memory access device. In some embodiments, the instruction queue allows operations such as insertion, deletion, and update of memory access instructions (including memory access instructions of the virtual machine and memory access instructions of the virtual machine monitor, the same below), and the present application does not impose any restrictions in this regard. The multiple pipelines of the memory access device are used to indicate the technical architecture implemented by the software and / or hardware in the memory access device, which is used to improve the execution efficiency of memory access instructions. For example, the multiple pipelines of the memory access device decompose the execution process of the memory access instruction into multiple different stages, so that different stages can be executed in parallel to improve the execution efficiency of the memory access instruction.

[0045] In some embodiments, the scheduling module is an issue unit (Issue Unit), or other technical architecture implemented by hardware and / or software that can be used to distribute memory access instructions in the instruction queue to multiple pipelines of the memory access device.

[0046] The control module 120 is configured to query the page table and update the second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor if the memory access instruction currently processed by the multiple pipelines does not hit the first mapping relationship and the memory access instruction is a memory access instruction of the virtual machine monitor.

[0047] Optionally, the control module is a memory management unit (MMU), or other technical architecture implemented by hardware and / or software in the memory access device that can query the page table and update the second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor.

[0048] As described above, a memory access instruction may carry a virtual address of the memory access subject and a context identifier. After the memory access instruction in the instruction queue is distributed to multiple pipelines of the memory access device, the control module 120 may query the first mapping relationship in the first cache module 130 based on the virtual address and context identifier carried by the memory access instruction. If a match is found in the first mapping relationship, the control module 120 may convert the virtual address carried by the memory access instruction of the memory access subject into a physical address, thereby accessing the memory based on the physical address.

[0049] For example, a first mapping relationship is queried based on the virtual address and context identifier carried by the memory access instruction of the virtual machine monitor, and if the first mapping relationship is hit, the virtual address carried by the memory access instruction of the virtual machine monitor is converted into a physical address, so that the virtual machine monitor can access the memory according to the physical address, or a first mapping relationship is queried based on the virtual address and context identifier carried by the memory access instruction of the virtual machine, and if the first mapping relationship is hit, the virtual address carried by the memory access instruction of the virtual machine is converted into a physical address, so that the virtual machine can access the memory according to the physical address. Wherein, whether the first mapping relationship is hit can be, for example, referred to the following standard: if there is a first mapping relationship corresponding to the virtual address carried by the memory access subject in the first cache module, then the first mapping relationship is hit.

[0050] Considering the limited capacity of the first cache module 130, the first cache module 130 usually caches part of the first mapping relationships in the page table corresponding to the memory access subject, for example, part of the first mapping relationships in the page table corresponding to the memory access subject with higher access frequency.

[0051] If the first mapping relationship corresponding to the virtual address carried by the memory access instruction of the memory access subject does not exist in the first cache module 130, a first mapping relationship miss will occur when the control module 120 queries the first cache module 130 according to the virtual address carried by the memory access instruction of the memory access subject.

[0052] In view of this, in order to ensure that the memory access instructions of the memory access subject can be executed correctly, when the first mapping relationship misses, it is necessary to access the memory and query the page table stored in the memory. At the same time, considering that the memory access instructions of the virtual machine monitor may account for a low proportion of the memory access instructions, in order to improve resource utilization, the page table entries obtained after querying the page table for different memory access subjects can be cached in different cache modules.

[0053] For example, when the memory access instructions currently processed by multiple pipelines of the memory access device do not hit the first mapping relationship, and the memory access instructions currently processed by multiple pipelines of the memory access device are memory access instructions of the virtual machine monitor, the page table can be queried according to the memory access instructions of the virtual machine monitor and the second mapping relationship in the second cache module 140 can be updated; when the memory access instructions currently processed by multiple pipelines of the memory access device do not hit the first mapping relationship, and the memory access instructions currently processed by multiple pipelines of the memory access device are memory access instructions of the virtual machine, the page table can be queried according to the memory access instructions of the virtual machine and the first mapping relationship in the first cache module 140 can be updated.

[0054] The page tables include, for example, page tables corresponding to virtual machines and page tables corresponding to virtual machine monitors. The page tables corresponding to virtual machines are a set of mapping relationships between virtual addresses and physical addresses carried by memory access instructions of the virtual machines, while the page tables corresponding to virtual machine monitors are a set of mapping relationships between virtual addresses and physical addresses carried by memory access instructions of the virtual machine monitor.

[0055] The second cache module 140 is configured to cache a second mapping relationship, where the second mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction of the virtual machine monitor that misses the first mapping relationship.

[0056] Exemplarily, the second mapping relationship can be used for, but not limited to, converting the virtual address carried by the memory access instruction of the virtual machine monitor that misses the first mapping relationship into a physical address, so that when the first mapping relationship is missed, the second mapping relationship in the second cache module can be queried according to the memory access instruction of the virtual machine monitor that misses the first mapping relationship and the virtual address can be converted into a physical address, and then the physical address can be used to access the memory.

[0057] In some embodiments, the second cache module 140 is a bypass buffer, or other technical architecture for caching the second mapping relationship based on hardware and / or software implementation in the memory access device.

[0058] In the above method, by caching the mapping relationship corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor that misses the first mapping relationship into the second cache module 140, when the memory access instruction of the virtual machine monitor accounts for a low proportion of all memory access instructions, the possible resource overhead in maintaining the first cache module 130 can be reduced, thereby improving resource utilization.

[0059] Considering that when the instruction queue includes memory access instructions from multiple virtual machine monitors with different context identifiers, the memory access instructions currently being processed by multiple pipelines of the memory access device may include memory access instructions from virtual machine monitors with different context identifiers. In view of this, in order to ensure that the memory access instructions from the multiple virtual machine monitors with different context identifiers can be correctly executed, when updating the second mapping relationship cached in the second cache module 140, it is necessary to distinguish the context identifiers of the second mapping relationship cached in the second cache module 140.

[0060] Exemplarily, when the context identifiers carried by the memory access instructions of the virtual machine monitor currently being processed by multiple pipelines of the memory access device are different, the control module 120, when querying the page table according to the memory access instruction of the virtual machine monitor and updating the second mapping relationship in the second cache module 140, is configured to: query the page table according to the virtual address carried by the memory access instruction of the virtual machine monitor; and update the second mapping relationship in the second cache module 140 according to the page table entry corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and the context identifier carried by the memory access instruction of the virtual machine monitor. For example, the second mapping relationship indicated by the page table entry corresponding to the memory access instruction of the virtual machine monitor that did not hit the first mapping relationship and the context identifier carried by the memory access instruction of the virtual machine monitor are backfilled into the second cache module 140 to update the second mapping relationship in the second cache module 140.

[0061] As described above, when the first mapping relationship misses, it is necessary to access the memory to update the second mapping relationship in the second cache module 140. Therefore, before the second mapping relationship in the second cache module 140 is updated, the memory access instruction of the virtual machine monitor can re-enter the instruction queue, wait for the second mapping relationship in the second cache module 140 to be updated, and then query the updated second mapping relationship in the second cache module 140 to obtain the physical address corresponding to the memory access instruction of the virtual machine monitor.

[0062] In some embodiments, when the context identifiers carried by the memory access instructions of the virtual machine monitors currently being processed by multiple pipelines of the memory access device are different, the control module 120 is further configured to: resend the memory access instructions of the virtual machine monitors that did not hit the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, query the updated second mapping relationship based on the memory access instructions of the virtual machine monitors resent to the instruction queue and the corresponding context identifier. The manner in which the memory access instructions of the virtual machine monitors that did not hit the second mapping relationship are resent to the instruction queue can be, for example, queue insertion, sequential insertion, out-of-order insertion, etc., and this application does not impose any restrictions in this regard (the same shall apply hereinafter and will not be repeated).

[0063] In the above method, since the second mapping relationship cached in the second cache module 140 can be updated, the second mapping relationship and the context identifier of the virtual machine monitor can be backfilled into the second cache module 140 at the same time, when the embodiment of the present application queries the second mapping relationship in the updated second cache module 140, the corresponding second mapping relationship can be queried according to the context identifier of the virtual machine monitor, thereby distinguishing the second mapping relationships of multiple virtual machine monitors with different context identifiers.

[0064] Taking into account that in actual application scenarios, the memory access instructions of the virtual machine monitor account for a relatively low proportion of all memory access instructions, in order to further reduce the complexity of the device hardware or software design, multiple pipelines in the memory access device can currently process the memory access instructions of the virtual machine monitor with a context identifier to reduce the resource overhead when distinguishing the context identifiers of the virtual machine monitor.

[0065] Exemplarily, when the context identifiers carried by memory access instructions of virtual machine monitors currently being processed by multiple pipelines are the same, the control module 120, when querying the page table based on the memory access instructions of the virtual machine monitors and updating the second mapping relationship in the second cache module 140, is configured to: query the page table based on the virtual address carried by the memory access instructions of the virtual machine monitors; and update the second mapping relationship based on the page table entry corresponding to the virtual address carried by the memory access instructions of the virtual machine monitors. For example, the second mapping relationship indicated by the page table entry corresponding to the memory access instruction of the virtual machine monitor that did not hit the first mapping relationship in the page table corresponding to the virtual machine monitor is backfilled into the second cache module 140 to update the second mapping relationship in the second cache module 140.

[0066] In some embodiments, when the context identifiers carried by the memory access instructions of the virtual machine monitor currently processed by multiple pipelines of the memory access device are the same, the control module 120 is also configured to: resend the memory access instructions of the virtual machine monitor that missed the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, query the updated second mapping relationship based on the memory access instructions of the virtual machine monitor resent to the instruction queue.

[0067] In some embodiments, to ensure that a memory access instruction of a virtual machine monitor can be correctly executed, when multiple pipelines of a memory access device are currently processing a memory access instruction of a virtual machine monitor with a context identifier, the memory access instruction of the virtual machine monitor with a context identifier currently processed by the multiple pipelines is, for example, the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor. The program instruction sequence of the virtual machine monitor is the order indicated by the logical and semantic relationships expressed in the program code of the memory access instructions of the virtual machine monitor.

[0068] In some embodiments, when multiple pipelines of a memory access device are currently processing a memory access instruction of a virtual machine monitor with a context identifier, the control module 120 is configured to: resend the memory access instruction of the virtual machine monitor to the instruction queue if the memory access instruction of the virtual machine monitor assigned to the multiple pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor.

[0069] When multiple pipelines of the memory access device are currently processing memory access instructions for a virtual machine monitor with a single context identifier, to ensure that memory access instructions for multiple virtual machine monitors with different context identifiers can be correctly executed sequentially, after the currently processed memory access instruction for the virtual machine monitor is executed, the second mapping relationship corresponding to the executed memory access instruction for the virtual machine monitor in the second cache module 140 needs to be promptly cleared. In view of this, in some embodiments, the control module 120 is further configured to: clear the updated second mapping relationship if a hit is found in the updated second mapping relationship.

[0070] The technical solution provided in the present application sets a second cache module to cache the second mapping relationship, and diverts the mapping relationship corresponding to the memory access instruction of the virtual machine monitor that misses the first mapping relationship and the first mapping relationship, so that when the memory access instruction of the virtual machine monitor accounts for a low proportion of all memory access instructions, the second mapping relationship corresponding to the memory access instruction of the virtual machine monitor that misses the first mapping relationship can be cached in the second cache module, thereby reducing the resource overhead of maintaining the first cache module and helping to improve resource utilization and device performance.

[0071] In some other possible implementations, the present application also provides a method for accessing memory. Figure 2 This is a flow chart of a method for accessing memory provided by an embodiment of the present application. Figure 2 The method for accessing memory provided in an embodiment of the present application includes the following steps.

[0072] Step S210 , allocating the memory access instructions in the instruction queue to multiple pipelines of the memory access device.

[0073] Step S220: If the memory access instruction currently processed by the multiple pipelines does not hit the first mapping relationship in the first cache module and the memory access instruction is a memory access instruction of the virtual machine monitor, query the page table according to the memory access instruction of the virtual machine monitor and update the second mapping relationship in the second cache module.

[0074] The first mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction, and the second mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction of a virtual machine monitor that misses the first mapping relationship.

[0075] In some embodiments, the context identifiers carried by the memory access instructions of the virtual machine monitors currently processed by multiple pipelines are different; querying the page table according to the memory access instructions of the virtual machine monitor and updating the second mapping relationship in the second cache module include: querying the page table according to the virtual address carried by the memory access instruction of the virtual machine monitor; updating the second mapping relationship according to the page table entry corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and the context identifier carried by the memory access instruction of the virtual machine monitor.

[0076] In some embodiments, the method also includes: resending the memory access instruction of the virtual machine monitor that misses the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, querying the updated second mapping relationship based on the virtual address and context identifier carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

[0077] In some embodiments, the context identifiers carried by the memory access instructions of the virtual machine monitors currently processed by multiple pipelines are the same; querying the page table according to the memory access instructions of the virtual machine monitor and updating the second mapping relationship in the second cache module include: querying the page table according to the virtual address carried by the memory access instructions of the virtual machine monitor; updating the second mapping relationship according to the page table entry in the page table corresponding to the virtual address carried by the memory access instructions of the virtual machine monitor.

[0078] In some embodiments, the method also includes: resending the memory access instruction of the virtual machine monitor that misses the first mapping relationship to the instruction queue; and when the second mapping relationship is updated, querying the updated second mapping relationship based on the virtual address carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

[0079] In some embodiments, the memory access instruction of the virtual machine monitor currently being processed by the multiple pipelines includes the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor.

[0080] In some embodiments, the method further includes: if the memory access instruction of the virtual machine monitor assigned to the plurality of pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor, reissuing the memory access instruction of the virtual machine monitor to the instruction queue.

[0081] In some embodiments, the method further includes: if the updated second mapping relationship is hit, clearing the updated second mapping relationship.

[0082] above Figure 2 The principle of the method of accessing memory shown above can be referred to Figure 1The method embodiment for accessing memory provided in the above embodiment and the memory access device embodiment are of the same concept, and their specific implementation process can be found in the memory access device embodiment.

[0083] In some other possible implementations, the present application also provides a processor. Figure 3 Schematic diagram of the structure of the processor provided in the embodiment of the present application. Figure 3 The processor provided in the embodiment of the present application includes an instruction fetch unit 310 and a memory access device 320. The instruction fetch unit 310 is configured to obtain a memory access instruction and send the memory access instruction to the memory access device 320. The memory access device 320 may be the above-mentioned Figure 1 Of course, the processor may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output, and the processor may also include other components for realizing device functions, which will not be described in detail here.

[0084] Figure 4 This is a schematic diagram of the architecture of the processor core provided in the embodiment of the present application. Figure 4 , Figure 4 The architecture of the processor core shown includes the instruction fetch unit 410 and the above Figure 1 The memory access device provided by its multiple embodiments. It should be noted that, Figure 4 The instruction fetch unit 410 and Figure 3 The principle of the instruction fetch unit 310 shown in FIG is the same as that of FIG. Figure 4 The memory access device and Figure 3 The principle of the memory access device 320 shown in FIG is also the same, and the same contents are not repeated here.

[0085] The scheduling module of the memory access device is, for example, the transmit unit 430 , the control module is, for example, the MMU 460 , the first cache module is, for example, the TLB, and the second cache module is, for example, the bypass buffer 4502 .

[0086] Optionally, the core of the processor provided in the embodiment of the present application also includes LSU450 (Load / Store Unit), the first cache module TLB includes a first-level TLB4501 and a second-level TLB4601, the first-level TLB4501 and the bypass buffer 4502 are integrated in the LSU450, for example, and the LSU450 is configured to query the first mapping relationship cached in the first-level TLB4501 according to the memory access instruction allocated by the emission unit 430.

[0087] Optionally, the second-level TLB4601 is integrated in the MMU460, for example, and the MMU460 is configured to query the page table stored in the memory and update the second mapping relationship in the bypass buffer 4502 according to the memory access instruction of the virtual machine monitor when the first mapping relationship cached in the first-level TLB4501 is missed and the currently processed memory access instruction is the memory access instruction of the virtual machine monitor.

[0088] Optionally, the core of the processor provided in the embodiment of the present application also includes an instruction cache configured to store an instruction queue.

[0089] Optionally, the core of the processor provided in an embodiment of the present application also includes a program counter, which is configured to store the address of the next instruction to be executed by the core of the processor, such as a memory access instruction to access a virtual machine monitor. The instruction fetch unit 410 obtains the memory access instruction, for example, by reading the memory access instruction according to the address stored in the program counter and sending the instruction to the instruction cache.

[0090] Optionally, the core of the processor provided in an embodiment of the present application further includes a decoding unit 420, which is configured to decode the memory access instruction obtained by the instruction fetch unit 410. The decoding unit 420 decodes the memory access instruction by, for example, determining the register required by the instruction and reading the value in the corresponding register from the register file (Register File) to obtain the source operand. The register file can also update the value in the register based on the data written back by the execution unit 440 and the LSU 450.

[0091] Optionally, the core of the processor provided in the embodiment of the present application also includes an execution unit 440, which is configured to determine the virtual address carried by the memory access instruction, and to process arithmetic operations, logical operations and other operations of other program instructions except the memory access instruction.

[0092] Optionally, the core of the processor provided in the embodiment of the present application further includes a rename register unit, which is configured to eliminate data dependencies between memory access instructions or other types of instructions to improve instruction parallelism. In some embodiments, the rename register unit is integrated into the decoding unit 420.

[0093] Optionally, the core of the processor provided in an embodiment of the present application also includes L1-cache4503 (level 1-cache, first-level cache) and L2-cache470 (level 2-cache, second-level cache), and L1-cache4503A and L2-cache470 are configured to cache data that may be used by the core of the processor to improve the computing efficiency of the core of the processor.

[0094] Optionally, the core of the processor provided in the embodiment of the present application can be one or more. In the case where the processor includes multiple cores, the processor also includes a CNM (coherent mesh network, on-chip interconnect network), which is configured to provide communication connections between the multiple cores of the processor, support cache consistency between the multiple cores, and have the characteristics of high bandwidth, low latency, and scalability. In some embodiments, the CNM can be connected to the main memory to enable data exchange or collaborative work between the main memory and the core of the processor.

[0095] In some other possible implementations, the present application further provides a computer-readable storage medium having stored thereon program instructions for accessing memory, which, when executed by one or more processors, enables the processor to implement the above-mentioned combination of Figure 2 The described method and steps of multiple embodiments thereof. The computer-readable storage medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0096] The present application also provides a computer program product comprising a computer program, which is executed by a processor to enable the computer to combine Figure 2 The method and steps of various embodiments thereof are described.

[0097] It should also be noted that the terms "first," "second," etc. (if any) in the specification and claims of the present application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0098] The term "and / or" in the embodiments of the present application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B currently exist, and B exists alone.

[0099] The above description is only for the purpose of facilitating the understanding of the technical solution of this application by those skilled in the art and is not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the principles of this application shall be included in the scope of protection of this application.

Claims

1. A memory access device, characterized in that: The memory access device includes a scheduling module, a control module, a first cache module and a second cache module; The scheduling module is configured to distribute the memory access instructions in the instruction queue to the multiple pipelines of the memory access device; The first cache module is configured to cache a first mapping relationship, where the first mapping relationship is a mapping relationship between a virtual address and a physical address carried by the memory access instruction; The control module is configured to query a page table and update a second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor if the memory access instruction currently processed by the multiple pipelines does not hit the first mapping relationship and the memory access instruction is a memory access instruction of the virtual machine monitor; The second cache module is configured to cache the second mapping relationship, where the second mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction of the virtual machine monitor that misses the first mapping relationship.

2. The memory access device according to claim 1, wherein: The memory access instructions of the virtual machine monitor currently processed by the multiple pipelines carry different context identifiers; When the control module queries the page table and updates the second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor, the control module is configured to: querying a page table according to a virtual address carried by a memory access instruction of the virtual machine monitor; The second mapping relationship is updated according to a page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and a context identifier carried by the memory access instruction of the virtual machine monitor.

3. The memory access device according to claim 2, wherein: The control module is further configured to: The memory access instruction of the virtual machine monitor that misses the first mapping relationship is resent to the instruction queue; when the second mapping relationship is updated, the updated second mapping relationship is queried based on the virtual address and context identifier carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

4. The memory access device according to claim 1, wherein: The memory access instructions of the virtual machine monitor currently processed by the multiple pipelines carry the same context identifier; When the control module queries the page table and updates the second mapping relationship in the second cache module according to the memory access instruction of the virtual machine monitor, the control module is configured to: querying a page table according to a virtual address carried by a memory access instruction of the virtual machine monitor; The second mapping relationship is updated according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor.

5. The memory access device according to claim 4, characterized in that: The control module is further configured to: The memory access instruction of the virtual machine monitor that does not hit the first mapping relationship is resent to the instruction queue; when the second mapping relationship is updated, the updated second mapping relationship is queried according to the virtual address carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

6. The memory access device according to claim 4, wherein: The memory access instruction of the virtual machine monitor currently processed by the multiple pipelines includes the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor.

7. The memory access device according to claim 6, wherein: The control module is further configured to: If the memory access instruction of the virtual machine monitor allocated to the plurality of pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor, the memory access instruction of the virtual machine monitor is resent to the instruction queue.

8. The memory access device according to claim 3 or 5, characterized in that: The control module is further configured to: In the case that the updated second mapping relationship is hit, the updated second mapping relationship is cleared.

9. A processor, characterized in that: The processor comprises an instruction fetch unit and a memory access device according to any one of claims 1 to 8, wherein the instruction fetch unit is configured to obtain a memory access instruction and send the memory access instruction to the memory access device.

10. A method for accessing memory, characterized in that: The method comprises: Distributing memory access instructions in the instruction queue to multiple pipelines of the memory access device; If the memory access instruction currently processed by the multiple pipelines does not hit the first mapping relationship in the first cache module and the memory access instruction is a memory access instruction of the virtual machine monitor, query the page table according to the memory access instruction of the virtual machine monitor and update the second mapping relationship in the second cache module; The first mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction, and the second mapping relationship is a mapping relationship between a virtual address and a physical address carried by a memory access instruction of the virtual machine monitor that misses the first mapping relationship.

11. The method according to claim 10, characterized in that The memory access instructions of the virtual machine monitor currently processed by the multiple pipelines carry different context identifiers; The querying of the page table according to the memory access instruction of the virtual machine monitor and updating the second mapping relationship in the second cache module includes: querying a page table according to a virtual address carried by a memory access instruction of the virtual machine monitor; The second mapping relationship is updated according to a page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor and a context identifier carried by the memory access instruction of the virtual machine monitor.

12. The method according to claim 11, characterized in that The method further comprises: The memory access instruction of the virtual machine monitor that misses the first mapping relationship is resent to the instruction queue; when the second mapping relationship is updated, the updated second mapping relationship is queried based on the virtual address and context identifier carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

13. The method according to claim 10, characterized in that The memory access instructions of the virtual machine monitor currently processed by the multiple pipelines carry the same context identifier; The querying of the page table according to the memory access instruction of the virtual machine monitor and updating the second mapping relationship in the second cache module includes: querying a page table according to a virtual address carried by a memory access instruction of the virtual machine monitor; The second mapping relationship is updated according to the page table entry in the page table corresponding to the virtual address carried by the memory access instruction of the virtual machine monitor.

14. The method according to claim 13, characterized in that The method further comprises: The memory access instruction of the virtual machine monitor that does not hit the first mapping relationship is resent to the instruction queue; when the second mapping relationship is updated, the updated second mapping relationship is queried according to the virtual address carried by the memory access instruction of the virtual machine monitor resent to the instruction queue.

15. The method according to claim 13, characterized in that The memory access instruction of the virtual machine monitor currently processed by the multiple pipelines includes the earliest memory access instruction of the virtual machine monitor in the instruction queue in terms of the program instruction sequence of the virtual machine monitor.

16. The method according to claim 15, characterized in that The method further comprises: If the memory access instruction of the virtual machine monitor allocated to the plurality of pipelines is not the earliest memory access instruction in the program instruction sequence of the virtual machine monitor, the memory access instruction of the virtual machine monitor is resent to the instruction queue.

17. The method according to claim 12 or 14, characterized in that The method further comprises: In the case that the updated second mapping relationship is hit, the updated second mapping relationship is cleared.

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