Method and apparatus for selecting address for memory training

Abstract

The invention relates to a method and apparatus for selecting an address for memory training. Systems, apparatus, articles of manufacture, and methods for selecting addresses for memory training are disclosed. An example non-transitory computer readable medium includes instructions that, when executed, cause a machine to: determine, based on an identification of a second memory address associated with an error, a first memory address for performing memory input / output training thereat; and causing memory input / output training to be performed at the first memory address.

Description

[0001] Related applications

[0002] This application is a continuation-in-part of international application No. PCT / CN2024 / 080233, filed on March 6, 2024. International application No. PCT / CN2024 / 080233 is incorporated herein by reference in its entirety. This application claims priority to international application No. PCT / CN2024 / 080233. Technical Field

[0003] The present disclosure relates generally to dynamic random access memory initialization, and more particularly, to methods and apparatus for selecting addresses for memory training. Background Art

[0004] Dynamic random access memory ("DRAM") is a specific type of volatile memory. When a device with DRAM is powered on, the DRAM must be initialized before it can begin operation. One step in the initialization process is read / write training. DRAM is commonly used as the main memory system in computers, servers, and other digital devices, where it provides temporary storage for data and instructions that are actively being processed by the central processing unit (CPU). DRAM is organized into rows and columns within memory banks, where each memory cell is accessed by selecting a specific row and column address. An example type of DRAM is double data rate (DDR) DRAM, which uses double data rate transmission. DDR memory modules exist in different generations, such as DDR, DDR2, DDR4, and DDR5, with each generation offering improvements in performance, efficiency, and capacity over the previous generation. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a non-transitory computer-readable medium is provided, comprising instructions that, when executed, cause a machine to perform the following operations: determine a first memory address at which to perform memory input / output training based on an identification of a second memory address associated with an error; and cause the memory input / output training to be performed at the first memory address.

[0006] According to one embodiment of the present disclosure, a device is provided, comprising: an interface circuit; machine-readable instructions; and at least one processor circuit, wherein the at least one processor circuit is programmed by the machine-readable instructions to perform the following operations: perform memory input / output training using a first memory address; determine that a result of the memory input / output training is an error; and retry the memory input / output training using a second memory address.

[0007] According to one embodiment of the present disclosure, a method is provided, comprising: performing a read / write training test on a first memory address; in response to a test failure using the first memory address, performing the read / write training test on a second memory address by at least one processor circuit programmed by at least one instruction; and repairing the first memory address by one or more processor circuits in the at least one processor circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an environment in which memory input / output (I / O) training circuitry operates to perform memory I / O training.

[0009] Figure 2 is a block diagram of an example implementation of a memory input / output (I / O) training circuit for performing memory input / output training.

[0010] Figure 3 is a block diagram of an example DDR5 memory subsystem.

[0011] Figure 4 is a block diagram of an example RDIMM DRAM device layout.

[0012] Figure 5 is a block diagram of an example DRAM memory organization hierarchy.

[0013] Figure 6 Example rows and columns in a DRAM bank are shown.

[0014] Figure 7 The memory address used for Write DQ Delay Training is shown.

[0015] Figure 8 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry. Figure 2 Memory I / O training circuit.

[0016] Figure 9 Example operation of the memory I / O training circuit in a use environment is shown.

[0017] Figure 10 is a block diagram of an example processing platform including programmable circuitry configured to run, instantiate, and / or execute Figure 8 Example machine readable instructions and / or execution Figure 8 Example operation to achieve Figure 2 Memory I / O training circuit.

[0018] Figure 11 yes Figure 10 A block diagram of an example implementation of a programmable circuit.

[0019] Figure 12 yes Figure 10 A block diagram of another example implementation of a programmable circuit.

[0020] Figure 13 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, and / or firmware (e.g., Figure 8 The invention also provides a method for distributing the invention to client devices associated with end users and / or consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or other end users such as direct purchasing customers).

[0021] In general, the same reference numerals will be used throughout the various drawings and the accompanying written description to refer to the same or similar parts. The drawings are not necessarily to scale. Rather, the thickness of layers or regions may be exaggerated in the drawings. Although the drawings show layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be imperceptible, blended, and / or irregular. DETAILED DESCRIPTION

[0022] Initializing DRAM and other types of memory involves setting up the computer system's memory subsystem to ensure that the memory modules are correctly configured and ready for use. During the startup process of a computer system, the system firmware (e.g., BIOS) performs a series of tests, including detecting and initializing key hardware components, such as memory modules. The system firmware detects the presence of memory modules installed in the system. The system identifies the type, capacity, and configuration of each memory module, including parameters such as speed, voltage, and timing settings. The memory controller executes memory training algorithms to optimize the timing parameters of the memory modules for reliable data transfer between the memory controller and the memory modules. This includes procedures such as data queue (DQ) delay training, which adjusts the timing of data signals to match the characteristics of the memory modules. The system firmware can perform memory tests to ensure the reliability and integrity of the memory modules. This can involve running memory test modes or performing read / write training to verify data integrity.

[0023] Read / write training optimizes the timing parameters of the memory interface to maximize data transfer rate and reliability. This includes adjusting signal timing, delay settings, and voltage levels to match the characteristics of the memory module and memory controller. The memory controller evaluates the data capture margin for read and write operations. The data capture margin represents the difference between the signal timing and the sampling window, reflecting the reliability of data transfer. When the data capture margin is insufficient, a zero margin error occurs, indicating a potential timing violation and the risk of data errors. When a zero margin error is reported, the memory controller can take corrective measures, such as disabling a specific memory channel.

[0024] For RDIMMs, write DQ delay training is the first training operation to access a DRAM row. The examples disclosed herein are intended to improve memory DQ read / write training to avoid disabling the memory channel when a zero margin error is reported. Instead, they attempt to retry the DQ training process with different settings by modifying the read / write training operation. Typically, during write DQ delay training, if zero margin is reported for any DQ channel, the basic input / output system (BIOS) memory reference code (MRC) attributes the zero margin error to a write data path failure. The MRC reports a fatal write data path error and disables the entire memory channel. Current MRCs do not check whether the zero margin error is caused by a DRAM row failure. Over time, more memory rows age and fail. During a cold start requiring write DQ delay training, if the MRC uses these faulty memory rows during training, the training code will report a zero margin error, which is a fatal error and will cause the system to hang. For a single row failure in DRAM, the probability of a training failure caused by it is 320 defects per million (DPM). The examples disclosed herein are intended to improve DRAM write DQ delay training. If the zero margin error is caused by a DRAM row failure, the zero margin error is recoverable. A postpackage repair (PPR) procedure can be used to repair the DRAM row failure by replacing the failed row with a backup row. The example disclosed in this article records the failed memory addresses during write DQ delay training. Subsequent write DQ delay training avoids these failed addresses and retries training at different addresses. Write DQ delay training then identifies DRAM row failures, and MRC applies PPR to these failed rows to recover the failed DRAM.

[0025] Figure 11 is a block diagram of an example environment 100 in which memory input / output (I / O) training circuitry operates to perform memory I / O training. Example environment 100 includes a processor 105, a memory controller 110 (including memory input / output (I / O) training circuitry 115), and a memory device 120.

[0026] The processor 105 initiates and manages operations in the memory device. The processor 105 initializes the DQ delay training process by sending a specific command to the memory controller 110 to read from or write to the memory device 120.

[0027] The memory controller 110 controls the data flow between the processor 105 and the memory device 120. It interprets commands from the processor 105 and coordinates memory operations accordingly. The memory controller 110 communicates directly with the memory device 120 to perform tasks such as activating rows, selecting columns, and reading or writing data. In DQ delay training, the memory controller 110 generates training patterns and sends them to the memory device 120. These patterns are used to evaluate the timing of the DQ signals relative to the clock signal. The memory controller 110 captures and evaluates the received data to evaluate the effectiveness of the DQ delay adjustment performed by the memory device 120. The DQ delay adjustment process continues to iterate until the optimal delay setting is determined, ensuring that the DQ signal is properly aligned with the clock signal. Once the DQ delay training process is completed, the memory controller 110 can perform additional verification processes to ensure the reliability and stability of the DQ signal timing adjustment.

[0028] The memory I / O training circuit 115 manages row failures in DQ delay training. Figure 2 Let's discuss the memory I / O training circuit 115.

[0029] Memory device 120 (typically a DRAM) stores data and is accessed by memory controller 110. During DQ delay training, memory device 120 adjusts the timing (e.g., delay) of its DQ signal relative to a clock signal under the direction of memory controller 110. Memory device 120 adjusts the delay of its DQ signal based on a received training pattern.

[0030] Figure 2 It is used to perform write DQ latency training on DDR5 Figure 1 1. Block diagram of an example implementation of memory input / output (I / O) training circuit 115. Figure 2 The memory I / O training circuit 115 may be instantiated (e.g., an instance of it is created, caused to exist for any length of time, materialized, realized, etc.) by a programmable circuit such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, Figure 2 The memory I / O training circuit 115 may be instantiated (e.g., an instance of it is created, caused to exist for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) that is constructed and / or configured to perform operations corresponding to the first instruction in response to execution of the second instruction. It should be understood that Figure 2 Some or all of the circuits may thus be instantiated at the same or different times. Figure 2 Some or all of the circuits of can be instantiated, for example, in one or more threads that are executed concurrently on hardware and / or serially on hardware. Figure 2 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0031] The example memory I / O training circuit 115 includes an example address selection circuit 205 , an example training circuit 210 , and an example repair circuit 215 .

[0032] The example address selection circuit 205 determines a first memory address based on an identification of a second memory address associated with an error, for performing memory input / output training at the first memory address. The memory address identifies a row address of a DRAM. The first memory address identifies a row that does not include any memory addresses associated with the error. The address selection circuit 205 identifies a row that does not include any memory addresses associated with errors across multiple memory modules. The second memory address is identified in a list of memory addresses associated with the error. The list of failed memory addresses associated with the error is addresses that have been detected by MRC write DQ delay training, BIOS MRC advanced memory testing, or reliability, availability, and stability (RAS) runtime code and recorded in non-volatile memory. The data structure that records the list of memory addresses associated with the error is a post-package repair (PPR) list. In the next restart when write DQ delay training is required, write DQ delay training checks the PPR repair list to avoid these failed addresses.

[0033] In some examples, the memory I / O training circuit includes a determining means for determining a first memory address at which to perform memory input / output training. For example, the determining means can be implemented by address selection circuit 205. In some examples, the address selection circuit 205 can be implemented by a programmable circuit (e.g., Figure 10For example, the address selection circuit 205 may be implemented by Figure 11 The example microprocessor 1100 executes machine-executable instructions (e.g., at least Figure 8 In some examples, the address selection circuit 205 may be instantiated by hardware logic circuitry that is configured and / or constructed to perform operations corresponding to the machine-readable instructions. Figure 12 The address selection circuit 205 may be implemented by an ASIC, XPU, or FPGA circuit 1200. Additionally or alternatively, the address selection circuit 205 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the address selection circuit 205 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured and / or constructed to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0034] The example training circuit 210 performs memory I / O training on a selected memory address. If the memory I / O training fails or a zero-margin error is detected, the training circuit 210 performs memory I / O training on another memory address. The training circuit 210 determines whether the result of the memory I / O training is an error and retries the memory I / O training using the second memory address. Memory training includes performing a read / write training test on a first memory address. In response to a test failure using the first memory address, a read / write training test is performed on a second memory address.

[0035] In some examples, the memory I / O training circuit includes means for performing memory input / output training. For example, the means for performing memory input / output training can be implemented by training circuit 210. In some examples, training circuit 210 can be implemented by a programmable circuit (e.g., Figure 10 For example, the training circuit 210 may be instantiated by Figure 11 The example microprocessor 1100 executes machine-executable instructions (e.g., at least Figure 8 In some examples, the training circuit 210 may be instantiated by hardware logic circuitry that is configured and / or constructed to perform operations corresponding to the machine-readable instructions. Figure 12The training circuit 210 may be implemented by an ASIC, XPU, or FPGA circuit 1200. Additionally or alternatively, the training circuit 210 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the training circuit 210 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured and / or constructed to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0036] The example repair circuit 215 repairs the memory address after determining an error after memory input / output training. When a read / write training test causes a fault on the first memory address, the first memory address is repaired. During write DQ delay training, the faulty address will be stored in the PPR repair list. Once write DQ delay training has passed, the MRC applies PPR to these faulty addresses to recover the faulty DRAM. PPR is a DRAM row sparing feature that replaces a faulty row with a spare row (also known as a PPR resource). PPR is intended to improve memory reliability and availability.

[0037] In some examples, the memory I / O training circuit 115 includes a repair device for repairing the memory address. For example, the repair device can be implemented by the repair circuit 215. In some examples, the repair circuit 215 can be implemented by a programmable circuit (e.g., Figure 10 For example, the repair circuit 215 may be implemented by Figure 11 The example microprocessor 1100 executes machine-executable instructions (e.g., at least Figure 8 In some examples, the repair circuit 215 may be instantiated by hardware logic circuitry that is configured and / or constructed to perform operations corresponding to the machine-readable instructions. Figure 12ASIC, XPU, or FPGA circuit 1200. Additionally or alternatively, repair circuit 215 may be instantiated by any other combination of hardware, software, and / or firmware. For example, repair circuit 215 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured and / or constructed to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0038] Although Figure 2 The diagram shows the implementation Figure 1 Example of a memory I / O training circuit, but Figure 2 One or more of the elements, processes, and / or devices shown in the examples may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Additionally, the example address selection circuit 205, the example training circuit 210, and the example repair circuit (and / or more generally, Figure 2 The example memory I / O training circuit 115 of the present invention may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example address selection circuit 205, the example training circuit 210, the example repair circuit 215, and / or more generally the example memory I / O training circuit 115 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPUs), digital signal processor(s) (DSPs), ASIC(s), programmable logic device(s) (PLDs), and / or field programmable logic device(s) (FPLDs) (e.g., FPGAs). Furthermore, Figure 2 An example memory I / O training circuit 115 may include, in addition to Figure 2 In addition to or in place of those shown in Figure 2 , and / or may include more than one of the illustrated elements, processes, and / or devices, and / or may include any or all of more than one of the illustrated elements, processes, and devices.

[0039] Figure 3 is a block diagram of an example double data rate 5 (DDR5) memory subsystem for controlling and accessing external memory devices. Figure 3 In the example shown, the DDR5 memory subsystem 300 includes: an example processor 105 including four example DDR5 integrated memory controllers (iMCs) 110A, 110B, 110C, 110D; two example DDR5 channels 310, 320 for each iMC; and example external dual in-line memory modules (DIMMs) 120A, 120B. The two DDR5 channels 310, 320 are in Figure 3 1 and 1. Each channel is populated with two DDR5 DIMMs 120A and 120B. These components are interconnected via internal and external buses. The memory physical address structure is organized as a hierarchy of <memory controller, channel, sub-channel, DIMM, rank, DRAM, bank group, bank, row, column>.

[0040] The central processing unit (CPU) 105 may be integrated with multiple memory controllers that are responsible for converting CPU memory access requests or training engine memory access requests into JEDEC (Joint Electron Device Engineering Council) compatible commands and addresses to access external memory. The memory controller 110A is connected to the DDR5 physical layer, which is responsible for transferring the logic signals from the memory controller 110A into analog signals for external DIMMs 120A, 120B access, and vice versa. The memory controller 110A and the DDR5 physical layer consist of multiple independent channels and sub-channels for simultaneous data transmission. Each sub-channel (e.g., Channel 0 and Channel 1) will extend the connection to the external DIMMs 120A, 120B through the DDR5 bus.

[0041] Figure 4 is a block diagram of an example layout of an RDIMM DRAM device 120. The RDIMM DRAM device 120 includes two sub-channels 310, 320 (e.g., Channel 0 and Channel 1), a row-to-column delay 405, a command / address bus 410, 415, and a data bus 420, 440 (for Channel 0 and Channel 1, respectively). Within each sub-channel 310, 320 (e.g., Channel 0 or Channel 1), there are two maximum registered DIMMs (RDIMMs), and for each RDIMM, there are two maximum DDR5 ranks 460, 465. Figure 4Only one RDIMM is shown per channel. A rank is a group of DRAM devices. Each rank includes a group of memory chips that are accessed together as a unit.

[0042] exist Figure 4 In the example shown, each rank 460 or 465 in the x4 RDIMM 120 includes ten x4 DRAM devices (eg, 430 or 450) that can drive a sub-channel's x32 data width and x8 error correction code (ECC).

[0043] Figure 5 FIG1 is a block diagram of an example DRAM memory organization hierarchy 500. DRAM device memory is organized in a hierarchy of bank groups and banks. Each DRAM 120 includes several bank groups, and each bank group includes several banks. Banks are organized into bank groups to support interleaved access, which increases parallelism within the DRAM 120, thereby increasing I / O bandwidth.

[0044] exist Figure 5 In the example shown, the x4 DRAM 120 includes eight memory groups (e.g., memory group 0, memory group 1, memory group 2, memory group 3, memory group 4, memory group 5, memory group 6, memory group 7), and each memory group includes four memory banks (e.g., memory bank 0, memory bank 1, memory bank 2, memory bank 3).

[0045] Figure 6 Example rows and columns in a DRAM bank 600 are shown, which includes a row address decoder 605, a column address decoder 610, a sense amplifier 615, and a charge storage unit 620. The DRAM bank 600 is typically arranged in a rectangular array of charge storage units 620. Long horizontal lines 625 are called rows and are accessed simultaneously. Each vertical line 630 is called a bit column. The bit column 630 connects one DRAM cell 620 from each row to a sense amplifier 615. The DRAM cell 620 stores data as charge in a capacitor. The sense amplifier 615 reads or manipulates the value of the DRAM cell by sampling or driving the bit column. For DDR5 X4 DRAM, four bit columns form an X4 column. During a DDR5 read / write operation on an X4 DRAM, 4 bits of data from the <row, X4 column> address are read / written during one clock unit interval (UI), and 16 consecutive X4 columns from a row are bursted through a read / write, forming 8 bytes of data.

[0046] exist Figure 6 In the example shown, the row address decoder 605 is used to decode the row address based on the address of the memory controller 110 ( Figure 1) to select a specific row within the DRAM bank 600. When the memory controller 110 sends a memory access request, it includes both a row address and a column address. The row address decoder 605 decodes the row address and activates the corresponding row in the DRAM bank 600. Once a row is activated, the data stored in that row is available for read or write operations.

[0047] The column address decoder 610 is used to select a specific column within the activated row to access the required data. After the row is activated, the memory controller 110 sends the column address to the DRAM 600. The column address decoder 610 decodes the column address and selects the appropriate column within the activated row. Once a column is selected, the data in that column can be read or written.

[0048] Figure 7 Memory addresses 700 used by memory testing during DDR5 write data queue (DQ) latency training are shown. DDR5 write DQ latency training is performed column-by-column. Each column group includes eight bank groups (501-508), each bank group has four banks, and each bank has 16 rows and 32 columns. In each bank group, the BIOS MRC selects the memory cells located in bank 0 and row 0 of the memory module for testing. The BIOS can continue testing other memory cells by incrementing the address by bank group and column while keeping the bank number and row number at 0. For example, address 710 tests bank 0, row 0, and column 0, address 712 tests bank 0, row 0, and column 1, and address 714 tests bank 0, row 0, and column 31.

[0049] During write DQ delay training, if any memory address in the address pattern fails, the data will be corrupted and the memory test will report a test failure for all write DQ DQS delay timing values. The BIOS MRC training algorithm will report zero margin for write DQ delay training. If a 4Gb x4 DRAM fails in one row, the failed row falls into Figure 7 The probability of the address pattern is 1 / 2 18 If the DIMMS is x4 DIMMS and each channel has a maximum of 4 ranks, the probability of failure per channel will be 20*4*(1 / 2 18 ), which is 320 defects per million (DPM).

[0050] exist Figure 8 1 and 2. There are shown in FIG. 1(a) a flow chart or flowcharts representing methods that may be executed by a programmable circuit to implement and / or instantiate Figure 2 Example machine readable instructions of the memory I / O training circuit 115 and / or representative instructions executable by programmable circuitry to implement and / or instantiate Figure 2Example operation of the memory I / O training circuit 115. The machine-readable instructions may be one or more executable programs or (one or more) parts of one or more executable programs for execution by programmable circuits, such as the ones described below. Figure 10 The programmable circuit 1012 shown in the example processor platform 1000 discussed below and / or may be Figure 11 and / or Figure 12 The example programmable circuits (e.g., FPGAs) discussed herein are intended to perform one or more functions or portions of functions. In some examples, machine-readable instructions cause operations, tasks, and the like to be performed and / or executed in an automated manner in the real world. As used herein, "automated" means without human involvement.

[0051] The program may be embodied as instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray discs, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable medium may program programmable circuitry located in one or more hardware devices and / or be executed by such circuitry, but the entire program and / or portions thereof may alternatively be executed and / or instantiated by one or more hardware devices other than programmable circuitry, and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer-readable storage medium may include one or more media. Additionally, while reference is made to Figure 8The example program is described using the flowchart(s) shown in the flowchart(s), but many other methods of implementing the example memory I / O training circuit 115 may be used instead. For example, the order of execution of the blocks of the flowchart(s) may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to perform the corresponding operations without executing software or firmware. The programmable circuits may be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuitry may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination (one or more) of these.

[0052] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, and the like), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, and the like), and the like) or a data structure (e.g., as part(s) of instructions, code, code representation, and the like) that can be utilized to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations on a network or collection of networks (e.g., in the cloud, in an edge device, and the like). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, and the like in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations (which together may form a program, such as that described herein).

[0053] In another example, machine-readable instructions may be stored in a state in which they can be read by programmable circuitry, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or corresponding program(s) may need to be configured (e.g., to store settings, input data, record network addresses, etc.) before the machine-readable instructions and / or corresponding program(s) can be executed in whole or in part. Thus, as used herein, a machine-readable, computer-readable, and / or machine-readable medium may include instructions and / or program(s) regardless of the particular format or state of the machine-readable instructions and / or program(s).

[0054] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented by any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0055] As mentioned above, Figure 8The example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transient computer-readable and / or machine-readable media. As used herein, the terms non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium, and / or non-transient machine-readable storage medium are explicitly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and exclude transmission media. Examples of such non-transient computer-readable media, non-transient computer-readable storage medium, non-transient machine-readable medium, and / or non-transient machine-readable storage medium include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for a longer period of time, permanent storage, short-term storage, for temporary buffering, and / or for caching of information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware that retains information over a period of time, but excludes propagating signals and excludes transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, that may or may not be configured with computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0056] Figure 8 is a flow diagram representative of example machine-readable instructions and / or example operations 800 that may be executed, instantiated, and / or performed by programmable circuitry to perform memory input / output training. Figure 8 The example machine readable instructions and / or example operations 800 begin at block 802, where the example address selection circuitry 205 obtains a list of failing addresses. The address selection circuitry 205 selects an address that is not included in the list (block 804).

[0057] The example training circuit 210 performs training on the DRAM using the selected address (block 806). The training can be write DQ delay training on the DRAM or any other memory training. The training circuit 210 detects whether an error is reported from the training (block 808). If no error is reported (block 808: No), then Figure 8 The instruction and / or operation 800 ends. If a training error is reported (block 808: yes), the training circuit 210 retries the training at a different address (block 810). In some examples, the retried training may be performed at a different row address. The training circuit 210 continues to try different row addresses until a retry threshold is reached. If the training circuit 210 has not yet reached the retry threshold (block 811: no), control returns to block 808 to determine whether an error is detected in the retry training at the new row address. If the retry threshold is reached (block 811: yes), the training circuit 210 concludes that the training error is not due to an internal DRAM row failure, but is a zero margin error caused by an interconnect or input-output (IO) failure. The training circuit 210 determines whether a zero margin error is reported (block 812). If a zero margin error is reported (block 812: yes), the memory controller 110 ( Figure 1 ) The error is handled by adjusting the write DQ delay setting (block 814), which fine-tunes the delay setting of the DQ line to optimize the timing of the write operation. The memory controller 110 can increase or decrease the delay value to find the optimal setting that provides sufficient data capture margin. Figure 8 The instructions and / or operations 800 end.

[0058] If no zero margin error is reported (block 812: NO), the example repair circuit 215 applies post-package repair (PPR) to the faulty row (block 816). The repair circuit 215 determines whether hard PPR or soft PPR is required (block 818). If hard PPR is required (block 818: HARD), the repair circuit 215 replaces the faulty row with a spare row. Figure 8 The instruction and / or operation 800 ends. If soft PPR is required (block 818: SOFT), the repair circuit 215 saves the failing address to the PPR repair list (block 820). Figure 8 The instructions and / or operations 800 end.

[0059] Figure 9Example operations 900 using memory I / O training circuitry in an environment are shown. The example operations 900 include an example memory controller 110 (including an example memory I / O training circuitry 115), an example DDR5 DRAM 120, and an example DDR5 physical layer 902. For example, the memory controller 110 can correspond to any of the memory controllers 110A, 110B, 110C, 110D described above. The DDR5 DRAM 120 can correspond to any of the DDR5 DRAMs 120A, 120B, 430, 450 described above. In write DQ latency training, a memory test algorithm tests memory subsystem data transfers to see if the data write path can successfully transfer data at specific timing values.

[0060] In the illustrated example operation 900, the memory controller 110 manages the processor 105 ( Figure 1 ) and the memory module 120. The memory controller 110 handles tasks such as issuing commands, controlling the timing of data transfers, and managing the flow of data between the processor 105 and the memory module 120. The memory controller is responsible for translating CPU memory access requests or training engine memory access requests into JEDEC (Joint Electron Device Engineering Council) compliant commands and addresses to access the external memory 120 (e.g., DRAM).

[0061] The example memory I / O training circuit 115 creates specific command sequences to send to the DDR5 memory module 120. These commands, including read, write, activate, and precharge, are necessary to access and modify data stored in memory cells. Prior to write DQ delay training, all command, control, read, and write DQS signals have been trained for proper operation. The BIOS MRC configures the memory I / O training circuit 115 to generate specific write and read command sequences to write a predefined data pattern to the DRAM and then read it back. The memory I / O training circuit 115 generates a write command sequence for a selected memory address on the DIMM, along with a specific data pattern. The memory I / O training circuit 115 sends the command sequence address 904 to the DRAM 120 via the control / command / address path 906 in the DDR5 physical layer 902. Data in the write data buffer 908 is transferred to the DRAM via the example data write path 910 to the DRAM 120. After the data pattern has been written to the DRAM 120, the memory I / O training circuit 115 generates a read command sequence to read back the data that has been written. The data from the DRAM 120 will be read back through the data read path 912 and stored in the read data buffer 914. The memory I / O training circuit 115 compares the read back data with the predefined data pattern to check whether there are any errors during the data transmission. If there is a data error, the BIOS MRC marks the current write DQ delay training value as a fault timing value. The current BIOS MRC algorithm assumes that the DRAM memory cells are healthy and that all data errors are attributed to the write DQ delay timing of the DDR5 physical layer. But in reality, if any DRAM memory cell used by the memory test fails, the data will also be damaged, and the memory test will also report a test failure for all write DQ delay timing values. The BIOS MRC training algorithm will report a zero margin for write DQ delay training.

[0062] exist Figure 9 In the example shown, the memory I / O training circuit 115 sends command and address instructions to the control / command / address path 906 via the example DDR5 memory controller (MC) physical layer interface 916. The DDR5 physical layer 902 converts the logical signals into analog signals for transmission to the DDR5 DRAM 120. The DDR5 physical layer 902 communicates with the DRAM 120 via the example external DDR5 bus 918.

[0063] DDR5 write DQ latency training is performed on a column-by-column basis. To achieve maximum input / output performance, the BIOS MRC will configure the memory I / O training circuit 115 to access DRAM banks in an interleaved manner, meaning that adjacent write / read commands are written to different bank groups.

[0064] Figure 10 is a block diagram of an example programmable circuit platform 1000 that is configured to execute and / or instantiate Figure 8 Example machine readable instructions and / or example operations to implement Figure 2 The programmable circuit platform 1000 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smart phone, an iPad, etc.). TM ), a personal digital assistant (PDA), an internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, headphones (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0065] The programmable circuit platform 1000 of the illustrated example includes a programmable circuit 1012. The programmable circuit 1012 of the illustrated example is hardware. For example, the programmable circuit 1012 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit 1012 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit 1012 implements the address selection circuit 205, the training circuit 210, and the repair circuit 215 and / or the memory I / O training circuit 115.

[0066] The programmable circuit 1012 of the illustrated example includes a local memory 1013 (e.g., cache, registers, etc.). The programmable circuit 1012 of the illustrated example communicates with main memories 1014 and 1016, including a volatile memory 1014 and a non-volatile memory 1016, via a bus 1018. The volatile memory 1014 can be a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), or a non-volatile memory. Dynamic Random Access Memory (DRAM) DynamicRandom Access Memory, ) and / or any other type of RAM device. The non-volatile memory 1016 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 1014, 1016 of the illustrated example is controlled by a memory controller 1017. In some examples, the memory controller 1017 can be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit to manage the flow of data into and out of the main memories 1014, 1016.

[0067] The programmable circuit platform 1000 of the illustrated example further includes an interface circuit 1020. The interface circuit 1020 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0068] In the illustrated example, one or more input devices 1022 are connected to the interface circuit 1020. The input device(s) 1022 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit 1012. The input device(s) 1022 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0069] One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. The output device(s) 1024 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuit 1020 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit, such as a GPU.

[0070] The interface circuitry 1020 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate data exchange with external machines (e.g., any type of computing device) over the network 1026. Communication can occur via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, and the like.

[0071] The programmable circuit platform 1000 of the illustrated example also includes one or more mass storage disks or devices 1028 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1028 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices (e.g., flash memory devices and / or SSDs).

[0072] can be Figure 8 The machine-readable instructions 1032 implemented by the machine-readable instructions may be stored in the mass storage device 1028, in the volatile memory 1014, in the non-volatile memory 1016, and / or on at least one removable non-transitory computer-readable storage medium such as a CD or DVD.

[0073] Figure 11 yes Figure 10 1012. In this example, Figure 10 The programmable circuit 1012 is implemented by the microprocessor 1100. For example, the microprocessor 1100 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit). The microprocessor 1100 executes Figure 8A portion or all of the machine-readable instructions of a flowchart to effectively Figure 2 In some such examples, the circuits are instantiated as logic circuits to perform operations corresponding to these machine-readable instructions. Figure 2 The circuit is instantiated by the hardware circuit of the microprocessor 1100 in combination with machine-readable instructions. For example, the microprocessor 1100 can be implemented by a multi-core hardware circuit, such as a CPU, DSP, GPU, XPU, and the like. Although it may include any number of example cores 1102 (e.g., 1 core), the microprocessor 1100 of this example is a multi-core semiconductor device including N cores. The cores 1102 of the microprocessor 1100 can operate independently or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1102, or may be executed by multiple cores in the cores 1102 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores in the cores 1102. The software program may correspond to Figure 8 The flowcharts may represent part or all of the machine-readable instructions and / or operations.

[0074] The cores 1102 can communicate via a first example bus 1104. In some examples, the first bus 1104 can be implemented by a communication bus to enable communications associated with one (or more) of the cores 1102. For example, the first bus 1104 can be implemented by at least one of an Inter-Integrated Circuit (IC) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1104 can be implemented by any other type of computing or electrical bus. The cores 1102 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit 1106. The cores 1102 can output data, instructions, and / or signals to one or more external devices via the interface circuit 1106. While the cores 1102 of this example include example local memory 1120 (e.g., a level 1 (L1) cache that may be partitioned into an L1 data cache and an L1 instruction cache), the microprocessor 1100 also includes example shared memory 1110 (e.g., a level 2 (L2 cache)) that may be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1110. The local memory 1120 and shared memory 1110 of each core 1102 may be a plurality of levels of cache memory and main memory (e.g., Figure 10 Cache memory is part of a hierarchy of storage devices (e.g., main memory 1014, 1016). Typically, higher-level memory in the hierarchy exhibits lower access times and has smaller storage capacity than lower-level memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0075] Each core 1102 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit. Each core 1102 includes a control unit circuit 1114, an arithmetic and logic (AL) circuit (sometimes referred to as an ALU) 1116, a plurality of registers 1118, a local memory 1120, and a second example bus 1122. Other structures may also exist. For example, each core 1102 may include a vector unit circuit, a single instruction multiple data (SIMD) unit circuit, a load / store unit (LSU) circuit, a branch / jump unit circuit, a floating-point unit (FPU) circuit, etc. The control unit circuit 1114 includes semiconductor-based circuitry configured to control (e.g., coordinate) data movement within the corresponding core 1102. The AL circuit 1116 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1102. Some examples of the AL circuit 1116 perform integer-based operations. In other examples, AL circuit 1116 also performs floating-point operations. In still other examples, AL circuit 1116 may include a first AL circuit that performs integer-based operations and a second AL circuit that performs floating-point operations. In some examples, AL circuit 1116 may be referred to as an arithmetic logic unit (ALU).

[0076] Registers 1118 are semiconductor-based structures used to store data and / or instructions, such as the results of one or more operations performed by the AL circuit 1116 of the corresponding core 1102. For example, registers 1118 may include vector register(s), SIMD register(s), general register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. Registers 1118 may include vector register(s), SIMD register(s), general register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. Figure 11 11. The registers 1118 are shown arranged as bank groups. Alternatively, the registers 1118 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 1102 to reduce access time. The second bus 1122 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0077] Each core 1102 and / or more generally the microprocessor 1100 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)), and / or other circuits. The microprocessor 1100 is a semiconductor device that is fabricated to include many interconnected transistors to implement the aforementioned structures in one or more integrated circuits (ICs) contained in one or more packages.

[0078] The microprocessor 1100 may include and / or cooperate with one or more accelerators (e.g., acceleration circuits, hardware accelerators, etc.). In some examples, the accelerator is implemented by logic circuits to perform certain tasks more quickly and / or efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on-board the microprocessor 1100, in the same chip package as the microprocessor 1100, and / or in one or more packages separate from the microprocessor 1100.

[0079] Figure 12 yes Figure 10 FIG. 1 is a block diagram of another example implementation of a programmable circuit 1012. In this example, the programmable circuit 1012 is implemented by an FPGA circuit 1200. For example, the FPGA circuit 1200 can be implemented by an FPGA. For example, the FPGA circuit 1200 can be used to perform operations that would otherwise be performed by Figure 11 The exemplary microprocessor 1100 of FIG. 1 is used to execute corresponding machine-readable instructions. However, once configured, the FPGA circuit 1200 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware, thereby often performing the operations / functions faster than a general-purpose microprocessor could execute corresponding software.

[0080] More specifically, Figure 11 The microprocessor 1100 (which is a general-purpose device that can be programmed to perform Figure 8 Compared to a flowchart (which represents part or all of the machine-readable instructions, but whose interconnections and logic circuits are fixed once they are manufactured), Figure 12 The example FPGA circuit 1200 includes interconnects and logic circuits that can be configured, constructed, programmed, and / or interconnected in different ways after fabrication to instantiate, for example, Figure 8 The FPGA circuit 1200 may be thought of as an array of logic gates, interconnects, and switches. The switches may be programmed to change the way the logic gates are interconnected, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit 1200 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuits. These operations may correspond to Figure 8 Thus, the FPGA circuit 1200 may be configured and / or constructed to effectively communicate with the Figure 8 A portion or all of the operations / functions corresponding to the machine-readable instructions of the flowchart are instantiated as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner similar to an ASIC. Figure 8 The speed at which some or all of the machine-readable instructions correspond to operations / functions may be faster than the speed at which a general-purpose microprocessor can execute those instructions.

[0081] exist Figure 12 In some examples, the FPGA circuit 1200 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHSIC Hardware Description Language, VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted into a binary file (e.g., by a compiler, a software application, etc.). In some examples, Figure 12 The FPGA circuit 1200 can access and / or load a binary file so that Figure 12The FPGA circuit 1200 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be provided by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or Figure 12 The FPGA circuit 1200 is accessible to machine-readable instructions to cause the Figure 12 The configuration and / or construction of the FPGA circuit 1200 or (one or more) parts thereof.

[0082] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output from a unified software platform utilized to program the FPGA. For example, the unified software platform may translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to the one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 12 The FPGA circuit 1200 can access and / or load a binary file so that Figure 12 The FPGA circuit 1200 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be provided by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or Figure 12 The FPGA circuit 1200 is accessible to machine-readable instructions to cause the Figure 12 The configuration and / or construction of the FPGA circuit 1200 or (one or more) parts thereof.

[0083] Figure 12The FPGA circuit 1200 includes example input / output (I / O) circuitry 1202 to obtain data from and / or output data to example configuration circuitry 1204 and / or external hardware 1206. For example, the configuration circuitry 1204 may be implemented by an interface circuit that may obtain a binary file that may be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuitry 1200, or (one or more) portions thereof. In some such examples, the configuration circuitry 1204 may obtain the binary file from a user, a machine (e.g., a hardware circuit (e.g., a programmed or dedicated circuit) that may implement an Artificial Intelligence / Machine Learning (AI / ML) model to generate a binary file), etc. and / or any (one or more) combinations of these. In some examples, the external hardware 1206 may be implemented by an external hardware circuit. For example, the external hardware 1206 may be implemented by Figure 11 The microprocessor 1100 is implemented.

[0084] FPGA circuit 1200 also includes an array of example logic gate circuits 1208, a plurality of example configurable interconnects 1210, and example storage circuits 1212. Logic gate circuits 1208 and configurable interconnects 1210 can be configured to instantiate Figure 8 At least some of the machine-readable instructions correspond to one or more operations / functions, and / or other desired operations. Figure 12 The logic gate circuits 1208 shown in FIG are fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Within each logic gate circuit 1208, there are electrically controllable switches (e.g., transistors) so that the electrical structures and / or logic gates can be configured to form circuits to perform desired operations / functions. The logic gate circuits 1208 may include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, and the like.

[0085] The configurable interconnect 1210 of the illustrated example is a conductive path, trace, via, or the like, which may include an electrically controllable switch (e.g., a transistor) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuits 1208 to program the desired logic circuit.

[0086] The storage circuit 1212 of the illustrated example is configured to store the result(s) of one or more operations performed by the corresponding logic gates. The storage circuit 1212 may be implemented by registers or the like. In the illustrated example, the storage circuit 1212 is distributed among the logic gate circuits 1208 to facilitate access and increase execution speed.

[0087] Figure 12 The example FPGA circuit 1200 also includes an example dedicated operation circuit 1214. In this example, the dedicated operation circuit 1214 includes a dedicated circuit 1216 that can be called to implement common functions to avoid the need to program these functions on site. Examples of such dedicated circuits 1216 include memory (e.g., DRAM) controller circuits, PCIe controller circuits, clock circuits, transceiver circuits, memories, and multiplier-accumulator circuits. Other types of dedicated circuits may also exist. In some examples, the FPGA circuit 1200 may also include an example general-purpose programmable circuit 1218, such as an example CPU 1220 and / or an example DSP 1222. Other general-purpose programmable circuits 1218 may exist additionally or alternatively, such as a GPU, XPU, etc., which can be programmed to perform other operations.

[0088] Although Figure 11 and Figure 12 Pictured Figure 10 These are two example implementations of the programmable circuit 1012, but many other implementations are contemplated. For example, an FPGA circuit may include an onboard CPU, such as Figure 12 One or more example CPUs 1220. Thus, Figure 10 The programmable circuit 1012 may additionally be configured by combining at least Figure 11 An example microprocessor 1100 and Figure 12 In some such hybrid examples, Figure 11 One or more cores 1102 can execute Figure 8 a first portion of the machine-readable instructions represented by the flowchart(s) to perform(s) a first operation / function(s), Figure 12 The FPGA circuit 1200 may be configured and / or constructed to perform with Figure 8 The second operation(s) / function(s) corresponding to the second portion of the machine-readable instructions represented by the flowchart of the embodiment of the present invention may be performed by the ASIC, and / or the ASIC may be configured and / or constructed to perform the second operation / function(s) corresponding to the second portion of the machine-readable instructions represented by the flowchart of the embodiment of the present invention ... Figure 8 The third portion of the machine-readable instructions represented by the flowchart corresponds to (one or more) third operations / functions.

[0089] It should be understood that Figure 2Some or all of the circuits may thus be instantiated at the same or different times. For example, Figure 11 The same and / or different portions of the microprocessor 1100 may be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, Figure 12 The same and / or different portions of the FPGA circuit 1200 may be configured and / or constructed to perform operations / functions corresponding to the portions of the machine-readable instructions at the same and / or different times.

[0090] In some examples, the code may be instantiated, for example, in one or more threads that execute concurrently and / or serially. Figure 2 For example, Figure 11 The microprocessor 1100 can execute machine-readable instructions in one or more threads of execution simultaneously and / or serially. In some examples, Figure 12 The FPGA circuit 1200 can be configured and / or constructed to perform operations / functions simultaneously and / or serially. In addition, in some examples, Figure 2 Some or all of the circuitry may be Figure 11 The microprocessor 1100 is implemented within one or more virtual machines and / or containers.

[0091] In some examples, Figure 10 The programmable circuit 1012 can be in one or more packages. For example, Figure 11 The microprocessor 1100 and / or Figure 12 The FPGA circuit 1200 can be in one or more packages. In some examples, the XPU can be composed of Figure 10 The XPU may be implemented as a programmable circuit 1012, which may be in one or more packages. For example, the XPU may include a CPU in one package (e.g., Figure 11 Microprocessor 1100, Figure 12 CPU 1220, etc.), a DSP in another package (e.g., Figure 12 DSP 1222), a GPU in another package, and an FPGA in another package (e.g., Figure 12 FPGA circuit 1200).

[0092] exist Figure 13 A block diagram is shown in FIG. 1 , which illustrates an example software distribution platform 1305 for distributing software such as Figure 10The example software distribution platform 1305 may be implemented by any computer server, data facility, cloud service, etc. that is capable of storing software and transmitting it to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 1305. For example, the entity that owns and / or operates the software distribution platform 1305 may be a software (e.g., a hardware device owned and / or operated by a third party other than the owner and / or operator of the software distribution platform). Figure 10 The third party may be a consumer, user, retailer, OEM, etc. who purchases and / or licenses the software for use and / or resale and / or sublicense. In the illustrated example, the software distribution platform 1305 includes one or more servers and one or more storage devices. The storage device stores the machine-readable instructions 1032, which may correspond to the instructions described above. Figure 8 The example software distribution platform 1305 server or servers are in communication with an example network 1310, which may correspond to the Internet and / or any one or more of the example networks described above. In some examples, one or more servers respond to a request to transfer software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or license of the software may be processed by one or more servers of the software distribution platform and / or by a third-party payment entity. These servers enable purchasers and / or licensors to download machine-readable instructions 1032 from the software distribution platform 1305. For example, Figure 8 Software corresponding to the example machine-readable instructions of the example programmable circuit platform 1000 may be downloaded to the example programmable circuit platform 1000, which is to execute the machine-readable instructions 1032 to implement the memory I / O training circuit 115. In some examples, one or more servers of the software distribution platform 1305 periodically provide, transmit, and / or force software updates (e.g., Figure 10 Example machine readable instructions 1032 of the present invention) to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end-user device. Although referred to as software above, the distributed "software" may alternatively be firmware.

[0093] "Include" and "comprising" (and all forms and tenses thereof) are used as opening terms in this document. Thus, whenever a claim employs any form of "include" or "comprising" (e.g., includes, comprises, having, etc.) as a preamble or used in any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transition term, such as in the preamble of a claim, it is opening in the same way that the terms "include" and "comprising" are opening. The term "and / or" when used, for example, in the form of A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or operation of a process, instruction, act, activity, or the like, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or operation of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0094] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of that object. The terms "a (or an)," "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Furthermore, although individual features may be included in different examples or claims, they may potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0095] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if at least a portion of the second part is between the Earth and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the Earth than the second part. As described above, a first part can be above or below a second part in one or more of the following situations: with other parts between them, without other parts between them, with the first and second parts in contact, or with the first and second parts not in direct contact with each other.

[0096] As used herein, reference to being connected (e.g., attached, coupled, connected, joined) may include reference to intermediate members between the elements referenced by the connection and / or relative movement between such elements, unless otherwise indicated. Thus, reference to being connected does not necessarily infer that two elements are directly connected and / or in a fixed relationship to each other. As used herein, a statement that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0097] Unless otherwise specifically stated, descriptors such as "first," "second," "third," and the like are used herein without importing or otherwise indicating any priority, physical order, arrangement in a list, and / or meaning of being ordered in any manner, but are merely used as labels and / or arbitrary names to distinguish elements so that the disclosed examples are easily understood. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (e.g., "second" or "third") in the claims. In such cases, it should be understood that such descriptors are only used to clearly identify these elements within the context of the discussion (e.g., within the claims), where these elements might otherwise share the same name, for example.

[0098] As used herein, "approximately" and "about" modify the subject matter / value to recognize the potential for variations that occur in real-world applications. For example, "approximately" and "approximately" may modify a dimension that may not be exact due to manufacturing tolerances and / or other real-world imperfections that would be understood by one of ordinary skill in the art. For example, "approximately" and "about" may indicate that such a dimension may be within a tolerance range of + / - 10%, unless otherwise indicated herein.

[0099] As used herein, "substantially real time" means occurring in a nearly instantaneous manner, recognizing that there may be real-world delays in computing time, transmission, etc. Thus, unless otherwise indicated, "substantially real time" means real time + / - 1 second.

[0100] As used herein, the phrase “in communication with”—including variations thereof—encompasses direct communication and / or indirect communication through one or more intermediate components, without requiring direct physical (e.g., wired) communication and / or constant communication, and also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0101] As used herein, “programmable circuitry” is defined as including (i) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) that are constructed to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmed with instructions to perform specific function(s) and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include: a programmable microprocessor, such as a central processor unit (CPU), which can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction so that the FPGA is configured and / or constructed to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit, such as an application specific integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination(s) of these), and coordination technology (e.g., one or more application programming interfaces (APIs)) that can assign(one or more) computing tasks to any one(or more) of the multiple types of programmable circuits that is best suited and available to perform the(one or more) computing tasks.

[0102] As used herein, an integrated circuit is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuit, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), and the like.

[0103] From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that generally relate to dynamic random access memory initialization, and more specifically, to methods and apparatus for improving memory reliability by dynamically selecting memory addresses for write DQ delay training.

[0104] The disclosed systems, apparatus, articles of manufacture, and methods improve memory reliability by dynamically selecting memory addresses for write DQ delay training, thereby improving the efficiency of computing devices. Thus, the disclosed systems, apparatus, articles of manufacture, and methods are intended to provide one or more improvements to the operation of a machine, such as a computer or other electronic and / or mechanical device.

[0105] It should be noted that this patent is a continuation-in-part application of the international application with application number PCT / CN2024 / 080233, and claims priority to the international application with application number PCT / CN2024 / 080233, which was filed on March 6, 2024 and is incorporated herein by reference in its entirety.

[0106] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for improving memory reliability by dynamically selecting memory addresses for write DQ delay training. Further examples and combinations thereof include the following:

[0107] Example 1 includes a non-transitory computer-readable medium comprising instructions that, when executed, cause a machine to perform the following operations: determine a first memory address at which to perform memory input / output training based on an identification of a second memory address associated with an error; and cause memory input / output training to be performed at the first memory address.

[0108] Example 2 includes the non-transitory computer-readable medium of Example 1, wherein the memory address identifies a row.

[0109] Example 3 includes the non-transitory computer readable medium of example 1, wherein the instructions, when executed, cause the machine to determine the first memory address based on the first memory address identifying a row that does not include any memory addresses associated with an error.

[0110] Example 4 includes the non-transitory computer-readable medium of Example 1, wherein the instructions, when executed, cause the machine to perform the following operations: determine the first memory address based on the first memory address identifying a row that does not include any memory addresses associated with errors across multiple memory modules.

[0111] Example 5 includes the non-transitory computer-readable medium of Example 1, wherein the second memory address is identified in a list of memory addresses associated with the error.

[0112] Example 6 includes the non-transitory computer-readable medium of Example 5, wherein the list is a post-packaging repair (PPR) list.

[0113] Example 7 includes the non-transitory computer-readable medium of Example 1, wherein the memory input / output training is write data queue latency training.

[0114] Example 8 includes the non-transitory computer-readable medium of Example 1, wherein the instructions are basic input and output system instructions.

[0115] Example 9 includes the non-transitory computer-readable medium of Example 1, wherein the non-transitory computer-readable medium is a flash memory coupled to the motherboard.

[0116] Example 10 includes the non-transitory computer readable medium of Example 1, wherein the instructions, when executed, cause the machine to perform the following operations: when memory input / output training using the first memory address fails, select a third memory address for memory input / output training.

[0117] Example 11 includes the non-transitory computer readable medium of Example 1, wherein the instructions, when executed, cause the machine to perform the following operations: if the memory input / output training detects a zero margin, select a third memory address for the memory input / output training.

[0118] Example 12 includes an apparatus comprising: an interface circuit; machine-readable instructions; and at least one processor circuit, the at least one processor circuit being programmed by the machine-readable instructions to: perform memory input / output training using a first memory address; determine that a result of the memory input / output training is an error; and retry the memory input / output training using a second memory address.

[0119] Example 13 includes the apparatus of Example 12, wherein, to perform memory input / output training, at least one processor circuit performs the following operations: writing data to a physical memory at a first memory address at a first time; and reading the data stored at the first memory address at a second time later than the first time.

[0120] Example 14 includes the apparatus of Example 13, wherein to perform memory input / output training, the at least one processor circuit performs the following operations: determining an error when the read data does not match the written data.

[0121] Example 15 includes the apparatus of Example 12, wherein the at least one processor circuit causes a repair operation to be performed on the first memory address after determining the error.

[0122] Example 16 includes a method comprising: performing a read / write training test on a first memory address; in response to a test failure using the first memory address, performing a read / write training test on a second memory address by at least one processor circuit programmed by at least one instruction; and repairing the first memory address by one or more processor circuits in the at least one processor circuit.

[0123] Example 17 includes the method of Example 16, further comprising selecting the first memory address based on a list of memory addresses for which errors were previously detected.

[0124] Example 18 includes the method of Example 17, wherein selecting the first memory address comprises determining a row of a plurality of memory modules, wherein the row does not include a memory address on the list having an error for any of the modules.

[0125] Example 19 includes the method of Example 16, wherein performing a read / write training test on a first memory address comprises: writing data to a physical memory at the first memory address at a first time; and reading the data stored at the first memory address at a second time later than the first time.

[0126] Example 20 includes the method of Example 19, further comprising determining that the read / write training test has failed when the read data does not match the written data.

[0127] The appended claims are hereby incorporated into this Detailed Description section by this reference. Although certain example systems, apparatus, articles of manufacture, and methods are disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods that fairly fall within the scope of the claims of this patent.

Claims

1. A non-transitory computer-readable medium comprising instructions that, when executed, cause a machine to: determining a first memory address at which to perform memory input / output training based on an identification of a second memory address associated with an error; and The memory input / output training is caused to be performed at the first memory address.

2. The non-transitory computer-readable medium of claim 1, wherein: The memory address identifies the row.

3. The non-transitory computer-readable medium of claim 1 , wherein: The instructions, when executed, cause the machine to determine the first memory address based on the first memory address identifying a row that does not include any memory addresses associated with an error.

4. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: The instructions, when executed, cause the machine to determine the first memory address based on the first memory address identifying a row that does not include any memory addresses associated with errors across multiple memory modules.

5. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: The second memory address is identified in a list of memory addresses associated with errors.

6. The non-transitory computer readable medium of claim 5, wherein: The list is a Post-Package Repair (PPR) list.

7. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: The memory input / output training is write data queue delay training.

8. The non-transitory computer readable medium of claim 1, wherein: The instructions are basic input and output system instructions.

9. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: The non-transitory computer readable medium is a flash memory coupled to the motherboard.

10. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: When executed, the instructions cause the machine to perform the following operations: if the memory input / output training using the first memory address fails, select a third memory address for the memory input / output training.

11. The non-transitory computer readable medium according to any one of claims 1 to 3, wherein: The instructions, when executed, cause the machine to perform the following operations: if the memory input / output training detects a zero margin, select a third memory address for the memory input / output training.

12. A device comprising: Interface circuit; machine-readable instructions; as well as at least one processor circuit programmed by the machine-readable instructions to: performing memory input / output training using the first memory address; determining that a result of the memory input / output training is an error; as well as The memory input / output training is retried using the second memory address.

13. The device according to claim 12, wherein To perform the memory input / output training, the at least one processor circuit performs the following operations: writing data to a physical memory at a first memory address at a first time; as well as Data stored at the first memory address is read at a second time later than the first time.

14. The device according to claim 13, wherein To perform the memory input / output training, the at least one processor circuit determines the error when the read data does not match the written data.

15. The device according to any one of claims 12 to 14, wherein The at least one processor circuit causes a repair operation to be performed on the first memory address after determining the error.

16. A method comprising: performing a read / write training test on the first memory address; in response to a test failure using the first memory address, performing, by at least one processor circuit programmed by at least one instruction, the read / write training test on a second memory address; as well as The first memory address is repaired by one or more processor circuits of the at least one processor circuit.

17. The method according to claim 16, further comprising: The first memory address is selected based on a list of memory addresses for which errors were previously detected.

18. The method according to claim 17, wherein Selecting the first memory address includes determining a row of a plurality of memory modules, wherein, for any of the modules, the row does not include a memory address on the list having an error.

19. The method according to claim 16, wherein Performing the read / write training test on the first memory address includes: writing data to physical memory at a first memory address at a first time; and Data stored at the first memory address is read at a second time later than the first time.

20. The method according to claim 19, further comprising: When the read data does not match the written data, it is determined that the read / write training test has failed.

21. The method according to any one of claims 16 to 20, wherein The at least one processor circuit causes a repair operation to be performed on the first memory address after determining the error.

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