LDPC (Low Density Parity Check) correction method and system for NAND flash error interval

Abstract

The invention provides an LDPC (Low Density Parity Check) correction method and system for an error interval of an NAND flash memory, and the method comprises the steps: recognizing an abnormal interval expansion trend of the NAND flash memory, recognizing an error code interval according to a data writing task of the flash memory, and judging whether an error code occurs in an interval, in which data is stored, in the flash memory or not; adjusting the LDPC correction of the flash memory according to the error code interval and the reading quality of data received by the flash memory, and adjusting the return state of a data reading result according to the execution state of the LDPC correction to ensure that the read return data is correct; according to information that LDPC correction is not completed in the power-on process of the flash memory, an LDPC correction guide is generated, and the LDPC correction operation on the flash memory is adjusted according to a task instruction received after the flash memory is powered on again, so that all error code intervals in the flash memory are effectively corrected, the intervals with data errors in the flash memory are prevented from being continuously increased and accumulated, and the error correction efficiency of the flash memory is improved. The overall data storage reliability of the NAND flash memory is improved, and the data reading / writing correctness of the NAND flash memory is ensured.

Description

Technical Field

[0001] The present invention relates to the field of storage device management, and in particular to an LDPC correction method and system for a NAND flash memory error interval. Background Art

[0002] NAND-Flash memory utilizes a nonlinear macrocell model, providing an effective solution for implementing inexpensive, solid-state, high-capacity memory. Its high capacity and fast rewrite speed have led to its widespread adoption. As NAND flash memory shrinks in size, the error rate of information storage increases. To improve the accuracy of NAND flash data storage, error correction algorithms are required to correct erroneous data. Low-density parity-check (LDPC) code technology offers low decoding complexity. The decoding process simultaneously integrates both hard and soft bit information within the NAND flash memory, enabling both short and long block performance. It is widely used for error correction in NAND flash memory, improving its data storage reliability. Currently, LDPC correction technology only corrects the data being read from NAND flash memory, not other memory regions. This results in a continuous accumulation of data error regions within the NAND flash memory, impacting the overall data storage reliability of the flash memory. Summary of the Invention

[0003] The purpose of the present invention is to provide an LDPC correction method and system for NAND flash memory error intervals, identify the expansion trend of abnormal intervals of NAND flash memory, and identify the error interval according to the data writing task of the flash memory, and judge whether the interval with data stored in the flash memory has an error; adjust the LDPC correction of the flash memory according to the error interval and the data reading quality received by the flash memory, and adjust the return status of the data reading result according to the execution status of the LDPC correction to ensure that the read and returned data is correct; generate LDPC correction instructions based on the LDPC correction information that the flash memory did not complete during the current power-on process, and adjust the LDPC correction operation of the flash memory according to the task instructions received after the flash memory is powered on again, effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, improve the overall data storage reliability of the NAND flash memory, and ensure the data reading / writing correctness of the NAND flash memory.

[0004] The present invention is achieved through the following technical solutions:

[0005] The LDPC correction method for NAND flash memory error range includes:

[0006] Identifying an abnormal interval of a NAND flash memory to obtain an abnormal interval expansion trend of the NAND flash memory; identifying an error interval of the NAND flash memory based on the abnormal interval expansion trend and a data writing task for the NAND flash memory;

[0007] Adjusting LDPC correction of the NAND flash memory according to the distribution of the bit error intervals and the data read instruction received by the NAND flash memory; and adjusting a return status of a data read result according to an execution status of the LDPC correction;

[0008] Generate an LDPC correction guide based on the unfinished LDPC correction information of the NAND flash memory during the current power-on process; and adjust the LDPC correction operation of the NAND flash memory based on the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

[0009] Optionally, performing abnormal interval identification on a NAND flash memory to obtain an abnormal interval expansion trend of the NAND flash memory; and identifying a bit error interval of the NAND flash memory according to the abnormal interval expansion trend and a data writing task for the NAND flash memory, includes:

[0010] Dynamically identify abnormal intervals of the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND flash memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution locations of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; wherein the abnormal interval expansion trend refers to the newly added number and location of abnormal intervals in the NAND flash memory;

[0011] According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the data written by the NAND flash memory is determined; and according to the abnormal interval expansion trend and the interval distribution, the error interval of the NAND flash memory is identified.

[0012] Optionally, during the abnormal interval identification process of the NAND flash memory, dynamically adjusting the sliding window used for abnormality identification includes:

[0013] Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory;

[0014] Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory;

[0015] Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position;

[0016] The abnormality degree factor is obtained by the following formula:

[0017]

[0018] Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value;

[0019] Comparing the abnormality degree factor with a preset factor reference value;

[0020] When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted;

[0021] When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved;

[0022] The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula:

[0023]

[0024] Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

[0025] Optionally, adjusting LDPC correction of the NAND flash memory according to the distribution of the bit error intervals and the data read instruction received by the NAND flash memory; and adjusting a return status of a data read result according to an execution status of the LDPC correction, including:

[0026] Parsing the data read instruction received by the NAND flash memory to determine the interval where the current read data is located; comparing the interval where the current read data is located with the distribution of the bit error interval to determine the interval where LDPC correction is required during the data reading process, thereby adjusting the interval implementation path of the LDPC correction of the NAND flash memory;

[0027] Obtain the LDPC correction execution progress of the corresponding interval in the NAND memory according to the interval implementation path, read the data in the interval where the LDPC correction is completed according to the execution progress, and return the data reading result directly to the user end.

[0028] Optionally, generating an LDPC correction guide according to uncompleted LDPC correction information of the NAND flash memory during the current power-on process; and adjusting an LDPC correction operation on the NAND flash memory according to the LDPC guide and a task instruction received by the NAND flash memory after the NAND flash memory is powered on again, including:

[0029] Obtaining an execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed;

[0030] After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instruction included in the task instruction received by the NAND flash memory.

[0031] The LDPC correction system for NAND flash memory error regions includes:

[0032] An abnormal interval expansion trend determination module is used to identify abnormal intervals of the NAND flash memory and obtain an abnormal interval expansion trend of the NAND flash memory;

[0033] an error interval identification module, configured to identify the error interval of the NAND flash memory according to an expansion trend of the abnormal interval and a data writing task to the NAND flash memory;

[0034] A correction adjustment module, configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory;

[0035] A data reading and returning module, configured to adjust a return status of a data reading result according to an execution status of the LDPC correction;

[0036] A correction guide generation module, configured to generate an LDPC correction guide based on uncompleted LDPC correction information of the NAND flash memory during this power-on process;

[0037] The secondary correction adjustment module is used to adjust the LDPC correction operation of the NAND flash memory according to the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

[0038] Optionally, the abnormal interval expansion trend determining module is configured to identify abnormal intervals of the NAND flash memory and obtain the abnormal interval expansion trend of the NAND flash memory, including:

[0039] Dynamically identify abnormal intervals of the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND flash memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution locations of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; wherein the abnormal interval expansion trend refers to the newly added number and location of abnormal intervals in the NAND flash memory;

[0040] The error interval identification module is used to identify the error interval of the NAND flash memory according to the abnormal interval expansion trend and the data writing task of the NAND flash memory, including:

[0041] According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the data written by the NAND flash memory is determined; and according to the abnormal interval expansion trend and the interval distribution, the error interval of the NAND flash memory is identified.

[0042] Optionally, during the abnormal interval identification process of the NAND flash memory, dynamically adjusting the sliding window used for abnormality identification includes:

[0043] Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory;

[0044] Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory;

[0045] Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position;

[0046] The abnormality degree factor is obtained by the following formula:

[0047]

[0048] Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value;

[0049] Comparing the abnormality degree factor with a preset factor reference value;

[0050] When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted;

[0051] When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved;

[0052] The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula:

[0053]

[0054] Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

[0055] Optionally, the correction adjustment module is configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory, including:

[0056] Parsing the data read instruction received by the NAND flash memory to determine the interval where the current read data is located; comparing the interval where the current read data is located with the distribution of the bit error interval to determine the interval where LDPC correction is required during the data reading process, thereby adjusting the interval implementation path of the LDPC correction of the NAND flash memory;

[0057] The data reading and returning module is used to adjust the return status of the data reading result according to the execution status of the LDPC correction, including:

[0058] Obtain the LDPC correction execution progress of the corresponding interval in the NAND memory according to the interval implementation path, read the data in the interval where the LDPC correction is completed according to the execution progress, and return the data reading result directly to the user end.

[0059] Optionally, the correction guide generation module is configured to generate an LDPC correction guide according to uncompleted LDPC correction information of the NAND flash memory during the current power-on process, including:

[0060] Obtaining an execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed;

[0061] The correction secondary adjustment module is used to adjust the LDPC correction operation of the NAND flash memory according to the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again, including:

[0062] After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instruction included in the task instruction received by the NAND flash memory.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] The LDPC correction method and system for NAND flash memory error intervals provided in the present application identify the expansion trend of abnormal intervals of NAND flash memory, and identify the error intervals based on the data writing task of the flash memory, and determine whether an error occurs in the interval where data is stored in the flash memory; adjust the LDPC correction of the flash memory based on the error interval and the data reading quality received by the flash memory, and adjust the return status of the data reading result based on the execution status of the LDPC correction to ensure that the read and returned data is correct; generate LDPC correction instructions based on the LDPC correction information that the flash memory did not complete during the current power-on process, and adjust the LDPC correction operation of the flash memory based on the task instructions received after the flash memory is powered on again, effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, improve the overall data storage reliability of the NAND flash memory, and ensure the data reading / writing correctness of the NAND flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. Among them:

[0066] Figure 1 This is a flow chart of the LDPC correction method for NAND flash memory error intervals provided by the present invention.

[0067] Figure 2 This is a structural diagram of the LDPC correction system for the NAND flash memory error interval provided by the present invention. DETAILED DESCRIPTION

[0068] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0069] As used herein, the terms "comprise," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0070] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0071] See also Figure 1 As shown, an embodiment of the present application provides an LDPC correction method for a NAND flash memory error interval. The LDPC correction method for a NAND flash memory error interval includes:

[0072] Identify abnormal intervals of the NAND flash memory and obtain the abnormal interval expansion trend of the NAND flash memory; identify the bit error interval of the NAND flash memory based on the abnormal interval expansion trend and the data writing task of the NAND flash memory;

[0073] Adjusting LDPC correction of the NAND flash memory based on the distribution of bit error intervals and the data read instruction received by the NAND flash memory; and adjusting the return status of the data read result based on the execution status of the LDPC correction;

[0074] An LDPC correction guide is generated according to unfinished LDPC correction information of the NAND flash memory during the current power-on process; and an LDPC correction operation on the NAND flash memory is adjusted according to the LDPC guide and a task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

[0075] The beneficial effects of the above embodiments are as follows: the LDPC correction method for the error interval of the NAND flash memory identifies the abnormal interval expansion trend of the NAND flash memory, and identifies the error interval according to the data writing task of the flash memory, and determines whether an error occurs in the interval where data is stored in the flash memory; according to the error interval and the data reading quality received by the flash memory, the LDPC correction of the flash memory is adjusted, and according to the execution status of the LDPC correction, the return status of the data reading result is adjusted to ensure that the read returned data is correct; according to the LDPC correction information that the flash memory did not complete during the current power-on process, an LDPC correction guide is generated, and according to the task instructions received after the flash memory is powered on again, the LDPC correction operation of the flash memory is adjusted to effectively correct all the error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, improve the overall data storage reliability of the NAND flash memory, and ensure the data reading / writing correctness of the NAND flash memory.

[0076] In another embodiment, abnormal intervals are identified for a NAND flash memory to obtain an abnormal interval expansion trend of the NAND flash memory; and according to the abnormal interval expansion trend and a data writing task for the NAND flash memory, an error interval of the NAND flash memory is identified, including:

[0077] Dynamically identify abnormal intervals in the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; the abnormal interval expansion trend refers to the number of newly added abnormal intervals in the NAND flash memory and the location of the newly added abnormal intervals;

[0078] According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined; according to the abnormal interval expansion trend and interval distribution, the error interval of the NAND flash memory is identified.

[0079] The beneficial effect of the above embodiment is that the NAND flash memory includes multiple intervals, each interval serves as an independent storage unit for storing data written from the outside. During the manufacturing process, the NAND memory is affected by manufacturing process factors, and it cannot be guaranteed that all internal intervals can store data normally. Some intervals have problems such as data storage errors. These intervals correspond to the initial abnormal intervals of the NAND memory. With the improvement of the production process, the probability of the initial abnormal intervals of the NAND memory is low, but it cannot be guaranteed that all NAND memories do not have any initial abnormal intervals. As the NAND memory continues to read / write data, the internal intervals of the NAND memory will add new abnormal intervals under the influence of external factors. The number and distribution of these new abnormal intervals are not only related to the read / write data status of the memory, but also related to the original initial abnormal intervals of the memory. Generally speaking, NAND memory segments with higher read / write frequency are more likely to become abnormal segments. Intervals adjacent to initial abnormal segments are also more likely to become abnormal segments. This means that as NAND memory operates, abnormal segments tend to increase and expand. When a segment within NAND memory becomes an abnormal segment, data stored within it is prone to errors, requiring LDPC correction when reading data from it. To address this issue, dynamic abnormal segment identification is performed on NAND memory to determine the distribution of initial abnormal segments and newly added abnormal segments. By analyzing the distribution of initial abnormal segments and newly added abnormal segments at different times, the number and location of new abnormal segments in the NAND memory in future periods can be determined, providing a reliable basis for subsequent identification of NAND memory error regions. The greater the number and wider the distribution of newly added abnormal segments within NAND memory, the more likely the segment containing the data to be an error segment when writing data to the NAND memory. Furthermore, the larger the amount of data written to the NAND memory, the larger the number of segments required to write data, and the more error segments in the NAND memory. To this end, based on the amount of data that needs to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined, and the above interval distribution is compared with the interval distribution involved in the abnormal interval expansion trend to determine whether the interval where the write data is located overlaps with the interval involved in the abnormal interval expansion trend. If so, it is determined that the interval where the above write data is located belongs to the error interval of the NAND flash memory, which facilitates the subsequent targeted priority LDPC correction of the corresponding error interval to ensure the data storage reliability of the NAND memory.

[0080] In another embodiment, dynamically adjusting a sliding window for abnormality identification during abnormal interval identification in a NAND flash memory includes:

[0081] Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory;

[0082] Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory;

[0083] Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position;

[0084] The abnormality degree factor is obtained by the following formula:

[0085]

[0086] Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value;

[0087] Comparing the abnormality degree factor with a preset factor reference value;

[0088] When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted;

[0089] When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved;

[0090] The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula:

[0091]

[0092] Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

[0093] The beneficial effects of the above-described embodiment include comprehensively evaluating the abnormality level by calculating the abnormality level factor based on the bit error rate when an abnormal interval occurs in the NAND flash memory, the number of newly added abnormal intervals, and the weight of their distribution locations. When the abnormality level factor exceeds a preset value, the sliding window size is adjusted based on the historical bit error rate and the current abnormality level factor, making the sliding window more adaptable to the actual abnormality. An appropriately sized sliding window helps more accurately capture abnormal intervals during data reading and monitoring, avoiding missing details due to an overly large window or missing key information due to a too-small window, thereby improving the accuracy of abnormality identification. This solution dynamically adjusts the sliding window size based on the real-time abnormality of the NAND flash memory. When the abnormality level is low, the window remains unchanged; when the abnormality level is high, it is flexibly adjusted based on historical data and the current abnormality level, allowing the system to adapt to varying degrees of abnormality. This adaptive adjustment mechanism allows the system to consistently monitor abnormalities with an appropriate window setting even when faced with complex and changing NAND flash memory operating conditions, enhancing the system's adaptability to different operating scenarios and abnormal conditions, and improving the stability and reliability of system operation. If the sliding window size is fixed, when the anomaly is complex, an inappropriate window size can lead to excessive resource consumption (e.g., a window that is too large requires processing too much data) or insufficient resource utilization (e.g., a window that is too small prevents comprehensive monitoring). Dynamically adjusting the sliding window size allows us to maintain a low-resource window setting when the anomaly level is low, and reasonably expand the window to obtain more information when the anomaly level is high. This ensures on-demand resource allocation, avoids resource waste, optimizes system resource utilization, and reduces system operating costs while ensuring effective anomaly identification.

[0094] on the other hand, It combines the bit error rate P, the number of newly added abnormal intervals n, and the weight wi of the distribution position of each interval. The bit error rate reflects the current data error level, the number of newly added abnormal intervals reflects the scale of the abnormality, and the distribution position weight considers the importance of abnormalities at different positions. The Sigmoid function maps the product of the weight and the bit error rate. Combining these factors can comprehensively and meticulously measure the abnormality level of the NAND flash memory, and provide an accurate basis for sliding window adjustment. The introduction of the Sigmoid function is a nonlinear processing that can more flexibly reflect the relationship between the weight and the bit error rate. Abnormal intervals at different positions have different effects on the overall abnormality level. The Sigmoid function can avoid the limitations of simple linear superposition, make the calculation of the abnormality level factor more in line with the actual situation, accurately characterize the severity of the abnormality, and improve the accuracy and reliability of abnormality assessment. At the same time, The sliding window size is adjusted using factors such as the anomaly severity factor S and the historical bit error rate Pi. The higher the anomaly severity, the larger the window size adjustment based on historical data, enabling faster response to severe anomalies and expanding the window to capture more data. When the anomaly severity is low, the adjustment is smaller, maintaining a stable window size and adapting it to NAND flash anomaly fluctuations, improving anomaly identification efficiency and accuracy. The window size is adjusted based on historical anomaly severity factors, taking into account the number of times m anomaly intervals were identified in historical data and the bit error rate Pi for each occurrence. This avoids the biased nature of adjustments based solely on current anomaly severity and instead incorporates historical experience to make window adjustments more scientific and reasonable, adapting to different stages and types of anomalies and enhancing the system's stability and adaptability to NAND flash anomaly detection. By taking the minimum of Qmin and the calculated value, the adjusted sliding window size is ensured to not fall below the preset minimum allowable value Qmin, preventing the window from being too small and thus failing to effectively detect anomalies. Maintaining the sliding window size within a reasonable range not only meets the data volume requirements for anomaly identification but also avoids resource waste caused by uncontrolled window expansion, thus balancing anomaly identification effectiveness with resource efficiency.

[0095] In another embodiment, adjusting LDPC correction of the NAND flash memory according to the distribution of bit error intervals and the data read instruction received by the NAND flash memory; and adjusting the return status of the data read result according to the execution status of the LDPC correction, including:

[0096] Parse and process the data read instructions received by the NAND flash memory to determine the interval where the current read data is located; compare the interval where the current read data is located with the distribution of the bit error interval to determine the interval that requires LDPC correction during the data reading process, thereby adjusting the interval implementation path of the LDPC correction for the NAND flash memory;

[0097] Obtain the progress of LDPC correction execution for the corresponding interval in the NAND memory according to the interval implementation path. According to the execution progress, read the data in the interval where LDPC correction is completed, and return the data reading result directly to the user end.

[0098] The beneficial effect of the above embodiment is that when reading data from a NAND flash memory, if the read data is from an error interval of the NAND memory, LDPC correction must first be performed on the data in the error interval to correct the original errors in the data to ensure the accuracy of the data read from the memory. Considering that each time data is read from the NAND memory, internal data must be read from a large number of intervals, which may result in data being read from an error interval. In order to ensure the accuracy of all read data during the data reading process, LDPC correction must be performed on the data read from the error interval first. To this end, the data read instruction received by the NAND flash memory is parsed and processed to determine the interval in which the current read data is located. This is then compared with the distribution of the error areas to determine the error interval in which the data is read during the data reading process, thereby adjusting the interval implementation path of the LDPC correction for the NAND flash memory. The interval implementation path refers to the spatial order of implementing LDPC correction on the corresponding error intervals within the NAND flash memory during the data reading process, thereby ensuring that if data is read from an error interval during the data reading process, LDPC correction can be directly performed on the read data, ensuring the accuracy of all read data. Then, according to the above interval implementation path, during the process of reading data from the corresponding interval of the NAND memory, the LDPC correction execution progress after the data is read from the corresponding interval is obtained to determine whether the LDPC correction operation of the data read from the corresponding error interval has been completed. If it has been completed, the data after the LDPC correction is completed will be returned directly to the user end; if not, the corresponding data will not be returned to the user end until the LDPC correction is completed to ensure the correctness of the read data.

[0099] In another embodiment, an LDPC correction guide is generated based on uncompleted LDPC correction information of the NAND flash memory during the current power-on process; and after the NAND flash memory is powered on again, an LDPC correction operation on the NAND flash memory is adjusted based on the LDPC guide and a task instruction received by the NAND flash memory, including:

[0100] Obtaining the execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of the intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed;

[0101] After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instructions included in the task instructions received by the NAND flash memory.

[0102] The beneficial effect of the above embodiment is that the NAND memory performs LDPC correction only during the power-on process. Considering the large number of error intervals in the NAND memory and the limited power-on duration of the NAND memory, it cannot be guaranteed that the NAND memory can perform LDPC correction on all error intervals during one power-on period; for example, the NAND memory can only perform LDPC correction on some error intervals during this power-on process, and another error interval cannot be corrected by LDPC in time. In order to be able to perform LDPC correction on all error intervals in a continuous manner every time the NAND memory is powered on, the execution progress of the LDPC correction of the NAND flash memory during this power-on process is first obtained, and the position of the interval of incomplete LDPC correction during this power-on process is determined, so as to generate a spatial sequence guide for correcting all the intervals for which LDPC correction has not been completed. After the NAND flash memory is powered on again, the correction order of all the intervals in the NAND flash memory for which LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instructions contained in the task instructions received by the NAND flash memory, so as to ensure that the NAND memory can continue to perform the corresponding LDPC correction for the LDPC correction that was not completed during the previous power-on period after each power-on, effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, and improve the overall data storage reliability of the NAND flash memory.

[0103] See also Figure 2 As shown, an LDPC correction system for NAND flash memory error intervals provided by an embodiment of the present application. The LDPC correction system for NAND flash memory error intervals includes:

[0104] The abnormal interval expansion trend determination module is used to identify the abnormal interval of the NAND flash memory and obtain the abnormal interval expansion trend of the NAND flash memory;

[0105] The error interval identification module is used to identify the error interval of the NAND flash memory based on the abnormal interval expansion trend and the data writing task to the NAND flash memory;

[0106] A correction adjustment module, configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory;

[0107] The data reading and returning module is used to adjust the return status of the data reading result according to the execution status of the LDPC correction;

[0108] A correction guide generation module is used to generate an LDPC correction guide based on the uncompleted LDPC correction information of the NAND flash memory during the current power-on process;

[0109] The correction secondary adjustment module is used to adjust the LDPC correction operation on the NAND flash memory according to the LDPC guidance and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

[0110] The beneficial effects of the above embodiments are as follows: the LDPC correction system for the error interval of the NAND flash memory identifies the abnormal interval expansion trend of the NAND flash memory, and identifies the error interval according to the data writing task of the flash memory, and determines whether an error occurs in the interval where data is stored in the flash memory; according to the error interval and the data reading quality received by the flash memory, the LDPC correction of the flash memory is adjusted, and according to the execution status of the LDPC correction, the return status of the data reading result is adjusted to ensure that the read and returned data is correct; according to the LDPC correction information that the flash memory did not complete during the current power-on process, an LDPC correction guide is generated, and according to the task instructions received after the flash memory is powered on again, the LDPC correction operation of the flash memory is adjusted to effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, improve the overall data storage reliability of the NAND flash memory, and ensure the data reading / writing correctness of the NAND flash memory.

[0111] In another embodiment, the abnormal interval expansion trend determination module is used to identify abnormal intervals of the NAND flash memory and obtain the abnormal interval expansion trend of the NAND flash memory, including:

[0112] Dynamically identify abnormal intervals in the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; the abnormal interval expansion trend refers to the number of newly added abnormal intervals in the NAND flash memory and the location of the newly added abnormal intervals;

[0113] The error interval identification module is used to identify the error interval of the NAND flash memory based on the abnormal interval expansion trend and the data writing task to the NAND flash memory. It includes:

[0114] According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined; according to the abnormal interval expansion trend and interval distribution, the error interval of the NAND flash memory is identified.

[0115] The beneficial effect of the above embodiment is that the NAND flash memory includes multiple intervals, each interval serves as an independent storage unit for storing data written from the outside. During the manufacturing process, the NAND memory is affected by manufacturing process factors, and it cannot be guaranteed that all internal intervals can store data normally. Some intervals have problems such as data storage errors. These intervals correspond to the initial abnormal intervals of the NAND memory. With the improvement of the production process, the probability of the initial abnormal intervals of the NAND memory is low, but it cannot be guaranteed that all NAND memories do not have any initial abnormal intervals. As the NAND memory continues to read / write data, the internal intervals of the NAND memory will add new abnormal intervals under the influence of external factors. The number and distribution of these new abnormal intervals are not only related to the read / write data status of the memory, but also related to the original initial abnormal intervals of the memory. Generally speaking, NAND memory segments with higher read / write frequency are more likely to become abnormal segments. Intervals adjacent to initial abnormal segments are also more likely to become abnormal segments. This means that as NAND memory operates, abnormal segments tend to increase and expand. When a segment within NAND memory becomes an abnormal segment, data stored within it is prone to errors, requiring LDPC correction when reading data from it. To address this issue, dynamic abnormal segment identification is performed on NAND memory to determine the distribution of initial abnormal segments and newly added abnormal segments. By analyzing the distribution of initial abnormal segments and newly added abnormal segments at different times, the number and location of new abnormal segments in the NAND memory in future periods can be determined, providing a reliable basis for subsequent identification of NAND memory error regions. The greater the number and wider the distribution of newly added abnormal segments within NAND memory, the more likely the segment containing the data to be an error segment when writing data to the NAND memory. Furthermore, the larger the amount of data written to the NAND memory, the larger the number of segments required to write data, and the more error segments in the NAND memory. To this end, based on the amount of data that needs to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined, and the above interval distribution is compared with the interval distribution involved in the abnormal interval expansion trend to determine whether the interval where the write data is located overlaps with the interval involved in the abnormal interval expansion trend. If so, it is determined that the interval where the above write data is located belongs to the error interval of the NAND flash memory, which facilitates the subsequent targeted priority LDPC correction of the corresponding error interval to ensure the data storage reliability of the NAND memory.

[0116] In another embodiment, dynamically adjusting a sliding window for abnormality identification during abnormal interval identification in a NAND flash memory includes:

[0117] Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory;

[0118] Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory;

[0119] Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position;

[0120] The abnormality degree factor is obtained by the following formula:

[0121]

[0122] Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value;

[0123] Comparing the abnormality degree factor with a preset factor reference value;

[0124] When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted;

[0125] When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved;

[0126] The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula:

[0127]

[0128] Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

[0129] The beneficial effects of the above-described embodiment include comprehensively evaluating the abnormality level by calculating the abnormality level factor based on the bit error rate when an abnormal interval occurs in the NAND flash memory, the number of newly added abnormal intervals, and the weight of their distribution locations. When the abnormality level factor exceeds a preset value, the sliding window size is adjusted based on the historical bit error rate and the current abnormality level factor, making the sliding window more adaptable to the actual abnormality. An appropriately sized sliding window helps more accurately capture abnormal intervals during data reading and monitoring, avoiding missing details due to an overly large window or missing key information due to a too-small window, thereby improving the accuracy of abnormality identification. This solution dynamically adjusts the sliding window size based on the real-time abnormality of the NAND flash memory. When the abnormality level is low, the window remains unchanged; when the abnormality level is high, it is flexibly adjusted based on historical data and the current abnormality level, allowing the system to adapt to varying degrees of abnormality. This adaptive adjustment mechanism allows the system to consistently monitor abnormalities with an appropriate window setting even when faced with complex and changing NAND flash memory operating conditions, enhancing the system's adaptability to different operating scenarios and abnormal conditions, and improving the stability and reliability of system operation. If the sliding window size is fixed, when the anomaly is complex, an inappropriate window size can lead to excessive resource consumption (e.g., a window that is too large requires processing too much data) or insufficient resource utilization (e.g., a window that is too small prevents comprehensive monitoring). Dynamically adjusting the sliding window size allows us to maintain a low-resource window setting when the anomaly level is low, and reasonably expand the window to obtain more information when the anomaly level is high. This ensures on-demand resource allocation, avoids resource waste, optimizes system resource utilization, and reduces system operating costs while ensuring effective anomaly identification.

[0130] on the other hand, It combines the bit error rate P, the number of newly added abnormal intervals n, and the weight wi of the distribution position of each interval. The bit error rate reflects the current data error level, the number of newly added abnormal intervals reflects the scale of the abnormality, and the distribution position weight considers the importance of abnormalities at different positions. The Sigmoid function maps the product of the weight and the bit error rate. Combining these factors can comprehensively and meticulously measure the abnormality level of the NAND flash memory, and provide an accurate basis for sliding window adjustment. The introduction of the Sigmoid function is a nonlinear processing that can more flexibly reflect the relationship between the weight and the bit error rate. Abnormal intervals at different positions have different effects on the overall abnormality level. The Sigmoid function can avoid the limitations of simple linear superposition, make the calculation of the abnormality level factor more in line with the actual situation, accurately characterize the severity of the abnormality, and improve the accuracy and reliability of abnormality assessment. At the same time, The sliding window size is adjusted using factors such as the anomaly severity factor S and the historical bit error rate Pi. The higher the anomaly severity, the larger the window size adjustment based on historical data, enabling faster response to severe anomalies and expanding the window to capture more data. When the anomaly severity is low, the adjustment is smaller, maintaining a stable window size and adapting it to NAND flash anomaly fluctuations, improving anomaly identification efficiency and accuracy. The window size is adjusted based on historical anomaly severity factors, taking into account the number of times m anomaly intervals were identified in historical data and the bit error rate Pi for each occurrence. This avoids the biased nature of adjustments based solely on current anomaly severity and instead incorporates historical experience to make window adjustments more scientific and reasonable, adapting to different stages and types of anomalies and enhancing the system's stability and adaptability to NAND flash anomaly detection. By taking the minimum of Qmin and the calculated value, the adjusted sliding window size is ensured to not fall below the preset minimum allowable value Qmin, preventing the window from being too small and thus failing to effectively detect anomalies. Maintaining the sliding window size within a reasonable range not only meets the data volume requirements for anomaly identification but also avoids resource waste caused by uncontrolled window expansion, thus balancing anomaly identification effectiveness with resource efficiency.

[0131] In another embodiment, the correction adjustment module is configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory, including:

[0132] Parse and process the data read instructions received by the NAND flash memory to determine the interval where the current read data is located; compare the interval where the current read data is located with the distribution of the bit error interval to determine the interval that requires LDPC correction during the data reading process, thereby adjusting the interval implementation path of the LDPC correction for the NAND flash memory;

[0133] The data read return module is used to adjust the return status of the data read result according to the execution status of the LDPC correction, including:

[0134] Obtain the progress of LDPC correction execution for the corresponding interval in the NAND memory according to the interval implementation path. According to the execution progress, read the data in the interval where LDPC correction is completed, and return the data reading result directly to the user end.

[0135] The beneficial effect of the above embodiment is that when reading data from a NAND flash memory, if the read data is from an error interval of the NAND memory, LDPC correction must first be performed on the data in the error interval to correct the original errors in the data to ensure the accuracy of the data read from the memory. Considering that each time data is read from the NAND memory, internal data must be read from a large number of intervals, which may result in data being read from an error interval. In order to ensure the accuracy of all read data during the data reading process, LDPC correction must be performed on the data read from the error interval first. To this end, the data read instruction received by the NAND flash memory is parsed and processed to determine the interval in which the current read data is located. This is then compared with the distribution of the error areas to determine the error interval in which the data is read during the data reading process, thereby adjusting the interval implementation path of the LDPC correction for the NAND flash memory. The interval implementation path refers to the spatial order of implementing LDPC correction on the corresponding error intervals within the NAND flash memory during the data reading process, thereby ensuring that if data is read from an error interval during the data reading process, LDPC correction can be directly performed on the read data, ensuring the accuracy of all read data. Then, according to the above interval implementation path, during the process of reading data from the corresponding interval of the NAND memory, the LDPC correction execution progress after the data is read from the corresponding interval is obtained to determine whether the LDPC correction operation of the data read from the corresponding error interval has been completed. If it has been completed, the data after the LDPC correction is completed will be returned directly to the user end; if not, the corresponding data will not be returned to the user end until the LDPC correction is completed to ensure the correctness of the read data.

[0136] In another embodiment, the correction guide generation module is configured to generate an LDPC correction guide based on uncompleted LDPC correction information of the NAND flash memory during the current power-on process, including:

[0137] Obtaining the execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of the intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed;

[0138] The secondary correction adjustment module is used to adjust the LDPC correction operation of the NAND flash memory according to the LDPC guidance and the task instructions received by the NAND flash memory after the NAND flash memory is powered on again, including:

[0139] After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instructions included in the task instructions received by the NAND flash memory.

[0140] The beneficial effect of the above embodiment is that the NAND memory performs LDPC correction only during the power-on process. Considering the large number of error intervals in the NAND memory and the limited power-on duration of the NAND memory, it cannot be guaranteed that the NAND memory can perform LDPC correction on all error intervals during one power-on period; for example, the NAND memory can only perform LDPC correction on some error intervals during this power-on process, and another error interval cannot be corrected by LDPC in time. In order to be able to perform LDPC correction on all error intervals in a continuous manner every time the NAND memory is powered on, the execution progress of the LDPC correction of the NAND flash memory during this power-on process is first obtained, and the position of the interval of incomplete LDPC correction during this power-on process is determined, so as to generate a spatial sequence guide for correcting all the intervals for which LDPC correction has not been completed. After the NAND flash memory is powered on again, the correction order of all the intervals in the NAND flash memory for which LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instructions contained in the task instructions received by the NAND flash memory, so as to ensure that the NAND memory can continue to perform the corresponding LDPC correction for the LDPC correction that was not completed during the previous power-on period after each power-on, effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, and improve the overall data storage reliability of the NAND flash memory.

[0141] In general, the LDPC correction method and system for NAND flash memory error intervals identify the expansion trend of abnormal intervals of NAND flash memory, and identify the error intervals based on the data writing task of the flash memory, and determine whether an error occurs in the interval where data is stored in the flash memory; according to the error interval and the data reading quality received by the flash memory, the LDPC correction of the flash memory is adjusted, and according to the execution status of the LDPC correction, the return status of the data reading result is adjusted to ensure that the read and returned data is correct; according to the LDPC correction information that the flash memory did not complete during the current power-on process, an LDPC correction guide is generated, and according to the task instructions received after the flash memory is powered on again, the LDPC correction operation of the flash memory is adjusted to effectively correct all error intervals in the flash memory, avoid the continuous increase and accumulation of data error intervals in the flash memory, improve the overall data storage reliability of the NAND flash memory, and ensure the data reading / writing correctness of the NAND flash memory.

[0142] The above is only a specific embodiment of the present invention, and any other improvements made based on the concept of the present invention are considered to be within the scope of protection of the present invention.

Claims

1. An LDPC correction method for an error interval of a NAND flash memory, characterized in that: include: Identifying abnormal intervals of the NAND flash memory to obtain an abnormal interval expansion trend of the NAND flash memory; Identifying a bit error interval of the NAND flash memory according to an expansion trend of the abnormal interval and a data writing task for the NAND flash memory; Adjusting LDPC correction of the NAND flash memory according to the distribution of the bit error intervals and the data read instruction received by the NAND flash memory; and adjusting a return status of a data read result according to an execution status of the LDPC correction; Generate an LDPC correction guide based on the unfinished LDPC correction information of the NAND flash memory during the current power-on process; and adjust the LDPC correction operation of the NAND flash memory based on the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

2. The LDPC correction method for a NAND flash memory error interval according to claim 1, wherein: Identifying an abnormal interval of a NAND flash memory to obtain an abnormal interval expansion trend of the NAND flash memory; and identifying an error interval of the NAND flash memory based on the abnormal interval expansion trend and a data writing task for the NAND flash memory, including: Dynamically identify abnormal intervals of the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND flash memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution locations of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; wherein the abnormal interval expansion trend refers to the newly added number and location of abnormal intervals in the NAND flash memory; According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined; according to the abnormal interval expansion trend and the interval distribution, the error interval of the NAND flash memory is identified.

3. The LDPC correction method for an error interval of a NAND flash memory according to claim 2, wherein: During the abnormal interval identification process of NAND flash memory, the sliding window used for abnormal identification is dynamically adjusted, including: Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory; Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory; Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position; The abnormality degree factor is obtained by the following formula: Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value; Comparing the abnormality degree factor with a preset factor reference value; When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted; When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved; The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula: Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

4. The LDPC correction method for an error range of a NAND flash memory according to claim 1, wherein: Adjusting LDPC correction of the NAND flash memory according to the distribution of the bit error intervals and the data read instruction received by the NAND flash memory; and adjusting a return status of a data read result according to an execution status of the LDPC correction, including: Parsing the data read instruction received by the NAND flash memory to determine the interval where the current read data is located; comparing the interval where the current read data is located with the distribution of the bit error interval to determine the interval where LDPC correction is required during the data reading process, thereby adjusting the interval implementation path of the LDPC correction of the NAND flash memory; Obtain the LDPC correction execution progress of the corresponding interval in the NAND memory according to the interval implementation path, read the data in the interval where the LDPC correction is completed according to the execution progress, and return the data reading result directly to the user end.

5. The LDPC correction method for an error range of a NAND flash memory according to claim 1, wherein: Generate an LDPC correction guide according to uncompleted LDPC correction information of the NAND flash memory during the current power-on process; and adjust an LDPC correction operation on the NAND flash memory according to the LDPC guide and a task instruction received by the NAND flash memory after the NAND flash memory is powered on again, including: Obtaining an execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed; After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instruction included in the task instruction received by the NAND flash memory.

6. LDPC correction system for NAND flash memory error interval, characterized by: include: An abnormal interval expansion trend determination module is used to identify abnormal intervals of the NAND flash memory and obtain an abnormal interval expansion trend of the NAND flash memory; an error interval identification module, configured to identify the error interval of the NAND flash memory according to an expansion trend of the abnormal interval and a data writing task to the NAND flash memory; A correction adjustment module, configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory; A data reading and returning module, configured to adjust a return status of a data reading result according to an execution status of the LDPC correction; A correction guide generation module, configured to generate an LDPC correction guide based on uncompleted LDPC correction information of the NAND flash memory during this power-on process; The secondary correction adjustment module is used to adjust the LDPC correction operation of the NAND flash memory according to the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again.

7. The LDPC correction system for NAND flash memory error intervals according to claim 6, wherein: The abnormal interval expansion trend determination module is used to identify abnormal intervals of the NAND flash memory and obtain the abnormal interval expansion trend of the NAND flash memory, including: Dynamically identify abnormal intervals of the NAND flash memory to determine the initial abnormal interval and newly added abnormal intervals of the NAND flash memory; obtain the abnormal interval expansion trend of the NAND flash memory based on the distribution locations of the initial abnormal interval and the newly added abnormal interval in the NAND flash memory; wherein the abnormal interval expansion trend refers to the newly added number and location of abnormal intervals in the NAND flash memory; The error interval identification module is used to identify the error interval of the NAND flash memory according to the abnormal interval expansion trend and the data writing task of the NAND flash memory, including: According to the amount of data required to be written in the data writing task of the NAND flash memory, the interval distribution corresponding to the NAND flash memory write data is determined; according to the abnormal interval expansion trend and the interval distribution, the error interval of the NAND flash memory is identified.

8. The LDPC correction system for NAND flash memory error intervals according to claim 7, wherein: During the abnormal interval identification process of NAND flash memory, the sliding window used for abnormal identification is dynamically adjusted, including: Real-time monitoring of the bit error rate corresponding to the abnormal range of the current NAND flash memory; Extract the number of newly added abnormal intervals and the corresponding weights of their distribution positions each time an abnormal interval appears in the NAND flash memory; Obtain an abnormality degree factor using the bit error rate corresponding to the abnormal interval when the NAND flash memory appears, the number of newly added abnormal intervals, and the weight corresponding to the distribution position; The abnormality degree factor is obtained by the following formula: Wherein, S represents the abnormality degree factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; n represents the number of newly added abnormal intervals; w i represents the weight of the distribution position corresponding to the i-th newly added abnormal interval; w c Indicates the preset weight reference value; Comparing the abnormality degree factor with a preset factor reference value; When the abnormality degree factor does not exceed the preset factor reference value, the size of the sliding window is not adjusted; When the abnormality factor exceeds a preset factor reference value, the historical bit error rate of the abnormal interval that occurred during the historical operation of the NAND flash memory is retrieved; The size of the current sliding window is adjusted using the historical bit error rate and the abnormality factor. The adjusted sliding window size is obtained using the following formula: Among them, Q represents the size of the sliding window after adjustment; Q0 represents the size of the sliding window before adjustment; Q min represents the preset minimum allowable value of the sliding window; S represents the abnormality factor; P represents the bit error rate corresponding to the abnormal interval of the NAND flash memory; m represents the number of times the abnormal interval is identified in the historical data; P i It represents the bit error rate corresponding to the abnormal interval identified for the i-th time.

9. The LDPC correction system for NAND flash memory error intervals according to claim 6, wherein: The correction adjustment module is configured to adjust the LDPC correction of the NAND flash memory according to the distribution of the bit error interval and the data read instruction received by the NAND flash memory, including: Parsing the data read instruction received by the NAND flash memory to determine the interval where the current read data is located; comparing the interval where the current read data is located with the distribution of the bit error interval to determine the interval where LDPC correction is required during the data reading process, thereby adjusting the interval implementation path of the LDPC correction of the NAND flash memory; The data reading and returning module is used to adjust the return status of the data reading result according to the execution status of the LDPC correction, including: Obtain the LDPC correction execution progress of the corresponding interval in the NAND memory according to the interval implementation path, read the data in the interval where the LDPC correction is completed according to the execution progress, and return the data reading result directly to the user end.

10. The LDPC correction system for NAND flash memory error intervals according to claim 6, wherein: The correction guide generation module is used to generate an LDPC correction guide according to the uncompleted LDPC correction information of the NAND flash memory during the current power-on process, including: Obtaining an execution progress of LDPC correction of the NAND flash memory during the current power-up process, determining the location of intervals where LDPC correction has not been completed during the current power-up process, and thereby generating an LDPC correction guide; wherein the LDPC correction guide includes a spatial order guide for correcting all intervals where LDPC correction has not been completed; The correction secondary adjustment module is used to adjust the LDPC correction operation of the NAND flash memory according to the LDPC guide and the task instruction received by the NAND flash memory after the NAND flash memory is powered on again, including: After the NAND flash memory is powered on again, the correction order of all intervals in the NAND flash memory where LDPC correction has not been completed is adjusted according to the LDPC guide and the data read / write instruction included in the task instruction received by the NAND flash memory.

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