High-frequency amplifier

Abstract

The high-frequency amplifier includes: a drive amplifier that amplifies an input high-frequency signal; and an asymmetric Doherty amplifier that amplifies the high-frequency signal output from the drive amplifier, the high-frequency amplifier having: a first laminated structure; a second laminated structure body laminated on the first laminated structure body; and a third laminated structure laminated on the second laminated structure, the asymmetric Doherty amplifier having: a carrier amplifier; a peak amplifier that starts an amplification operation when the output of the carrier amplifier reaches a saturation region, and has a saturation output different from that of the carrier amplifier; a branch circuit to which the high-frequency signal output from the drive amplifier is input; a first signal path; a second signal path; and a phase adjustment circuit. The second laminated structure has a first wiring layer, a second wiring layer, a dielectric layer, and one or more capacitors.

Description

Technical Field

[0001] The present disclosure relates to a high-frequency amplifier. Background Art

[0002] In recent years, broadbandization has been advancing in mobile communication systems such as mobile phones. Consequently, power amplifiers used in base station devices and other systems are expected to achieve improved power efficiency across a wide frequency band. Asymmetric Doherty amplifiers, comprising a carrier amplifier and a peaking amplifier, are known as power amplifiers for achieving this improved power efficiency. The carrier amplifier is sometimes also referred to as the main amplifier. It should be noted that the asymmetric Doherty amplifier is connected to the subsequent stage of the driver amplifier. Furthermore, high-frequency amplifiers have been proposed that incorporate a driver amplifier, a carrier amplifier, and a peaking amplifier in a three-dimensional configuration.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-170703

[0006] In recent years, there has been an increasing demand for improved high-frequency characteristics of high-frequency amplifiers. Summary of the Invention

[0007] An object of the present disclosure is to provide a high-frequency amplifier capable of improving high-frequency characteristics.

[0008] The high-frequency amplifier disclosed herein comprises: a driver amplifier for amplifying an input high-frequency signal; and an asymmetric Doherty amplifier for amplifying a high-frequency signal output from the driver amplifier, the high-frequency amplifier comprising: a first stacked structure; a second stacked structure stacked on the first stacked structure; and a third stacked structure stacked on the second stacked structure, the asymmetric Doherty amplifier comprising: a carrier amplifier; a peaking amplifier that starts amplification when the output of the carrier amplifier reaches a saturation region and has a saturation output different from that of the carrier amplifier; a branch circuit to which the high-frequency signal output from the driver amplifier is input; a first signal path provided between the branch circuit and the carrier amplifier; a second signal path provided between the branch circuit and the peaking amplifier; and a phase adjustment circuit provided in at least one of the first signal path and the second signal path to adjust the input signal of the carrier amplifier. The branch circuit delays at least one of the phase of the high-frequency signal output from the driver amplifier and the phase of the input signal to the first signal path and the second signal path. The second stacked structure comprises: a first wiring layer provided between the first stacked structure and the third stacked structure; a second wiring layer provided between the first wiring layer and the third stacked structure; a dielectric layer provided between the first wiring layer and the second wiring layer; and one or more capacitors including a portion of the first wiring layer, a portion of the second wiring layer, and a portion of the dielectric layer. The driver amplifier, the carrier amplifier, and the peaking amplifier are provided in the first stacked structure, the branch circuit and the phase adjustment circuit are provided in the third stacked structure, and the capacitor is electrically connected to any one of the driver amplifier, the carrier amplifier, and the peaking amplifier.

[0009] Effects of the Invention

[0010] According to the present disclosure, high-frequency characteristics can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a block diagram showing a high-frequency amplifier according to an embodiment.

[0012] Figure 2 This is a circuit diagram showing the configuration of a driver amplifier, an input matching circuit, an output matching circuit, and an output bias circuit.

[0013] Figure 3 This is a circuit diagram showing the configuration of an asymmetric Doherty amplifier.

[0014] Figure 4 It is a cross-sectional view showing a high-frequency amplifier according to the embodiment.

[0015] Figure 5 This is a diagram showing the layout of the wiring layer (part 1).

[0016] Figure 6 This is a diagram showing the layout of the wiring layer (part 2).

[0017] Figure 7 This is a diagram showing the layout of the wiring layer (part 3).

[0018] Figure 8 This is a diagram showing the layout of the wiring layer (part 4).

[0019] Figure 9 This is a diagram showing the layout of the wiring layer (part 5).

[0020] Figure 10 This is a diagram showing the layout of the wiring layer (part 6).

[0021] Figure 11 This is a cross-sectional view (Part 1) showing a method for manufacturing a high-frequency amplifier according to an embodiment.

[0022] Figure 12 This is a cross-sectional view (part 2) showing a method for manufacturing a high-frequency amplifier according to an embodiment.

[0023] Figure 13 This is a cross-sectional view showing a method for manufacturing a high-frequency amplifier according to an embodiment (Part 3).

[0024] Figure 14 This is a cross-sectional view (Part 4) showing a method for manufacturing a high-frequency amplifier according to an embodiment.

[0025] Figure 15 This is a cross-sectional view showing a method for manufacturing a high-frequency amplifier according to an embodiment (Part 5).

[0026] Figure 16 This is a cross-sectional view showing a method for manufacturing a high-frequency amplifier according to an embodiment (Part 6).

[0027] Figure 17 This is a cross-sectional view showing a method for manufacturing a high-frequency amplifier according to an embodiment (Part 7).

[0028] Figure 18 This is a diagram showing the layout in the first example.

[0029] Figure 19 This is a diagram showing the layout in the second example.

[0030] Description of Reference Numerals

[0031] 1: High frequency amplifier;

[0032] 10: driving amplifier;

[0033] 10a, 10b, 20a, 20b, 30a, 30b: main surfaces;

[0034] 11, 21, 31: input matching circuit;

[0035] 12, 22, 32: output matching circuit;

[0036] 14: Output bias circuit;

[0037] 18, 28, 38: input terminals;

[0038] 19, 29, 39: output terminals;

[0039] 20: carrier amplifier;

[0040] 23, 33: Phase adjustment circuit;

[0041] 24, 34: input bias circuit;

[0042] 30: Peak amplifier;

[0043] 40: Asymmetric Doherty amplifier;

[0044] 41: branch circuit;

[0045] 41A: first signal path;

[0046] 41B: second signal path;

[0047] 42: Doherty Network;

[0048] 51, 52, 80: surface mount components;

[0049] 60: amplifier;

[0050] 61, 62, 63, 64, 121, 122, 123, 124, 125, 126: wiring layer;

[0051] 70: arrow;

[0052] 71, 91, 92, 93, 141, 142, 143, 144, 151, 153, 155, 156, 157, 721, 722, 723: conductive vias;

[0053] 100: printed circuit board;

[0054] 101: base member;

[0055] 102, 103: signal wiring;

[0056] 104: ground wiring;

[0057] 111: first stacked structure;

[0058] 112: second stacked structure;

[0059] 113: third stacked structure;

[0060] 121G, 122G, 123G, 124G, 125G, 126G: ground pattern;

[0061] 131, 132, 133, 134, 135, 136: dielectric layer;

[0062] 211, 212, 213, 214: gate terminals;

[0063] 221, 222: source terminal;

[0064] 231, 232, 233, 234: drain terminals;

[0065] C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C15, C16, C21, C23, C24, C25, C26, C28, C29, C30, C32: capacitors;

[0066] L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, L17: inductors;

[0067] R3, R4, R5: resistance elements;

[0068] RFin: input terminal;

[0069] RFout: output terminal;

[0070] Vg: power supply;

[0071] λ: wavelength. DETAILED DESCRIPTION

[0072] [Description of Embodiments of the Present Disclosure]

[0073] First, embodiments of the present disclosure will be described below.

[0074] [1] A high-frequency amplifier according to one embodiment of the present disclosure comprises: a driver amplifier for amplifying an input high-frequency signal; and an asymmetric Doherty amplifier for amplifying a high-frequency signal output from the driver amplifier, the high-frequency amplifier comprising: a first stacked structure; a second stacked structure stacked on the first stacked structure; and a third stacked structure stacked on the second stacked structure, the asymmetric Doherty amplifier comprising: a carrier amplifier; a peaking amplifier that starts amplification when the output of the carrier amplifier reaches a saturation region and has a saturation output different from that of the carrier amplifier; a branch circuit to which the high-frequency signal output from the driver amplifier is input; a first signal path provided between the branch circuit and the carrier amplifier; a second signal path provided between the branch circuit and the peaking amplifier; and a phase adjustment circuit provided in at least one of the first signal path and the second signal path to adjust the phase of the carrier amplifier. The branch circuit branches the high-frequency signal output from the driver amplifier and outputs it to the first signal path and the second signal path, the second stacked structure comprising: a first wiring layer, provided between the first stacked structure and the third stacked structure; a second wiring layer, provided between the first wiring layer and the third stacked structure; a dielectric layer, provided between the first wiring layer and the second wiring layer; and one or more capacitors, including a portion of the first wiring layer, a portion of the second wiring layer and a portion of the dielectric layer, the driver amplifier, the carrier amplifier and the peak amplifier are provided in the first stacked structure, the branch circuit and the phase adjustment circuit are provided in the third stacked structure, and the capacitor is electrically connected to any one of the driver amplifier, the carrier amplifier or the peak amplifier.

[0075] A capacitor comprising a portion of the first wiring layer, a portion of the second wiring layer, and a portion of the dielectric layer is located between the driver amplifier, carrier amplifier, and peaking amplifier on the one hand, and the branch circuit and phase adjustment circuit on the other. This reduces signal interference between the driver amplifier, carrier amplifier, and peaking amplifier on the other hand, and the branch circuit and phase adjustment circuit on the other hand, thereby improving high-frequency characteristics.

[0076] [2] In [1], the high-frequency amplifier may include a first input matching circuit, the first input matching circuit including the capacitor, connected to the input terminal of the driver amplifier. In this case, the number of surface-mount components included in the first input matching circuit can be reduced.

[0077] [3] In [2], the first input matching circuit may be provided in the first stacked structure and the second stacked structure. In this case, a portion of the first wiring layer may be used as an electrode of a capacitor included in the first input matching circuit.

[0078] [4] In any of [1] to [3], the high-frequency amplifier may include a second input matching circuit, the second input matching circuit including the capacitor, connected to the input terminal of the carrier amplifier. In this case, the number of surface-mount components included in the second input matching circuit can be reduced.

[0079] [5] In [4], the second input matching circuit may be provided in the first stacked structure and the second stacked structure. In this case, a portion of the first wiring layer may be used as an electrode of a capacitor included in the second input matching circuit.

[0080] [6] In any of [1] to [5], the high-frequency amplifier may include a third input matching circuit, the third input matching circuit including the capacitor, connected to the input terminal of the peak amplifier. In this case, the number of surface-mount components included in the third input matching circuit can be reduced.

[0081] [7] In [6], the third input matching circuit may be provided in the first stacked structure and the second stacked structure. In this case, a portion of the first wiring layer may be used as an electrode of a capacitor included in the third input matching circuit.

[0082] [8] In any of [1] to [7], the first wiring layer may include a ground region, wherein the ground region overlaps with a transmission line that transmits a high-frequency signal output from the carrier amplifier or the peaking amplifier, at least in a plan view. In particular, high-frequency signals output from the carrier amplifier or the peaking amplifier are susceptible to parasitic capacitance, and the provision of the ground region can easily suppress degradation of the high-frequency signal associated with parasitic capacitance.

[0083] [9] In any of [1] to [8], when n is an integer greater than or equal to 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the carrier amplifier, calculated as the phase of the high-frequency signal, may be within a range of [(2n+1)×π-π / 2] to [(2n+1)×π+π / 2]. In this case, even when the driver amplifier and the carrier amplifier are close to each other, the electrical characteristics of the carrier amplifier can be easily stabilized.

[0084]

[10] In any of [1] to [9], when n is an integer greater than or equal to 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the peaking amplifier may be within a range of [(2n+1)×π-π / 2] or greater and [(2n+1)×π+π / 2] or less, as calculated based on the phase of the high-frequency signal. In this case, even when the driver amplifier and the peaking amplifier are close to each other, the electrical characteristics of the carrier amplifier can be easily stabilized.

[0085]

[11] In any one of [1] to

[10] , the saturated output of the peak amplifier may be greater than the saturated output of the carrier amplifier. The phase shift amount for achieving optimal matching of the peak amplifier may be greater than the phase shift amount for achieving optimal matching of the carrier amplifier.

[0086] [Details of the embodiments of the present disclosure]

[0087] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited thereto. It should be noted that in this specification and the accompanying drawings, for components that have substantially the same functional structure, repeated descriptions are sometimes omitted by marking the same figure marks. In addition, in the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is set for the purpose of explanation and does not limit the posture of the semiconductor device. In addition, when observing from an arbitrary point, the +Z side is sometimes referred to as the top, upper side, or top, and the -Z side is sometimes referred to as the bottom, lower side, or bottom.

[0088] (High-frequency amplifier circuit)

[0089] First, the circuit of the high-frequency amplifier according to the embodiment will be described. Figure 1 This is a block diagram showing a high-frequency amplifier according to an embodiment.

[0090] The high-frequency amplifier 1 of the embodiment is mounted on a communication device such as a base station device in a mobile communication system. The high-frequency amplifier 1 is used to amplify transmission signals, for example. The high-frequency amplifier 1 amplifies high-frequency (RF) signals with a frequency of approximately 5 GHz to 6 GHz.

[0091] If we focus on the circuit structure, Figure 1As shown, the high-frequency amplifier 1 has an input terminal RFin, an output terminal RFout, a driver amplifier 10, and an asymmetric Doherty amplifier 40. The asymmetric Doherty amplifier 40 has a branch circuit 41, a first signal path 41A, a second signal path 41B, a carrier amplifier 20, and a peaking amplifier 30. The high-frequency amplifier 1 further has an input matching circuit 11, an output matching circuit 12, and an output bias circuit 14. The asymmetric Doherty amplifier 40 further has a phase adjustment circuit 23, an input matching circuit 21, an output matching circuit 22, an input bias circuit 24, a phase adjustment circuit 33, an input matching circuit 31, an output matching circuit 32, an input bias circuit 34, and a Doherty network 42.

[0092] The input matching circuit 11 is connected to the input terminal RFin. The input matching circuit 11 also functions as an input bias circuit. The input matching circuit 11 is connected to the input terminal 18 of the driver amplifier 10, and the output matching circuit 12 and the output bias circuit 14 are connected to the output terminal 19 of the driver amplifier 10. An RF signal is input from the input terminal RFin to the driver amplifier 10 via the input matching circuit 11, and the driver amplifier 10 amplifies the input RF signal. The driver amplifier 10 amplifies the RF signal to a level that allows the asymmetric Doherty amplifier 40 to amplify the signal to a predetermined transmission power, for example. The RF signal amplified by the driver amplifier 10 is output via the output matching circuit 12. The input matching circuit 11 is an example of a first input matching circuit.

[0093] The RF signal output by the output matching circuit 12 is input to the branch circuit 41. A first signal path 41A is provided between the branch circuit 41 and the carrier amplifier 20, and a second signal path 41B is provided between the branch circuit 41 and the peaking amplifier 30. The branch circuit 41 branches the input RF signal and outputs it to the first signal path 41A and the second signal path 41B. For example, the branch circuit 41 is a Wilkinson-type splitter that equally divides the RF signal amplified by the driver amplifier 10 and outputs it to the first signal path 41A and the second signal path 41B.

[0094] Phase adjustment circuit 23 and input matching circuit 21 are provided in first signal path 41A. Input matching circuit 21 and input bias circuit 24 are connected to input terminal 28 of carrier amplifier 20, while output matching circuit 22 is connected to output terminal 29 of carrier amplifier 20. Phase adjustment circuit 23 delays the phase of the signal output from branch circuit 41 to first signal path 41A (the input signal to carrier amplifier 20). An RF signal is input to carrier amplifier 20 via input matching circuit 21, and carrier amplifier 20 amplifies the input RF signal. The RF signal amplified by carrier amplifier 20 is output via output matching circuit 22. Input matching circuit 21 is an example of a second input matching circuit.

[0095] The phase adjustment circuit 33 and input matching circuit 31 are provided in the second signal path 41B. The input matching circuit 31 and input bias circuit 34 are connected to the input terminal 38 of the peak amplifier 30, and the output matching circuit 32 is connected to the output terminal 39 of the peak amplifier 30. The phase adjustment circuit 33 delays the phase of the signal output from the branch circuit 41 to the second signal path 41B (the input signal to the peak amplifier 30). The RF signal is input to the peak amplifier 30 via the input matching circuit 31, and the peak amplifier 30 amplifies the input RF signal. The peak amplifier 30 begins amplification when the output of the carrier amplifier 20 reaches the saturation region. The peak amplifier 30 has a saturated output different from that of the carrier amplifier 20. The RF signal amplified by the peak amplifier 30 is output via the output matching circuit 32. The input matching circuit 31 is an example of a third input matching circuit.

[0096] The RF signal output via the output matching circuit 22 and the RF signal output via the output matching circuit 32 are input to the Doherty network 42 .

[0097] Next, the circuit configuration of the driver amplifier 10 , the input matching circuit 11 , the output matching circuit 12 , and the output bias circuit 14 will be described. Figure 2 1 is a circuit diagram showing the configuration of the driver amplifier 10 , the input matching circuit 11 , the output matching circuit 12 , and the output bias circuit 14 .

[0098] Input matching circuit 11 includes capacitor C2, capacitor C3, and capacitor C4, as well as inductors L1 and L2. Capacitor C3 and inductor L1 are connected in series to input terminal RFin in this order. The gate of driver amplifier 10 is connected to the downstream of inductor L1. Inductor L2 is connected in parallel to capacitor C3. Capacitor C2 is connected between the node between capacitor C3 and inductor L1 and ground. Capacitor C4 is connected between the node between inductor L1 and the gate of driver amplifier 10 and ground.

[0099] Output matching circuit 12 includes capacitor C8, inductor L4, inductor L5, inductor L9, and inductor L10. Capacitor C8, inductor L10, and inductor L9 are connected in series to the drain of driver amplifier 10 in this order. Inductor L4 is connected between the node between inductor L10 and inductor L9 and ground. Inductor L5 is connected between inductor L9 and ground at a subsequent stage to inductor L9.

[0100] Output bias circuit 14 includes capacitor C6 and inductor L3. Inductor L3 is connected between the node for inputting voltage Vd and the drain of driver amplifier 10. Capacitor C6 is connected between the node for inputting voltage Vd and ground. Voltage Vd is supplied via inductor L3 as a drain bias for driver amplifier 10. Capacitor C6 serves as a bypass capacitor for voltage Vd.

[0101] Next, the asymmetric Doherty amplifier 40 will be described. The asymmetric Doherty amplifier 40 further amplifies the RF signal amplified by the driver amplifier 10 and outputs the asymmetric Doherty amplifier from the output terminal RFout. Figure 3 4 is a circuit diagram showing the configuration of the asymmetric Doherty amplifier 40 .

[0102] As described above, the asymmetric Doherty amplifier 40 has a branch circuit 41, a first signal path 41A, a second signal path 41B, a carrier amplifier 20, a peak amplifier 30, a phase adjustment circuit 23, an input matching circuit 21, an output matching circuit 22, an input bias circuit 24, a phase adjustment circuit 33, an input matching circuit 31, an output matching circuit 32, an input bias circuit 34 and a Doherty network 42.

[0103] Branch circuit 41 includes capacitor C23, capacitor C24, and capacitor C29, inductors L11 and L12, and resistor R3. Inductor L11 is connected between output matching circuit 12 and phase adjustment circuit 23. Inductor L12 is connected between output matching circuit 12 and phase adjustment circuit 33. Capacitor C23 is connected between the node between output matching circuit 12 and inductors L11 and L12, and ground. Capacitor C24 is connected between inductor L11 and ground at the stage following inductor L11. Capacitor C29 is connected between inductor L12 and ground at the stage following inductor L12. Resistor R3 is connected between inductor L11 and inductor L12 at the stage following capacitor C24 and capacitor C29.

[0104] Phase adjustment circuit 23 includes capacitor C30, inductor L13, and inductor L14. Inductor L13 and inductor L14 are connected in series to inductor L11 in this order. Capacitor C30 is connected between a node between inductor L13 and inductor L14 and ground.

[0105] Phase adjustment circuit 33 includes capacitor C32, capacitor C1, and inductor L15. Capacitor C32 and capacitor C1 are connected in series to inductor L12 in this order. Inductor L15 is connected between a node between capacitor C32 and capacitor C1 and ground.

[0106] Input matching circuit 21 includes capacitor C11, capacitor C12, capacitor C7, and inductor L17. Capacitor C11 and inductor L17 are connected in series with inductor L14 in this order. The gate of carrier amplifier 20 is connected to the downstream of inductor L17. Capacitor C12 is connected between the node between capacitor C11 and inductor L17 and ground. Capacitor C7 is connected between the node between inductor L17 and the gate of carrier amplifier 20 and ground.

[0107] Input bias circuit 24 includes capacitor C15, resistor R4, and inductor L6. Resistor R4 and inductor L6 are connected in series, in that order, between power supply Vg and the gate of carrier amplifier 20. Capacitor C15 is connected between the node between power supply Vg and resistor R4 and ground. A gate bias voltage is supplied to carrier amplifier 20 from power supply Vg via inductor L6. Capacitor C15 serves as a bypass capacitor for power supply Vg, and resistor R4 serves as an adjustment resistor.

[0108] Input matching circuit 31 includes capacitor C10, capacitor C5, capacitor C13, and inductor L7. Capacitor C10 and inductor L7 are connected in series to capacitor C1 in that order. The gate of peak amplifier 30 is connected to the downstream of inductor L7. Capacitor C5 is connected between the node between capacitor C10 and inductor L7 and ground. Capacitor C13 is connected between the node between inductor L7 and the gate of peak amplifier 30 and ground.

[0109] Input bias circuit 34 includes capacitor C21, resistor R5, and inductor L8. Resistor R5 and inductor L8 are connected in series in this order between power supply Vg and the gate of peak amplifier 30. Capacitor C21 is connected between the node between power supply Vg and resistor R5 and ground.

[0110] Output matching circuit 22 includes capacitor C9 and capacitor C26. Capacitor C26 is connected between the drain of carrier amplifier 20 and Doherty network 42. Capacitor C26 is a capacitor used to block DC components. Capacitor C9 is connected between the node between capacitor C26 and Doherty network 42 and ground. It should be noted that voltage Vd is supplied from an external output bias circuit as a drain bias voltage for carrier amplifier 20.

[0111] Output matching circuit 32 includes capacitor C28, capacitor C16, and inductor L16. Capacitor C28 and inductor L16 are connected in series, in that order, between the drain of peak amplifier 30 and Doherty network 42. Capacitor C28 blocks DC components. Capacitor C16 is connected between the node between the drain of peak amplifier 30 and capacitor C28 and ground. It should be noted that voltage Vd is supplied from an external output bias circuit as a drain bias voltage for peak amplifier 30.

[0112] The Doherty network 42 includes a capacitor C25 connected between a node between the capacitor C26 and the inductor L16 and the output terminal RFout and ground.

[0113] (Structure of high-frequency amplifier)

[0114] Next, the configuration of the high-frequency amplifier 1 according to the embodiment will be described. Figure 4 1 is a cross-sectional view showing a high-frequency amplifier according to an embodiment. Figure 4 The schematic cross section of the high frequency amplifier 1 is shown in FIG. 1 , and the arrangement of the driver amplifier 10, the carrier amplifier 20, the peak amplifier 30, the surface mount components, the transmission line pattern, and the conductive vias are shown in FIG. Figures 1 to 3 The circuits shown do not constitute a correspondence.

[0115] Focusing on the cross-sectional composition, such as Figure 4 As shown, the high-frequency amplifier 1 includes a first stacked structure 111, a second stacked structure 112, and a third stacked structure 113. The second stacked structure 112 is provided on the first stacked structure 111, and the third stacked structure 113 is provided on the second stacked structure 112. The first stacked structure 111, the second stacked structure 112, and the third stacked structure 113 have, for example, a square planar shape with each side being 6 mm long.

[0116] The first stacked structure 111 includes a wiring layer 121 , a dielectric layer 131 , a wiring layer 122 , a dielectric layer 132 , a driver amplifier 10 , a carrier amplifier 20 , a peaking amplifier 30 , and a plurality of surface mount components 51 .

[0117] The wiring layer 122 is provided on the lower surface of the dielectric layer 132. The thickness of the dielectric layer 132 is, for example, not less than 0.1 mm and not more than 0.2 mm. For example, the relative dielectric constant of the dielectric layer 132 is not less than 3.0 and not more than 3.7, and the dielectric loss tangent is not less than 0.002 and not more than 0.007. The thickness of the wiring layer 122 is, for example, not less than 10 μm and not more than 45 μm. The thickness of the wiring layer 122 can also be not less than 35 μm and not more than 45 μm. The wiring layer 122 is, for example, a copper layer. The details will be described later, but a transmission line pattern and a ground pattern are formed in the wiring layer 122. The conductivity of copper is 6.25×10 17 S / m approximately.

[0118] The driver amplifier 10 is mounted on the lower surface of the wiring layer 122. The driver amplifier 10 is, for example, an amplifier including a gallium nitride (GaN)-based high electron mobility transistor (HEMT). The driver amplifier 10 includes a substrate and a semiconductor layer provided on the substrate. The driver amplifier 10 has a rectangular parallelepiped three-dimensional shape having a main surface 10a and a main surface 10b opposite to the main surface 10a. The main surface 10a is located on the semiconductor layer, and the main surface 10b is located on the substrate. An amplifier circuit including a semiconductor layer is formed on the main surface 10a. On the main surface 10a, a gate pad is provided near one of two parallel sides, and a drain pad is provided near the other side. In addition, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes provided on the main surface 10b. The main surface 10a faces upward, and the main surface 10b faces downward.

[0119] The carrier amplifier 20 is mounted on the lower surface of the wiring layer 122. The carrier amplifier 20 is, for example, an amplifier including a GaN-based HEMT. The carrier amplifier 20 includes a substrate and a semiconductor layer disposed on the substrate. The carrier amplifier 20 has a rectangular parallelepiped shape having a main surface 20a and a main surface 20b opposite to the main surface 20a. The main surface 20a is located on the semiconductor layer, and the main surface 20b is located on the substrate. An amplifier circuit including the semiconductor layer is formed on the main surface 20a. A gate pad is provided near one of two parallel sides of the main surface 20a, and a drain pad is provided near the other side. Furthermore, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes disposed on the main surface 20b. The main surface 20a faces upward, and the main surface 20b faces downward.

[0120] Peak amplifier 30 is mounted on the lower surface of wiring layer 122. Peak amplifier 30 is, for example, an amplifier including a GaN-based HEMT. Peak amplifier 30 includes a substrate and a semiconductor layer disposed on the substrate. Peak amplifier 30 has a rectangular parallelepiped shape having a main surface 30a and a main surface 30b opposite to main surface 30a. Main surface 30a is located on the semiconductor layer, while main surface 30b is located on the substrate. An amplifier circuit including the semiconductor layer is formed on main surface 30a. On main surface 30a, a gate pad is provided near one of two parallel sides, and a drain pad is provided near the other side. In addition, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes disposed on main surface 30b. Main surface 30a faces upward, while main surface 30b faces downward.

[0121] Surface mount component 51 is, for example, a capacitor, an inductor, or a resistor, and is mounted on the lower surface of wiring layer 122 .

[0122] Dielectric layer 131 is provided below dielectric layer 132. Dielectric layer 131 covers wiring layer 122 and surface mount components 51 from below. Dielectric layer 131 also covers the side surfaces of driver amplifier 10, carrier amplifier 20, and peaking amplifier 30 from the sides. Main surface 10b of driver amplifier 10, main surface 20b of carrier amplifier 20, and main surface 30b of peaking amplifier 30 are not covered by dielectric layer 131 but are exposed from dielectric layer 131. The thickness of dielectric layer 131 is, for example, not less than 0.3 mm and not more than 0.4 mm. The relative dielectric constant of dielectric layer 131 is, for example, not less than 3.0 and not more than 3.7, and the dielectric loss tangent is, for example, not less than 0.002 and not more than 0.007.

[0123] Wiring layer 121 is provided on the lower surface of dielectric layer 131. The thickness of wiring layer 121 is, for example, not less than 10 μm and not more than 120 μm. Alternatively, the thickness of wiring layer 121 may be not less than 80 μm and not more than 120 μm. Wiring layer 121 is, for example, a copper layer. While details will be described later, wiring layer 121 includes a transmission line pattern and a ground pattern.

[0124] Second stacked structure 112 includes wiring layer 123, dielectric layer 133, and wiring layer 124. Wiring layer 123 is provided on the lower surface of dielectric layer 133, and wiring layer 124 is provided on the upper surface of dielectric layer 133. Dielectric layer 133 is provided between wiring layer 123 and wiring layer 124.

[0125] Wiring layer 123 is provided on dielectric layer 132. The thickness of wiring layer 123 is, for example, not less than 10 μm and not more than 35 μm. The thickness of wiring layer 123 may also be not less than 10 μm and not more than 18 μm. Wiring layer 123 is, for example, a copper layer. While details will be described later, capacitor electrode patterns and a ground pattern are formed in wiring layer 123. The ground pattern is formed in a べた (Japanese: べた) pattern, separated from the electrode pattern. Wiring layer 123 is an example of a first wiring layer.

[0126] The thickness of dielectric layer 133 is, for example, not less than 1 μm and not more than 24 μm. For example, dielectric layer 133 has a relative dielectric constant of not less than 7.0 and not more than 10.0, and a dielectric loss tangent of not less than 0.01 and not more than 0.03.

[0127] The thickness of wiring layer 124 is, for example, not less than 10 μm and not more than 35 μm. Alternatively, the thickness of wiring layer 124 may be not less than 10 μm and not more than 18 μm. Wiring layer 124 is, for example, a copper layer. While details will be described later, a ground pattern is formed throughout wiring layer 124. Wiring layer 124 is an example of a second wiring layer.

[0128] Third stacked structure 113 includes dielectric layer 134, wiring layer 125, dielectric layer 135, wiring layer 126, dielectric layer 136, and a plurality of surface mount components 52. Wiring layer 125 is provided on the lower surface of dielectric layer 135, and wiring layer 126 is provided on the upper surface of dielectric layer 135. Dielectric layer 135 is provided between wiring layer 125 and wiring layer 126.

[0129] The thickness of the dielectric layer 135 is, for example, not less than 0.1 mm and not more than 0.2 mm. For example, the relative dielectric constant of the dielectric layer 135 is not less than 3.0 and not more than 3.7, and the dielectric loss tangent is not less than 0.002 and not more than 0.007. The thickness of the wiring layer 125 is, for example, not less than 10 μm and not more than 35 μm. The thickness of the wiring layer 125 can also be not less than 20 μm and not more than 35 μm. The thickness of the wiring layer 126 is, for example, not less than 10 μm and not more than 45 μm. The thickness of the wiring layer 126 can also be not less than 30 μm and not more than 45 μm. The wiring layer 125 and the wiring layer 126 are, for example, copper layers. The details will be described later, but a ground pattern is formed all over the wiring layer 125, and a transmission line pattern and a ground pattern are formed in the wiring layer 126.

[0130] Dielectric layer 134 is provided between dielectric layer 133 and dielectric layer 135, covering wiring layer 124 from above and wiring layer 125 from below. The thickness of dielectric layer 134 is, for example, not less than 0.1 mm and not more than 0.2 mm. For example, dielectric layer 134 has a relative dielectric constant of not less than 3.0 and not more than 3.7, and a dielectric loss tangent of not less than 0.002 and not more than 0.007.

[0131] The surface mount component 52 is, for example, a capacitor, an inductor, or a resistor, and is mounted on the upper surface of the wiring layer 126 .

[0132] Dielectric layer 136 is provided on dielectric layer 135. Dielectric layer 136 covers wiring layer 126 and surface mount components 52 from above. The thickness of dielectric layer 136 is, for example, 0.4 mm to 1.0 mm. For example, dielectric layer 136 has a relative dielectric constant of 3.0 to 4.0, and a dielectric loss tangent of 0.002 to 0.012.

[0133] Conductive vias 141 and 142 for signal transmission, as well as conductive via 151 for grounding, are provided in dielectric layer 131. Conductive vias 141, 142, and 151 electrically connect a portion of wiring layer 121 to a portion of wiring layer 122, respectively. The portion of wiring layer 121 connected to conductive via 141 functions as input terminal RFin, while the portion of wiring layer 121 connected to conductive via 142 functions as output terminal RFout. The portion of wiring layer 121 connected to conductive via 151 functions as a ground terminal, assigned a ground potential.

[0134] Conductive vias 143 for signal transmission are provided in the dielectric layer 132. The conductive vias 143 electrically connect a portion of the wiring layer 122 and a portion of the wiring layer 123.

[0135] Conductive vias 153 for grounding are provided in the dielectric layer 133. The conductive vias 153 electrically connect a part of the wiring layer 123 and a part of the wiring layer 124.

[0136] A conductive via 155 for grounding is provided in the dielectric layer 135. The conductive via 155 electrically connects a part of the wiring layer 125 and a part of the wiring layer 126.

[0137] Conductive vias 156 for grounding are provided in dielectric layers 133, 134, and 135. Conductive vias 156 electrically connect a portion of wiring layer 123, a portion of wiring layer 124, a portion of wiring layer 125, and a portion of wiring layer 126.

[0138] Conductive vias 144 for signal transmission and conductive vias 157 for grounding are provided in dielectric layers 132, 133, 134, and 135. Conductive vias 144 electrically connect a portion of wiring layer 122 to a portion of wiring layer 126. Conductive vias 144 may also be electrically connected to a portion of wiring layer 123. Conductive vias 157 electrically connect a portion of wiring layer 122, a portion of wiring layer 123, a portion of wiring layer 124, a portion of wiring layer 125, and a portion of wiring layer 126.

[0139] The stripline circuit is formed by the transmission line pattern formed in wiring layer 122, the ground pattern formed in wiring layer 123, and the portion of dielectric layer 132 located between the transmission line pattern and the ground pattern. Furthermore, the stripline circuit is formed by the transmission line pattern formed in wiring layer 126, the ground pattern formed in wiring layer 125, and the portion of dielectric layer 135 located between the transmission line pattern and the ground pattern. The ground pattern formed in wiring layer 123, wiring layer 124, or wiring layer 125 shields electromagnetic waves generated in the first stacked structure 111 from propagating toward the third stacked structure 113, and shields electromagnetic waves generated in the third stacked structure 113 from propagating toward the first stacked structure 111.

[0140] In the second stacked structure 112, the electrode pattern formed on the wiring layer 123 is not electrically connected to the wiring layer 124, and a thin film capacitor is formed by the electrode pattern formed on the wiring layer 123, the ground pattern formed on the wiring layer 124, and the portion of the dielectric layer 133 located between the electrode pattern and the ground pattern.

[0141] High-frequency amplifier 1 is mounted on, for example, a printed circuit board 100 of a communication device. Printed circuit board 100 includes a base member 101, a signal trace 102 connected to input terminal RFin, a signal trace 103 connected to output terminal RFout, and a ground trace 104 connected to a ground terminal. Signal trace 102, signal trace 103, and ground trace 104 are provided on the top surface of base member 101.

[0142] The portion of the transmission line pattern of wiring layer 121 connected to signal wiring 102 connected to input terminal RFin is connected to a portion of the transmission line pattern of wiring layer 122 (the input of input matching circuit 11) via conductive via 141. Furthermore, the portion of the transmission line pattern of wiring layer 121 connected to signal wiring 103 connected to output terminal RFout is connected to a portion of the transmission line pattern of wiring layer 122 (the output of Doherty network 42) via conductive via 142. Furthermore, the ground pattern of wiring layer 121 is connected to the ground patterns of wiring layers 122, 123, 124, 125, and 126 via conductive vias 151, 153, 155, 156, and 157. Grounding conductive vias may also be provided in dielectric layer 132.

[0143] The portion of the transmission line pattern of the wiring layer 122 connected to the drain pad (output terminal 19) of the driver amplifier 10 is connected via a conductive via 144 ( Figure 5 and Figure 9 The conductive via 91 in the wiring layer 126 is connected to a portion of the transmission line pattern (the input of the output matching circuit 12). The portion of the transmission line pattern of the wiring layer 126 connected to the output of the phase adjustment circuit 23 is connected via a conductive via 144 ( Figure 5 and Figure 9 The conductive via 92 in the wiring layer 126 is connected to a portion of the transmission line pattern of the wiring layer 122 (the input of the input matching circuit 21). The portion of the transmission line pattern of the wiring layer 126 connected to the output of the phase adjustment circuit 33 is connected via a conductive via 144 ( Figure 5 and Figure 9 The conductive via 93 in the wiring layer 122 is connected to a portion of the transmission line pattern (the input of the input matching circuit 31).

[0144] A portion of the transmission line pattern of the wiring layer 122 is connected to a portion of the electrode pattern of the wiring layer 123 through the conductive via 143 .

[0145] Next, the layout of each wiring layer will be described. Figure 5 1 is a diagram showing the layout of the wiring layer 126 . Figure 6 1 is a diagram showing the layout of the wiring layer 125 . Figure 7 1 is a diagram showing the layout of the wiring layer 124 . Figure 8 1 is a diagram showing the layout of the wiring layer 123 . Figure 9 1 is a diagram showing the layout of the wiring layer 122 . Figure 10 1 is a diagram showing the layout of the wiring layer 121. Figures 5 to 10 In the ground pattern, a pear-skin pattern (a dot-like pattern) is marked. Figure 5Also shown is a surface mount component 52. Figure 9 Also shown are a surface mount component 51 , a driver amplifier 10 , a carrier amplifier 20 , and a peaking amplifier 30 .

[0146] like Figure 5 As shown, wiring layer 126 includes a ground pattern 126G, a transmission line pattern that constitutes output bias circuit 14, and a transmission line pattern that constitutes output matching circuit 12. Wiring layer 126 also includes transmission line patterns that constitute branch circuit 41, phase adjustment circuit 23, and phase adjustment circuit 33. Capacitors C6, C8, C23, C24, C29, C30, and C32, capacitor C1, inductors L3, L10, L4, L9, L5, L11, L12, L13, L14, and L15, and resistor R3 are mounted as surface mount components 52 on the upper surface of the transmission line pattern of wiring layer 126.

[0147] like Figure 6 As shown, a ground pattern 125G is formed all over the wiring layer 125. An opening through which the conductive via 144 passes is formed in the wiring layer 125.

[0148] like Figure 7 As shown, a ground pattern 124G is formed all over the wiring layer 124. An opening through which the conductive via 144 passes is formed in the wiring layer 124.

[0149] like Figure 8 As shown, a ground pattern 123G is formed throughout the wiring layer 123. Furthermore, electrode patterns for capacitors C2 or C4 of the input matching circuit 11, capacitors C12 or C7 of the input matching circuit 21, and capacitors C5 or C13 of the input matching circuit 31 are formed in the wiring layer 123. Openings are formed in the wiring layer 123 through which the conductive vias 144 extend.

[0150] like Figure 9As shown, the wiring layer 122 includes a ground pattern 122G, a transmission line pattern constituting the input matching circuit 11, and a transmission line pattern constituting the Doherty network 42. Furthermore, the wiring layer 122 includes a transmission line pattern constituting the input matching circuit 21, a transmission line pattern constituting the input bias circuit 24, and a transmission line pattern constituting the output matching circuit 22. Furthermore, the wiring layer 122 includes a transmission line pattern constituting the input matching circuit 31, a transmission line pattern constituting the input bias circuit 34, and a transmission line pattern constituting the output matching circuit 32. Capacitor C3, capacitor C11, capacitor C15, capacitor C9, capacitor C26, capacitor C10, capacitor C21, capacitor C28, capacitor C16 and capacitor C25, inductor L1, inductor L2, inductor L17, inductor L6, inductor L7, inductor L8 and inductor L16, and resistor element R4 and resistor element R5 are mounted as surface mount components 51 on the lower surface of the transmission line pattern of the wiring layer 122.

[0151] like Figure 10 As shown, a ground pattern 121G is formed all over the wiring layer 121 .

[0152] The output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20 may be adjacent to each other. However, if the spatial distance between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20 is small and the phase difference of the RF signal between the output terminal 19 and the input terminal 28 is small (including the same phase), there is a risk of electrical instability. For example, oscillation may occur.

[0153] In contrast, if the phase of the RF signal between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20 becomes opposite, electrical instability can be minimized. For example, if the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20, converted into the phase of the wavelength λ of the RF signal input to the input terminal RFin, is within the range of [(2n+1)×π-π / 2] or greater and [(2n+1)×π+π / 2] or less, the phase of the RF signal approaches opposite phase, making electrical instability less likely. In other words, even when the driver amplifier 10 and the carrier amplifier 20 are close to each other, the electrical characteristics of the carrier amplifier 20 are more easily stabilized. Here, n is an integer greater than 0.

[0154] Furthermore, the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peaking amplifier 30 may be adjacent to each other. However, if the spatial distance between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peaking amplifier 30 is small and the phase difference of the RF signal between the output terminal 19 and the input terminal 38 is small (including the same phase), there is a risk of electrical instability. For example, oscillation may occur.

[0155] In contrast, if the phase of the RF signal between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peaking amplifier 30 becomes opposite, electrical instability can be minimized. For example, if the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peaking amplifier 30, converted into the phase of the wavelength λ of the RF signal input to the input terminal RFin, is within the range of [(2n+1)×π-π / 2] or greater and [(2n+1)×π+π / 2] or less, the phase of the RF signal approaches opposite phase, making electrical instability less likely. In other words, even when the driver amplifier 10 and the peaking amplifier 30 are close to each other, the electrical characteristics of the peaking amplifier 30 are easily stabilized.

[0156] In this embodiment, the wiring layer 126 has Figure 5 The transmission line pattern shown in FIG. 1 is such that the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30 is within the range of [(2n+1)×π-π / 2] or more and [(2n+1)×π+π / 2] or less. Specifically, for example, Figure 5 In the diagram, the transmission line pattern from the output terminal (drain output) of the driver amplifier 10 to the branch circuit 41 curves significantly from the center to the right half. Furthermore, the phase adjustment circuit 23 is provided between the branch circuit 41 and the carrier amplifier 20, and the phase adjustment circuit 33 is provided between the branch circuit 41 and the peaking amplifier 30. Furthermore, the transmission line pattern from the output of the branch circuit 41 to the conductive via 92 and the transmission line pattern from the output of the branch circuit 41 to the conductive via 93 are not straight lines but curved.

[0157] Furthermore, heat generated by driver amplifier 10 is transferred from main surface 10b to wiring layer 121, heat generated by carrier amplifier 20 is transferred from main surface 20b to wiring layer 121, and heat generated by peaking amplifier 30 is transferred from main surface 30b to wiring layer 121. The heat transferred to wiring layer 121 is then released to the outside via ground wiring 104 of printed circuit board 100.

[0158] (Operation of a high-frequency amplifier)

[0159] Next, the operation of the high-frequency amplifier 1 will be described.

[0160] The RF signal input to the input terminal RFin (a part of the wiring layer 121) via the signal wiring 102 reaches the wiring layer 122 via the conductive via 141, and is input to the driver amplifier 10 via the input matching circuit 11 provided in the wiring layer 122. The RF signal amplified by the driver amplifier 10 travels through the conductive via 91 to the wiring layer 126. The RF signal is then transmitted to the branch circuit 41 via the output matching circuit 12 in the wiring layer 126, and is branched by the branch circuit 41 and output to the first signal path 41A and the second signal path 41B.

[0161] The RF signal output to first signal path 41A is input to phase adjustment circuit 23. Phase adjustment circuit 23 delays the phase of the input RF signal (input signal to carrier amplifier 20) by a predetermined distributed constant and outputs the signal. Meanwhile, the RF signal output to second signal path 41B is input to phase adjustment circuit 33. Phase adjustment circuit 33 delays the phase of the input RF signal (input signal to peak amplifier 30) by a predetermined distributed constant and outputs the signal. The RF signal output from phase adjustment circuit 23 travels through conductive via 92 to wiring layer 122 and is input to carrier amplifier 20 via input matching circuit 21. The RF signal output from phase adjustment circuit 33 travels through conductive via 93 to wiring layer 122 and is input to peak amplifier 30 via input matching circuit 31.

[0162] In the asymmetric Doherty amplifier 40, the peaking amplifier 30 and the carrier amplifier 20 exhibit different maximum output intensities for the input RF signal. For example, the peaking amplifier 30 has a saturated output (magnitude) approximately twice that of the carrier amplifier 20, and the peaking amplifier 30 begins amplification when the output of the carrier amplifier 20 reaches the saturation region. Specifically, the carrier amplifier 20 operates in class AB or class B, while the peaking amplifier 30 operates in class C. When the instantaneous power is low, the carrier amplifier 20 operates while the peaking amplifier 30 does not, thereby improving power efficiency. When the instantaneous power is high, both the carrier amplifier 20 and the peaking amplifier 30 operate, thereby maintaining high power efficiency and increasing the saturated power. When the saturated output of the peaking amplifier 30 is greater than that of the carrier amplifier 20, the phase shift required to achieve optimal matching in the peaking amplifier 30 is greater than the phase shift required to achieve optimal matching in the carrier amplifier 20.

[0163] For example, the driver amplifier 10 has a size sufficient to output 10 W, the carrier amplifier 20 has a size sufficient to output 15 W, and the peaking amplifier 30 has a size sufficient to output 30 W. In this case, the current consumption or power consumption may increase in the order of the driver amplifier 10, the carrier amplifier 20, and the peaking amplifier 30. Furthermore, the amount of heat generated during operation may also increase in the order of the driver amplifier 10, the carrier amplifier 20, and the peaking amplifier 30.

[0164] The RF signal amplified by the carrier amplifier 20 is input to the Doherty network 42 via the output matching circuit 22, and the RF signal amplified by the peak amplifier 30 is input to the Doherty network 42 via the output matching circuit 32. The RF signal output from the Doherty network 42 then reaches the output terminal RFout (a part of the wiring layer 121) via the conductive via 142 and is output via the signal wiring 103.

[0165] (Method for manufacturing high-frequency amplifier)

[0166] Next, a method for manufacturing the high-frequency amplifier 1 will be described. Figures 11 to 17 It is a cross-sectional view showing a method of manufacturing the high-frequency amplifier according to the embodiment.

[0167] First, if Figure 11 As shown, a laminate is produced in which a wiring layer 125 is formed on the lower surface of a dielectric layer 135, a wiring layer 126 is formed on the upper surface of the dielectric layer 135, and a conductive via 155 is formed within the dielectric layer 135. This laminate can be produced using, for example, a copper-clad laminate. It should be noted that at this point in time, the portion of the wiring layer 126 that overlaps with the conductive via 144, the conductive via 156, or the conductive via 157 has not yet been formed.

[0168] In addition, if Figure 12 As shown, a second stacked structure 112 is formed with a wiring layer 123 formed on the lower surface of a dielectric layer 133, a wiring layer 124 formed on the upper surface of the dielectric layer 133, and conductive vias 153 formed inside the dielectric layer 133. The second stacked structure 112 can be made of, for example, a copper-clad laminate.

[0169] Then, if Figure 13 As shown, dielectric layer 132, wiring layer 122, and conductive via 143 are formed under second stacked structure 112. It should be noted that at this point in time, the portion of wiring layer 122 that overlaps conductive via 144 or conductive via 157 has not yet been formed.

[0170] Then, if Figure 14 As shown, the dielectric layer 134 is configured in Figure 13 The stack shown is Figure 11 The stacking method shown makes Figure 11 The stack shown overlaps Figure 13 On top of the stack shown.

[0171] Then, if Figure 15 As shown, conductive vias 144, 156, and 157 are formed. At this time, portions of wiring layer 126 overlapping with conductive vias 144, 156, or 157 and portions of wiring layer 122 overlapping with conductive vias 144 or 157 are also formed.

[0172] Then, if Figure 16 As shown, surface mount component 52 is mounted on the upper surface of wiring layer 126, and surface mount component 51, driver amplifier 10, carrier amplifier 20, and peak amplifier 30 are mounted on the lower surface of wiring layer 122. In addition, conductive vias 141 and 142 are provided on the lower surface of wiring layer 122. Copper members can be used as conductive vias 141 and 142.

[0173] Then, if Figure 17 As shown, dielectric layer 136 is formed on dielectric layer 135, dielectric layer 131 is formed below dielectric layer 132, and wiring layer 121 is formed below dielectric layer 131. When forming dielectric layer 131, the dielectric layer to become dielectric layer 131 is formed thicker than dielectric layer 131, and then polished to expose the main surface 10b of driver amplifier 10, main surface 20b of carrier amplifier 20, and main surface 30b of peaking amplifier 30. Furthermore, wiring layer 121 includes a ground pattern connected to main surface 10b of driver amplifier 10, main surface 20b of carrier amplifier 20, and main surface 30b of peaking amplifier 30, as well as a transmission line pattern connected to conductive via 141 and a transmission line pattern connected to conductive via 142.

[0174] In this manner, the high-frequency amplifier 1 according to the embodiment can be manufactured.

[0175] In high-frequency amplifier 1, second multilayer structure 112 comprising wiring layer 123, dielectric layer 133, and wiring layer 124 is located between driver amplifier 10, carrier amplifier 20, and peaking amplifier 30, and branch circuit 41, phase adjustment circuit 23, and phase adjustment circuit 33. Therefore, signal interference between driver amplifier 10, carrier amplifier 20, and peaking amplifier 30 and branch circuit 41, phase adjustment circuit 23, and phase adjustment circuit 33 is less likely to occur, thereby improving high-frequency characteristics.

[0176] Furthermore, the uniformity of the path lengths between capacitors C2 , C4 , C7 , C12 , C5 , and C13 and the inputs of driver amplifier 10 , carrier amplifier 20 , or peak amplifier 30 is improved, thereby improving high-frequency characteristics.

[0177] Here, refer to Figure 18 and Figure 19 The high-frequency characteristics of the amplifier in two examples with different capacitor configurations will be described. Figure 18 is a diagram showing the layout in the first example, Figure 19 This is a diagram showing the layout in the second example.

[0178] exist Figure 18 In the first example shown, the amplifier 60 has gate terminals 211 , 212 , 213 , and 214 , source terminals 221 , 222 , and drain terminals 231 , 232 , 233 , and 234 .

[0179] Gate terminals 211, 212, 213, and 214 are arranged in this order along the first axis. Gate terminals 211, 212, 213, and 214 are connected to wiring layer 61. Wiring layer 61 is connected to a capacitor via conductive vias 71. This capacitor is provided in second stacked structure 112, similar to high-frequency amplifier 1.

[0180] Source terminal 221 and source terminal 222 are arranged in this order along the first axis. Source terminal 221 is located on the positive side of a second axis perpendicular to the first axis, relative to the rows of gate terminals 211, 212, 213, and 214. Source terminal 221 is located on the negative side of the first axis relative to gate terminal 211, while source terminal 222 is located on the positive side of the first axis relative to gate terminal 214. Source terminal 221 and source terminal 222 are connected to wiring layer 62. Wiring layer 62 is grounded via conductive vias 721 and 722. Conductive via 721 is located on the negative side of the first axis relative to amplifier 60, while conductive via 722 is located on the positive side of the first axis relative to amplifier 60.

[0181] Drain terminal 231, drain terminal 232, drain terminal 233, and drain terminal 234 are arranged in this order along the first axis. Drain terminal 231, drain terminal 232, drain terminal 233, and drain terminal 234 are located on the positive side of the second axis relative to the row of source terminals 221 and source terminals 222. Drain terminal 231 is located on the positive side of the first axis relative to source terminal 221, while drain terminal 234 is located on the negative side of the first axis relative to source terminal 222. Drain terminal 231, drain terminal 232, drain terminal 233, and drain terminal 234 are connected to wiring layer 63.

[0182] The input signal of amplifier 60 is input to wiring layer 61. The output signal of amplifier 60 is output to wiring layer 63. In amplifier 60, the signal flows as indicated by arrow 70. Driver amplifier 10, carrier amplifier 20, and peak amplifier 30 in high-frequency amplifier 1 can have the same structure as amplifier 60.

[0183] In amplifier 60, the signal path length between conductive via 71 and gate terminal 211 can be made equal to the signal path length between conductive via 71 and gate terminal 214. In addition, the signal path length between conductive via 71 and gate terminal 212 can be made equal to the signal path length between conductive via 71 and gate terminal 213.

[0184] exist Figure 19 In the second example shown, a wiring layer 64 is provided, and a capacitor of a surface mount component 80 is provided between the wiring layer 61 and the wiring layer 64. The wiring layer 64 is grounded through a conductive via 723. The rest of the configuration of the second example is the same as that of the first example.

[0185] In the second example, the difference in signal path lengths between the capacitor and the gate terminal 211 , the gate terminal 212 , the gate terminal 213 , and the gate terminal 214 is greater than that in the first example.

[0186] Thus, in the first example, the difference in signal path length between the capacitor and each of the gate terminals 211 , 212 , 213 , and 214 of the amplifier 60 is reduced compared to the second example, thereby achieving excellent high-frequency characteristics.

[0187] Furthermore, capacitors C2, C4, C7, C12, C5, and C13 are formed in the second stacked structure, eliminating the need for surface-mount components for these capacitors. Therefore, the number of surface-mount components can be reduced compared to using surface-mount components for these capacitors.

[0188] For example, by including capacitor C2 and capacitor C4 in input matching circuit 11, the number of surface-mounted components in input matching circuit 11 can be reduced. Furthermore, by including capacitor C7 and capacitor C12 in input matching circuit 21, the number of surface-mounted components in input matching circuit 21 can be reduced. Furthermore, by including capacitor C5 and capacitor C13 in input matching circuit 31, the number of surface-mounted components in input matching circuit 31 can be reduced.

[0189] Compared to using surface-mount components such as multilayer ceramic capacitors, the parasitic resistance and inductance of capacitors C2, C4, C7, C12, C5, and C13 formed in the second multilayer structure are reduced. Therefore, RF signal matching (high-frequency matching) can be performed with low impedance.

[0190] Furthermore, the ground pattern of wiring layer 123 is formed in a full-surface pattern. Therefore, even if dielectric layer 133 has a high relative permittivity, the influence of dielectric layer 133 on the RF signal propagating through the transmission line pattern of wiring layer 122 can be suppressed. In particular, output matching circuit 22, output matching circuit 32, and Doherty network 42 are susceptible to parasitic capacitance arising from the surrounding dielectric layers. Providing ground patterns (ground regions) in the portions of wiring layer 123 that overlap with the transmission line pattern of output matching circuit 22, the portions that overlap with the transmission line pattern of output matching circuit 32, and the portions that overlap with Doherty network 42 in plan view makes it easier to suppress degradation of RF signals in output matching circuit 22, output matching circuit 32, and Doherty network 42.

[0191] It should be noted that if either phase adjustment circuit 23 or phase adjustment circuit 33 is provided, the other one may not be provided. For example, if phase adjustment circuit 23 is provided, phase adjustment circuit 33 may not be provided; and if phase adjustment circuit 33 is provided, phase adjustment circuit 23 may not be provided.

[0192] Alternatively, a base member made of a metal such as copper may be used instead of the wiring layer 121. In this case, for example, the main surface 10b of the driver amplifier 10, the main surface 20b of the carrier amplifier 20, and the main surface 30b of the peak amplifier 30 may be bonded to the base member using a sintered material of silver or copper, and electrically connected to the base member.

[0193] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope described in the claims.

Claims

1. A high-frequency amplifier having: A driving amplifier amplifies the input high frequency signal; and an asymmetric Doherty amplifier, amplifying the high-frequency signal output from the driver amplifier, The high-frequency amplifier has: a first stacked structure; a second stacked structure stacked on the first stacked structure; and a third stacked structure stacked on the second stacked structure, The asymmetric Doherty amplifier has: Carrier amplifier; a peak amplifier that starts amplification when the output of the carrier amplifier reaches a saturation region and has a saturation output different from that of the carrier amplifier; a branch circuit to which the high-frequency signal output from the driving amplifier is input; a first signal path provided between the branch circuit and the carrier amplifier; a second signal path provided between the branch circuit and the peak amplifier; and a phase adjustment circuit provided in at least one of the first signal path or the second signal path, and delaying at least one of the phase of the input signal of the carrier amplifier or the phase of the input signal of the peak amplifier; The branch circuit branches the high-frequency signal output from the driver amplifier and outputs the signal to the first signal path and the second signal path. The second stacked structure has: a first wiring layer provided between the first stacked structure and the third stacked structure; a second wiring layer provided between the first wiring layer and the third stacked structure; a dielectric layer provided between the first wiring layer and the second wiring layer; as well as one or more capacitors including a portion of the first wiring layer, a portion of the second wiring layer, and a portion of the dielectric layer, The driver amplifier, the carrier amplifier, and the peak amplifier are provided in the first stacked structure. The branch circuit and the phase adjustment circuit are provided in the third stacked structure. The capacitor is electrically connected to any one of the driver amplifier, the carrier amplifier, or the peak amplifier.

2. The high-frequency amplifier according to claim 1, comprising: The first input matching circuit includes the capacitor and is connected to the input terminal of the driver amplifier.

3. The high-frequency amplifier according to claim 2, wherein The first input matching circuit is provided in the first stacked structure and the second stacked structure.

4. The high-frequency amplifier according to any one of claims 1 to 3, comprising: The second input matching circuit includes the capacitor and is connected to the input terminal of the carrier amplifier.

5. The high-frequency amplifier according to claim 4, wherein The second input matching circuit is provided in the first stacked structure and the second stacked structure.

6. The high-frequency amplifier according to any one of claims 1 to 3, comprising: The third input matching circuit includes the capacitor and is connected to the input terminal of the peak amplifier.

7. The high-frequency amplifier according to claim 6, wherein The third input matching circuit is provided in the first stacked structure and the second stacked structure.

8. The high-frequency amplifier according to any one of claims 1 to 3, wherein The first wiring layer has a ground region that overlaps with a transmission line that transmits a high-frequency signal output from the carrier amplifier or the peak amplifier at least in a plan view.

9. The high-frequency amplifier according to any one of claims 1 to 3, wherein: When n is an integer greater than or equal to 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the carrier amplifier is within a range of greater than or equal to [(2n+1)×π-π / 2] and less than or equal to [(2n+1)×π+π / 2] when converted into the phase of the high-frequency signal.

10. The high-frequency amplifier according to any one of claims 1 to 3, wherein When n is an integer greater than or equal to 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier is within a range of greater than or equal to [(2n+1)×π-π / 2] and less than or equal to [(2n+1)×π+π / 2] when converted into the phase of the high-frequency signal.

11. The high-frequency amplifier according to any one of claims 1 to 3, wherein The saturated output of the peak amplifier is greater than the saturated output of the carrier amplifier.

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