Gating signal adjustment method, electronic equipment, storage medium and product

Abstract

The invention relates to a gating signal adjusting method, electronic equipment, a storage medium and a product, and the method comprises the steps: generating a target leading output signal based on a read enable signal; the target preamble output signal is a preamble output signal of which the data strobe signal DQS period number captured in an effective window reaches a DQS period number threshold value; based on the target leading output signal, respectively performing gating fine tuning on a leading gating path and a trailing gating path through a logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gate control signal is aligned with the first rising edge of a leading section of the DQS, and the rising edge of the trailing gate control signal is aligned with the last rising edge of a trailing section of the DQS; and performing exclusive-or operation on the leading gate control signal and the trailing gate control signal to obtain a target gate control signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of microelectronics technology, and in particular to a gate signal adjustment method, electronic equipment, storage medium, and product. Background Art

[0002] The purpose of read enable signal training is to determine the round-trip delay between the physical layer and the dynamic random access memory (DRAM), so that the physical layer's data strobe signal is activated by the read gate at the correct time to capture the complete burst of read data. Therefore, read enable signal-based training is an essential step in the training process.

[0003] In related technologies, the training of the read enable signal relies on an additionally configured delay-locked loop (DLL) for gate alignment, which introduces significant hardware overhead and timing complexity as the DQS (Data Strobe Signal) data increases. Summary of the Invention

[0004] The present invention provides a gate signal adjustment method, electronic device, storage medium, and product that can solve the technical problem that traditional methods that rely on DLLs for gate alignment introduce significant hardware overhead and timing complexity. The technical solution is as follows.

[0005] In one aspect, a method for adjusting a gate signal is provided, the method comprising: Generate a target leading output signal based on the read enable signal; the target leading output signal is a leading output signal whose number of data strobe signal DQS cycles captured within the valid window reaches a DQS cycle number threshold; Based on the target leading output signal, gate fine-tuning is performed on the leading gating path and the trailing gating path respectively by a logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gating signal is aligned with the first rising edge of the leading segment of the DQS, and the rising edge of the trailing gating signal is aligned with the last rising edge of the trailing segment of the DQS; An exclusive OR operation is performed on the leading gating signal and the trailing gating signal to obtain the target gating signal.

[0006] On the other hand, an electronic device is provided, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the above-mentioned gating signal adjustment method.

[0007] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, and the computer program is loaded and executed by a processor to implement the above-mentioned gating signal adjustment method.

[0008] On the other hand, a computer program product is provided, comprising a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions that, when executed by a computer, cause the computer to execute to implement the gating signal adjustment method provided in the various optional implementations described above.

[0009] The gating signal adjustment method provided in the embodiments of the present application dynamically monitors the number of DQS valid window cycles and generates a target leading output signal. Combined with logic circuit fine-tuning techniques for the leading and trailing gating paths, this method directly achieves precise alignment of the gating signal with the leading and trailing segments of the DQS signal. The target gating signal is then obtained by performing an exclusive-OR operation on the leading and trailing gating signals. Compared to traditional DLL-dependent solutions, this method eliminates the need for additional DLL circuitry and dynamically adjusts the gating signal solely through programmable logic circuitry. This significantly reduces hardware overhead and timing complexity, effectively shortens training time, and avoids introducing additional interference. Furthermore, the target gating signal generated through the exclusive-OR operation can adaptively cover the entire valid window of the DQS signal, ensuring reliable data capture. This method is particularly suitable for high-speed, multi-channel storage interface scenarios, improving system performance while reducing power consumption.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0012] Figure 1 A flow chart of a method for adjusting a gate signal provided by an exemplary embodiment of the present application is shown; Figure 2 A flow chart of a method for adjusting a gate signal provided by another exemplary embodiment of the present application is shown; Figure 3 shows a timing diagram of a preamble gating signal provided by an exemplary embodiment of the present application; Figure 4 shows a timing diagram of a trailing gating signal provided by an exemplary embodiment of the present application; Figure 5 A schematic diagram of the system structure of a main device provided by an exemplary embodiment of the present application is shown; Figure 6 A schematic diagram illustrating a gating signal adjustment process provided by an exemplary embodiment of the present application is shown; Figure 7 A schematic diagram of a signal acquisition process provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present application. Rather, they are merely examples of methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0014] The embodiment of the present application provides a gating signal adjustment method, which can achieve gating alignment through internal synchronization logic, thereby eliminating the dependence on an additional delay-locked loop, effectively reducing system complexity while ensuring the accuracy and reliability of gating signal adjustment. Figure 1 FIG1 shows a flow chart of a gate signal adjustment method provided by an exemplary embodiment of the present application. The method can be executed by a host device, which can carry a DRAM (Dynamic Random-Access Memory). Figure 1 As shown, the method may include the following steps.

[0015] Step 110 , generating a target preamble output signal based on the read enable signal; the target preamble output signal is a preamble output signal when the number of cycles of the data strobe signal DQS captured within the valid window reaches a DQS cycle number threshold.

[0016] Among them, the read enable signal (RE) is a signal used to start the data reading process. The signal source of the read enable signal can be based on the DFI (DDR PHY Interface Protocol, DDR physical layer interface) protocol and generated by a hardware circuit, such as dfi_rddata_en (DFI Read Data Enable Signal, DFI read data enable signal), and its effective length can be aligned with the effective DQS length.

[0017] After obtaining the read enable signal, the master device can convert the read enable signal from a multi-bit signal to a single-bit signal through the rden_widen (read enable widening) module. That is, the read enable signal is equivalent to a continuous high-level 1-bit gating signal to generate an initial preamble output signal. Based on the preamble output signal, a gating signal is generated to capture the DQS cycle through the gating signal to obtain the DQS cycle corresponding to the preamble output signal. The DQS cycle number threshold is used to determine whether the gating position of the preamble output signal needs to be adjusted. After the position of the preamble output signal is adjusted and the number of DQS cycles corresponding to the preamble output signal reaches the DQS cycle number threshold, the preamble output signal is determined as the target preamble output signal. In other words, the target preamble output signal is a preamble signal triggered by the read enable signal and capable of capturing a sufficient number of DQS cycles within the valid time window.

[0018] During this process, the master device can dynamically monitor the valid window of the DQS signal during the training phase through the DDR PHY (double data rate physical layer interface). When it is monitored that N consecutive complete DQS cycles fall within the valid level range of the leading output signal, it is determined that a valid target leading output signal is generated. The value of the DQS cycle number threshold can be configured according to the specifications of the memory or the actual application scenario, and this application does not impose any restrictions on this.

[0019] Step 120: Based on the target leading output signal, gate fine-tuning is performed on the leading gating path and the trailing gating path respectively through the logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gating signal is aligned with the first rising edge of the leading segment of DQS, and the rising edge of the trailing gating signal is aligned with the last rising edge of the trailing segment of DQS.

[0020] The target leading output signal is the result of coarse adjustment of the read enable signal. In order to improve the accuracy of the gating signal, after obtaining the leading output signal, the master device can perform gating fine-tuning in two ways based on the leading output signal; among them, the logic circuit of the leading gating circuit is used to adjust the rising edge position of the leading gating signal to align it with the first rising edge of the DQS leading segment; the logic circuit of the trailing gating path is used to adjust the rising edge position of the trailing gating signal to align it with the last rising edge of the DQS trailing segment.

[0021] In an embodiment of the present application, the logic circuit of the trailing gating path performs gating fine-tuning based on the gating state signal corresponding to the target leading output signal, wherein the gating state signal is used to indicate the number of DQS cycles captured within the valid window corresponding to the target leading output signal, so as to achieve dynamic calibration.

[0022] Step 130 , performing an exclusive OR operation on the leading gating signal and the trailing gating signal to obtain a target gating signal.

[0023] The leading gating signal and the trailing gating signal are input into the exclusive OR logic circuit to output the final target gating signal. Since the rising edge of the leading gating signal corresponds to the starting position of the DQS leading segment and the rising edge of the trailing gating signal corresponds to the ending position of the DQS trailing segment, the high level interval of the target gating signal obtained after the exclusive OR operation will cover the valid data window of DQS, thereby ensuring the reliability and integrity of data capture.

[0024] In summary, the gating signal adjustment method provided in the embodiments of the present application dynamically monitors the number of DQS valid window cycles and generates a target leading output signal. Combined with logic circuit fine-tuning techniques for the leading and trailing gating paths, this method directly achieves precise alignment of the gating signal with the leading and trailing segments of the DQS. The target gating signal is then obtained by performing an XOR operation on the leading and trailing gating signals. Compared to traditional DLL-dependent solutions, this method eliminates the need for additional DLL circuits and dynamically adjusts the gating signal solely through programmable logic circuits. This significantly reduces hardware overhead and timing complexity, effectively shortens training time, and avoids introducing additional interference. Furthermore, the target gating signal generated through the XOR operation can adaptively cover the entire valid window of the DQS signal, ensuring reliable data capture. This method is particularly suitable for high-speed, multi-channel storage interface scenarios, improving system performance while reducing power consumption.

[0025] Figure 2 FIG. 1 shows a flow chart of a gate signal adjustment method provided by another exemplary embodiment of the present application. The method can be executed by a host device, which can carry a DRAM, such as Figure 2 As shown, the method may include the following steps.

[0026] Step 210 , generating a target preamble output signal based on the read enable signal; the target preamble output signal is a preamble output signal when the number of cycles of the data strobe signal DQS captured within the valid window reaches a DQS cycle number threshold.

[0027] In one possible implementation, the process of obtaining the number of DQS cycles corresponding to the leading output signal can be implemented as follows: The read enable signal is delayed according to the initial delay parameter to obtain a write data preamble gating signal. The delay position corresponding to the write data preamble gating signal is at least N clock cycles to the left of the DQS valid window, where N is a positive integer. The delay parameter is negatively correlated with the advance generation time of the read enable signal relative to DQS. Converting the write data leading gating signal into a serial signal to obtain a leading output signal; The number of cycles is captured within a valid window corresponding to the leading output signal to obtain the number of DQS cycles corresponding to the leading output signal.

[0028] Among them, the initial delay parameter can be set based on actual needs, and the master device can use the delay adjustment module to initially delay the read enable signal according to the initial delay parameter. Schematically, the master device can delay the position of the read enable signal to a position more than N clock cycles to the left of the RX DQS (Receive Data Strobe, receiving end data selection signal) to obtain the write data leading gating signal. Schematically, the position of the read enable signal after demonstration can be more than 8 clock cycles to the left of the RX DQS to ensure that the leading output signal obtained through subsequent adjustment can frame the leading segment of the DQS. The value of N can be set based on actual needs, and this application does not impose any restrictions on this.

[0029] After obtaining the write data pre-gating signal, the master device can convert the parallel write data preamble gating signal into a serial preamble output signal through the read enable stretching module to complete the signal format conversion; then, the master device performs cycle number capture within the valid window of the preamble output signal to obtain the DQS cycle corresponding to the preamble output signal; in one possible implementation, the master device can implement cycle number capture through a multiplexer and a logic circuit. The master device can configure channel 0 of the multiplexer as the input path of the preamble output signal, output the multiplexer gating signal corresponding to the preamble output signal, perform a logical AND operation on the multiplexer gating signal and DQS, and generate the currently valid gated data selection signal; the gated counter counts the read clock cycle of the gated data selection signal, and the counting result is the DQS cycle number corresponding to the preamble output signal. The counting result can be returned to the master device through the gated status signal, so that the master device can determine whether the current preamble output signal meets the timing requirements by comparing the counting result with the DQS cycle number threshold.

[0030] In the case where the DQS cycle number does not reach the DQS cycle number threshold, the master device can iteratively adjust the position of the read enable signal to coarsely adjust the read enable signal, so that the target leading output signal obtained after the adjustment can frame the DQS that reaches the DQS cycle number threshold. The process of generating the target leading output signal based on the read enable signal can be implemented as follows: When the number of DQS cycles corresponding to the leading output signal does not reach the DQS cycle number threshold, increase the delay parameter; generating an adjusted preamble output signal based on the increased delay parameter and the read enable signal; Iteratively adjust the delay parameter until the number of DQS cycles corresponding to the leading output signal reaches the DQS cycle number threshold, thereby obtaining the target leading output signal.

[0031] The master device can determine the number of DQS cycles framed by the leading output signal by judging the value of the gating status signal. If the number of DQS cycles framed by it does not reach the DQS cycle number threshold, the master device adjusts the delay parameter to increase the UIdelay (Unit Interval delay) of the leading gating path, resets the gating counter for counting, and repeatedly adjusts the delay parameter until the number of DQS cycles corresponding to the leading output signal reaches the DQS cycle number threshold. The master device stops adjusting the unit interval delay of the leading gating path, completes the training of the read enable signal, and obtains the target leading output signal.

[0032] Furthermore, in response to the delay parameter reaching a maximum parameter value but the number of DQS cycles being less than a DQS cycle threshold, an adjustment failure message is generated and reported. That is, if the DQS cycle number still does not meet the search condition when the delay parameter is adjusted to its maximum value, the master device generates and reports the adjustment failure message to the host. The adjustment failure message may be a flag indicating a training failure. The master device may then reset the preamble settings and exit training. Upon receiving a retraining instruction message from the host, the master device may re-perform the process of determining the target preamble output signal based on the read enable signal.

[0033] After obtaining the target leading output signal, the master device generates two gating signals based on the target leading output signal, namely the leading gating signal and the trailing gating signal, which respectively lock the leading segment and the trailing segment of the DQS.

[0034] Step 220 : Perform gate fine-tuning on the leader gating path through a logic circuit based on the target leader output signal to obtain a leader gating signal.

[0035] The process of generating the leading gating signal can be realized by the corresponding data strobe synchronization module and the corresponding logic circuit. The process can be implemented as follows: Inputting the target leading output signal and DQS into the first data strobe synchronization module to generate a leading gating signal which is initially at a low level; Performing an AND operation on the leading gating inverse signal of the leading gating signal and the target leading output signal to obtain a direct trigger signal and inputting the direct trigger signal into the first data strobe synchronization module, so that the first data strobe synchronization module updates the leading gating signal from a low level to a high level in response to the arrival of the first rising edge of DQS and the direct trigger signal being a high level until the target leading output signal is a low level; The position where the leading gating signal is updated from a low level to a high level is determined as the gating position of the leading gating signal.

[0036] In one possible implementation, before inputting the target preamble output signal into the first data strobe synchronization module, the method further includes: on the preamble gating path, the master device may first reduce the delay parameter of the unit interval delay line to ensure that the target preamble output signal is on the left side of the DQS preamble segment; thereafter, inputting the adjusted target preamble output signal and the DQS into the first data strobe synchronization module, the first data strobe synchronization module outputting a preamble gating signal that is initially at a low level, i.e., the signal is set to 0 by default, the preamble gating signal is inverted, and a logical AND operation is performed on the preamble gating signal and the target preamble output signal to generate a trigger signal for the first data strobe synchronization module, i.e., a direct trigger signal; Figure 3 FIG. 1 shows a timing diagram of a leading gating signal provided by an exemplary embodiment of the present application, as shown in FIG. Figure 3 As shown in the figure, when the DQS clock valid edge arrives, the leading gating signal is pulled high at the same time, and correspondingly, the direct trigger signal (gate_pre_direct) is pulled low at the same time. Therefore, the leading gating signal (pre_gate) switches from low level to high level at the first DQS edge and maintains it. Starting from the first leading segment, the gating position of the leading gating signal is determined by the above timing relationship, thereby realizing the generation of the leading gating signal.

[0037] Step 230 : Perform gate fine-tuning on the downstream gating path through a logic circuit based on the target leading output signal to obtain a downstream gating signal.

[0038] The process of generating the trailing gating signal can be implemented by the corresponding data strobe synchronization module and the corresponding logic circuit. The process can be implemented as follows: Obtaining a gating state signal of a target leading output signal, where the gating state signal is used to indicate the number of DQS cycles captured within a valid window corresponding to the target leading output signal; Input the gating state signal and DQS into the second data strobe synchronization module to generate a trailing gating signal initially at a low level; Inputting a trailing gating inverse signal of the trailing gating signal into the second data strobe synchronization module, so that the second data strobe synchronization module updates the trailing gating signal from a low level to a high level in response to the gating state signal jumping from a high level to a low level; The position where the trailing gating signal is updated from a low level to a high level is determined as the gating position of the trailing gating signal.

[0039] Among them, the gating state signal of the target leading output signal can be generated based on the counting result of the gating counter counting the DQS cycle of the gated data selection signal corresponding to the target leading output signal. When the gating state signal reaches the cycle number threshold, a high pulse level signal can be obtained. The position of the high pulse is the synchronization trigger point. Therefore, the master device synchronizes the trailing gating reverse signal with the gating state signal through the second data selection synchronization module. After the gating state signal is triggered to a high level, the second data selection synchronization module locks the state and outputs its reverse signal as the trailing gating signal. Figure 4 FIG. 1 shows a timing diagram of a trailing gate control signal provided by an exemplary embodiment of the present application, as shown in FIG. Figure 4 As shown in the figure, when the gate status signal (i.e., gate_status) jumps from a high level to a low level, the trailing gating signal (i.e., pst_gate) is updated from a low level to a high level. At this time, the rising edge of the trailing gating signal is just aligned with the last valid rising edge of DQS, thereby accurately locking the gating position of the trailing gating signal and realizing the generation of the trailing gating signal.

[0040] Step 240 , performing an exclusive OR operation on the leading gating signal and the trailing gating signal to obtain a target gating signal.

[0041] After obtaining the two gating signals, the master device performs an exclusive OR logic calculation on the leading gating signal and the trailing gating signal, thereby obtaining the enable gating that can select the DQS leading segment and the effective DQS, that is, the target gating signal.

[0042] After obtaining the target gating signal, the master device can obtain the gated data strobe signal based on the target gating signal. This process can be implemented as follows: Perform an AND operation on the target gating signal and DQS to obtain a gated data selection signal after gated operation.

[0043] In one possible implementation, the master device can configure channel 1 of the multiplexer as the input path of the target gating signal, output the multiplexer gating signal corresponding to the target gating signal, perform a logical AND operation on the multiplexer gating signal and DQS, and obtain a gated data selection signal after gated operation.

[0044] In another possible implementation, in order to ensure that the preamble gating signal is always before the DQS in the service, after determining the preamble gating signal, the master device may increase the preamble gating signal by a delay compensation of n unit intervals to obtain an adjusted preamble gating signal, where n is a positive integer; An XOR operation is performed on the adjusted leading gating signal and the trailing gating signal to obtain a target gating signal.

[0045] Among them, the value of n can be set based on actual needs and is not restricted in this application. The above adjustment can improve the anti-interference ability of the target gating signal. For example, when factors such as PVT (Process-Voltage-Temperature) cause the DQS phase to change, delay compensation provides a buffer space for DQS phase drift, ensuring that the gating signal always effectively covers the data window within a certain range, thereby reducing additional retraining processes, improving system stability, and saving adjustment time.

[0046] In summary, the gating signal adjustment method provided in the embodiments of the present application dynamically monitors the number of DQS valid window cycles and generates a target leading output signal. Combined with logic circuit fine-tuning techniques for the leading and trailing gating paths, this method directly achieves precise alignment of the gating signal with the leading and trailing segments of the DQS. The target gating signal is then obtained by performing an XOR operation on the leading and trailing gating signals. Compared to traditional DLL-dependent solutions, this method eliminates the need for additional DLL circuits and dynamically adjusts the gating signal solely through programmable logic circuits. This significantly reduces hardware overhead and timing complexity, effectively shortens training time, and avoids introducing additional interference. Furthermore, the target gating signal generated through the XOR operation can adaptively cover the entire valid window of the DQS signal, ensuring reliable data capture. This method is particularly suitable for high-speed, multi-channel storage interface scenarios, improving system performance while reducing power consumption.

[0047] In addition, by calling back the leading gating signal after training to compensate for the delay of several unit intervals, the system's anti-interference ability can be improved and the system stability can be improved.

[0048] The gating signal adjustment method provided in the embodiment of the present application can be applied to the training process design on the DDR PHY side of the master device. It can be constructed by digital circuits and implement read gate (read gating) generation, gate counting, gate ui delaylane (gating signal unit interval delay channel), synchronizer and other logic circuits through RTL (Register Transfer Level) code. The training execution is controlled by reading and writing relevant registers through software, the training status is judged, and the calculation and writing of the final result are completed. Figure 5 A schematic diagram of the system structure of a main device provided by an exemplary embodiment of the present application is shown in FIG. Figure 5 As shown, the master device may include a delay adjustment module 510, a gate counting module 520, a read enable widening module 530 and a data strobe synchronization module 540. Figure 5As shown in the figure, after the read enable signal is input into the system, the gated DQS signal is finally output. Each module in the system is implemented through digital circuits, and its functions are: The delay adjustment module 510 can be implemented as a unit interval delay line (UI_delayline), which adds a UI (Unit Interval) level delay to the current read enable signal to move the read enable signal backward to preset the initial position or move the read enable signal to scan DQS.

[0049] The gate counting module 520 can be implemented by a counter to count the number of cycles of DQS in the gated data gate_dqs (gate data strobe signal), and convert the cycle count value into a binary gated state signal according to a relational conversion formula. Schematically, taking the cycle number as x as an example, the relational conversion formula can be expressed as:

[0050] Through the above conversion, the high pulse signal of the gate state signal corresponds to the second to last bit of the DQS cycle number, that is, the last bit of the valid DQS.

[0051] In a possible implementation, the gate counter module can be implemented by FIFO, and the DQS clock after the gate is used as the read clock of the FIFO. The gate position can be determined by adjusting the FIFO write data.

[0052] The read enable stretching module 530 is used to stretch the number of bits of the read enable signal, converting it from a multi-bit signal to a single-bit signal, so as to convert the read enable signal into a continuous high-level 1-bit gating signal, which is used to generate a leading gating signal; In one possible implementation, the read enable stretching module can be replaced with a FIFO (First-In-First-Out Circuit). The FIFO can support cross-clock domain serial-to-parallel conversion and convert the read enable signal into a 1-bit gate signal.

[0053] The data strobe synchronization module 540 can be implemented by a combinational logic circuit. In one possible implementation, a sequential logic MUX circuit (Multiplexer) can be designed. The clock is DQS, and the input gate signal and the gate inversion signal are input. The output is switched by a selection signal to synchronize the trained gate signal with the DQS to ensure that the gate signal is aligned with the DQS edge, and to ensure that the leading gate signal can cover the leading segment of the DQS, and the trailing gate signal can cover the trailing segment of the DQS.

[0054] The rest can be realized through logic gate circuits.

[0055] Based on Figure 5 The system structure of the main device shown in the figure is as follows: Figure 6 FIG. 1 shows a schematic diagram of a gate signal adjustment process provided by an exemplary embodiment of the present application, as shown in FIG. Figure 6 As shown, the read enable signal (i.e., read en) is input into the system and enters the leading gating path. First, the read enable signal is delayed by the delay parameter (i.e., pre_uisel) at the delay adjustment module. After the delay, the read enable signal forms the write data leading gating signal (i.e., gate_pre_wrdata). Its signal position is adjusted to a distance of 100 ms from the RX N clock cycles on the left side of DQS; then, the write data leading gating signal is input into the read enable widening module, which converts the parallel write data leading gating signal into serial one, and outputs the leading output signal (i.e., pre_out). The leading output signal is output through channel 0 of the multiplexer as the multiplexer gating signal (i.e., mux_gate) and performs a logical AND operation with DQS to obtain the currently valid gated data selection signal (i.e., gate_dqs); the gated data selection signal is sent as input to the gated counter on the subsequent gating path, and the gated counter counts the signal and outputs the gated status signal (i.e., gate_status); the master device determines the value of the gated status signal to determine whether to adjust the delay parameter. If the number of DQS cycles indicated by the gated status signal does not reach the DQS cycle number threshold, the delay parameter is adjusted, the leading output signal is regenerated, and the above detection process is repeated until any of the following conditions is met: the DQ indicated by the gated status signal The number of S cycles reaches the DQS cycle number threshold, or the delay parameter is adjusted to the maximum value but still does not reach the DQS cycle number threshold; when the delay parameter is adjusted to the maximum value but still does not reach the DQS cycle number threshold, the master device determines that the training has failed, performs a reset operation, and exits the current training process; if the DQS cycle number reaches the DQS cycle number threshold, the master device obtains the target preamble output signal, and generates two gating signals based on the target preamble output signal through the corresponding data selection synchronization module on each gating path. On the preamble gating path, preamble gating synchronization processing is performed to align the preamble gating signal with the DQS preamble segment, thereby determining the gating position of the preamble gating signal and outputting the preamble gating signal (i.e., pre_gate). On the postamble gating path, postamble gating synchronization processing is performed to align the postamble gating signal with the DQS postamble segment, thereby determining the gating position of the postamble gating signal and outputting the postamble gating signal (i.e., pst_gate). The process of generating corresponding gating signals by each gating path can be referred to. Figure 2The relevant contents of the illustrated embodiment will not be repeated here. Afterwards, the master device performs an XOR operation on the leading gating signal and the trailing gating signal to obtain an enable gating signal (i.e., use_gate). Furthermore, the master device may also generate an enable gating signal, i.e., a target gating signal, after performing delay compensation on the leading gating signal by calling back a number of unit intervals.

[0056] Figure 7 FIG. 1 shows a schematic diagram of a signal acquisition process provided by an exemplary embodiment of the present application, as shown in FIG. Figure 7 As shown in the figure, after obtaining the target gating signal, the master device can read the DQS based on the target gating signal. The leading segment, valid DQS and trailing segment of the DQS can be framed by the target gating signal to achieve reliable data capture and obtain the target gating signal.

[0057] In an exemplary embodiment, an electronic device is provided, which can be implemented as a main device in the embodiment of the present application. The electronic device includes a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the above Figure 1 or Figure 2 All or part of the steps of any embodiment shown in any embodiment.

[0058] In an exemplary embodiment, a computer-readable storage medium is further provided. The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to implement all or part of the steps in the above-described gating signal adjustment method. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, or an optical data storage device.

[0059] In an exemplary embodiment, a computer program product is further provided, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, which, when executed by a computer, enable the computer to execute the above-mentioned Figure 2 or Figure 6 All or part of the steps of any embodiment shown in any embodiment.

[0060] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0061] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A gate signal adjustment method, characterized in that: The method comprises: Generate a target leading output signal based on the read enable signal; the target leading output signal is a leading output signal whose number of data strobe signal DQS cycles captured within the valid window reaches a DQS cycle number threshold; Based on the target leading output signal, gate fine-tuning is performed on the leading gating path and the trailing gating path respectively by a logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gating signal is aligned with the first rising edge of the leading segment of the DQS, and the rising edge of the trailing gating signal is aligned with the last rising edge of the trailing segment of the DQS; An exclusive OR operation is performed on the leading gating signal and the trailing gating signal to obtain the target gating signal.

2. The method according to claim 1, characterized in that The method further comprises: Delaying the read enable signal according to an initial delay parameter to obtain a write data preamble gating signal, wherein a delay position corresponding to the write data preamble gating signal is located at least N clock cycles to the left of the DQS valid window, where N is a positive integer; the delay parameter is negatively correlated with the advance generation duration of the read enable signal relative to the DQS; Converting the write data leading gating signal into a serial signal to obtain a leading output signal; The number of cycles is captured within a valid window corresponding to the leading output signal to obtain the number of DQS cycles corresponding to the leading output signal.

3. The method according to claim 2, characterized in that Generating a target leading output signal based on a read enable signal includes: When the number of DQS cycles corresponding to the leading output signal does not reach the DQS cycle number threshold, increasing the delay parameter; generating the adjusted preamble output signal based on the increased delay parameter and the read enable signal; The delay parameter is iteratively adjusted until the number of DQS cycles corresponding to the preamble output signal reaches the DQS cycle number threshold, thereby obtaining the target preamble output signal.

4. The method according to claim 3, characterized in that The method further comprises: In response to the delay parameter reaching a maximum parameter value but the DQS cycle number being less than the DQS cycle number threshold, adjustment failure information is generated and reported.

5. The method according to claim 1, wherein Performing gate fine-tuning on a leader gating path through a logic circuit based on the target leader output signal, including: Inputting the target leading output signal and the DQS into a first data strobe synchronization module to generate the leading gating signal initially at a low level; performing an AND operation on a leading gating inverse signal of the leading gating signal and the target leading output signal to obtain a direct trigger signal and inputting the direct trigger signal into the first data strobe synchronization module, so that the first data strobe synchronization module updates the leading gating signal from a low level to a high level in response to the arrival of a first rising edge of the DQS and the direct trigger signal being at a high level, until the target leading output signal is at a low level; The position where the leading gating signal is updated from a low level to a high level is determined as the gating position of the leading gating signal.

6. The method according to claim 1, characterized in that Performing gate fine-tuning on a subsequent gating path through a logic circuit based on the target leading output signal, including: Acquire a gating state signal of the target leading output signal, where the gating state signal is used to indicate the number of DQS cycles captured within a valid window corresponding to the target leading output signal; Inputting the gating state signal and the DQS into a second data strobe synchronization module to generate the trailing gating signal initially at a low level; inputting a trailing gating inverse signal of the trailing gating signal into the second data strobe synchronization module, so that the second data strobe synchronization module updates the trailing gating signal from a low level to a high level in response to the gating state signal jumping from a high level to a low level; A position where the subsequent gating signal is updated from a low level to a high level is determined as a gating position of the subsequent gating signal.

7. The method according to claim 1, characterized in that The performing an XOR operation on the leading gating signal and the trailing gating signal to obtain the target gating signal includes: Adding a delay compensation of n unit intervals to the preamble gating signal to obtain an adjusted preamble gating signal, where n is a positive integer; An exclusive OR operation is performed on the adjusted leading gating signal and the trailing gating signal to obtain the target gating signal.

8. The method according to claim 1, characterized in that The method further comprises: An AND operation is performed on the target gating signal and the DQS to obtain a gated data strobe signal.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the gating signal adjustment method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one computer program, and the computer program is loaded and executed by the processor to implement the gating signal adjustment method according to any one of claims 1 to 8.

11. A computer program product, characterized in that The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program includes program instructions. When the program instructions are executed by a computer, the computer is caused to execute to implement the gating signal adjustment method according to any one of claims 1 to 8.

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