Quantum resistance device carrying platform without liquid helium conduction cooling

Abstract

The invention relates to a liquid-helium-conduction-free cooling quantum resistance device carrying platform, and the carrying platform comprises a cold conduction column which is provided with a heat conduction thread at the outer edge of the bottom and is used for binding a cold conduction belt; the center of the bottom of the chip carrying table is fixedly connected with the top of the cold conduction column; the circuit board group comprises an interface circuit board, a first carrier plate, a second carrier plate, a third carrier plate and a fourth carrier plate which are stacked from top to bottom and are electrically connected with one another through gold-plated contact pins; the first carrier plate is fixed below the interface circuit board through an isolated interface, the second carrier plate and the third carrier plate are fixedly mounted on the upper side of the chip carrier, and the fourth carrier plate is fixedly connected below the third carrier plate; the resistor chip is fixed on the upper surface of the chip carrier and is electrically connected with the gold-plated patch on the surface of the second carrier through a bonding lead; and the gold-plated patch and the gold-plated pin form a path. The operation complexity is obviously reduced, long-term stable operation of the quantum resistor in a liquid-helium-free environment is realized, and the traceability precision of resistance value transmission is ensured.

Description

Technical Field

[0001] The present application relates to the field of quantum measurement technology, and in particular to a liquid helium-free conduction-cooled quantum resistance device carrier. Background Art

[0002] As the core component of quantum resistance standards, quantum Hall resistor chips play an irreplaceable role in precision measurement, semiconductor testing, and quantum information. They need to operate in extremely low temperatures (usually below 4K), vacuum, and strong magnetic field environments to ensure the stability of the quantum Hall effect. Traditional technologies rely on liquid helium refrigeration systems to maintain low-temperature environments, but liquid helium is expensive, complex to store and transport, and has the risk of gasification and leakage, which limits the widespread application of quantum resistance standards. In recent years, liquid helium-free refrigeration technologies (such as pulse tube refrigerators and GM refrigerators) have gradually replaced liquid helium systems, but there are still technical bottlenecks in chip thermal management, interface connection, and mechanical fixation, as shown below: In existing liquid helium-free devices, quantum Hall resistor chips are typically coupled to the cryocooler cold head via thermally conductive adhesive or metal pressing plates. However, uneven chip power distribution (e.g., variations in electrode contact resistance, localized Joule heating) and design flaws in the heat transfer path (e.g., high interface thermal resistance, anisotropy of the thermal conductive material) can lead to significant temperature gradients on the chip surface. This uneven heat distribution can cause temperature fluctuations that disrupt the integer quantum states of the quantum Hall resistor, causing the resistance value to deviate from the theoretical value.

[0003] The quantum resistor chip needs to be connected to the external circuit via high-temperature superconducting wires to reduce the interference of the wire resistance on the measurement. In the existing technology, the interface connection between the superconducting wires and the chip electrodes is poorly compatible and easily damages the bonding wires of the resistor chip. In addition, the multi-layer interface (cold head-cooling column-carrier-chip) introduces additional thermal resistance, resulting in reduced cooling efficiency and difficulty in disassembling the Hall resistor chip. It is sensitive to electromagnetic interference, and an unreasonable wire layout (such as long parallel wires) introduces parasitic inductance. The chip carrier and its fixing structure (such as the near-point position screw) are magnetic, which makes the carrier prone to eddy current loss and hysteresis loss in a magnetic field environment. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned prior art, a liquid helium-free conduction-cooled quantum resistor device carrier is provided to achieve high-stability conduction cooling, mechanical fixation and superconducting lead connection of the resistor chip.

[0005] The present invention provides a liquid helium-free conductive cooling quantum resistance device carrier, comprising: The cooling column has a heat-conducting thread on the bottom outer edge for binding the cooling belt; The chip carrier, the center of the bottom is fixedly connected to the top of the cooling column; A circuit board assembly includes an interface circuit board, a first carrier board, a second carrier board, a third carrier board, and a fourth carrier board stacked from top to bottom, each board electrically interconnected via gold-plated pins; the first carrier board is fixed to the bottom of the interface circuit board via an isolated interface, the second and third carrier boards are fixedly mounted on the upper side of the chip carrier, and the fourth carrier board is fixedly connected to the bottom of the third carrier board; The resistor chip is fixed on the upper surface of the chip carrier and is electrically connected to the gold-plated patch on the surface of the second carrier through bonding wires; the gold-plated patch and the gold-plated pin form a path.

[0006] In one embodiment, a magnet connection hole is opened on the side wall of the cooling column, and the magnet connection hole cooperates with the connecting piece to rigidly assemble the superconducting magnet.

[0007] In one embodiment, the chip carrier is provided with a support structure, a limiting mechanism is provided on the upper surface of the support structure, and the fourth carrier is fixed on the lower surface.

[0008] In one embodiment, the limiting mechanism is provided with a chamfered structure near the center side of the chip carrier to compensate for the influence of processing tolerance on the positioning of the circuit board assembly.

[0009] In one embodiment, the second carrier plate, the third carrier plate and the fourth carrier plate are annular structures, and the inner sides of the second carrier plate, the third carrier plate and the fourth carrier plate are provided with groove structures, and the groove structures cooperate with the limiting mechanism to fix the second carrier plate, the third carrier plate and the fourth carrier plate on the chip carrier.

[0010] In one embodiment, a through hole is provided at the top of the interface circuit board, the first through hole is connected to the internal electrical lead of the superconducting magnet; and the second through hole is connected to the first carrier board through the gold-plated pin.

[0011] In one embodiment, a superconducting lead slot is built into the first through hole. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pin to the fourth carrier board, forming a connection path with an external detection instrument.

[0012] In one embodiment, the superconducting wire slot is detachably connected to the resistor chip and the chip carrier.

[0013] In one embodiment, the first carrier board is provided with a gold-plated pin hole corresponding to the interface circuit board, and an additional gold-plated pin hole connected to the gold-plated pin hole, so that the resistor chip can be directly or indirectly connected to the external circuit through the gold-plated pin.

[0014] In one embodiment, the gold-plated patch and bonding wire are spaced apart from the gold-plated pins.

[0015] Compared with the prior art, the embodiment of the present application uses a threaded coupling cooling column connected to an external cooling belt to form an efficient heat conduction path, solving the problem of local temperature drift of the resistor chip; The support structure and the limit mechanism are used to prevent the displacement of the circuit board assembly caused by the vibration of the GM refrigerator. A chamfered structure is set on the side of the limit mechanism close to the center of the carrier to reduce the impact of machining and assembly errors on the bonding accuracy of the resistor chip; Set up superconducting lead slots and space isolation layout to avoid mechanical damage to the bonding wires during plugging and unplugging operations; This application significantly reduces the operational complexity of quantum resistor switching and maintenance in traditional liquid helium-free devices, achieves long-term stable operation of quantum resistors in a liquid helium-free environment, and ensures the traceability accuracy of resistance value transmission.

[0016] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 This is a schematic diagram of the overall structure of a liquid helium-free conductive cooling quantum resistance device carrier provided in an embodiment of the present application; Figure 2 This is a schematic diagram of a resistor chip carrier circuit module provided in an embodiment of the present application; Figure 3 This is a schematic diagram of a cooling column provided in an embodiment of the present application; Figure 4 Schematic diagram of a resistor chip carrier provided in an embodiment of the present application; Figure 5 This is a schematic diagram of the first carrier structure provided in an embodiment of the present application; Figure 6 This is a schematic structural diagram of the second carrier board, the third carrier board, and the fourth carrier board provided in an embodiment of the present application.

[0018] In the figure: 1. First through hole; 2. Second through hole; 3. Interface circuit board; 4. First carrier board; 5. Gold-plated pin; 6. Resistor chip; 7. Bonding wire; 8. Gold-plated patch; 9. Fixing part; 10. Second carrier board; 11. Third carrier board; 12. Fourth carrier board; 13. Chip carrier; 14. External thread; 15. Cooling column; 16. Magnet connection hole; 17. Thermal thread; 18. Limiting mechanism; 19. Support structure; 20. Chamfer structure; 21. Gold-plated pin hole; 22. Additional gold-plated pin hole; 23. Inner through hole; 24. Outer through hole. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of this application.

[0020] In the description of the present invention, it should be understood that the terms "center", "transverse", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0021] The terms "first," "second," and "third" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of such features.

[0022] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0023] like Figures 1-6 As shown, the embodiment of the present application provides a liquid helium-free conductive cooling quantum resistance device carrier, comprising: The cooling column 15 has a heat-conducting thread 17 at the bottom outer edge for binding the cooling belt; Specifically, the thermal conductive thread 17 at the outer edge of the bottom of the cooling column 15 is threadedly connected to the external oxygen-free copper cooling belt to reduce the interface thermal resistance, improve the overall heat conduction efficiency, and solve the problem of local temperature drift of the resistor chip 6.

[0024] The chip carrier 13, the center of the bottom is fixedly connected to the top of the cooling column 15; The circuit board assembly includes an interface circuit board 3, a first carrier board 4, a second carrier board 10, a third carrier board 11, and a fourth carrier board 12 stacked from top to bottom. The boards are electrically interconnected via gold-plated pins 5. The first carrier board 4 is fixed to the bottom of the interface circuit board 3 via an isolated interface. The second carrier board 10 and the third carrier board 11 are fixedly mounted on the upper side of the chip carrier 13. The fourth carrier board 12 is fixedly connected to the bottom of the third carrier board 11. For example, a Φ0.5 mm gold-plated pin is used.

[0025] The resistor chip 6 is fixed on the upper surface of the chip carrier 13 and electrically connected to the gold-plated patch 8 on the surface of the second carrier 10 through the bonding wire 7; the gold-plated patch 8 and the gold-plated pin 5 form a path.

[0026] Exemplarily, the resistor chip 6 is bonded to the upper surface of the chip carrier 13 by a low-temperature epoxy adhesive with a thermal conductivity of ≥1.5 W / m·K; and a gold wire bonding machine is used to complete the connection between the resistor chip 6 and the gold-plated patch 8 .

[0027] In some embodiments of the present application, Figure 3 As shown, a magnet connection hole 16 is opened on the side wall of the cooling column 15, and the magnet connection hole 16 cooperates with the connecting piece to rigidly assemble the superconducting magnet.

[0028] Specifically, an external thread 14 is provided at the center of the top of the cooling column for screwing with the chip carrier 13 .

[0029] Exemplarily, the cooling column 15 is a cylindrical high thermal conductivity oxygen-free copper component, with a Φ6 mm magnet connection hole 16 provided on the side wall, and is rigidly assembled with the superconducting magnet cold head through copper nails.

[0030] In some embodiments of the present application, Figure 2 、 4 As shown, the chip carrier 13 is provided with a support structure 19 , a limiting mechanism 18 is provided on the upper surface of the support structure 19 , and the fourth carrier plate 12 is fixed on the lower surface.

[0031] Specifically, the limiting mechanism 18 cooperates with the third carrier plate 11 and the fourth carrier plate 12 to form a vibration-proof locking mechanism to suppress the displacement of the circuit board assembly caused by the vibration of the GM refrigerator operation and prevent the bonding wires 7 of the resistor chip 6 from breaking.

[0032] Preferably, the support structure 19 is precisely machined with a tolerance of ±0.1 mm, so that the surface of the gold-plated patch 8 and the bonding surface of the resistor chip 6 remain coplanar, reducing the mechanical stress of the bonding wire 7.

[0033] Exemplarily, the chip carrier 13 is an oxygen-free copper substrate with an M6 internal thread provided at the center of the bottom; a lateral limiting mechanism 18 with a depth of 2 mm is provided on the upper surface of the support structure 19 of the chip carrier 13 .

[0034] In some embodiments of the present application, Figure 3 As shown, the limiting mechanism 18 is provided with a chamfer structure 20 near the center side of the chip carrier 13 to compensate for the influence of processing tolerance on the positioning of the circuit board assembly.

[0035] Exemplarily, the chamfer structure 20 is configured as a R0.5mm chamfer.

[0036] In some embodiments of the present application, Figure 2 、 6 As shown, the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 are annular structures, and the inner sides of the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 are provided with a groove structure, and the groove structure cooperates with the limiting mechanism 18 to fix the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 on the chip carrier 13.

[0037] Specifically, the second carrier board 10, the third carrier board 11 and the fourth carrier board 12 are provided with through holes, the inner through holes 23 are used for the gold-plated pins 5 to fix the second carrier board 10 and the third carrier board 11, and the outer through holes 24 are used for the fixing parts 9 to fix the second carrier board 10, the third carrier board 11 and the fourth carrier board 12.

[0038] In some embodiments of the present application, Figure 2 As shown, a through hole is provided on the top of the interface circuit board 3 , the first through hole 1 is connected to the electrical lead inside the superconducting magnet; the second through hole 2 is connected to the first carrier board 4 through the gold-plated pin 5 .

[0039] In some embodiments of the present application, Figure 2 As shown, a superconducting lead slot is built into the first through hole 1. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pin 5 to the fourth carrier board 12, forming a connection path with the external detection instrument.

[0040] In some embodiments of the present application, the superconducting wire slot is detachably connected to the resistor chip 6 and the chip carrier 13 .

[0041] In some embodiments of the present application, Figure 5 As shown, the first carrier board 4 is provided with a gold-plated pin hole 21 corresponding to the interface circuit board 3, and an additional gold-plated pin hole 22 connected to the gold-plated pin hole 21, so that the resistor chip 6 can be directly or indirectly connected to the external circuit through the gold-plated pin 5.

[0042] In some embodiments of the present application, Figure 2 As shown, the gold-plated patch 8 and the bonding wire 7 are spaced apart from the gold-plated pin 5 , and the mechanical stress of the bonding wire 7 during the plugging and unplugging of the interface circuit board 3 is reduced through the spatial isolation design.

[0043] For example, the embodiment of the present application is tested at a temperature of 3K, and its uncertainty is better than , verifying the cooling and fixing effectiveness of the embodiment of the present application.

[0044] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A liquid helium-free conductive cooling quantum resistance device carrier, characterized in that: include: The cooling column has a heat-conducting thread on the bottom outer edge for binding the cooling belt; The chip carrier, the center of the bottom is fixedly connected to the top of the cooling column; A circuit board assembly includes an interface circuit board, a first carrier board, a second carrier board, a third carrier board, and a fourth carrier board stacked from top to bottom, each board electrically interconnected via gold-plated pins; the first carrier board is fixed to the bottom of the interface circuit board via an isolated interface, the second and third carrier boards are fixedly mounted on the upper side of the chip carrier, and the fourth carrier board is fixedly connected to the bottom of the third carrier board; The resistor chip is fixed on the upper surface of the chip carrier and is electrically connected to the gold-plated patch on the surface of the second carrier through bonding wires; the gold-plated patch and the gold-plated pin form a path.

2. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 1, characterized in that: The side wall of the cooling column is provided with a magnet connection hole, and the magnet connection hole cooperates with the connector to rigidly assemble the superconducting magnet.

3. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 1, characterized in that: The chip carrier is provided with a supporting structure, the upper surface of the supporting structure is provided with a limiting mechanism, and the lower surface thereof is fixed with the fourth carrier plate.

4. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 3, characterized in that: The limiting mechanism is provided with a chamfered structure near the center side of the chip carrier, so as to compensate for the influence of machining tolerance on the positioning of the circuit board assembly.

5. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 3, characterized in that: The second carrier plate, the third carrier plate and the fourth carrier plate are annular structures, and the inner sides of the second carrier plate, the third carrier plate and the fourth carrier plate are provided with groove structures, and the groove structures cooperate with the limiting mechanism to fix the second carrier plate, the third carrier plate and the fourth carrier plate on the chip carrier.

6. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 1, characterized in that: A through hole is provided on the top of the interface circuit board, the first through hole is connected to the internal electrical lead of the superconducting magnet; and the second through hole is connected to the first carrier board through the gold-plated pin.

7. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 6, characterized in that: The first through hole has a built-in superconducting lead slot. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pin to the fourth carrier board, forming a connection path with an external detection instrument.

8. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 7, characterized in that: The superconducting lead slot is detachably connected to the resistor chip and the chip carrier.

9. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 1, characterized in that: The first carrier board is provided with a gold-plated pin hole corresponding to the interface circuit board, and an additional gold-plated pin hole connected to the gold-plated pin hole, so that the resistor chip can be directly or indirectly connected to the external circuit through the gold-plated pin.

10. The liquid helium-free conductively cooled quantum resistor device carrier according to claim 1, characterized in that: The gold-plated patches and bonding wires are spaced apart from the gold-plated pins.

Images