Method and system for dynamic generation of wideband signals based on multiple clock sources

Abstract

The embodiment of the application provides a kind of wide frequency signal dynamic generation method and system based on multiple clock sources, the method comprises: by field programmable gate array real-time monitoring target frequency, and based on the frequency band of target frequency belongs to automatically switched to corresponding target clock source;When the target clock source is switched, the phase difference corresponding to the new and old target clock source is corrected by phase compensation register, and the compensation value is loaded to the phase offset register of direct digital frequency synthesis chip;Based on direct digital frequency synthesis chip, generate the fundamental wave waveform of wide frequency signal, and superimpose multiple harmonic components by sub-accumulation method, and the amplitude of each harmonic is independently controlled by look-up table method;The output signal of power amplifier is extracted by analog-digital converter, and the error information of measured waveform and theoretical waveform is extracted and dynamically corrected phase offset register and harmonic amplitude look-up table coefficient, and output target wide frequency signal.The application realizes the unity of wide frequency coverage, high resolution and fast response.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic measuring instruments, and specifically relates to a method and system for dynamically generating broadband signals based on multiple clock sources. Background Art

[0002] Direct digital synthesis (DDS) technology is widely used in precision signal generation due to its high frequency resolution and fast response. Traditional DDS architectures use a single high-precision reference clock (such as a 125MHz oven-controlled crystal oscillator (OCXO)) to generate the target frequency through a phase accumulator.

[0003] However, this design presents inherent contradictions: at low-frequency output, limited by the Nyquist sampling theorem, the minimum frequency step of the 28-bit phase accumulator is Δf = fclk / 228 (fclk is the reference clock frequency). Taking a 125MHz clock as an example, when outputting a 100kHz signal, Δf = 0.466Hz, which is difficult to meet the 0.1Hz resolution required for scenarios like precision sensor excitation. Forcibly lowering the clock frequency to increase resolution (for example, using a 50MHz clock) limits the high-frequency output range. Furthermore, the phase noise performance of mainstream DDS chips like the AD9833 deteriorates to -120dBc / Hz at 1kHz due to the reduced clock source signal-to-noise ratio, resulting in insufficient signal purity. Furthermore, when traditional solutions implement frequency switching by overloading the phase accumulator, they suffer from phase discontinuities of hundreds of microseconds, impacting dynamic test accuracy.

[0004] Although existing technologies attempt to use phase-locked loop (PLL) frequency multiplication or external clock switching circuits, the former introduces phase jitter, and the latter increases system complexity and requires manual intervention in clock source selection.

[0005] Therefore, there is an urgent need for a DDS architecture that can adaptively match the requirements of different frequency bands while ensuring phase continuity, so as to achieve the unity of broadband coverage, high resolution and fast response. Summary of the Invention

[0006] The present application proposes a method and system for dynamically generating a broadband signal based on multiple clock sources, which are used to address the above-mentioned defects of the prior art.

[0007] According to a first aspect of an embodiment of the present application, a method for dynamically generating a broadband signal based on multiple clock sources is provided, comprising:

[0008] Monitor the target frequency in real time through a field programmable gate array, and automatically switch to the corresponding target clock source based on the frequency band to which the target frequency belongs;

[0009] When the target clock source is switched, the phase difference between the old and new target clock sources is corrected by the phase compensation register, and the compensation value is loaded into the phase offset register of the direct digital frequency synthesis chip;

[0010] The fundamental waveform of the broadband signal is generated based on the direct digital frequency synthesis chip, and multiple harmonic components are superimposed by a fractional accumulation method, and the amplitude of each harmonic is independently controlled by a table lookup method;

[0011] The output signal of the power amplifier is sampled through an analog-to-digital converter to extract the error information between the measured waveform and the theoretical waveform;

[0012] The phase offset register and the harmonic amplitude lookup table coefficients are dynamically modified according to the error information, and a target broadband signal is output.

[0013] In some implementations, the target clock source includes a high-frequency clock source or a low-frequency clock source, and automatically switching to the corresponding target clock source based on the frequency band to which the target frequency belongs includes:

[0014] When the target frequency reaches a high frequency threshold, the high frequency clock source is enabled, and when the target frequency is lower than a low frequency threshold, the low frequency clock source is switched to.

[0015] The high-frequency threshold is 400 Hz, and the low-frequency threshold is the same as the high-frequency threshold.

[0016] When the target frequency is greater than or equal to 400 Hz, switch to the high-frequency clock source, which is a 12 MHz oven-controlled crystal oscillator clock source;

[0017] When the target frequency is less than 400 Hz, the low-frequency clock source is switched to, and the low-frequency clock source is a 50 kHz temperature compensated crystal oscillator clock source.

[0018] In some embodiments, when the target clock source is switched, correcting the phase difference between the old and new target clock sources using a phase compensation register and loading the compensation value into a phase offset register of a direct digital frequency synthesis chip includes:

[0019] Using a high-order phase accumulator, a phase increment is calculated according to the target frequency and the current clock frequency;

[0020] When the clock source is switched, the phase accumulation value corresponding to the old target clock source before the switch is recorded in real time;

[0021] Calculate the phase accumulation value corresponding to the new target clock source after switching in real time;

[0022] Loading a compensation value through the phase compensation register, wherein the compensation value is a phase accumulation value corresponding to the old target clock source before switching and a phase accumulation value corresponding to the new target clock source after switching;

[0023] The compensation value is written into the phase offset register of the direct digital frequency synthesis chip and the output signal phase difference is corrected.

[0024] In some embodiments, sampling the output signal of the power amplifier through an analog-to-digital converter to extract error information between a measured waveform and a theoretical waveform includes:

[0025] Sampling the output signal of the power amplifier through the analog-to-digital converter to obtain the measured waveform;

[0026] Time-synchronize the measured waveform with the theoretical waveform generated by the direct digital frequency synthesis chip;

[0027] performing a cross-correlation operation on the synchronized measured waveform and the theoretical waveform;

[0028] Obtaining an actual phase deviation based on the cross-correlation operation;

[0029] The cross-correlation operation is expressed by the following formula:

[0030]

[0031] in, represents the cross-correlation function value, represents the delay index, represents the total number of relevant points, Indicates the sampling point index, represents the theoretical waveform, Indicates the measured waveform.

[0032] In some embodiments, sampling the output signal of the power amplifier through an analog-to-digital converter to extract error information between the measured waveform and the theoretical waveform further includes:

[0033] Retrieving the output signal of the power amplifier through the analog-to-digital converter;

[0034] Performing windowing on the output signal and suppressing spectrum leakage;

[0035] Performing a fast Fourier transform on the windowed output signal to extract the fundamental wave amplitude and the amplitudes of each harmonic;

[0036] Evaluating the distortion of the broadband signal by comparing the amplitudes of the respective harmonics with the amplitude of the fundamental wave;

[0037] The distortion is calculated by the following formula:

[0038] ;

[0039] in, Indicates the distortion, represents the fundamental amplitude, Indicates the amplitude of each harmonic.

[0040] In some embodiments, dynamically correcting the phase offset register and the harmonic amplitude lookup table coefficients according to the error information includes:

[0041] Based on whether the actual phase deviation exceeds a preset threshold, controlling whether to adjust the value of the phase offset register,

[0042] If the actual phase deviation exceeds the preset threshold, the value of the phase offset register is adjusted according to the proportional coefficient; if the actual phase deviation does not exceed the preset threshold, the value of the phase offset register is maintained;

[0043] Based on whether the distortion reaches a preset standard, control whether to adjust the harmonic amplitude lookup table coefficient,

[0044] If the distortion does not reach the preset standard, the harmonic amplitude lookup table coefficient is adjusted; if the distortion reaches the preset standard, the harmonic amplitude lookup table coefficient is maintained.

[0045] In some implementations, the phase difference between the new and old target clock sources is calculated using the following formula:

[0046]

[0047] in, represents the phase difference, represents the target frequency, represents the temperature compensation coefficient, Indicates the current clock frequency;

[0048] The temperature compensation coefficient Calculated by the following formula:

[0049]

[0050] in, represents the crystal temperature coefficient, Indicates the ambient temperature.

[0051] In some embodiments, the target broadband signal may include a sine wave, a square wave, a triangle wave, or a harmonic superposition signal of any combination thereof.

[0052] In some embodiments, before outputting the target broadband signal, the method includes:

[0053] Obtaining phase noise data of a reference clock at a target offset frequency;

[0054] Based on the frequency of the reference clock and the target frequency, a reference phase noise is calculated using a carrier frequency conversion formula;

[0055] Acquire the internal noise of the direct digital frequency synthesis chip, and superimpose the internal noise and the reference phase noise to obtain a total phase noise evaluation value;

[0056] When the total phase noise evaluation value does not exceed a preset noise standard, outputting the target broadband signal;

[0057] When the total phase noise evaluation value exceeds the preset noise standard, the operation of automatically switching to the corresponding target clock source based on the frequency band to which the target frequency belongs or retrieving the output signal of the power amplifier through the analog-to-digital converter is triggered.

[0058] According to a second aspect of the present application, a system for dynamically generating a broadband signal based on multiple clock sources is provided, comprising:

[0059] A clock source switching module is used to monitor the target frequency in real time through a field programmable gate array and automatically switch to the corresponding target clock source based on the frequency band to which the target frequency belongs;

[0060] A phase difference compensation module is used to correct the phase difference between the new and old target clock sources through the phase compensation register when the target clock source is switched, and load the compensation value into the phase offset register of the direct digital frequency synthesis chip;

[0061] A multiple harmonic superposition module is used to generate a fundamental waveform of a broadband signal based on the direct digital frequency synthesis chip, and to superimpose multiple harmonic components by a fractional accumulation method, with the amplitude of each harmonic being independently controlled by a table lookup method;

[0062] The error information calculation module is used to retrieve the output signal of the power amplifier through the analog-to-digital converter and extract the error information between the measured waveform and the theoretical waveform;

[0063] The target signal output module is used to dynamically correct the phase offset register and the harmonic amplitude lookup table coefficient according to the error information, and output the target broadband signal.

[0064] The beneficial effects of the method and system for dynamically generating a broadband signal based on multiple clock sources according to the embodiments of the present application include at least:

[0065] The embodiment of the present application dynamically monitors the target frequency in real time and automatically switches the clock source to solve the inherent contradiction between high-frequency and low-frequency signal generation, ensures the output stability of the full frequency band (0.01Hz-100kHz), and avoids the accuracy degradation of a single clock source in non-applicable frequency bands, thereby optimizing frequency adaptability from the hardware level; by correcting the phase difference between the old and new clocks through the phase compensation register at the moment of clock switching, the phase jump of the output signal is directly eliminated, ensuring the timing continuity when the waveform is switched. This operation achieves nanosecond response through register loading, meets the stringent requirements of real-time signal generation, and realizes phase continuity guarantee; based on the direct digital frequency synthesis core The chip generates the fundamental wave and combines the fractional accumulation and table lookup method to independently control the amplitude of each harmonic, realizing the precise reconstruction of complex waveforms. The independent control mechanism of harmonic components effectively suppresses spectrum leakage and improves signal purity. By sampling the output signal of the power amplifier and extracting the measured / theoretical waveform error, the real response of the load end (including the nonlinear distortion of the power amplifier) ​​is directly captured, breaking through the limitations of the traditional open-loop system and providing a data basis for closed-loop correction. The phase offset and harmonic amplitude coefficient are dynamically adjusted according to the error information, and the transmission delay and nonlinear effects of the power amplifier are compensated in real time. An autonomous system of generation, detection and correction is formed to continuously ensure the accuracy and stability of broadband signal output. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 Schematic diagram of the flow of a method for dynamically generating a broadband signal based on multiple clock sources according to an embodiment of the present application;

[0067] Figure 2 Schematic diagram of the structure of a broadband signal dynamic generation system based on multiple clock sources according to an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0069] The following detailed description of the embodiments of the present application is provided in conjunction with the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of the present application, but are not intended to limit the scope of the present application, i.e., the present application is not limited to the described embodiments.

[0070] The embodiment of the present application provides a method for dynamically generating a broadband signal based on multiple clock sources, which is performed by a system for dynamically generating a broadband signal based on multiple clock sources. The method includes the following steps 110-150.

[0071] Step 110 : monitor the target frequency in real time through a field programmable gate array (FPGA), and automatically switch to a corresponding target clock source based on the frequency band to which the target frequency belongs.

[0072] In some embodiments, the multiple clock sources are dual clock sources, for example, the target clock source includes a high-frequency clock source or a low-frequency clock source. For example, the multiple clock sources may include a 12 MHz highly stable oven-controlled crystal oscillator (OCXO) and a 50 kHz temperature-compensated crystal oscillator (TCXO), with dynamic switching of the clock sources achieved via an electronic switch controlled by a field programmable gate array.

[0073] In some embodiments, the automatic switching to the corresponding target clock source based on the frequency band to which the target frequency belongs includes: enabling the high-frequency clock source when the target frequency reaches the high-frequency threshold, and switching to the low-frequency clock source when the target frequency is lower than the low-frequency threshold; wherein the high-frequency threshold is 400Hz, the low-frequency threshold is the same as the high-frequency threshold, when the target frequency is greater than or equal to 400Hz, switching to the high-frequency clock source, the high-frequency clock source is a 12MHz constant-temperature crystal oscillator clock source; when the target frequency is less than 400Hz, switching to the low-frequency clock source, the low-frequency clock source is a 50kHz temperature-compensated crystal oscillator clock source.

[0074] For example, the dynamic clock switching logic of this application includes real-time monitoring of the target frequency and dynamic selection of the target clock source. For example, the system dynamically selects a 12MHz or 50kHz clock source by monitoring the target frequency in real time. The specific process may include frequency band determination and a switching trigger mechanism. Among them, the frequency band determination conditions include: when the target frequency is ≥400Hz, the 12MHz high-frequency clock is enabled to ensure a high-frequency band (400Hz-100kHz) resolution of 0.0447Hz; when the target frequency is <400Hz, the clock is switched to a 50kHz low-frequency clock, increasing the low-frequency band (0.01Hz-400Hz) resolution to 0.000186Hz. The switching trigger mechanism includes the field gate programmable array polling the target frequency input (from the host computer or panel knob) at a 1ms cycle. If the target frequency is detected to cross the 400Hz threshold, the state machine is triggered to enter the clock switching process. The state machine prioritizes maintaining the current output phase value and synchronously updates it after the new clock parameters are loaded to avoid signal interruption.

[0075] In some embodiments, the target frequency switching time is less than 10 μs, which may include, for example: a logic delay of controlling clock source switching through a field gate programmable array is ≤ 2 μs; a time consumption of updating a frequency tuning word (FTW) is ≤ 1.33 μs; and a phase compensation algorithm execution time is ≤ 83 ns.

[0076] For example, the total frequency switching time estimate includes the frequency tuning word update time, the logic delay of the field gate programmable array (FPGA) controlling the clock source switch, the time required to update the frequency tuning word (FTW), and the execution time of the phase compensation algorithm. The frequency tuning word update time includes 16 clock cycles (1.33 μs at a 12 MHz clock) required to update the frequency tuning word via the SPI interface. The field gate programmable array switching logic delay includes the sum of input / output (I / O) delay and logic gate delay, which is ≤ 2 μs (measured trigger signal to output settling time). The phase compensation algorithm execution time is calculated in the 12-bit phase compensation register, which takes only one clock cycle (83 ns at 12 MHz). Therefore, the total time estimate is 1.33 μs (FTW update) + 2 μs (FPGA delay) + 0.083 μs (compensation), which is approximately 3.4 μs, less than 10 μs.

[0077] In some implementations, the dynamic clock switching process of the embodiments of the present application does not require external intervention, and the field gate programmable array monitors the target frequency changes in real time and automatically completes the clock source switching.

[0078] Step 120: When the target clock source is switched, the phase difference between the old and new target clock sources is corrected using the phase compensation register, and the compensation value is loaded into the phase offset register of the direct digital frequency synthesis chip.

[0079] In some embodiments, this step of the present application is a phase continuity compensation step, referred to as a phase compensation step.

[0080] In some embodiments, when the target clock source is switched, the phase difference corresponding to the old and new target clock sources is corrected through a phase compensation register, and the compensation value is loaded into a phase offset register of a direct digital frequency synthesis chip, including: using a high-bit phase accumulator to calculate a phase increment based on the target frequency and the current clock frequency; when the clock source is switched, recording in real time the phase accumulation value corresponding to the old target clock source before the switch; calculating in real time the phase accumulation value corresponding to the new target clock source after the switch; loading the compensation value through the phase compensation register, the compensation value being the phase accumulation value corresponding to the old target clock source before the switch and the phase accumulation value corresponding to the new target clock source after the switch; writing the compensation value into the phase offset register of the direct digital frequency synthesis chip and correcting the output signal phase difference.

[0081] In some embodiments, the phase compensation step of the present application includes: calculating the phase increment corresponding to the target frequency, dynamically correcting the phase increment of the clock source, correcting the phase difference corresponding to the new and old clock sources through the phase compensation register, and loading the compensation value using the phase offset register.

[0082] In an exemplary embodiment, the high-bit phase accumulator is a 28-bit phase accumulator.

[0083] In an exemplary embodiment, the phase increment corresponding to the target frequency is calculated as follows:

[0084]

[0085] in, represents the phase increment, Indicates the target frequency, Indicates the current clock frequency.

[0086] In an exemplary embodiment, the phase compensation algorithm dynamically corrects the phase increment of the clock source by introducing a temperature sensor to collect the temperature of the temperature compensation crystal oscillator in real time. The phase difference between the new and old target clock sources is calculated using the following formula:

[0087]

[0088] in, represents the phase difference, Indicates the target frequency, represents the temperature compensation coefficient, Indicates the current clock frequency.

[0089] In an exemplary embodiment, the temperature compensation coefficient Calculated by the following formula:

[0090]

[0091] in, represents the crystal temperature coefficient, Indicates the ambient temperature.

[0092] In one embodiment, correcting the phase difference between the old and new clock sources using the phase compensation register includes setting the 28-bit frequency tuning word (FTW) register to double buffer mode, allowing the field programmable gate array to update the frequency parameters without interrupting the output. The phase offset register (12 bits) is used to load the compensation value. , where the compensation value is calculated by the following formula:

[0093]

[0094] in, is the accumulated phase corresponding to the clock source before switching, which is calculated by the following formula:

[0095] ,

[0096] is the old clock duration, For the old clock source;

[0097] is the initial phase under the new clock source, which is calculated by the following formula:

[0098] ,

[0099] Increment for the new clock source, The switching takes time;

[0100] ,

[0101] Indicates the clock frequency corresponding to the new clock source.

[0102] Record the phase accumulation value under the current clock source , calculated based on the new clock source, by Correct the phase difference. The 28-bit phase accumulator accumulates the frequency tuning word (FTW) and the current phase value every cycle and outputs the phase data. .

[0103] In an exemplary embodiment, using the phase offset register to load the compensation value includes reading the phase register (eg, address 0x4000_0000) to obtain the real-time phase value under the current clock source. .

[0104] Step 130 : Generate a fundamental waveform of a broadband signal based on the direct digital frequency synthesis chip, and superimpose multiple harmonic components by a fractional accumulation method, and independently control the amplitude of each harmonic by a table lookup method.

[0105] In some embodiments, the fundamental waveform may include one or more of a sine wave, a square wave, and a triangle wave.

[0106] In some embodiments, the multiple harmonic component is a 32nd harmonic component.

[0107] In some embodiments, the fractional accumulation method includes: successively superimposing 32nd harmonic components in a sine lookup table; and independently controlling the amplitude of each harmonic by a table lookup method, with an adjustment step of 0.1 dB.

[0108] For example, when the target frequency is in the high frequency band (e.g., 400Hz-100kHz) and a 12MHz high-stability oven-controlled crystal oscillator is enabled, the frequency resolution reaches 0.0447Hz; when the target frequency is in the low frequency band (e.g., 0.01Hz-400Hz) and a 50kHz high-stability oven-controlled crystal oscillator is switched to, the frequency resolution is increased to 0.000186Hz.

[0109] For example, frequency resolution It is calculated as follows:

[0110]

[0111] Among them, when the target frequency is high frequency band (12MHz clock frequency), the clock frequency =12MHz (that is Hz), phase accumulator bits N =28. Therefore, .

[0112] In addition, when the target frequency is the low frequency band (50kHz clock frequency), =50kHz, the number of bits of phase accumulator N =28. Therefore, .

[0113] Based on this, the embodiment of the present application has a 1000-fold improvement in resolution compared to the traditional solution. =0.466Hz; high frequency band of the embodiment of the present application =0.0447Hz, this application achieves 0.466 / 0.0447≈10.4 times improvement. This application low frequency band =0.000186Hz, while traditional solutions require reducing the clock to 50kHz, but the high frequency band cannot cover the 100kHz upper limit. This application improves the average resolution across the entire frequency band by more than 1000 times.

[0114] In an exemplary embodiment, the harmonic superposition control includes complex waveform synthesis based on 32 harmonic superposition and fractional accumulation method, which may specifically include harmonic coefficient table generation, fractional accumulation logic layout and amplitude adjustment. Among them, the harmonic coefficient table generation includes storing 32 groups of harmonic amplitude coefficient tables (each group has 256 orders) in a field gate programmable array, corresponding to the amplitude adjustment requirements of different harmonic orders. The fractional accumulation logic layout includes generating the corresponding frequency component through an independent phase accumulator for each harmonic superposition, multiplying the amplitude of each harmonic by the corresponding coefficient and then superimposing it into the sine lookup table. In the harmonic superposition scenario, after the clock switching is completed, the phase offset registers of each harmonic need to be updated synchronously. For example, the fundamental phase compensation after switching , nth harmonic compensation , ensuring the overall phase continuity of the harmonic sequence. Amplitude adjustment involves the user inputting an amplitude step command (0.1dB). Each step's corresponding gain coefficient is converted to a 16-bit digital signal (e.g., in the range 0x0000-0xFFFF) via a table lookup. The gain coefficient is then applied to the harmonic components via a multiplier, ensuring total harmonic distortion ≤ -80dBc. The core steps of the table lookup method are: Each harmonic gain coefficient (0.1dB step) is precalculated and stored in a field-gate programmable array. The user then enters the target gain (e.g., -9.5dB) corresponding to the table address (e.g., the 95th order). The table lookup retrieves a 16-bit digital signal (e.g., 0x2100), which is then multiplied by the harmonic components and output, ensuring amplitude accuracy and dynamic range (≤-80dBc). The process of applying the gain coefficient and multiplier to the harmonic component includes: obtaining the gain coefficient through table lookup, and extracting the corresponding 16-bit digital signal from the gain coefficient table stored in the field gate programmable array through table lookup according to the target gain input by the user (such as -9.5dB); generating harmonic components, and generating the original components of the fundamental and harmonics through the sine lookup table; multiplier operation, multiplying the 16-bit gain coefficient (such as 0x2100) obtained from the table lookup with the 12-bit output of the harmonic component to achieve amplitude adjustment (such as attenuating the amplitude of the third harmonic to the target value); superposition output, the adjusted harmonic component is converted into an analog signal through a digital-to-analog converter, superimposed with the fundamental and other harmonic components, and finally outputting a composite waveform of the specified amplitude (such as a sine wave containing 32nd harmonics).

[0115] Step 140 : sampling the output signal of the power amplifier through an analog-to-digital converter (ADC) to extract error information between the measured waveform and the theoretical waveform.

[0116] In some embodiments, this step of the present application is a step of adaptively adjusting the algorithm, which may include, for example, dynamic compensation of phase error and amplitude nonlinear correction.

[0117] In some embodiments, sampling the output signal of the power amplifier through an analog-to-digital converter and extracting error information between the measured waveform and the theoretical waveform includes: sampling the output signal of the power amplifier through the analog-to-digital converter to obtain the measured waveform; time-synchronizing the measured waveform with the theoretical waveform generated by the direct digital frequency synthesis chip; performing a cross-correlation operation on the synchronized measured waveform and the theoretical waveform; and obtaining an actual phase deviation based on the cross-correlation operation.

[0118] For example, dynamic compensation of phase error includes two aspects: error detection and compensation update. Error detection calculates the actual phase deviation by performing a cross-correlation operation between the analog-to-digital converter's sampled signal and the theoretical output waveform. ; Compensation updates include: When the threshold (e.g. 1°) is exceeded, the phase offset register is updated. For example, to set the proportional coefficient , then the new compensation value = old compensation value , gradually reduce the deviation to the allowable range.

[0119] In some embodiments, performing a cross-correlation operation specifically includes signal alignment and sliding multiplication. Signal alignment involves time-synchronizing the measured waveform sampled by the analog-to-digital converter with the theoretical output waveform; sliding multiplication involves multiplying and accumulating the discrete sampling points of the two signals to obtain a cross-correlation function value.

[0120] In an exemplary embodiment, the cross-correlation operation is represented by the following equation:

[0121]

[0122] in, represents the cross-correlation function value, represents the delay index, represents the total number of relevant points, Indicates the sampling point index, represents the theoretical waveform, Indicates the measured waveform.

[0123] In some embodiments, the specific steps of performing the cross-correlation operation further include peak detection. Peak detection includes the time delay corresponding to the maximum value of the cross-correlation function. That is the signal offset, which is further converted into phase deviation. The conversion formula is as follows:

[0124] ,

[0125] in, represents the phase deviation, Indicates the maximum delay, Indicates the signal period.

[0126] This step of the present application does not require frequency domain conversion and is suitable for scenarios with high real-time requirements.

[0127] In some embodiments, sampling the output signal of the power amplifier through an analog-to-digital converter and extracting error information between the measured waveform and the theoretical waveform also includes: sampling the output signal of the power amplifier through the analog-to-digital converter; windowing the output signal and suppressing spectrum leakage; performing a fast Fourier transform on the windowed output signal to extract the fundamental wave amplitude and the amplitudes of each harmonic; and evaluating the distortion of the broadband signal by comparing the amplitudes of each harmonic with the fundamental wave amplitude.

[0128] For example, amplitude nonlinearity correction can be performed by performing Fast Fourier Transform (FFT) analysis on the signal sampled by the analog-to-digital converter and then calculating the total harmonic distortion (THD). THD); The lookup coefficient correction includes dynamically adjusting the harmonic amplitude lookup coefficient when the total harmonic distortion does not meet the standard.

[0129] The fast Fourier transform analysis process includes: adding a window (such as a Hanning window) to the analog-to-digital converter signal to suppress spectrum leakage; performing an N-point fast Fourier transform to obtain the frequency domain amplitude distribution; extracting the fundamental frequency (frequency is ) and each harmonic (frequency is ) amplitude.

[0130] In an exemplary embodiment, total harmonic distortion (THD) measures the degree of distortion by comparing the energy of the harmonics in the signal with the energy of the fundamental frequency. The total harmonic distortion is calculated as follows:

[0131] ;

[0132] in, Indicates the distortion, represents the fundamental amplitude, Indicates the amplitude of each harmonic. If THD does not meet the standard (such as > 0.5%), the harmonic amplitude lookup table coefficient will be dynamically adjusted.

[0133] In some embodiments, the method also includes a frequency parameter update mechanism. For example, to prevent output signal interruption caused by frequency switching, the system employs a double-buffered register and pipeline update strategy. The double-buffered registers set the frequency tuning word register to double-buffered mode, allowing the field gate programmable array to update parameters in the background while maintaining the current output frequency in the foreground. The pipeline control includes a state machine within the field gate programmable array that decomposes the frequency update into three phases: parameter calculation (1 μs), register loading (0.5 μs), and phase compensation (0.5 μs), with a total time of ≤ 2 μs, ensuring a seamless switching process.

[0134] In some embodiments, the method also includes exception handling and adaptive adjustment, such as clock source fault detection and automatic recovery. Specifically, it can include clock source monitoring and adaptive compensation. Among them, clock source monitoring is based on the internal counter of the field gate programmable array to monitor the period stability of the 12MHz and 50kHz clock signals in real time; if the clock period deviation exceeds ±10ppm, the fault flag is triggered and the backup clock source is switched. Adaptive compensation is when the temperature change causes the temperature compensation crystal oscillator frequency to drift, the field gate programmable array collects temperature sensor data through analog-to-digital conversion, and dynamically adjusts the phase increment of the 50kHz clock source Compensation value.

[0135] In some embodiments, the method also includes system debugging and performance optimization, such as phase noise testing, resolution verification, dynamic response testing, and dynamic response optimization. Phase noise testing involves setting up test equipment, test conditions, and result analysis. The test equipment is a phase noise analyzer. Test conditions are a 10kHz carrier frequency and a 10H resolution bandwidth (RBW). Results analysis includes phase noise measurements of -145.3dBc / Hz at 1kHz offset for a 12MHz clock and -120.1dBc / Hz at 1kHz offset for a 50kHz clock, verifying the necessity of dual clock source switching. Resolution verification includes high-band and low-band testing. The high-band test involves setting the target frequency to 99.999Hz and measuring frequency steps of 0.0447Hz (error <0.05%). The low-band test involves setting the target frequency to 0.05Hz and achieving a resolution of 0.000186Hz (consistent with the theoretical value). Dynamic response testing includes switching time measurement and phase continuity verification. Switching time is measured by capturing waveform transition edges with an oscilloscope, resulting in a typical frequency switching time of 8.2μs. Phase continuity is verified by performing 1000 switching tests at the 400Hz threshold, with an average phase jump angle of <0.8° (meeting the design goal of <1°). Dynamic response optimization includes shortening the FPGA state machine transition path, for example, by controlling clock switching delay to within 2μs; optimizing register loading order, for example, prioritizing frequency tuning word updates over phase compensation values; and adjusting synchronization signals, for example, by capturing output waveform transition edges with an oscilloscope and adjusting the synchronization relationship of the FPGA trigger signal to ensure a glitch-free switching process.

[0136] This step in the embodiment of the present application adds a sampling channel of the high-speed analog-to-digital converter, thereby forming a closed-loop feedback link in the dynamic generation process of the broadband signal.

[0137] For example, a 16-bit, 1MS / s high-speed analog-to-digital converter (ADC) is connected in parallel to the output of a power amplifier (e.g., a programmable amplifier) ​​to acquire the analog voltage waveform of the output signal in real time. The ADC data undergoes digital frequency conversion (DDC) processing within the field-programmable gate array (FPGA), extracting fundamental amplitude, harmonic amplitude, and phase error information. Based on this error information, the FPGA dynamically adjusts the phase offset register (preferably 12 bits) and amplitude lookup table coefficients (preferably 256 steps). This forms a closed-loop feedback process encompassing signal output, filtering, amplifiers, ADC acquisition, error detection, compensation parameter updates, and error adjustment.

[0138] Step 150 : Dynamically modify the phase offset register and harmonic amplitude lookup table coefficients according to the error information, and output a target broadband signal.

[0139] In some embodiments, the dynamically correcting the phase offset register and the harmonic amplitude lookup table coefficient based on the error information comprises: controlling whether to adjust the value of the phase offset register based on whether the actual phase deviation exceeds a preset threshold, and controlling whether to adjust the harmonic amplitude lookup table coefficient based on whether the distortion degree reaches a preset standard.

[0140] In an exemplary embodiment, the controlling whether to adjust the value of the phase offset register based on whether the actual phase deviation exceeds a preset threshold comprises: adjusting the value of the phase offset register by a proportional coefficient if the actual phase deviation exceeds the preset threshold, and maintaining the value of the phase offset register if the actual phase deviation does not exceed the preset threshold.

[0141] In an exemplary embodiment, the adjusting the harmonic amplitude lookup table coefficient if the distortion degree does not reach the preset standard, and maintaining the harmonic amplitude lookup table coefficient if the distortion degree reaches the preset standard.

[0142] In some embodiments, the signal type of the target wideband signal comprises a sine wave, a square wave, a triangular wave, or a harmonic superposition signal of any combination thereof.

[0143] In some embodiments, before outputting the target wideband signal, the method further comprises: obtaining phase noise data of a reference clock at a target offset frequency; calculating a reference phase noise by a carrier frequency conversion formula based on a frequency of the reference clock and the target frequency; obtaining internal noise of the direct digital frequency synthesis chip, and superimposing the internal noise and the reference phase noise to obtain a total phase noise evaluation value; outputting the target wideband signal when the total phase noise evaluation value does not exceed a preset noise standard; and triggering automatic switching of a frequency band to which the target frequency belongs to a corresponding target clock source or operation of resampling an output signal of a power amplifier by an analog-to-digital converter when the total phase noise evaluation value exceeds the preset noise standard.

[0144] In an exemplary embodiment, the phase noise data satisfies the following condition: ≤-145 dBc / Hz at 1 kHz carrier offset.

[0145] For example, the calculation method of the phase noise of-145 dBc / Hz @ 1 kHz comprises: the phase noise represents a ratio of a single sideband (SSB) noise power of a signal source at a specific frequency offset to a carrier power, in units of dBc / Hz (dB value relative to the carrier, normalized to 1 Hz bandwidth). @ 1 kHz represents the phase noise value at 1 kHz offset, which refers to the phase noise value at a distance of 1 kHz from the carrier frequency.

[0146] The phase noise formula is as follows:

[0147] ,

[0148] in, is the output frequency, is the reference clock frequency.

[0149] For example, the phase noise of the oven-controlled crystal oscillator reference clock at 50MHz is -130dBc / Hz@1kHz. The corresponding phase noise value is:

[0150]

[0151] Furthermore, by adding the internal noise (approximately -109dBc / Hz), the final phase noise is approximately -145dBc / Hz.

[0152] In some embodiments, the noise removal of the embodiments of the present application includes adaptive filtering and phase compensation data verification. The adaptive filtering algorithm includes a modified Kalman filter arranged in a field gate programmable array, which eliminates short-term jitter interference by recursively calculating the optimal estimate.

[0153] Exemplarily, the Kalman filter implementation includes: establishing a dynamic model equation, an observation model equation, and a recursive process. The dynamic model equation is established as follows:

[0154] ,

[0155] The observation model equation is as follows:

[0156] ,

[0157] Where k is the time index, is the state vector (target frequency and rate of change), is the observed value (the sampling frequency of the analog-to-digital converter), is the state transition matrix, is the observation matrix, is the process noise, is the observation noise.

[0158] The recursive process includes: prediction step and update step.

[0159] The prediction step equation is as follows:

[0160] ,

[0161] The update step equation is as follows:

[0162] ,

[0163] ,

[0164] ,

[0165] in, is the Kalman gain, is the covariance matrix, and is the noise covariance parameter, is the identity matrix.

[0166] Exemplarily, the phase compensation data verification includes: Before switching, the field gate programmable array performs a rationality check on the compensation value: if the phase difference exceeds 90°, it is determined to be an abnormal switching and triggers the reset process to avoid sudden changes in the output signal.

[0167] In some embodiments, the output signal types include sine waves, square waves, triangle waves, and any combination of harmonic superposition signals. The square wave duty cycle is programmable in 1% increments. The harmonic superposition module employs an adaptive amplitude distribution strategy: when the output signal amplitude exceeds the linear range of the programmable amplifier, it automatically reduces the proportion of higher harmonics, prioritizing the fundamental and lower harmonic energy distribution.

[0168] The embodiment of the present application dynamically monitors the target frequency in real time and automatically switches the clock source to solve the inherent contradiction between high-frequency and low-frequency signal generation, ensures the output stability of the full frequency band (0.01Hz-100kHz), and avoids the accuracy degradation of a single clock source in non-applicable frequency bands, thereby optimizing frequency adaptability from the hardware level; by correcting the phase difference between the old and new clocks through the phase compensation register at the moment of clock switching, the phase jump of the output signal is directly eliminated, ensuring the timing continuity when the waveform is switched. This operation achieves nanosecond response through register loading, meets the stringent requirements of real-time signal generation, and realizes phase continuity guarantee; based on the direct digital frequency synthesis core The chip generates the fundamental wave and combines the fractional accumulation and table lookup method to independently control the amplitude of each harmonic, realizing the precise reconstruction of complex waveforms. The independent control mechanism of harmonic components effectively suppresses spectrum leakage and improves signal purity. By sampling the output signal of the power amplifier and extracting the measured / theoretical waveform error, the real response of the load end (including the nonlinear distortion of the power amplifier) ​​is directly captured, breaking through the limitations of the traditional open-loop system and providing a data basis for closed-loop correction. The phase offset and harmonic amplitude coefficient are dynamically adjusted according to the error information, and the transmission delay and nonlinear effects of the power amplifier are compensated in real time. An autonomous system of generation, detection and correction is formed to continuously ensure the accuracy and stability of broadband signal output.

[0169] Reference Figure 2 As shown, an embodiment of the present application also discloses a broadband signal dynamic generation system based on multiple clock sources, including: a clock source switching module 210, a phase difference compensation module 220, a multiple harmonic superposition module 230, an error information calculation module 240 and a target signal output module 250.

[0170] The clock source switching module 210 is configured to monitor the target frequency in real time through a field programmable gate array, and automatically switch to a corresponding target clock source based on the frequency band to which the target frequency belongs.

[0171] The phase difference compensation module 220 is used to correct the phase difference between the new and old target clock sources through the phase compensation register when the target clock source is switched, and load the compensation value into the phase offset register of the direct digital frequency synthesis chip.

[0172] The multiple harmonic superposition module 230 is used to generate the fundamental waveform of the broadband signal based on the direct digital frequency synthesis chip, and superimpose multiple harmonic components by a fractional accumulation method, and the amplitude of each harmonic is independently controlled by a table lookup method.

[0173] The error information calculation module 240 is used to retrieve the output signal of the power amplifier through an analog-to-digital converter and extract the error information between the measured waveform and the theoretical waveform.

[0174] The target signal output module 250 is used to dynamically correct the phase offset register and the harmonic amplitude lookup table coefficient according to the error information, and output a target broadband signal.

[0175] At the hardware architecture level, the embodiment of the present application uses a 12MHz high-stability constant-temperature crystal oscillator and a 50kHz temperature-compensated crystal oscillator as independent reference sources. The phase noise of the high-frequency clock unit at 125MHz reaches -160dBc / Hz@1kHz offset; the temperature stability of the low-frequency clock unit is ±2ppm / ℃, and the power consumption is less than 1.5mA. The two clock sources are dynamically switched through the internal logic gate circuit of the field programmable gate array: when the target frequency is ≥400Hz, the 12MHz clock is enabled to meet the 0.0447Hz resolution requirement of the high frequency band (400Hz-100kHz); when the target frequency is <400Hz, it automatically switches to the 50kHz clock, so that the resolution of the low frequency band (0.01Hz-400Hz) is increased to 0.000186Hz. The frequency band division threshold is derived based on the resolution crossover point calculation formula, taking into account both high-frequency output capability and low-frequency resolution requirements.

[0176] To address the phase discontinuity issues caused by clock switching, the present embodiment of the application has designed a phase continuity guarantee mechanism. A built-in 28-bit phase accumulator calculates the phase increment, and the field programmable gate array uses a 12-bit phase compensation register to correct the phase difference between the new and old clock sources in real time. In the specific implementation, the field programmable gate array maintains the original phase value before switching the clock, and then synchronously updates the phase compensation value after the new clock parameters are loaded to avoid transient jitter.

[0177] Signal synthesis implements fundamental wave generation for sine, square, and triangle waves, as well as 32nd harmonic superposition. Sine wave generation utilizes a 4096×24-bit lookup table combined with a 12-bit digital-to-analog converter, covering an output frequency range of 1μHz-125MHz. Square waves are generated by dividing the phase accumulator output by two using a frequency divider, with duty cycle adjustment in 1% steps. Triangle waves are generated using a linear ramp phase accumulator with sign bit truncation. Harmonic superposition utilizes a fractional addition method, adding the 32nd harmonic components to the sine lookup table. The amplitude of each harmonic is independently controlled using a 256-step lookup table with 0.1dB adjustment steps, resulting in a total harmonic distortion (THD) better than -80dBc. The output signal passes through a fifth-order low-pass filter (with selectable cutoff frequencies of 100kHz / 500kHz) to suppress image frequencies, before being amplitude-adjusted by a programmable amplifier (ranging from 0.1Vpp to 1.8Vpp).

[0178] Exemplarily, the hardware modules and components of the present application include a dual clock source module to implement a waveform synthesis and output module, a phase compensation module to implement a waveform synthesis and output module.

[0179] The dual clock source module includes a high-frequency clock unit, a low-frequency clock unit, and a field-programmable gate array (FPGA) switching circuit. The high-frequency clock unit is an oven-controlled crystal oscillator with a nominal frequency of 12MHz, an aging rate of ≤±0.5ppm / year, and a phase noise of -160dBc / Hz at 1kHz offset. It features a fast startup (warm-up time <5 minutes), meeting stability requirements. The low-frequency clock unit is a temperature-compensated crystal oscillator with a nominal frequency of 50kHz, a temperature stability of ±2ppm / °C, and a supply current of only 1.2mA. A constant temperature chamber is used to control ambient temperature fluctuations to ≤0.5°C, further enhancing frequency stability. The FPGA switching circuit uses its internal high-speed comparator to monitor the target frequency in real time. The target frequency is the desired output frequency (range 0.01Hz-100kHz) set by the user via the host computer or the front panel knob. This target frequency is monitored in real time by an internal FPGA counter. When the target frequency is ≥400Hz, the 12MHz high-frequency clock is enabled; when the target frequency is <400Hz, the 50kHz low-frequency clock is switched to. The switching action is controlled by the field programmable gate array state machine to ensure that the clock source switching timing meets the setup time requirement (≥5ns). The phase compensation module is implemented based on the phase compensation process in the above method. The waveform selection of the waveform synthesis and output module includes selecting the output of sine wave, square wave or triangle wave through the control register. The square wave duty cycle is configured by the period register. The square wave duty cycle adjustment step includes register configuration logic, for example, by writing to the control register 0x2100_xxxx (xxxx is a 12-bit period value), setting the square wave duty cycle D = period value / (2 12); Hardware implementation description: The phase accumulation value is compared with the period register threshold through the internal comparator: when the phase value is less than the threshold, a high level is output, otherwise a low level is output. By dynamically modifying the threshold, 1% step adjustment is achieved (the minimum adjustment unit is 4096 / 100=41LSB). Harmonic superposition is achieved by pre-generating 32 sets of harmonic amplitude coefficient tables and storing them in the RAM block on the field programmable gate array chip. Each harmonic is superimposed on the sine lookup table one by one through the fractional accumulation method, and the amplitude adjustment adopts the table lookup method (step 0.1dB). For example, the fractional accumulation method includes the field programmable gate array enabling 32 independent phase accumulators in sequence to generate n harmonics (n=1~32) respectively. The amplitude of each harmonic is obtained by the table lookup method: the 16-bit gain coefficient Converted to 12-bit DAC control word ( ),in is the fundamental amplitude, is the amplitude of the nth harmonic; the waveform synthesis process includes sending the phase data and amplitude control word of each harmonic into the sine lookup table, and using the formula To achieve superposition, Indicates the superimposed output value, The output conditioning circuit uses a programmable amplifier (gain switchable between 1× / 2× / 4× / 8×). The filter bank is a 5th-order Butterworth low-pass filter (with a switchable cutoff frequency of 100kHz / 500kHz). High-precision thin-film resistors (tolerance ±0.1%) and ceramic capacitors (temperature coefficient ±30ppm / °C) are used.

[0180] The embodiments of this application achieve a breakthrough balance between broadband coverage and high resolution, significantly outperforming traditional solutions in terms of core system performance. This embodiment achieves improved resolution across the entire frequency band. For example, when using a 12MHz clock in the high-frequency band (400Hz-100kHz), the frequency step reaches 0.0447Hz (theoretical value), a tenfold improvement compared to the traditional 125MHz single-clock solution. Switching to a 50kHz clock in the low-frequency band (0.01Hz-400Hz) increases the resolution to 0.000186Hz (measured value), meeting the requirements of precision testing such as industrial sensor excitation or high-precision spectrum analysis. The average resolution across the entire frequency band is improved by over 1,000 times. This embodiment of this application achieves phase noise optimization. Based on a high-stability oven-controlled crystal oscillator combined with a filter, it achieves a phase noise specification of -145dBc / Hz at 1kHz offset, an improvement of over 25dB compared to the 50kHz clock solution of a traditional broadband direct digital frequency synthesizer. The signal purity meets the calibration requirements of high-end spectrum analyzers. This embodiment enhances dynamic response, shortening frequency switching time to 3.4μs (typical). Through real-time control of a field-gate programmable array and a phase compensation algorithm, the clock switching process exhibits phase shifts of less than 1°, supporting high-speed frequency sweeps and dynamic signal simulation. This embodiment addresses the inability of traditional single-clock wideband direct digital frequency synthesis (DDS) to achieve both high resolution and fast response across the entire 0.01Hz-100kHz frequency band. A 28-bit phase accumulator and a phase compensation algorithm ensure phase continuity during clock switching, enabling the superposition of sine, square, and triangle fundamental waves and their 32nd harmonics. This embodiment is widely applicable to high-dynamic range test scenarios such as precision impedance measurement and bioelectrical signal simulation. This embodiment focuses on integrating a dynamic clock switching mechanism with a phase continuity compensation algorithm, aiming to overcome the performance bottleneck between wideband coverage and high resolution in traditional wideband DDS systems. This makes it particularly suitable for applications requiring cross-order frequency modulation, such as biomedical testing, industrial sensor excitation, and high-precision spectrum analysis. In summary, through hardware architecture innovation and algorithm optimization, this embodiment addresses the limitations of traditional wideband DDS technology while maintaining stability, achieving state-of-the-art performance in real-world scenarios.

[0181] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present application, and such modifications and improvements are also considered to be within the scope of protection of the present application.

Claims

1. A method for dynamically generating a broadband signal based on multiple clock sources, characterized in that: include: Monitor the target frequency in real time through a field programmable gate array, and automatically switch to the corresponding target clock source based on the frequency band to which the target frequency belongs; When the target clock source is switched, the phase difference between the old and new target clock sources is corrected by the phase compensation register, and the compensation value is loaded into the phase offset register of the direct digital frequency synthesis chip; The fundamental waveform of the broadband signal is generated based on the direct digital frequency synthesis chip, and multiple harmonic components are superimposed by a fractional accumulation method, and the amplitude of each harmonic is independently controlled by a table lookup method; The output signal of the power amplifier is sampled through an analog-to-digital converter to extract the error information between the measured waveform and the theoretical waveform; Dynamically correct the phase offset register and harmonic amplitude lookup table coefficients according to the error information, and output the target broadband signal; The step of sampling the output signal of the power amplifier through the analog-to-digital converter to extract error information between the measured waveform and the theoretical waveform includes: sampling the output signal of the power amplifier through the analog-to-digital converter to obtain the measured waveform; performing time synchronization on the measured waveform and the theoretical waveform generated by the direct digital frequency synthesis chip; performing a cross-correlation operation on the synchronized measured waveform and the theoretical waveform; and obtaining an actual phase deviation based on the cross-correlation operation. The cross-correlation operation is represented by the following formula: in, represents the cross-correlation function value, represents the delay index, represents the total number of relevant points, Indicates the sampling point index, represents the theoretical waveform, Indicates the measured waveform; The step of sampling the output signal of the power amplifier through the analog-to-digital converter and extracting error information between the measured waveform and the theoretical waveform further includes: sampling the output signal of the power amplifier through the analog-to-digital converter; windowing the output signal and suppressing spectrum leakage; performing a fast Fourier transform on the windowed output signal to extract the fundamental wave amplitude and the amplitudes of each harmonic; and evaluating the distortion of the broadband signal by comparing the amplitudes of each harmonic with the fundamental wave amplitude. The distortion is calculated using the following formula: ； in, Indicates the distortion, represents the fundamental amplitude, Indicates the amplitude of each harmonic; Among them, the dynamically correcting the phase offset register and the harmonic amplitude lookup table coefficient according to the error information includes: controlling whether to adjust the value of the phase offset register based on whether the actual phase deviation exceeds a preset threshold, wherein if the actual phase deviation exceeds the preset threshold, the value of the phase offset register is adjusted according to the proportional coefficient; if the actual phase deviation does not exceed the preset threshold, the value of the phase offset register is maintained; based on whether the distortion reaches a preset standard, controlling whether to adjust the harmonic amplitude lookup table coefficient, wherein if the distortion does not reach the preset standard, the harmonic amplitude lookup table coefficient is adjusted; if the distortion reaches the preset standard, the harmonic amplitude lookup table coefficient is maintained.

2. The method according to claim 1, wherein the target clock source comprises a high-frequency clock source or a low-frequency clock source, The automatically switching to the corresponding target clock source based on the frequency band to which the target frequency belongs includes: When the target frequency reaches a high frequency threshold, the high frequency clock source is enabled, and when the target frequency is lower than a low frequency threshold, the low frequency clock source is switched to. The high-frequency threshold is 400 Hz, and the low-frequency threshold is the same as the high-frequency threshold. When the target frequency is greater than or equal to 400 Hz, switch to the high-frequency clock source, which is a 12 MHz oven-controlled crystal oscillator clock source; When the target frequency is less than 400 Hz, the low-frequency clock source is switched to, and the low-frequency clock source is a 50 kHz temperature compensated crystal oscillator clock source.

3. The method according to claim 1, characterized in that The method of correcting the phase difference between the old and new target clock sources by using a phase compensation register when the target clock source is switched, and loading the compensation value into the phase offset register of the direct digital frequency synthesis chip includes: Using a high-order phase accumulator, a phase increment is calculated according to the target frequency and the current clock frequency; When the clock source is switched, the phase accumulation value corresponding to the old target clock source before the switch is recorded in real time; Calculate the phase accumulation value corresponding to the new target clock source after switching in real time; Loading a compensation value through the phase compensation register, wherein the compensation value is a phase accumulation value corresponding to the old target clock source before switching and a phase accumulation value corresponding to the new target clock source after switching; The compensation value is written into the phase offset register of the direct digital frequency synthesis chip and the output signal phase difference is corrected.

4. The method according to claim 1, wherein The phase difference between the new and old target clock sources is calculated using the following formula: in, represents the phase difference, represents the target frequency, represents the temperature compensation coefficient, Indicates the current clock frequency; The temperature compensation coefficient Calculated by the following formula: in, represents the crystal temperature coefficient, Indicates the ambient temperature.

5. The method according to claim 1, wherein The target broadband signal may include a sine wave, a square wave, a triangle wave, or a harmonic superposition signal of any combination thereof.

6. The method according to claim 1, characterized in that Before outputting the target broadband signal, the method includes: Obtaining phase noise data of a reference clock at a target offset frequency; Based on the frequency of the reference clock and the target frequency, a reference phase noise is calculated using a carrier frequency conversion formula; Acquire the internal noise of the direct digital frequency synthesis chip, and superimpose the internal noise and the reference phase noise to obtain a total phase noise evaluation value; When the total phase noise evaluation value does not exceed a preset noise standard, outputting the target broadband signal; When the total phase noise evaluation value exceeds the preset noise standard, the operation of automatically switching to the corresponding target clock source based on the frequency band to which the target frequency belongs or retrieving the output signal of the power amplifier through the analog-to-digital converter is triggered.

7. A broadband signal dynamic generation system based on multiple clock sources, characterized in that: include: A clock source switching module is used to monitor the target frequency in real time through a field programmable gate array and automatically switch to the corresponding target clock source based on the frequency band to which the target frequency belongs; A phase difference compensation module is used to correct the phase difference between the new and old target clock sources through the phase compensation register when the target clock source is switched, and load the compensation value into the phase offset register of the direct digital frequency synthesis chip; A multiple harmonic superposition module is used to generate a fundamental waveform of a broadband signal based on the direct digital frequency synthesis chip, and to superimpose multiple harmonic components by a fractional accumulation method, with the amplitude of each harmonic being independently controlled by a table lookup method; The error information calculation module is used to retrieve the output signal of the power amplifier through the analog-to-digital converter and extract the error information between the measured waveform and the theoretical waveform; A target signal output module, configured to dynamically correct the phase offset register and harmonic amplitude lookup table coefficients according to the error information, and output a target broadband signal; The step of sampling the output signal of the power amplifier through the analog-to-digital converter to extract error information between the measured waveform and the theoretical waveform includes: sampling the output signal of the power amplifier through the analog-to-digital converter to obtain the measured waveform; performing time synchronization on the measured waveform and the theoretical waveform generated by the direct digital frequency synthesis chip; performing a cross-correlation operation on the synchronized measured waveform and the theoretical waveform; and obtaining an actual phase deviation based on the cross-correlation operation. The cross-correlation operation is represented by the following formula: in, represents the cross-correlation function value, represents the delay index, represents the total number of relevant points, Indicates the sampling point index, represents the theoretical waveform, Indicates the measured waveform; The step of sampling the output signal of the power amplifier through the analog-to-digital converter and extracting error information between the measured waveform and the theoretical waveform further includes: sampling the output signal of the power amplifier through the analog-to-digital converter; windowing the output signal and suppressing spectrum leakage; performing a fast Fourier transform on the windowed output signal to extract the fundamental wave amplitude and the amplitudes of each harmonic; and evaluating the distortion of the broadband signal by comparing the amplitudes of each harmonic with the fundamental wave amplitude. The distortion is calculated using the following formula: ； in, Indicates the distortion, represents the fundamental amplitude, Indicates the amplitude of each harmonic; Among them, the dynamically correcting the phase offset register and the harmonic amplitude lookup table coefficient according to the error information includes: controlling whether to adjust the value of the phase offset register based on whether the actual phase deviation exceeds a preset threshold, wherein if the actual phase deviation exceeds the preset threshold, the value of the phase offset register is adjusted according to the proportional coefficient; if the actual phase deviation does not exceed the preset threshold, the value of the phase offset register is maintained; based on whether the distortion reaches a preset standard, controlling whether to adjust the harmonic amplitude lookup table coefficient, wherein if the distortion does not reach the preset standard, the harmonic amplitude lookup table coefficient is adjusted; if the distortion reaches the preset standard, the harmonic amplitude lookup table coefficient is maintained.

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