Floating point operation unit of sine and cosine functions, floating point operation acceleration method, equipment and medium

Abstract

The invention discloses a floating-point operation unit of sine and cosine functions, a floating-point operation acceleration method, equipment and a medium, and relates to the technical field of microprocessors, and the floating-point operation unit comprises an instruction fetching module which is used for obtaining a floating-point data operation demand, selecting a target multiply-add instruction based on the floating-point data operation demand, and sending the target multiply-add instruction to a decoding module; the decoding module is used for analyzing and extracting a table look-up index control signal and a multiply-add component switching signal in the target multiply-add instruction; the table look-up module is used for accessing the coefficient table according to the table look-up index control signal and reading the corresponding target Taylor expansion coefficient; the dynamic switching module is used for switching a data operation path according to the multiply-add component switching signal; and the SIMD multiplication and addition component is used for calling a corresponding data operation path to carry out floating point data operation on the target Taylor expansion coefficient and a source operand in the floating point data operation requirement, and outputting an operation result in a corresponding output format. Hardware is reused, multiple sets of independent circuits are not needed, dynamic bit width adjustment is supported, and the chip area is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessors, and in particular to a floating-point operation unit of sine and cosine functions, a floating-point operation acceleration method, a device and a medium. Background Art

[0002] In high-performance computing fields such as graphics rendering, scientific computing, and 5G communications (fifth-generation mobile networks), fast computation of sine and cosine functions is a core requirement. For example, real-time graphics rendering requires processing millions of trigonometric transformations of vertex coordinates per second; in 5G baseband processing, the Fast Fourier Transform (FFT) relies on efficient sine and cosine functions to generate rotation factors; and scientific simulations (such as fluid dynamics) require high-precision floating-point operations to ensure reliable results. However, existing solutions suffer from the following significant drawbacks: Traditional approaches design separate computational units for different precisions (FP16 / FP32 / FP64), resulting in a surge in chip area and power consumption. For example, GPUs (Graphics Processing Units) require dedicated modules for both FP16 and FP32 to meet mixed-precision rendering requirements, resulting in wasted resources. Existing hardware accelerators in 5G communication baseband chips only support a single precision format (such as FP32) and are unable to adapt to the low-power FP16 mode, resulting in poor energy efficiency. Furthermore, software implementations of Taylor series terms require multiple memory accesses to load coefficients and cannot process different expansion forms in parallel (e.g., Form 1 requires 8 iterations, Form 2 requires 4 iterations). For example, in autonomous driving point cloud processing, software calculations of sine and cosine functions experience latency as high as 50 cycles, failing to meet real-time requirements. While existing hardware accelerators reduce computation cycles, they only support fixed expansion forms and cannot flexibly adapt to polynomial rearrangements after algorithm optimization. In summary, traditional technologies cannot efficiently support multiple Taylor expansion forms and multi-precision calculations in the same computing unit, resulting in low resource utilization and high computing latency in scenarios such as graphics rendering and communication baseband processing. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a floating-point operation unit for sine and cosine functions, a floating-point operation acceleration method, device, and medium, which can accelerate the operation of floating-point data in a microprocessor. The specific solution is as follows: In the first aspect, the present application discloses a floating-point operation unit for sine and cosine functions, including an instruction fetch module, a decoding module, a table lookup module, a coefficient table, a dynamic switching module, and a SIMD multiplication and addition component, wherein: The instruction fetch module is configured to obtain a floating-point data operation requirement, select a target multiply-add instruction based on the floating-point data operation requirement, and send the target multiply-add instruction to the decoding module; The decoding module is used to parse and extract the table lookup index control signal and the multiplication and addition component switching signal in the target multiplication and addition instruction; The table lookup module is used to access the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; The dynamic switching module is used to switch the data operation path according to the multiplication and addition component switching signal; The SIMD multiplication-addition component is used to call the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement, so as to output the operation result in the corresponding output format.

[0004] Optionally, the decoding module includes: a parsing unit, configured to parse an opcode, an immediate field, and a precision mode field of the target multiply-add instruction; a first extraction unit, configured to identify from the opcode whether the target multiply-add instruction is a preset single-coefficient multiply-add instruction or a preset double-coefficient multiply-add instruction, to obtain a corresponding instruction type; wherein the preset single-coefficient multiply-add instruction is a multiply-add instruction for calculating a nested iterative Taylor series term; and the preset double-coefficient multiply-add instruction is a multiply-add instruction for calculating a grouped Taylor series term; A second extraction unit, configured to extract an immediate value from the immediate value field; A third extraction unit is configured to extract a target precision from the precision mode field; wherein the target precision is half precision, single precision, or double precision; a first signal generating unit, configured to concatenate the sign bits of the immediate number and the source operand required for the floating-point data operation to generate a table lookup index control signal; A second signal generating unit is configured to generate a corresponding multiplication-addition component switching signal according to the instruction type; the multiplication-addition component switching signal includes a first multiplication-addition component switching signal and a second multiplication-addition component switching signal; The third signal generating unit is configured to generate a corresponding output format signal according to the target accuracy; wherein the output format signal includes a first output format signal, a second output format signal, and a third output format signal.

[0005] Optionally, the coefficient table is implemented based on a multi-port register stack and is used to pre-store 16 groups of Taylor expansion coefficients of sine and cosine functions.

[0006] Optionally, the dynamic switching module includes: a first switching unit, configured to switch the data operation path to a first data operation path according to a switching signal of the first multiplication and addition component; The second switching unit is configured to switch the data operation path to the second data operation path according to the second multiplication and addition component switching signal.

[0007] Optionally, the SIMD multiplication-addition component includes: a first operation unit, configured to call the adder and the multiplier of the first data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient to obtain a new source operand, and jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient until all Taylor series term operations are completed to obtain an initial floating-point data operation result; a second operation unit, configured to call the adder and the multiplier of the second data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, determine the next source operand as a new source operand according to the Taylor series term expansion order, jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, until all Taylor series term operations are completed, and accumulate all the partial operation results to obtain an initial floating-point data operation result; The third operation unit is used to dynamically adjust the mantissa bit width of the initial floating-point data operation result according to the output format signal to obtain a target operation result in a corresponding format.

[0008] Optionally, the second computing unit includes: a first adjustment unit, configured to adjust the mantissa bit width of the initial floating-point data operation result to 10 bits according to the first output format signal, so as to obtain a target operation result in a corresponding output format; A second adjustment unit is configured to adjust the mantissa bit width of the initial floating-point data operation result to 23 bits according to the second output format signal, so as to obtain a target operation result in a corresponding output format; The third adjustment unit is used to adjust the mantissa bit width of the initial floating-point data operation result to 52 bits according to the third output format signal to obtain a target operation result under the corresponding output format.

[0009] Optionally, the coefficient table contains Taylor expansion coefficients arranged in index order and carrying positive and negative signs.

[0010] In a second aspect, the present application discloses a floating-point operation acceleration method based on a floating-point operation unit, wherein the floating-point operation unit is the floating-point operation unit disclosed above; wherein the method comprises: obtaining floating-point data operation requirements, and selecting a target multiply-add instruction based on the floating-point data operation requirements; Parsing and extracting a table lookup index control signal and a multiplication-addition component switching signal in the target multiplication-addition instruction; Accessing a coefficient table according to the table lookup index control signal to read corresponding target Taylor expansion coefficients; Switching the data operation path according to the multiplication and addition component switching signal; The corresponding data operation path is called to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format.

[0011] In a third aspect, the present application discloses an electronic device, comprising: Memory, used to store computer programs; The processor is used to execute the computer program to implement the steps of the floating-point operation acceleration method based on the floating-point operation unit disclosed above.

[0012] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned floating-point operation acceleration method based on a floating-point operation unit are implemented.

[0013] It can be seen that the present application discloses a floating-point operation unit for sine and cosine functions, including an instruction fetch module, a decoding module, a table lookup module, a coefficient table, a dynamic switching module, and a SIMD multiplication-addition component, wherein the instruction fetch module is used to obtain floating-point data operation requirements, and select a target multiplication-addition instruction based on the floating-point data operation requirements, and send the target multiplication-addition instruction to the decoding module; the decoding module is used to parse and extract the table lookup index control signal and the multiplication-addition component switching signal in the target multiplication-addition instruction; the table lookup module is used to access the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; the dynamic switching module is used to switch the data operation path according to the multiplication-addition component switching signal; the SIMD multiplication-addition component is used to call the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format. It can be seen that this application selects two forms of target multiplication and addition instructions to dynamically adapt to Taylor expansion based on the requirements of floating-point data operations; parses the table lookup index control signal and the multiplication and addition component switching signal in the instruction to generate index signals and switching signals, so as to further access the coefficient table through the table lookup index control signal, read single coefficients or double coefficients, and then dynamically switch the input paths of the source operand and the Taylor coefficient according to the multiplication and addition component switching signal to realize hardware multiplexing, without the need for multiple sets of independent circuits, reuse existing SIMD multipliers and adders, support dynamic bit width adjustment, and reduce chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0015] Figure 1 This is a diagram of the floating-point arithmetic unit architecture of a sine and cosine function disclosed in this application; Figure 2 This is a processing flow chart of an FTMAD instruction disclosed in this application; Figure 3 A hardware processing structure diagram of the FTMAD instruction disclosed in this application; Figure 4 This is a processing flow chart of the FTMAD2C instruction disclosed in this application; Figure 5 A hardware processing structure diagram of the FTMAD2C instruction disclosed in this application; Figure 6 This is a flow chart of a floating-point operation acceleration method based on a floating-point operation unit disclosed in this application; Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] In high-performance computing fields such as graphics rendering, scientific computing, and 5G communications, fast computation of sine and cosine functions is a core requirement. For example, real-time graphics rendering requires processing millions of trigonometric transformations of vertex coordinates per second; in 5G baseband processing, the Fast Fourier Transform (FFT) relies on efficient sine and cosine functions to generate rotation factors; and scientific simulations (such as fluid dynamics) require high-precision floating-point operations to ensure reliable results. However, existing technical solutions have the following significant drawbacks: Traditional solutions design separate computational units for different precisions (FP16 / FP32 / FP64), resulting in a surge in chip area and power consumption. For example, GPUs must deploy both FP16 and FP32 dedicated modules to meet mixed-precision rendering requirements, resulting in resource waste. In 5G communication baseband chips, existing hardware accelerators only support a single precision format (such as FP32) and are unable to adapt to the low-power FP16 mode, resulting in poor energy efficiency. Furthermore, software implementations of Taylor series calculations require multiple memory accesses to load coefficients and cannot process different expansion forms in parallel (e.g., Form 1 requires 8 iterations, Form 2 requires 4 iterations). For example, in autonomous driving point cloud processing, software calculations of sine and cosine functions can experience latency as high as 50 cycles, failing to meet real-time requirements. While existing hardware accelerators reduce computation cycles, they only support fixed expansion forms and cannot flexibly adapt to polynomial rearrangement requirements after algorithm optimization. In summary, traditional technologies cannot efficiently support multiple Taylor expansion forms and multi-precision calculations within the same computational unit, resulting in low resource utilization and high computational latency in scenarios such as graphics rendering and communication baseband processing.

[0018] To this end, the present invention provides a floating-point operation unit for sine and cosine functions and a floating-point operation acceleration solution, which can accelerate the operation of floating-point data in a microprocessor.

[0019] Reference Figure 1 As shown, the embodiment of the present invention discloses a floating-point operation unit for sine and cosine functions, including an instruction fetch module 11, a decoding module 12, a table lookup module 13, a coefficient table 14, a dynamic switching module 15, and a SIMD multiplication and addition unit 16, wherein: The instruction fetch module 11 is configured to obtain floating-point data operation requirements, select a target multiply-add instruction based on the floating-point data operation requirements, and send the target multiply-add instruction to the decoding module; The decoding module 12 is used to parse and extract the table lookup index control signal and the multiplication and addition component switching signal in the target multiplication and addition instruction; The table lookup module 13 is configured to access the coefficient table 14 according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; The dynamic switching module 15 is used to switch the data operation path according to the multiplication and addition component switching signal; The SIMD multiplication-addition component 16 is used to call the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format.

[0020] The decoding module 12 includes: a parsing unit, configured to parse an opcode, an immediate field, and a precision mode field of the target multiply-add instruction; a first extraction unit, configured to identify from the opcode whether the target multiply-add instruction is a preset single-coefficient multiply-add instruction or a preset double-coefficient multiply-add instruction, to obtain a corresponding instruction type; wherein the preset single-coefficient multiply-add instruction is a multiply-add instruction for calculating a nested iterative Taylor series term; and the preset double-coefficient multiply-add instruction is a multiply-add instruction for calculating a grouped Taylor series term; A second extraction unit, configured to extract an immediate value from the immediate value field; A third extraction unit is configured to extract a target precision from the precision mode field; wherein the target precision is half precision, single precision, or double precision; a first signal generating unit, configured to concatenate the sign bits of the immediate number and the source operand required for the floating-point data operation to generate a table lookup index control signal; A second signal generating unit is configured to generate a corresponding multiplication-addition component switching signal according to the instruction type; the multiplication-addition component switching signal includes a first multiplication-addition component switching signal and a second multiplication-addition component switching signal; The third signal generating unit is configured to generate a corresponding output format signal according to the target accuracy; wherein the output format signal includes a first output format signal, a second output format signal, and a third output format signal.

[0021] The coefficient table 14 is implemented based on a multi-port register stack and is used to pre-store 16 groups of Taylor expansion coefficients of the sine and cosine functions.

[0022] The coefficient table 14 contains Taylor expansion coefficients arranged in index order and carrying positive and negative signs.

[0023] The dynamic switching module 15 includes: a first switching unit, configured to switch the data operation path to a first data operation path according to a switching signal of the first multiplication and addition component; The second switching unit is configured to switch the data operation path to the second data operation path according to the second multiplication and addition component switching signal.

[0024] The SIMD multiplication and addition component 16 includes: a first operation unit, configured to call the adder and the multiplier of the first data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient to obtain a new source operand, and jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient until all Taylor series term operations are completed to obtain an initial floating-point data operation result; a second operation unit, configured to call the adder and the multiplier of the second data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, determine the next source operand as a new source operand according to the Taylor series term expansion order, jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, until all Taylor series term operations are completed, and accumulate all the partial operation results to obtain an initial floating-point data operation result; The third operation unit is used to dynamically adjust the mantissa bit width of the initial floating-point data operation result according to the output format signal to obtain a target operation result in a corresponding format.

[0025] The second computing unit includes: a first adjustment unit, configured to adjust the mantissa bit width of the initial floating-point data operation result to 10 bits according to the first output format signal, so as to obtain a target operation result in a corresponding output format; A second adjustment unit is configured to adjust the mantissa bit width of the initial floating-point data operation result to 23 bits according to the second output format signal, so as to obtain a target operation result in a corresponding output format; The third adjustment unit is used to adjust the mantissa bit width of the initial floating-point data operation result to 52 bits according to the third output format signal to obtain a target operation result under the corresponding output format.

[0026] It is understandable that Taylor expansion operations of sine and cosine functions will appear in the geometric transformation, lighting model, and animation interpolation of graphics rendering scenes. In the vertex transformation in graphics rendering, each vertex requires multiple rotation transformations, involving a large number of sine and cosine calculations. When the rotation transformation matrix of the vertex of the graphics rendering scene is: ; in, represents the rotation matrix, Indicates the rotation angle, represents the sine function, Represents the cosine function.

[0027] Therefore, when Normalize to [ ,π / 4], and then the vertex transformation process is calculated. To accelerate this calculation process, the corresponding floating-point data calculation requirements are generated, which are the vertex rotation acceleration calculation requirements in the graphics rendering scene. Correspondingly, in the graphics rendering scene, for the normal vector calculation, normal vector interpolation, and specular reflection calculation in the lighting model, the sine and cosine functions need to be frequently called. For example, the highlight term in the Blinn-Phong model needs to call the sine and cosine functions. To accelerate the normal vector calculation of the lighting model, the frequently called sine and cosine functions need to be accelerated. Therefore, the corresponding floating-point data calculation requirements are generated, which are the lighting model acceleration calculation requirements in the graphics rendering scene. When simulating the movement of fluid within a periodic boundary, the Fourier series expansion of the velocity field and pressure field needs to be frequently calculated, involving high-precision sine and cosine operations. Therefore, the corresponding floating-point data calculation requirements are generated, which are the Fourier series acceleration calculation requirements of the velocity field and pressure field in the fluid scene. The floating-point calculation requirements in other scenes are not further elaborated.

[0028] In this embodiment, a floating-point data operation requirement is obtained. For example, after the current floating-point data operation requirement is analyzed and processed, it is obtained as a Taylor expansion polynomial operation of the sine function sinx, wherein 1, 1 / 3!, 1 / 5!, 1 / 7!, 1 / 9!, 1 / 11!, 1 / 13!, and 1 / 15! are Taylor expansion coefficients after the sinx Taylor expansion. Then, the corresponding target multiplication and addition instruction is further selected according to the expansion form of the current sinx Taylor expansion polynomial. Specifically, when the expansion form of the sinx Taylor expansion polynomial is (0•x2-1 / 15!), ((0•x2-1 / 15!)x2+1 / 13!), (((0•x2-1 / 15!)x2+1 / 13!)x2-1 / 11!), ((((0•x2-1 / 15!)x2+1 / 13!)x2-1 / 11!)x2-1 / 9!), (((((0•x2-1 / 15!)x 2+1 / 13!)x2-1 / 11!)x2-1 / 9!)x2-1 / 7!), ((((((0·x2-1 / 15!)x2+1 / 13!)x2-1 / 11!)x2-1 / 9! )x2-1 / 7!))x2-1 / 5!), (((((((0•x2-1 / 15!)x2+1 / 13!)x2-1 / 11!)x2-1 / 9!)x2-1 / 7!))x2-1 / 5!)x2-1 / 3!), ((((((((0•x2-1 / 15!)x2+1 / 13!)x2-1 / 11!)x2-1 / 9!)x2-1 / 7!))x2-1 / 5!)x2-1 / 3!)x2+1), it indicates that the current Taylor series term is a step-by-step iterative complex Taylor expansion. For the operation of the current Taylor series term, the target multiplication-addition instruction is determined to be the preset single-coefficient multiplication-addition instruction, that is, FTMAD. When the expansion form of the sinx Taylor expansion polynomial is (1-1 / 3!•x2), (1 / 5!-1 / 7!•x2), (1 / 9!-1 / 11!•x2), (1 / 13!-1 / 15!•x2), it indicates that the current Taylor series term is an independently grouped Taylor series term. For the operation of the current Taylor series term, the target multiplication and addition instruction is determined to be the preset double-coefficient multiplication and addition instruction, that is, FTMAD2C.

[0029] In this embodiment, the decoding module parses and extracts the target multiply-add instruction to obtain a parsed binary code, including an opcode, an immediate field, a precision mode field, and a register addressing mode field; further, the current instruction type can be obtained based on the opcode.

[0030] like Figure 2As shown, when the instruction type is the FTMAD instruction type, the binary encoding is a 32-bit fixed-length encoding, where bits [31:26] is the opcode field 0x1F, bits [25:20] is the immediate field IMM, bits [19:15] is the target register RD, and bits [14:0] is the source register RS1 / RS2. In this way, the encoding position of each field can be determined, and the immediate number IMM can be further extracted from the immediate field, the source register information and the target register information can be extracted from the register addressing mode field, and the corresponding target precision can be determined from the precision mode field. Finally, the table index control signal is generated based on the sign bit splicing of the immediate number and the source operand, and the first multiplication and addition component switching signal, the output format signal, and the sign correction signal are also generated. Among them, as Figure 3 As shown in the figure, when the instruction type is determined to be FTMAD, the opcode is used to trigger the single coefficient multiplication and addition logic, and the immediate value is the upper 3 bits of the table lookup index, which is used to concatenate with the sign bit of the source operand. The source register (RS1) is used to store the square of the input value (such as the normalized x 2 , its absolute value and sign need to be read. The source register (RS2) stores the intermediate results of the iterative calculation, initially set to 0 or the result of the previous iteration. The destination register (RD) specifies the write location for the current iteration result and is typically the same as RS2, used for loop updates. The precision mode determines the data bit width, such as FP16 / FP32 / FP64. The generated table lookup index control signal generates a 4-bit index (3-bit immediate value + 1-bit sign bit) for accessing the register-based coefficient table. The first multiply-add unit switch signal configures the input source and operation mode of the multiply-add unit. The output format signal dynamically adjusts the mantissa bit width and exponent alignment logic based on the precision mode. For example, in FP16 mode, the mantissa bit width is 10 bits and the exponent is 5 bits; in FP32 mode, the mantissa bit width is 23 bits and the exponent is 8 bits. The sign correction signal automatically handles the coefficient sign. Note that the lookup table coefficients already have pre-stored signs, so no additional operation is required; the signed coefficients can be directly read using the index.

[0031] like Figure 4As shown, when the instruction type is FTMAD2C instruction type, the decoding module needs to parse the instruction field and generate the control signals required for the dual coefficient table lookup and parallel multiplication and addition. Specifically, the binary encoding is a 32-bit fixed-length encoding, the opcode bits [31:26], and the instruction type is identified as 0x1E, which is used to distinguish it from FTMAD's 0x1F. The immediate field IMM_A: bits [25:22], a 3-bit immediate number, is used to generate the upper 3 bits of the first table lookup index. IMM_B: bits [21:18], a 3-bit immediate number, is used to generate the upper 3 bits of the second table lookup index. The destination register (RD) bits [17:13] specifies the result write location. The source register (RS1) bits [12:8] stores the square of the input value, such as the normalized x 2 The source and destination registers (RS2) bits [7:3] store intermediate results or auxiliary operands. The precision mode field, bits [2:0], identifies the data format, such as 000 = FP16, 001 = FP32, and 010 = FP64. The corresponding table index control signal, Index A, is a 4-bit concatenated combination of the RS1 sign bit (1 bit) and IMM_A (3 bits). Index B is a 4-bit concatenated combination of the RS1 sign bit (1 bit) and IMM_B (3 bits). The dual table index signal is used to generate two 4-bit indices (IDX1 and IDX2) to access the register-based coefficient table to retrieve dual coefficients. The second multiply-add unit switching signal configures the multiply-add unit to process dual coefficients in parallel. The output format signal dynamically adjusts the mantissa bit width and exponent alignment logic based on the precision mode. For example, in the FP16 precision mode, the mantissa is 10 bits and the exponent is 5 bits. In the FP32 precision mode, the mantissa is 23 bits and the exponent is 8 bits. In the FP64 precision mode, the mantissa is 52 bits and the exponent is 11 bits. The sign correction signal is used to automatically process the signs of the double coefficients. It should be noted that the lookup table coefficients have pre-stored signs.

[0032] It should be noted that after generating each signal, the decoding module sends the above signal to the corresponding table lookup module and dynamic switching module in the execution stage.

[0033] The table lookup module accesses and reads the corresponding target Taylor expansion coefficient from the coefficient table in the register upon receiving the relevant control signal (table lookup index control signal). For example, in the FTMAD instruction, the index is generated by RS1 sign bit + imm3, so the generated single index is used to read the corresponding single target Taylor expansion coefficient; in the FTMAD2C instruction, index 1 is generated by RS1 sign bit + imma3 and index 2 is generated by RS1 sign bit + immb3, that is, a double index is obtained, so the double index is used to read the corresponding double target Taylor expansion coefficients from the coefficient table in the register.

[0034] The dynamic switching module dynamically switches the input source and operation mode of the SIMD (Single Instruction, Multiple Data) multiplication and addition component based on the received multiplication and addition component switching signal. For example: under the FTMAD instruction, the multiplication and addition component switching signal configures the SIMD multiplication and addition component to multiply the absolute value of RS2 by RS1 and then add it to the target Taylor expansion coefficient COEF. Figure 5 As shown in the figure, in the FTMAD2C instruction, the multiply-add unit switching signal configures the SIMD multiply-add unit to simultaneously process the dual target Taylor expansion coefficients (COEF1 and COEF0). The multiply-add unit switching signal controls the multiplexer (MUX) to switch input sources, ensuring that the SIMD multiply-add unit adapts to different instruction requirements when multiplexing.

[0035] Finally, the SIMD multiplication and addition component switches the data operation path according to the above multiplication and addition component switching signal, and performs floating-point data operations on the target Taylor expansion coefficient and the source operand. Under the Taylor expansion polynomial selection FTMAD instruction of the sine function sinx, the floating-point operation process is: Source operand (input value): x 2 (Pre-calculated and stored in register RS1), initial intermediate result: RS2 = 0 (initial value of the first iteration). Coefficient table (TBL): Pre-stored Taylor coefficients, arranged by index (for example, index 0 corresponds to 1 / 15!, index 1 corresponds to 1 / 13!, and so on).

[0036] Iteration steps, a total of 8 FTMAD instructions, the first iteration calculation (0x 2 1 / 15!).

[0037] Operand preparation.

[0038] RS1 = x 2 (The square of the normalized input value).

[0039] RS2=0 (initial intermediate result).

[0040] Generate table index.

[0041] Immediate value IMM=0 (corresponding to index 0).

[0042] Index IDX = RS2 sign bit (0) + IMM (0) = 0.

[0043] Coefficient reading: The table lookup module reads the coefficient COEF=-\frac{1}{15!} through IDX=0.

[0044] Multiplication and addition operation: Multiplication: RS2×|RS1| =0×x 2 =0.

[0045] Addition: 0+COEF=-\frac{1}{15!}.

[0046] Result update: Intermediate result RS2 = -\frac{1}{15!}, used for the next iteration.

[0047] Iteration 2: Calculate ( x 2 / 15!+1 / 13!), operand preparation.

[0048] RS1 =x 2 (remains unchanged).

[0049] RS2 =-\frac{1}{15!} (previous result).

[0050] Generate table index.

[0051] Immediate value IMM = 1 (corresponding to index 1).

[0052] Index IDX = RS2 sign bit (1, because the value is negative) + IMM (1) = 2 (assuming the sign bit is 1).

[0053] Coefficient reading: The table lookup module reads the coefficient COEF=+\frac{1}{13!} through IDX=1.

[0054] Multiply and add operations.

[0055] Multiplication: RS2×|RS1|=-\frac{1}{15!}×x 2 .

[0056] Addition: -\frac{1}{15!}x 2 +\frac{1}{13!}.

[0057] Result update: Intermediate result RS2=-\frac{1}{15!}x 2 +\frac{1}{13!}.

[0058] Iterations 3 to 7: The subsequent coefficients are processed in sequence, and IMM and RS2 are updated in each iteration. The process is similar and will not be described in detail.

[0059] Iteration 8: Calculate the final term (previous result x 2 +1).

[0060] Operand preparation.

[0061] RS1 = x 2 .

[0062] RS2=\text{previous result} (value after the 7th iteration).

[0063] Lookup index generation:

[0064] Immediate value IMM=7 (corresponding to index 7).

[0065] Index IDX = RS2 sign bit + IMM (7) = 8 (actually adjusted according to the sign bit).

[0066] Coefficient reading.

[0067] The table lookup module reads the coefficient COEF=+1 through IDX=7.

[0068] Multiply and add operations.

[0069] Multiplication: RS2×|RS1| =\text{previous result}×x 2 .

[0070] Addition: \text{previous result}×x 2 +1.

[0071] Final result: RS2 =\left(\cdots\right)x 2 +1, which means that all series calculations are completed.

[0072] This shows that the index for each iteration is generated by concatenating the immediate value and the sign bit of the previous result, ensuring that the coefficient sign is automatically handled (for example, no additional logic is required for the negative sign). For example, if the previous result was negative and the sign bit was 1, the index is IMM+1; if it was positive, the sign bit was 0 and the index is IMM. SIMD multiplication and addition components are reused: the multiplier always calculates RS2×|RS1|. The adder adds the product result to the lookup table coefficient and writes the result back to RS2 for the next iteration. The final result is multiplied by x (the original input before normalization) to obtain an approximate value of sinx. This process significantly reduces the latency and resource consumption of software calculations through the iteration and reuse of hardware instructions.

[0073] When selecting the FTMAD2C instruction for the Taylor expansion polynomial of the sine function sinx, two target Taylor expansion coefficients are processed in parallel with a single instruction, significantly reducing the number of iterations. The following details the hardware implementation process and explains its relationship with iterations with a specific example. The Taylor expansion polynomial of the sine function sinx requires four FTMAD2C instructions, each processing a double coefficient term within brackets. x 2 / 3!) as an example.

[0074] Step 1: Instruction decoding and data preparation steps are as follows: Target item: 1 x 2 / 3!, instruction field: imma3 = 0 (corresponding to the index of coefficient 1). immb3 = 1 (corresponding to the index of coefficient -1 / 3!).

[0075] Source operand: RS1=x 2 (the square of the input value).

[0076] Step 2: Look up the table to read the double coefficients.

[0077] Index generation.

[0078] IDX1=imma3=0, which means COEF1=1 is read.

[0079] IDX2 = immb3 = 1, which means COEF0 = -1 / 3!.

[0080] Step 3: Perform the multiplication and addition operation as follows.

[0081] Evaluates an expression.

[0082] COEF1×|RS1|+COEF0=1×x 2 +( 1 / 3!)=x 2 -x 2 / 3!.

[0083] Result: The output is x 2 -x 2 / 3!, which is the target item.

[0084] Step 4: Accumulate to the final result. The steps are as follows.

[0085] The hardware accumulator sums this result with the results of the other three FTMAD2C instructions and multiplies it by x to get sinx.

[0086] This allows each FTMAD2C instruction to independently process a two-coefficient term, and the results are directly accumulated without requiring the previous result to be used as input for the next. The hardware then combines the results of all terms in parallel using the accumulator. The four FTMAD2C instructions can be executed sequentially or in parallel without waiting for intermediate results to be delivered, making them suitable for pipeline parallel acceleration.

[0087] It should be noted that the above floating-point operation results are initial floating-point data operation results. Before output, the mantissa bit width of the initial result needs to be adjusted according to the output format signal under the corresponding precision format to obtain the final output result.

[0088] It can be seen that the present application discloses a floating-point operation unit for sine and cosine functions, including an instruction fetch module, a decoding module, a table lookup module, a coefficient table, a dynamic switching module, and a SIMD multiplication-addition component, wherein the instruction fetch module is used to obtain floating-point data operation requirements, and select a target multiplication-addition instruction based on the floating-point data operation requirements, and send the target multiplication-addition instruction to the decoding module; the decoding module is used to parse and extract the table lookup index control signal and the multiplication-addition component switching signal in the target multiplication-addition instruction; the table lookup module is used to access the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; the dynamic switching module is used to switch the data operation path according to the multiplication-addition component switching signal; the SIMD multiplication-addition component is used to call the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format. It can be seen that this application selects two forms of target multiplication and addition instructions to dynamically adapt to Taylor expansion based on the requirements of floating-point data operations; parses the table lookup index control signal and the multiplication and addition component switching signal in the instruction to generate index signals and switching signals, so as to further access the coefficient table through the table lookup index control signal, read single coefficients or double coefficients, and then dynamically switch the input paths of the source operand and the Taylor coefficient according to the multiplication and addition component switching signal to realize hardware multiplexing, without the need for multiple sets of independent circuits, reuse existing SIMD multipliers and adders, support dynamic bit width adjustment, and reduce chip area.

[0089] Reference Figure 6 As shown, the present invention also correspondingly discloses a floating-point operation acceleration method based on a floating-point operation unit, wherein the floating-point operation unit is the floating-point operation unit disclosed above; wherein the method includes: Step S11: obtaining floating-point data operation requirements, and selecting a target multiply-add instruction based on the floating-point data operation requirements; Step S12: parsing and extracting the table lookup index control signal and the multiplication and addition component switching signal in the target multiplication and addition instruction; Step S13: accessing the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; Step S14: switching the data operation path according to the multiplication and addition component switching signal; Step S15: calling the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format.

[0090] It can be seen that the present application discloses obtaining floating-point data operation requirements, selecting a target multiplication-addition instruction based on the floating-point data operation requirements, and sending the target multiplication-addition instruction to the decoding module; parsing and extracting the table lookup index control signal and the multiplication-addition component switching signal in the target multiplication-addition instruction; accessing the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; switching the data operation path according to the multiplication-addition component switching signal; calling the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format. It can be seen that this application selects two forms of target multiplication and addition instructions to dynamically adapt to Taylor expansion based on the requirements of floating-point data operations; parses the table lookup index control signal and the multiplication and addition component switching signal in the instruction to generate index signals and switching signals, so as to further access the coefficient table through the table lookup index control signal, read single coefficients or double coefficients, and then dynamically switch the input paths of the source operand and the Taylor coefficient according to the multiplication and addition component switching signal to realize hardware multiplexing, without the need for multiple sets of independent circuits, reuse existing SIMD multipliers and adders, support dynamic bit width adjustment, and reduce chip area.

[0091] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram should not be considered as any limitation to the scope of application of the present application.

[0092] Figure 7 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the floating-point operation acceleration method based on a floating-point operation unit disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0093] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0094] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0095] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0096] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, enabling the processor 21 to operate and process the massive amounts of data 223 in the memory 22. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to including computer programs capable of implementing the floating-point unit-based floating-point operation acceleration method disclosed in any of the aforementioned embodiments and executed by the electronic device 20, the computer programs 222 may further include computer programs capable of performing other specific tasks. Data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0097] Furthermore, this application discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned floating-point operation unit-based floating-point operation acceleration method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0098] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0099] Professionals may further appreciate that the units and algorithmic steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory RAM (Random Access Memory), memory, read-only memory ROM (Read Only Memory), electrically programmable EPROM (Electrically Programmable Read Only Memory), electrically erasable programmable EEPROM (Electric Erasable Programmable Read Only Memory), registers, hard disk, removable disk, CD-ROM (Compact Disc-Read Only Memory), or any other form of storage medium known in the technical field.

[0100] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0101] The above is a detailed introduction to the solution provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A floating-point arithmetic unit for sine and cosine functions, characterized in that: It includes instruction fetch module, decoding module, table lookup module, coefficient table, dynamic switching module, and SIMD multiplication and addition component, among which, The instruction fetch module is configured to obtain a floating-point data operation requirement, select a target multiply-add instruction based on the floating-point data operation requirement, and send the target multiply-add instruction to the decoding module; The decoding module is used to parse and extract the table lookup index control signal and the multiplication and addition component switching signal in the target multiplication and addition instruction; The table lookup module is used to access the coefficient table according to the table lookup index control signal to read the corresponding target Taylor expansion coefficient; The dynamic switching module is used to switch the data operation path according to the multiplication and addition component switching signal; The SIMD multiplication-addition component is used to call the corresponding data operation path to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement, so as to output the operation result in the corresponding output format.

2. The floating-point arithmetic unit of the sine and cosine functions according to claim 1, wherein: The decoding module includes: a parsing unit, configured to parse an opcode, an immediate field, and a precision mode field of the target multiply-add instruction; a first extraction unit, configured to identify from the opcode whether the target multiply-add instruction is a preset single-coefficient multiply-add instruction or a preset double-coefficient multiply-add instruction, to obtain a corresponding instruction type; wherein the preset single-coefficient multiply-add instruction is a multiply-add instruction for calculating a nested iterative Taylor series term; and the preset double-coefficient multiply-add instruction is a multiply-add instruction for calculating a grouped Taylor series term; A second extraction unit, configured to extract an immediate value from the immediate value field; A third extraction unit is configured to extract a target precision from the precision mode field; wherein the target precision is half precision, single precision, or double precision; a first signal generating unit, configured to concatenate the sign bits of the immediate number and the source operand required for the floating-point data operation to generate a table lookup index control signal; A second signal generating unit is configured to generate a corresponding multiplication-addition component switching signal according to the instruction type; the multiplication-addition component switching signal includes a first multiplication-addition component switching signal and a second multiplication-addition component switching signal; The third signal generating unit is configured to generate a corresponding output format signal according to the target accuracy; wherein the output format signal includes a first output format signal, a second output format signal, and a third output format signal.

3. The floating-point arithmetic unit of the sine and cosine functions according to claim 1, wherein: The coefficient table is implemented based on a multi-port register stack and is used to pre-store 16 groups of Taylor expansion coefficients of sine and cosine functions.

4. The floating-point arithmetic unit of the sine and cosine functions according to claim 2, wherein: The dynamic switching module includes: a first switching unit, configured to switch the data operation path to a first data operation path according to a switching signal of the first multiplication and addition component; The second switching unit is configured to switch the data operation path to the second data operation path according to the second multiplication and addition component switching signal.

5. The floating-point operation unit of the sine and cosine functions according to claim 4, wherein: The SIMD multiplication and addition component includes: a first operation unit, configured to call the adder and the multiplier of the first data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient to obtain a new source operand, and jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding single target Taylor expansion coefficient until all Taylor series term operations are completed to obtain an initial floating-point data operation result; a second operation unit, configured to call the adder and the multiplier of the second data operation path to perform a multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, determine the next source operand as a new source operand according to the Taylor series term expansion order, jump to the step of performing the multiplication-addition operation on the absolute value of the source operand in the floating-point operation requirement and the corresponding two target Taylor expansion coefficients to obtain a partial operation result, until all Taylor series term operations are completed, and accumulate all the partial operation results to obtain an initial floating-point data operation result; The third operation unit is used to dynamically adjust the mantissa bit width of the initial floating-point data operation result according to the output format signal to obtain a target operation result in a corresponding format.

6. The floating-point operation unit of the sine and cosine functions according to claim 5, characterized in that: The second computing unit includes: a first adjustment unit, configured to adjust the mantissa bit width of the initial floating-point data operation result to 10 bits according to the first output format signal, so as to obtain a target operation result in a corresponding output format; A second adjustment unit is configured to adjust the mantissa bit width of the initial floating-point data operation result to 23 bits according to the second output format signal, so as to obtain a target operation result in a corresponding output format; The third adjustment unit is used to adjust the mantissa bit width of the initial floating-point data operation result to 52 bits according to the third output format signal to obtain a target operation result under the corresponding output format.

7. The floating-point operation unit of the sine and cosine functions according to claim 1, wherein: The coefficient table contains Taylor expansion coefficients arranged in index order and carrying positive and negative signs.

8. A floating-point operation acceleration method based on a floating-point operation unit, characterized in that: The floating-point arithmetic unit is a floating-point arithmetic unit according to any one of claims 1 to 7; wherein the method comprises: Obtaining floating-point data operation requirements, and selecting a target multiply-add instruction based on the floating-point data operation requirements; Parsing and extracting a table lookup index control signal and a multiplication-addition component switching signal in the target multiplication-addition instruction; Accessing a coefficient table according to the table lookup index control signal to read corresponding target Taylor expansion coefficients; Switching the data operation path according to the multiplication and addition component switching signal; The corresponding data operation path is called to perform floating-point data operation on the target Taylor expansion coefficient and the source operand in the floating-point data operation requirement to output the operation result in the corresponding output format.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the floating-point operation acceleration method based on a floating-point operation unit as claimed in claim 8.

10. A computer-readable storage medium, characterized in that Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the floating-point operation acceleration method based on a floating-point operation unit as claimed in claim 8 are implemented.

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