A re-timer

Abstract

The application relates to a re-timer, comprising an analog signal front-end processing module, a clock data recovery module, a clock trigger driving module, and further comprising: a phase control decision device, which is used for fixed-point sampling and decision of the processed analog signal based on an optimal sampling clock phase to obtain a digital signal, and scoring the reliability of each bit of the digital signal; a forward error correction decoding module, which is used for error correction and repair of the digital signal according to the score of the reliability of each bit of the digital signal to obtain a repaired digital signal; and the repaired digital signal is sent into the clock trigger driving module to be converted into an analog differential signal. The application integrates the forward error correction function in the re-timer, corrects the error code of the received code stream, avoids the uniform transmission of the error code to the receiving end, can efficiently process the error code, reduces the link delay, prolongs the transmission distance, and further improves the stability and reliability of the system.

Description

Technical Field

[0001] This invention relates to the fields of high-speed serial communication, integrated circuit design, digital signal processing and system fault tolerance, and in particular to a high-speed link retimer with self-healing capability. Background Technology

[0002] In the field of high-speed interconnection and data communication, PCI Express (PCIe), as a high-bandwidth, low-latency serial bus standard, is widely used in computing platforms, servers, and data centers. With the continuous increase in data rates, PCIe buses face problems such as decreased signal integrity and limited transmission distance in practical deployments. To address these issues, retimers have been introduced as link relay components to re-timing and reshaping high-speed signals, improving link transmission quality. However, traditional retimer designs are mostly fixed-function devices, lacking the ability to sense and adapt to operating states. Especially in long-distance transmission environments, they often struggle to effectively maintain transmission robustness when facing problems such as link degradation and increased bit error rates.

[0003] To address the aforementioned issues, a common solution is to use an enhanced retimer link architecture. This approach introduces multiple retimer devices with clock recovery and equalization capabilities into the physical channel to achieve long-distance, high-speed signal regeneration and transmission. Enhanced retimers typically integrate modules such as continuous-time linear equalizers (CTLE), decision feedback equalizers (DFE), or forward equalizers (FFE) to compensate for channel attenuation and inter-symbol interference, and combine this with clock data recovery (CDR) mechanisms for signal retiming, thereby maintaining transmission signal quality. This type of solution does not rely on high-order physical link modifications and has good protocol compatibility, thus it is widely used in high-speed interconnect scenarios, such as the interconnection between PCIe, Ethernet, and AI training platforms.

[0004] However, retimers essentially only have signal reconstruction capabilities and cannot correct erroneous data; once the link error exceeds the physical tolerance threshold, the system may still experience an outage. Furthermore, simply increasing the number of retimer nodes to extend the distance can lead to problems such as latency accumulation, increased power consumption, and system management complexity, limiting their effectiveness in longer-distance, high-error-rate environments.

[0005] Therefore, the existing technology has the following problems: Although enhanced retimer links can improve the signal transmission quality of long-distance physical channels to a certain extent, this solution still has several significant technical bottlenecks in practical applications. First, retimers essentially only have signal reconstruction and clock recovery capabilities, and cannot correct bit errors generated during transmission. This means that bit errors occurring on the link between the transmitter and the retimer cannot be corrected and can only be transmitted to the receiver for centralized processing, thus increasing the error correction burden on the receiver. Second, in order to ensure that the overall link bit error rate is within an acceptable range, the system usually needs to connect multiple retimer nodes in series in the line to compensate for signal loss step by step, but this will bring significant latency accumulation problems. In high-speed interconnect protocols such as PCIe, the link has strict requirements for end-to-end transmission latency. If the physical layer forwarding latency caused by retimers exceeds expectations, it may lead to link initialization failure or data transmission interruption. In addition, stacking retimer nodes will significantly increase system power consumption and hardware costs, and increase the overall management complexity of the link. Therefore, how to achieve both bit error correction and low-latency transmission without introducing multiple levels of retimers remains a key technical challenge in the design of current long-distance high-speed physical links. Summary of the Invention

[0006] The purpose of this invention is to provide a novel retimer architecture that can perform forward error correction and repair on signals, thereby improving the fault tolerance and single-segment transmission distance of the link, reducing link transmission latency, and improving link transmission efficiency.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A re-timer includes an analog signal front-end processing module for receiving analog signals from a preceding physical link and performing front-end processing on the analog signals to obtain a processed analog signal; a clock data recovery module connected to the analog signal front-end processing module for determining an optimal sampling clock phase based on the processed analog signal; and a clock trigger driving module for outputting analog differential signals to a subsequent physical link. The re-timer further includes:

[0009] A phase control decision unit is connected to the analog signal front-end processing module and the clock data recovery module, respectively. The phase control decision unit is used to perform fixed-point sampling and decision on the processed analog signal based on the optimal sampling clock phase to obtain a digital signal, and to score the reliability of each bit of the digital signal.

[0010] A forward error correction decoding module is connected to the phase control decision unit. The forward error correction decoding module is used to correct and repair the digital signal according to the confidence level score corresponding to each bit of the digital signal to obtain the repaired digital signal.

[0011] The clock-triggered driving module is connected to the forward error correction decoding module, and the repaired digital signal is sent to the clock-triggered driving module to be converted into the analog differential signal.

[0012] According to one embodiment of the present invention, the forward error correction decoding module includes one or more error correction and repair channels.

[0013] Preferably, the error correction and repair channel includes a data cache module for temporarily storing the digital signal and triggering error correction and repair when the number of bytes of the temporarily stored digital signal reaches a preset value, a confidence register for synchronously storing the confidence score corresponding to each bit of the digital signal, and a fast positioning and repair module for performing error correction and repair on the digital signal. The fast positioning and repair module is connected to the data cache module and the confidence register, respectively.

[0014] More preferably, the error correction channel includes two data cache modules that work alternately.

[0015] In a preferred embodiment, the data buffer module is configured with a counter for counting the flag bits in the digital signal.

[0016] Furthermore, the rapid location and repair module includes an integrated BCH or RS decoder.

[0017] Furthermore, in the rapid location and repair module, the BMA algorithm is used to generate a misalignment position polynomial for the digital signal, and Chien Search is run to find the error location. Then, the reliability score corresponding to each bit of the digital signal is combined to assist in error location. Finally, the Forney algorithm is used to complete byte repair.

[0018] In one embodiment, in the rapid location and repair module, the portion of the digital signal with the lower confidence score has a higher priority for error correction and repair.

[0019] Preferably, in the phase control decision unit, the reliability of each bit of the digital signal is scored based on the distance between the sampled value of the analog signal sampled at fixed points and the decision threshold. The closer the sampled value is to the decision threshold, the lower the reliability score.

[0020] More preferably, in the phase control decision device, the range of the distance between the sampled value and the decision threshold is divided into n intervals, where n is a positive integer greater than or equal to 2, and each interval corresponds to a confidence level score.

[0021] Preferably, the clock-triggered driving module is also connected to the phase control decision unit; when the forward error correction decoding module is not required, the phase control decision unit outputs the digital signal to the clock-triggered driving module, and the digital signal is converted into the analog differential signal in the clock-triggered driving module.

[0022] More preferably, during the training phase of the link where the retimer is located, it is determined whether to enable the forward error correction decoding module based on the rate supported by the link.

[0023] According to one embodiment of the present invention, the analog signal front-end processing module includes a continuous-time linear equalizer for compensating for channel loss of the analog signal, and a variable-gain amplifier for dynamically amplifying the compensated analog signal. The continuous-time linear equalizer is connected to the front-end physical link, and the variable-gain amplifier is connected to the continuous-time linear equalizer. The clock data recovery module and the phase control decision unit are respectively connected to the variable-gain amplifier. The analog signal front-end processing module also includes an adaptive engine module connected to the variable-gain amplifier and used for dynamically controlling the variable-gain amplifier.

[0024] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art: The present invention integrates the forward error correction function into the re-timer to correct the error of the received bit stream, avoids the uniform transmission of errors to the receiving end, can efficiently process errors, reduce link delay, extend transmission distance, and thus improve the stability and reliability of the system. Attached Figure Description

[0025] Appendix Figure 1 This is a schematic diagram of the architecture of the retimer of the present invention.

[0026] Appendix Figure 2 This is a schematic diagram of the top-level state switching and looping process in the re-timer of the present invention.

[0027] Appendix Figure 3 This is a flowchart illustrating the confidence synchronization process of the forward error correction decoding module in the retimer of this invention.

[0028] Appendix Figure 4 This is a flowchart illustrating the state transition of the fast positioning and repair module in the forward error correction decoding module of the retimer in this invention.

[0029] Appendix Figure 5 This is a schematic diagram of the link training fixed flag bit in the retimer of the present invention.

[0030] Appendix Figure 6 This is a schematic diagram of the link training enable signal in the retimer of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] Example 1: As shown in the attached document Figure 1 As shown, an enhanced retimer (a repairable retimer integrating forward error correction to improve the robustness of long-distance PCIe physical layer transmission) includes an analog signal front-end processing module, a clock data recovery module (CDR), a phase control decision unit (Slicer), a forward error correction decoding module (FEC Repair), and a clock triggered driver module. The analog signal front-end processing module is connected to the preceding physical link, the clock data recovery module is connected to the analog signal front-end processing module, the phase control decision unit is connected to both the analog signal front-end processing module and the clock data recovery module, the forward error correction decoding module is connected to the phase control decision unit, and the clock triggered driver module is connected to the clock data recovery module, the phase control decision unit, and the forward error correction decoding module. Based on the traditional retimer data path, the forward error correction decoding module is embedded into the retimer data path, forming a composite physical layer node with dual functions of signal retiming and error repair.

[0033] The analog signal front-end processing module receives analog signals from the preceding physical link and performs front-end processing on them to obtain a processed analog signal. In this embodiment, the analog signal front-end processing module includes a continuous-time linear equalizer (CTLE) connected to the preceding physical link and a variable-gain amplifier (VGA) connected to the CTLE. It also includes an adaptation engine module connected to both the CTLE and the VGA. The CTLE receives the high-speed waveform analog signal from the preceding physical link and compensates for the channel loss of the analog signal. The VGA dynamically amplifies the compensated analog signal to obtain the processed analog signal, adapting it to different channel environments. The VGA is dynamically controlled by the adaptation engine module, adjusting its gain response in real time.

[0034] The clock data recovery module is connected to a variable gain amplifier (VDA), which determines the optimal sampling clock phase based on the processed analog signal. The amplified analog signal is fed into the clock data recovery module, which recovers the optimal sampling clock phase according to the parameters of the link training phase where the retimer is located. The CDR clock signal containing this optimal sampling clock phase is then sent to the phase control decision unit and the clock trigger drive module, respectively.

[0035] The phase-controlled decision unit is connected to the variable gain amplifier and clock data recovery module in the analog signal front-end processing module. It performs fixed-point sampling and decision-making on the processed analog signal based on the optimal sampling clock phase to obtain a digital signal (digital bitstream), and simultaneously scores the confidence level (assimilarity) of each bit of the digital signal. In the phase-controlled decision unit, the confidence level of each bit of the digital signal is scored based on the distance between the sampled value (from the fixed-point sampling of the analog signal) and the decision threshold. The closer the sampled value is to the decision threshold (center line), the lower the confidence level score, and it is marked as "low confidence." The decision threshold is provided by the clock data recovery module, which detects whether the current sampled value is close to the decision threshold to determine its confidence level score.

[0036] The forward error correction decoding module is connected to the phase control decision unit and is used to correct and repair the digital signal based on the confidence score corresponding to each bit of the digital signal, so as to obtain the repaired digital signal.

[0037] The aforementioned forward error correction decoding module includes one or more error correction and repair channels. Specifically, each error correction and repair channel includes a data cache module (Fifo_1), a confidence register (Fifo_2), and a fast location and repair module (Repair_ctrl), wherein the fast location and repair module is connected to the data cache module and the confidence register, respectively. (See attached...) Figure 3 As shown, the data buffer module temporarily stores digital signals and triggers the fast location and repair module for error correction when the number of bytes of the temporarily stored digital signal reaches a preset value. The confidence register synchronously stores the confidence score corresponding to each bit of the digital signal, while the fast location and repair module performs error correction on the digital signal. The fast location and repair module includes an integrated BCH or RS decoder. The phase control decision unit performs fixed-point sampling and decision-making to obtain the digital signal, which is then stored in the data buffer module. The synchronously obtained confidence score is stored in the confidence register for reference by the subsequent fast location and repair module and can be uploaded to the software system for error analysis or link status awareness.

[0038] The data buffer module is equipped with a counter for counting the marker bits in the digital signal. After the decision, the digital signal enters the data buffer module of the forward error correction decoding module, which counts the marker bits at fixed positions in the data stream, identifies data frame boundaries, and writes the data into the data buffer module. Based on the preset value in the data buffer module and the position of the marker bits, the corresponding count value can be determined. In this embodiment, the preset value in the data buffer module is set to 544 bytes. When the data temporarily stored in the data buffer module reaches a complete 544-byte (FEC Block) (for example, there is a marker bit every 256 bits; counting the existing marker bits determines whether there is enough data), the error correction and repair logic of the fast location and repair module is triggered. After the fast location and repair module starts, it reads the 544-byte data in the data buffer module and the corresponding confidence score in the confidence register, performs the error correction process through the integrated BCH or RS decoder, locates and repairs recoverable errors. After repair, the data enters the subsequent transmission path.

[0039] The clock-triggered driver module is connected to the forward error correction decoding module, the phase control decision unit, and the clock data recovery module. The clock-triggered driver module outputs analog differential signals to the subsequent physical link. When the forward error correction decoding module is enabled, the digital signal repaired by the forward error correction decoding module is sent to the clock-triggered driver module and converted into an analog differential signal. When the forward error correction decoding module is not needed, the phase control decision unit outputs a digital signal to the clock-triggered driver module, which converts the digital signal into an analog differential signal. The clock-triggered driver module, combined with the CDR clock signal, converts the repaired digital signal or the original digital signal into an analog differential signal for output, which is then transmitted to the next-level retimer or target device.

[0040] The aforementioned enhanced retimer integrates a data processing control state machine with forward error correction (FEC) logic. Its purpose is to perform chunking, confidence marking, error detection, and repair on the received bit stream. This state machine module possesses complete state transition capabilities and response mechanisms, ensuring efficient and low-latency error repair in complex link environments.

[0041] The overall structure of the state machine is as follows:

[0042] IDLE: Idle state, the system waits for the phase control decision unit to output data and initializes the relevant registers;

[0043] ACCUMULATE: Data accumulation status. The data cache module's counter monitors the alignment flag and caches FECBlock data.

[0044] BLOCK_READY: The FEC cache block is filled and ready to call the FEC module for repair operations;

[0045] FEC_REPAIR: The fast location and repair module is being called to perform repair processing, and the repairable location is determined by combining the confidence register.

[0046] FORWARD: Repair complete or skip repair, forward data to the output driver and restore the next set of data.

[0047] As attached Figure 2 As shown, the state transition logic and conditions for a single FEC repair top-level module are explained below:

[0048] 1) IDLE → ACCUMULATE

[0049] Conditions: The phase control decision unit starts outputting a valid bit stream, and the valid enable signal from the phase control decision unit goes high (determining whether to enable the forward error correction decoding module).

[0050] Actions: Initialize the cache, clear the counters in the data cache module, and enable the confidence recording logic.

[0051] 2) IDLE → SEND

[0052] Condition: The valid signal is pulled low (this channel is not a PCIe 6.0 transmission and the forward error correction decoding module is not enabled).

[0053] Action: Directly transmit the valid bit stream output of the phase control decision unit (switch to backward compatible mode).

[0054] 3) ACCUMULATE → BLOCK_READY

[0055] Condition: The cumulative count of the counter in the data cache module reaches the preset FEC block length (e.g., 544 bytes).

[0056] Actions: Freeze the current cache contents, lock the confidence register; generate the Block_Ready signal.

[0057] 4) BLOCK_READY → FEC_REPAIR

[0058] Condition: The Block_Ready signal is high, and the fast location and repair module is idle;

[0059] Action: Quickly locate and repair the module, read cache and confidence information, and start the error correction decoder.

[0060] 5) FEC_REPAIR → FORWARD

[0061] Condition: The current fast location and repair module has completed the error correction process for the entire 544B data block or detected an "unrepairable error";

[0062] Action: Transfer the repaired bitstream to the output module and report any errors (if any).

[0063] 6) FORWARD → ACCUMULATE

[0064] Conditions: Data output complete, buffer cleared;

[0065] Action: Release the cache, reset the state machine, and enter the next data block acquisition cycle.

[0066] A confidence threshold mechanism is employed, meaning that in the rapid location and repair module, the lower the confidence score of the digital signal, the higher the priority for error correction and repair. In other words, low-confidence bits are processed and repaired first, significantly reducing the cycle time consumed by repair and thus lowering latency. If the confidence score of the entire data set is extremely low (all below a preset confidence value), the system can skip repair and mark the data block as "uncorrectable." This allows the receiver to choose to skip erroneous data blocks directly, accelerating retransmission.

[0067] A single data block transmission mechanism is adopted, that is, the error handling process in the enhanced retimer is uniformly scheduled by a set of state control mechanisms. Its core is to centrally repair the received 544-byte complete FEC Block data in combination with confidence information, and output it uniformly after the repair is completed.

[0068] Multi-threaded repair is supported, allowing multiple FEC blocks (i.e., multiple error correction and repair channels) to be processed in parallel. Taking a dual-channel setup as an example, alternating ping-pong operations during dual FEC repair avoid FEC block backlog. Since 544 bytes of data need to be registered for repair, subsequent data streams may need to wait; synchronized sending and repair improves efficiency. The state machine creates multiple repair channels to prevent BitsReam from getting stuck.

[0069] A dual-buffering mechanism (Ping-Pong Buffer) is adopted, meaning that each error correction channel includes two data buffer modules (Buffer A and Buffer B) that work alternately (alternating between receiving and sending data), as shown in the table below:

[0070]

[0071] For the single-threaded pre-repair and post-repair caches, a dual-buffer mechanism is designed. One cache receives data into a complete 544B data block, while the other cache is responsible for sending it, in order to reduce the latency caused by waiting for a single cache to fill a FECBlock.

[0072] An example state transition process for the forward error correction decoding module is as follows: Upon receiving a valid bit stream from the phase control decision unit in the IDLE state, the system immediately transitions to ACCUMULATE. The data buffer module's counter begins counting the flag bits, writing to the buffer for each valid bit received, until a total of 544 bytes are accumulated, generating a Block_Ready signal. At this point, the state transitions to FEC_REPAIR, and the decoder of the quick-locator repair module calls the confidence register, analyzing bit by bit which bits are repairable and which are not, and completing the corresponding repair process. After repair, the data is sent to the FORWARD state, the output module retransmits the data according to the clock drive, and the state returns to IDLE.

[0073] The confidence scoring mechanism and synchronization marker in the phase-controlled decision maker are as follows:

[0074] The phase-controlled decision unit employs a confidence scoring mechanism based on the distance between decision levels. As mentioned earlier, it scores the confidence level of each bit of the digital signal based on the distance between the sampled value of the analog signal obtained from fixed-point sampling and the decision threshold. Furthermore, the phase-controlled decision unit divides the range of distances between the sampled value and the decision threshold into n intervals, where n is a positive integer greater than or equal to 2. Each interval corresponds to a confidence level score. In this embodiment, four intervals are equally divided, each corresponding to a score. These intervals can be directly called upon during use, or they can be merged into two intervals for scoring according to actual needs. Higher signal complexity requires more intervals, and error correction is performed progressively from low to high scores. Interval analysis of the amplitude of the sampled instantaneous voltage generates corresponding confidence level flags. This confidence signal is synchronously buffered with the bit in the re-timer's internal buffer and serves as an important auxiliary basis for the subsequent FEC error correction module. This reduces the impact of increased end-to-end delay caused by FEC repair, improving error location capabilities, optimizing decoder performance, and enhancing link robustness. Flag detection involves determining whether the extracted voltage is close to the decision threshold and simultaneously storing the confidence level in the confidence register. Prioritizing flag identification for repair can significantly reduce branch attempts in the syndrome decoding search tree, improving repair speed and accuracy.

[0075] In the rapid location and repair module, the confidence level is extracted from the confidence register and repaired preferentially, as shown in the attached figure. Figure 4 As shown, the state machine transitions of its single FEC repair module are as follows:

[0076] IDLE: Waiting for the 544B buffer to fill (either the market bit count is full or the FIFO completion flag signal can be used to notify).

[0077] SYNDROME: Detects the presence and severity of errors;

[0078] LOCATE_ERR: Uses the BMA algorithm to generate a misalignment position polynomial for the digital signal and runs Chien Search to find the error location;

[0079] CONFIDENCE_AID: Combined with the confidence score of each bit of the digital signal, error-assisted localization (assisted filtering and repair bits) is performed.

[0080] CORRECT_ERR: Byte repair is performed using the Forney algorithm;

[0081] DONE: Outputs the repair block and resets the system state.

[0082] The aforementioned retimer is applied to the PCIe link. The PCIe link's handler or the vendor-defined negotiation mechanism used is as follows:

[0083] During the TS1 / TS2 training phase of PCIe link initialization, a field is inserted specifically for confirming the enhanced retimer capability. This allows both endpoints (receiver and transmitter) to synchronously confirm the long-distance link capability before the physical link is established, ensuring successful initialization and preventing link training failure. During the training phase of the link where the retimer resides, the decision to enable the forward error correction decoding module is determined based on the link's supported rate.

[0084] Before entering LTSSM training, a Vendor-defined negotiation message is proactively sent to the peer.

[0085] In the PCIe link initialization process, the TS1 / TS2 training sequence provides a low-level, hardware-level communication means for both ends of the link.

[0086] End-to-end confirmation of long-distance training capability (by adding a verdor_longrange long-distance transmission sublayer to the training layer to enable end-to-end confirmation of latency tolerance):

[0087] Insert a Vendor-defined field bit (LD_CAP) into the TS1 / TS2 training frames;

[0088] This field is located at a fixed byte offset in each frame (e.g., the 12th byte after the Marker Bit).

[0089] After the negotiation is completed, the receiver's status will be adjusted accordingly:

[0090] When both parties continuously exchange TS1 / TS2 during training, the LD_CAP bit of the peer frame is parsed.

[0091] If both sides set LD_CAP == 1, it confirms that the other end supports long-latency training;

[0092] Ensure the time required for long-distance transmission links.

[0093] The fixed position of the Marker Bit is trained to prevent it from going out of bounds. The Marker Bit is a frame header position marker obtained during the training phase by both ends of the link (transmitter and receiver) through TS1 / TS2 frame alignment, as shown in the attached figure. Figure 5As shown. Once training is complete, the sending and receiving ends, including the retimer, agree on "how many bits constitute a complete data frame", which allows subsequent data transmissions to be periodically aligned and parsed in the physical layer bitstream; the retimer only needs to count bits in the received digital signal, starting from the predetermined marker bit position (usually the first bit).

[0094] The aforementioned retimer employs a backward-compatible design and a retimer identification and switching mechanism. Because PCIe 6.0 introduces a mandatory FEC encoding mechanism (such as Reed-Solomon encoding) to support transmission rates up to 64 GT / s, which was not used in earlier versions (such as PCIe 5.0 / 4.0 / 3.0 / 2.0), therefore: the retimer cannot have the forward error correction decoding module enabled by default; if the peer device is an older version or does not support FEC, forced repair will result in stream corruption; and the decision to enable the FEC repair path must be dynamically determined based on the negotiation results during the link training phase.

[0095] 1. Training layer negotiation judgment

[0096] During the training phase (TS1 / TS2 frames), the receiver parses the device's Link Capabilities (found in the Link State Register in the PCIe 6.0 specification). If the Max Link Speed ​​field is 0110b, it indicates that the device supports and forcibly enables the PCIe 6.0 FEC repair mechanism. The process is as follows: (See attached) Figure 6 As shown, the received training frame is held by a shift register; the lower 4 bits of the offset 0Ch address (i.e., Max Link Speed) are extracted; a comparison module is designed to compare with 0110b. If they are equal, it indicates support for PCIe 6.0, and the FEC repair module is enabled.

[0097] 2. Signal notification

[0098] If the training layer learns that subsequent normal message frames do not support FEC, the forward error correction decoding module needs to be turned off. An enable flag can be set, and after the comparison module compares the bytes at a fixed position, if FEC is supported, the enable bit of the module is pulled high; otherwise, the enable bit is pulled low to ensure that subsequent working frames skip this module (the top-level SEND state) and are forwarded directly.

[0099] This invention adopts a modular integrated design, which integrates forward error correction function into the retimer and works in conjunction with a confidence-based bit error detection mechanism to achieve enhanced signal recovery and high fault-tolerant transmission for long-distance PCIe physical links.

[0100] First, this invention embeds a forward error correction (FEC) module into the retimer structure, enabling direct error correction of the received bitstream. This achieves local repair of errors in the front end of the physical link, avoiding the uniform transmission of errors to the receiving end. To improve processing efficiency, the integrated FEC module incorporates a low-latency error correction path and confidence judgment mechanism, which can quickly locate and repair correctable bits, reducing the impact of the error correction process on link latency.

[0101] Secondly, this invention employs a handshake mechanism based on the Vendor-defined mechanism during the link initialization phase to verify the capabilities of the peer device in long-distance links, ensuring that the link can still be established normally even in environments with significant differences in physical transmission capabilities, thereby improving the stability and reliability of the system.

[0102] Furthermore, this invention designs an automatic identification and switching mechanism between enhanced retimers and traditional retimers. Without compromising protocol compatibility, it can select the appropriate retimer working mode based on link capabilities, achieving broad compatibility with PCIe 6.0 and earlier versions.

[0103] In summary, this invention constructs a retimer enhancement system with repair capabilities through the coordinated work of FEC function integration, error confidence detection, link capability negotiation, and compatibility switching mechanism, providing a new implementation path for solving the problem of error accumulation and delay in long-distance transmission of PCIe physical layer.

[0104] Compared with existing technologies, this technical solution mainly solves the following technical problems:

[0105] 1. It realizes the error correction capability of bit error in the physical link before the re-timer, and improves the fault tolerance of the physical link and the single-segment transmission distance;

[0106] 2. Significantly reduced the number of timers, lowered link transmission latency, and improved overall system transmission efficiency;

[0107] 3. It ensures the reliability of end-to-end negotiation in long-distance physical links, avoiding link initialization failures or loss issues;

[0108] 4. Protocol compatibility and automatic identification switching between enhanced retimers and traditional retimers have been achieved, improving the system's adaptability and stability.

[0109] Compared with existing technologies, the beneficial effects of this technical solution are as follows:

[0110] 1. Enhanced Transmission Distance and Fault Tolerance: This invention integrates FEC functionality into the retimer, enabling real-time error correction of the link front-end without relying on the main control or protocol stack. This effectively improves the error tolerance of the physical link, significantly extending the transmission distance of each link segment. Compared to traditional retimer structures that can only retime, this solution significantly enhances the link's self-healing capability and signal integrity assurance.

[0111] 2. Reduced Link Latency and Re-timer Deployment Complexity: This invention reduces the number of re-timers required in a link by introducing an error correction mechanism into a single re-timer, thereby effectively reducing the overall system's forwarding latency and link initialization time. It also reduces system wiring complexity and power consumption. Compared to traditional multi-hop re-timer schemes, this solution performs better in terms of low latency and high stability.

[0112] 3. Improved Link Reliability and Negotiation Stability: This invention introduces a PCIe Vendor-defined mechanism to confirm the capabilities of the peer during the link initialization phase, avoiding negotiation failures or link loss due to excessive link length. This mechanism improves the system's compatibility and initialization success rate in complex physical environments, ensuring the predictability and maintainability of the link.

[0113] 4. Enhanced protocol compatibility and adaptability: This invention designs an automatic identification and switching mechanism between the enhanced retimer and the traditional retimer, which can support versions below PCIe 6.0 without affecting protocol compatibility, achieve seamless adaptation to devices with multiple generations of protocols, and enhance the system integration flexibility and backward compatibility of the product.

[0114] In summary, compared with existing technologies, this technical solution has significant advantages in improving transmission distance and fault tolerance, reducing link latency and system deployment complexity, enhancing link reliability, and improving protocol compatibility.

[0115] Due to its advanced nature, this technical solution has wide applications in high-speed interconnect systems, data center servers, embedded control, and intelligent vehicles. 1) High-speed interconnect systems: This technical solution proposes a mechanism that integrates FEC error correction and confidence assessment into a retimer, effectively improving the link reliability of PCIe 6.0 and above in long-distance, high-speed transmission. Its ability to support real-time error correction and suppression significantly reduces link interruption probability and retransmission overhead, making it particularly suitable for high-speed interconnect systems such as AI computing platforms, high-speed GPU interconnects, and SerDes architecture optimization. 2) Data centers and servers: In high-performance computing and storage environments, link error rate and relay node reliability are crucial for stable system operation. This technical solution uses a hardware-level FEC mechanism to perform real-time repair of physical link errors, reducing system interruptions and software overhead, thereby improving overall system performance and throughput, and is particularly suitable for data transmission over PCIe 6.0 links. 3) Embedded Systems and Industrial Control: Due to its hardware-independent error correction, low power consumption, and high fault tolerance, this technology is well-suited for deployment in resource-constrained embedded control scenarios, such as robots, smart terminals, and industrial equipment. It effectively resists the impact of environmental noise on communication quality and improves data link stability. 4) Smart Cars and In-Vehicle Networks: This technical solution supports a confidence-driven error correction mechanism, enhancing the fault tolerance of in-vehicle links. It ensures information communication security in high-speed in-vehicle Ethernet and multi-link converged environments, meeting automotive-grade stability and functional safety requirements. In summary, this technical solution, through a repairable retimer architecture, provides a hardware-level solution with real-time recovery capabilities for high-speed, high-error-rate, and high-latency links. It has broad application prospects in key scenarios such as servers, data centers, high-end interconnects, smart industries, and in-vehicle platforms, meeting the comprehensive requirements of next-generation high-speed communication for reliability, compatibility, and performance.

[0116] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A re-timer, comprising an analog signal front-end processing module for receiving an analog signal from a preceding physical link and performing front-end processing on the analog signal to obtain a processed analog signal, a clock data recovery module connected to the analog signal front-end processing module for determining an optimal sampling clock phase based on the processed analog signal, and a clock trigger driving module for outputting an analog differential signal to a subsequent physical link, characterized in that: The re-timer also includes: A phase control decision unit is connected to the analog signal front-end processing module and the clock data recovery module, respectively. The phase control decision unit is used to perform fixed-point sampling and decision on the processed analog signal based on the optimal sampling clock phase to obtain a digital signal, and to score the reliability of each bit of the digital signal. A forward error correction decoding module is connected to the phase control decision unit. The forward error correction decoding module is used to correct and repair the digital signal according to the confidence level score corresponding to each bit of the digital signal to obtain the repaired digital signal. The clock-triggered driving module is connected to the forward error correction decoding module. The repaired digital signal is sent to the clock-triggered driving module and converted into the analog differential signal. The clock-triggered driving module is also connected to the phase control decision unit. When the forward error correction decoding module is not required, the phase control decision unit outputs the digital signal to the clock-triggered driving module, and the digital signal is converted into the analog differential signal in the clock-triggered driving module. During the training phase of the link where the retimer is located, it is determined whether to enable the forward error correction decoding module based on the rate supported by the link.

2. The re-timer according to claim 1, characterized in that: The forward error correction decoding module includes one or more error correction and repair channels.

3. The re-timer according to claim 2, characterized in that: The error correction and repair channel includes a data cache module for temporarily storing the digital signal and triggering error correction and repair when the number of bytes of the temporarily stored digital signal reaches a preset value, a confidence register for synchronously storing the confidence score corresponding to each bit of the digital signal, and a fast positioning and repair module for performing error correction and repair on the digital signal. The fast positioning and repair module is connected to the data cache module and the confidence register, respectively.

4. The re-timer according to claim 3, characterized in that: The error correction and repair channel includes two data caching modules that work alternately.

5. The re-timer according to claim 3, characterized in that: The data buffer module is configured with a counter for counting the flag bits in the digital signal.

6. The re-timer according to claim 3, characterized in that: The rapid location and repair module includes an integrated BCH or RS decoder.

7. The re-timer according to claim 3, characterized in that: In the rapid location and repair module, the BMA algorithm is used to generate a misalignment position polynomial for the digital signal, and Chien Search is run to find the error location. Then, the reliability score corresponding to each bit of the digital signal is combined to assist in error location. Finally, the Forney algorithm is used to complete byte repair.

8. The re-timer according to claim 3, characterized in that: In the rapid positioning and repair module, the portion of the digital signal with the lower the confidence level score has a higher priority for error correction and repair.

9. The re-timer according to claim 1, characterized in that: In the phase-controlled decision unit, the reliability of each bit of the digital signal is scored based on the distance between the sampled value of the analog signal sampled at fixed points and the decision threshold. The closer the sampled value is to the decision threshold, the lower the reliability score.

10. The re-timer according to claim 9, characterized in that: In the phase control decision device, the range of the distance between the sampled value and the decision threshold is divided into n intervals, where n is a positive integer greater than or equal to 2, and each interval corresponds to a confidence level score.

11. The re-timer according to claim 1, characterized in that: The analog signal front-end processing module includes a continuous-time linear equalizer for compensating the channel loss of the analog signal and a variable gain amplifier for dynamically amplifying the compensated analog signal. The continuous-time linear equalizer is connected to the front-end physical link, and the variable gain amplifier is connected to the continuous-time linear equalizer. The clock data recovery module and the phase control decision unit are respectively connected to the variable gain amplifier.

12. The re-timer according to claim 11, characterized in that: The analog signal front-end processing module also includes an adaptive engine module connected to the variable gain amplifier and used for dynamically controlling the variable gain amplifier.

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