Pixel driving circuit, driving method thereof and display panel

Abstract

The invention provides a pixel driving circuit, a driving method thereof and a display panel, and belongs to the technical field of display. The pixel driving circuit comprises a driving transistor which is connected with a first node and a third node and is used for controlling the magnitude of driving current under the control of voltage on a second node; the driving transistor is a metal oxide transistor; the data writing unit is used for responding to a first scanning signal to load data voltage to a third node; the threshold compensation unit is used for making the second node and the first node electrically conducted in response to a grid reset control signal; the first light emitting control unit is used for responding to a light emitting control signal to load the driving power supply voltage to the first node; the second light-emitting control unit is used for responding to the light-emitting control signal to enable the third node and the fourth node to be electrically conducted; the storage capacitor is connected with the second node and the fourth node; the fourth node is used for connecting a light-emitting element. The pixel driving circuit can reduce the power consumption of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] With the development of information technology, the market for display devices, which serve as a medium connecting users to information, has continued to grow. Display devices such as quantum dot displays (QDDs), liquid crystal displays (LCDs), and organic light-emitting diode (OLED) displays have been increasingly used.

[0003] In the field of display technology, the demand for low power consumption is growing stronger and stronger. Especially for mobile display terminals, low-power display devices can significantly improve the terminal's battery life. Therefore, it is necessary to continue to develop display technologies with lower power consumption.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a pixel driving circuit and a driving method thereof, and a display panel, so as to reduce the power consumption of the display panel.

[0006] According to one aspect of the present disclosure, there is provided a pixel driving circuit, comprising:

[0007] a driving transistor connected to the first node and the third node, and configured to control the magnitude of the driving current under the control of the voltage on the second node; the driving transistor being a metal oxide transistor;

[0008] a data writing unit, configured to load a data voltage onto the third node in response to a first scanning signal;

[0009] a threshold compensation unit, configured to enable electrical conduction between the second node and the first node in response to a gate reset control signal;

[0010] a first light emitting control unit, configured to load a driving power supply voltage to the first node in response to a light emitting control signal;

[0011] a second light emitting control unit, configured to enable electrical conduction between the third node and the fourth node in response to the light emitting control signal;

[0012] a storage capacitor connected to the second node and the fourth node;

[0013] The fourth node is used to connect the light emitting element.

[0014] According to one embodiment of the present disclosure, the pixel driving circuit also includes a first reset unit; the first end of the first reset unit is used to load a first voltage, the second end of the first reset unit is directly or indirectly connected to the second node, and the control end of the first reset unit is used to respond to a first reset control signal to be turned on and enable the first voltage to be directly or indirectly loaded to the second node.

[0015] According to an embodiment of the present disclosure, the second end of the first reset unit is electrically connected to the first node or the second node.

[0016] According to an embodiment of the present disclosure, the first voltage is a first initialization voltage or a driving power supply voltage.

[0017] According to an embodiment of the present disclosure, the first reset unit includes a plurality of first reset transistors connected in series, and the first reset transistors are low-temperature polysilicon transistors; or, the first reset unit includes one first reset transistor, and the first reset transistor is a metal oxide transistor.

[0018] According to one embodiment of the present disclosure, the pixel driving circuit also includes a second reset unit; the first end of the second reset unit is used to load a second initialization voltage, the second end of the second reset unit is electrically connected to the fourth node, and the control end of the second reset unit is used to be turned on in response to a second reset control signal.

[0019] According to an embodiment of the present disclosure, the second reset unit has one or more second reset transistors; the second reset transistors are low-temperature polysilicon transistors, and the gates of the second reset transistors are used to load the second reset control signal.

[0020] According to one embodiment of the present disclosure, the second reset unit includes one or more second reset transistors, and the second light emitting control unit includes one or more second light emitting control transistors; the transistor type of the second reset transistor is opposite to the transistor type of the second light emitting control transistor; the second reset control signal and the light emitting control signal are the same control signal;

[0021] According to one embodiment of the present disclosure, the second reset unit has one or more second reset transistors, and the threshold compensation unit has one or more threshold compensation transistors; the transistor type of the second reset transistor is the same as the transistor type of the threshold compensation transistor; the second reset control signal and the gate reset control signal are the same control signal.

[0022] According to an embodiment of the present disclosure, the driving transistor has a bottom gate and a top gate, the bottom gate of the driving transistor is electrically connected to the third node, and the top gate of the driving transistor is electrically connected to the second node.

[0023] According to an embodiment of the present disclosure, the data writing unit includes a data writing transistor having a top gate and a bottom gate; the bottom gate and the top gate of the data writing transistor are both used to load the first scanning signal.

[0024] According to an embodiment of the present disclosure, the threshold compensation unit includes a threshold compensation transistor having a top gate and a bottom gate; both the bottom gate and the top gate of the threshold compensation transistor are used to load a gate reset control signal.

[0025] According to an embodiment of the present disclosure, the first light emitting control unit includes a plurality of first light emitting control transistors connected in series, and a gate of each of the first light emitting control transistors is used to load the light emitting control signal.

[0026] According to a second aspect of the present disclosure, a driving method of the above-mentioned pixel driving circuit is provided, comprising:

[0027] In the data writing phase, the first scanning signal and the gate reset control signal are applied to the pixel driving circuit so that the data voltage is written into the second node;

[0028] In the light emitting stage, a light emitting control signal is applied to the pixel driving circuit, so that the pixel driving circuit outputs a driving current to the light emitting element according to the voltage on the second node.

[0029] According to a third aspect of the present disclosure, a display panel is provided, comprising display units arranged in an array, wherein the display units include the above-mentioned pixel driving circuit and light-emitting elements driven by the pixel driving circuit.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0032] Figure 1FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0033] Figure 2 Schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0034] Figure 3-1 Schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0035] Figure 3-2 Schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0036] Figure 4 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0037] Figure 5 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0038] Figure 6 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0039] Figure 7 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0040] Figure 8 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0041] Figure 9 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0042] Figure 10 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0043] Figure 11 FIG1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0044] Figure 12 FIG. 4 is another driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0045] Figure 13 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0046] Figure 14 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0047] Figure 15 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0048] Figure 16 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0049] Figure 17 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0050] Figure 18 FIG. 1 is a driving timing diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0051] Figure 19 1 is an equivalent circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0052] Figure 20 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0054] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0055] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0056] In the embodiment of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor.

[0057] In an embodiment of the present disclosure, at least part of the signal has a high level and a low level; one of the high level and the low level can be used as the on-level of the signal, and the on-level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the off-level of the signal, and the off-level of the signal can turn off the controlled transistor. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its on-level is a low level, and its off-level is a high level. For another example, for a signal that controls an N-type transistor (the signal can be loaded to the control terminal of the N-type transistor), its on-level is a high level, and its off-level is a low level.

[0058] In the embodiments of the present disclosure, unless otherwise specified, loading a signal to a transistor or a unit including a transistor refers to loading the conduction level of the signal to the transistor or the unit including the transistor.

[0059] In the embodiments of the present disclosure, unless otherwise specified, the low-temperature polysilicon transistor is a P-type transistor, and the metal oxide transistor is an N-type transistor.

[0060] Embodiments of the present disclosure provide a pixel driving circuit PDC and a display panel PNL using the pixel driving circuit PDC, so as to reduce power consumption of the display panel PNL.

[0061] See also Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with an array of display units DU, each of which includes subpixels PX and a pixel driving circuit PDC that drives the subpixels PX. The display panel PNL does not have display units DU in the peripheral area BB, or the display units DU provided are not used for displaying images.

[0062] In one example, see Figure 1 The display panel PNL is provided with a plurality of scan lines GL extending along the row direction DH in the display area AA, and each scan line GL is provided in a one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, and each data line DL is provided in a one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to a scan line GL and a data line DL. The scan line GL is used to control whether the data writing transistor of the pixel driving circuit PDC is turned on or off, and the data line DL is used to load the pixel driving circuit PDC with a data voltage.

[0063] Accordingly, in this example, the pixel driving circuits PDC are arranged into a plurality of driving circuit rows and a plurality of driving circuit columns.

[0064] It is understandable that in some other embodiments of the present disclosure, the display panel PNL has other structures, such as a special-shaped structure or having openings, or the pixel driving circuit PDC has different distribution densities in different areas.

[0065] Optionally, the sub-pixel PX may be a current-driven self-luminous light-emitting element, for example, any one of OLED, PLED, QLED, Micro LED, Mini LED, etc. In one example, the sub-pixel PX is an OLED.

[0066] Figure 2 FIG. 1 is a structural diagram of a pixel driving circuit PDC in one embodiment of the present disclosure.

[0067] See also Figure 2 , the pixel driving circuit PDC includes:

[0068] a driving transistor T3 connected to the first node N1 and the third node N3, and configured to control the magnitude of the driving current under the control of the voltage on the second node N2; the driving transistor T3 is a metal oxide transistor;

[0069] a data writing unit M4, configured to respond to a first scan signal and load a data voltage to the third node N3;

[0070] a threshold compensation unit M2, configured to enable electrical conduction between the second node N2 and the first node N1 in response to a gate reset control signal ResetN;

[0071] a first light emitting control unit M5, configured to load a driving power supply voltage VDD to the first node N1 in response to a light emitting control signal EM;

[0072] a second light emitting control unit M6, configured to make the third node N3 and the fourth node N4 electrically connected in response to the light emitting control signal EM;

[0073] a storage capacitor Cst, connected to the second node N2 and the fourth node N4;

[0074] The fourth node N4 is used to connect to the light emitting element LD.

[0075] The pixel driving circuit PDC can be driven by the following driving method:

[0076] In the data writing phase, a first scanning signal and a gate reset control signal ResetN are applied to the pixel driving circuit PDC to turn on the data writing unit M4 and the threshold compensation unit M2, thereby writing the data voltage Vdata and the threshold voltage of the driving transistor T3 into the second node N2;

[0077] In the light emitting stage, a light emitting control signal EM is applied to the pixel driving circuit PDC, so that the driving transistor T3 generates a driving current under the control of the voltage on the second node N2, and the driving current drives the light emitting element LD to emit light.

[0078] The driver transistor T3 of the pixel driver circuit (PDC) provided in the present disclosure is a metal oxide transistor. Compared to low-temperature polysilicon transistors, this metal oxide transistor has a smaller source-drain voltage difference when generating the same drive current (i.e., the metal oxide transistor has a smaller voltage drop across the transistor). This reduces the power consumption of the driver transistor T3 during the light-emitting phase, thereby reducing the overall power consumption of the pixel driver circuit (PDC). Furthermore, this reduces the voltage requirement for the driver power supply voltage (VDD), thereby reducing the power consumption of the driver power supply voltage (VDD) routing and the power manager.

[0079] In the embodiments of the present disclosure, "applying a signal to a pixel driver circuit PDC" refers to applying a conduction level of the signal to the pixel driver circuit PDC, which can turn on a unit or transistor controlled by the signal. Accordingly, "a transistor or unit responding to a signal" refers to turning on the transistor or unit when the conduction level of the signal is applied to the transistor or unit.

[0080] Generally, a signal can have a high level and a low level. One of the high level and the low level can turn on the unit or transistor controlled by the signal (the level is called the on-level of the signal), and the other can turn off the unit or transistor controlled by the signal (the level is called the off-level of the signal). For example, the gate of a P-type transistor is used to load the A signal. Loading the A signal to the P-type transistor means loading the low level of the A signal to the gate of the P-type transistor (making the P-type transistor turned on), and not loading the A signal to the P-type transistor means loading the high level of the A signal to the gate of the P-type transistor (making the P-type transistor turned off). For another example, the gate of an N-type transistor is used to load the B signal. Loading the B signal to the N-type transistor means loading the high level of the B signal to the gate of the N-type transistor (making the N-transistor turned on), and not loading the B signal to the N-transistor means loading the low level of the B signal to the gate of the N-type transistor (making the N-transistor turned off).

[0081] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The first electrode of the driving transistor T3 is electrically connected to the third node N3, the second electrode of the driving transistor T3 is electrically connected to the first node N1, and the gate of the driving transistor T3 includes a bottom gate and a top gate, the bottom gate is electrically connected to the third node N3, and the top gate is electrically connected to the second node N2.

[0082] In this manner, the driving transistor T3 has a top gate and a bottom gate. The top and bottom gates can simultaneously apply voltage to the channel region of the driving transistor T3, thereby increasing the on-current of the driving transistor T3. This not only meets the current demand of driving the light-emitting element LD, but also helps reduce the power consumption of the driving transistor T3 itself. Furthermore, the simultaneous application of voltage to the top and bottom gates of the driving transistor T3 helps eliminate surface defects in the channel region of the driving transistor T3. This not only improves the uniformity of the driving transistors T3 in different pixel driving circuits PDC on the display panel PNL, but also further reduces the impedance of the driving transistor T3 when it is on, further reducing the power consumption of the driving transistor T3. Furthermore, the simultaneous application of voltage to the channel region of the driving transistor T3 by the top and bottom gates can increase the switching speed of the driving transistor T3 between the on-state and the off-state, thereby increasing the conduction rate during the light-emitting phase, thereby ensuring the uniformity of the light-emitting time of each light-emitting element LD and improving the display quality of the display panel PNL. More importantly, by increasing the conduction speed and on-state current of the driving transistor T3, the pixel driving circuit PDC has the potential to be applied to a high refresh rate display panel PNL, thereby enabling the display panel PNL to have the potential to reduce power consumption at a high refresh rate.

[0083] exist Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 In the example shown in FIG1 , the top gate of the driving transistor T3 is connected to the second node N2, and the bottom gate is connected to the third node N3. It is understood that in other embodiments of the present disclosure, the top gate and bottom gate of the driving transistor T3 may also be connected in other ways. For example, the top gate of the driving transistor T3 is connected to the third node N3, and the bottom gate of the driving transistor T3 is connected to the second node N2. For another example, both the top gate and the bottom gate of the driving transistor T3 are connected to the second node N2.

[0084] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The data writing unit M4 includes a data writing transistor T4; a first electrode of the data writing transistor T4 is electrically connected to a data voltage terminal for loading a data voltage Vdata, a gate of the data writing transistor T4 is electrically connected to a first scanning signal terminal for loading a first scanning signal, and a second electrode of the data writing transistor T4 is electrically connected to a third node N3.

[0085] In an example, the data writing transistor T4 is a low-temperature polysilicon transistor to ensure that the data writing transistor T4 has a faster turn-on speed and a larger turn-on current.

[0086] In one example, the gate of the data write transistor T4 includes a bottom gate and a top gate, both of which are electrically connected to the first scan signal terminal. This further increases the conduction speed and on-state current of the data write transistor T4. This not only helps improve the charging rate of the pixel drive circuit PDC, but also helps the pixel drive circuit PDC increase its refresh rate when needed, avoiding the problem of insufficient charging rate caused by shortened data write time due to the increased refresh rate. This further enhances the potential of the pixel drive circuit PDC for application in high refresh rate display panels PNL.

[0087] In one example, the data writing unit M4 includes only one data writing transistor T4 .

[0088] It is understood that in other embodiments of the present disclosure, the data write unit M4 may also be implemented in other ways. For example, the data write unit M4 includes multiple data write transistors T4, and the data write transistors T4 are low-temperature polysilicon transistors. For another example, the data write unit M4 includes one data write transistor T4, and the data write transistor T4 is a metal oxide transistor.

[0089] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The threshold compensation unit M2 includes a threshold compensation transistor T2; a first electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, a second electrode of the threshold compensation transistor T2 is electrically connected to the second node N2, and a gate of the threshold compensation transistor T2 is electrically connected to a gate reset control signal terminal for loading a gate reset control signal ResetN.

[0090] In one example, the threshold compensation transistor T2 is a metal oxide transistor to ensure that the threshold compensation transistor T2 has a low leakage current. During the light-emitting phase, the threshold compensation transistor T2 is turned off and has a low leakage current, which helps maintain the voltage of the second node N2. In this way, the pixel driver circuit PDC can operate at a lower refresh rate, for example, a refresh rate of 1 to 30 Hz, which can further reduce the power consumption of the pixel driver circuit PDC.

[0091] In one example, the gate of the threshold compensation transistor T2 includes a bottom gate and a top gate, both of which are electrically connected to the gate reset control signal terminal. On the one hand, this can further reduce the leakage current of the threshold compensation transistor T2 in the off state, further extend the voltage holding time of the second node N2, and further enhance the application potential of the pixel drive circuit PDC in low refresh rate display panels. On the other hand, the top gate and bottom gate of the threshold compensation transistor T2 simultaneously apply gate voltage to the channel region of the threshold compensation transistor T2, which can increase the conduction rate and maximum on-state current of the threshold compensation transistor T2 when it is turned on, especially during the data writing phase, to ensure the charging efficiency of the second node N2 and improve the charging rate of the pixel drive circuit PDC. In this way, the threshold compensation transistor T2 will not affect the application potential of the pixel drive circuit PDC in high refresh rate display panels PNL.

[0092] In one example, the threshold compensation unit M2 includes only one threshold compensation transistor T2.

[0093] It is understood that in some other embodiments of the present disclosure, the threshold compensation unit M2 may also be implemented in other ways. For example, the threshold compensation unit M2 includes two threshold compensation transistors T2 connected in series. For another example, the threshold compensation transistor T2 is a low-temperature polysilicon transistor.

[0094] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19The first electrode of the driving transistor T3 is electrically connected to the third node N3, the second electrode of the driving transistor T3 is electrically connected to the first node N1, the gate of the driving transistor T3 includes a bottom gate and a top gate, and at least one of the top gate and the bottom gate of the driving transistor T3 is electrically connected to the second node N2; for example, the bottom gate of the driving transistor T3 is connected to the third node N3 and the top gate of the driving transistor T3 is connected to the second node N2, or the bottom gate of the driving transistor T3 is connected to the second node N2 and the top gate of the driving transistor T3 is connected to the first node N1, or both the bottom gate and the top gate of the driving transistor T3 are connected to the second node N2. The data writing unit M4 includes a data writing transistor T4, which is a low-temperature polysilicon transistor; the gate of the data writing transistor T4 includes a bottom gate and a top gate, and both the bottom gate and the top gate are electrically connected to the first scanning signal terminal. The threshold compensation unit M2 includes a threshold compensation transistor T2, which is a metal oxide transistor; the gate of the threshold compensation transistor T2 includes a bottom gate and a top gate, and both the bottom gate and the top gate are electrically connected to the gate reset control signal terminal.

[0095] In this way, the pixel driver circuit PDC can adapt to both high and low refresh rate drive modes, making it suitable for a wide range of scenarios. In particular, when the display panel PNL has a variable refresh rate function, the pixel driver circuit PDC has a high upper limit and a low lower limit for the refresh rate, which is conducive to further improving the performance of the display panel PNL.

[0096] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The first light-emitting control unit M5 includes two first light-emitting control transistors T5 connected in series. The first electrode of the first first light-emitting control transistor T5 is electrically connected to a driving power supply voltage terminal for applying a driving power supply voltage VDD, the second electrode of the first first light-emitting control transistor T5 is electrically connected to the first electrode of the second first light-emitting control transistor T5, and the second electrode of the second first light-emitting control transistor T5 is electrically connected to a first node N1. The gates of both first light-emitting control transistors T5 are electrically connected to a light-emitting control signal terminal for applying a light-emitting control signal EM. In this way, during the non-light-emitting phase, the leakage current of the first light-emitting control unit M5 is low, which can reduce the power consumption caused by leakage current in the first light-emitting control unit M5 and reduce the power consumption of the pixel driving circuit PDC.

[0097] In an example, the first light emission control transistor T5 is a low-temperature polysilicon transistor to ensure that the first light emission control transistor T5 has a faster turn-on speed and a larger turn-on current.

[0098] It is understood that in other embodiments of the present disclosure, the first light-emitting control unit M5 may also be implemented in other ways. For example, the first light-emitting control unit M5 includes a first light-emitting control transistor T5, and the first light-emitting control transistor T5 is a low-temperature polysilicon transistor. For another example, the first light-emitting control unit M5 includes a first light-emitting control transistor T5, and the first light-emitting control transistor T5 is a metal oxide transistor; further, the first light-emitting control transistor T5 has a top gate and a bottom gate, and the top gate and the bottom gate are both electrically connected to the light-emitting control signal terminal.

[0099] In one embodiment of the present disclosure, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The second light-emission control unit M6 includes a second light-emission control transistor T6. A first electrode of the second light-emission control transistor T6 is electrically connected to the third node N3, a second electrode of the second light-emission control transistor T6 is electrically connected to the fourth node N4, and a gate of the second light-emission control transistor T6 is electrically connected to a light-emission control signal terminal for applying the light-emission control signal EM. The second light-emission control transistor T6 and the first light-emission control transistor T5 are of the same transistor type to ensure that both are controlled by the light-emission control signal EM, thereby reducing the number of wirings on the display panel PNL.

[0100] In one example, the second light-emitting control unit M6 includes only one second light-emitting control transistor T6, and the second light-emitting control transistor T6 is a low-temperature polysilicon transistor. In this way, the number of transistors can be reduced while ensuring that the conduction current of the second light-emitting control transistor T6 is sufficiently large, thereby saving layout area.

[0101] It is understood that in other embodiments of the present disclosure, the second light-emitting control unit M6 may also be implemented in other ways. For example, the second light-emitting control unit M6 includes a second light-emitting control transistor T6, and the second light-emitting control transistor T6 is a metal oxide transistor; further, the second light-emitting control transistor T6 has a top gate and a bottom gate, and the top gate and the bottom gate are both electrically connected to the light-emitting control signal terminal.

[0102] In one embodiment of the present disclosure, see Figure 3-1 and Figure 3-2The pixel driving circuit PDC further includes a first reset unit M1, which is used to reset the second node N2 in a reset phase (before a data writing phase) so that the driving transistor T3 is in a turned-on state.

[0103] Optionally, the first reset unit M1 is configured to apply a first voltage V1 to the second node N2 in response to a first reset control signal Reset1, thereby turning on the driving transistor T3. Specifically, a first terminal of the first reset unit is electrically connected to a first voltage terminal for applying the first voltage V1, a control terminal of the first reset unit is electrically connected to a first reset control signal terminal for applying the first reset control signal Reset1, and a second terminal of the first reset unit is directly or indirectly electrically connected to the second node N2.

[0104] Alternatively, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The first voltage V1 can be the first initialization voltage Vinit1 or the driving power supply voltage VDD, that is, the first end of the first reset unit is electrically connected to the first initialization voltage end for loading the first initialization voltage Vinit1, or is electrically connected to the driving power supply voltage end for loading the driving power supply voltage VDD.

[0105] For example, see Figure 4 、 Figure 8 、 Figure 15 and Figure 17 The first voltage V1 is the driving power supply voltage VDD. In this way, the number of power supplies on the display panel PNL can be reduced.

[0106] For another example, see Figure 6 、 Figure 10 、 Figure 13 and Figure 19 The first voltage V1 is the first initialization voltage Vinit1. This can reduce the load of the driving power supply voltage VDD, thereby improving the uniformity of the driving power supply voltage VDD and thus improving the uniformity of the display panel PNL. Furthermore, the voltage of the first initialization voltage Vinit1 can be optimized specifically based on the reset requirement of the second node N2, thereby reducing the magnitude of the voltage required to reset the second node N2 and, in turn, reducing the power consumption of the pixel driving circuit PDC and the display panel PNL.

[0107] Alternatively, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The second end of the first reset unit can be electrically connected to the first node N1 or the second node N2. When the second end of the first reset unit is electrically connected to the first node N1, during the reset phase, the threshold compensation unit M2 needs to be synchronously turned on so that the first voltage V1 is written to the second node N2 via the first reset unit M1 and the threshold compensation unit M2. When the second end of the first reset unit is electrically connected to the second node N2, the state of the threshold compensation unit M2 is not required during the reset phase.

[0108] For example, see Figure 3-1 、 Figure 4 、 Figure 6 、 Figure 8 、 Figure 15 、 Figure 17 and Figure 19 , a second end of the first reset unit is electrically connected to the first node N1.

[0109] For another example, see Figure 3-2 、 Figure 10 、 Figure 13 , a second end of the first reset unit is electrically connected to the second node N2.

[0110] Alternatively, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The first reset unit M1 may include one or more transistors, and the transistors of the first reset unit M1 may be low-temperature polysilicon transistors or metal oxide transistors.

[0111] For example, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 15 、 Figure 17 and Figure 19 The first reset unit M1 includes two first reset transistors T1 connected in series, and both first reset transistors T1 are low-temperature polysilicon transistors. This can reduce leakage in the first reset unit M1, thereby reducing leakage power consumption at the first voltage terminal and extending the voltage maintenance time of the second node N2.

[0112] For another example, see Figure 13The first reset unit M1 includes a first reset transistor T1, and the first reset transistor T1 is a metal oxide transistor. In this way, leakage of the first reset unit M1 can be reduced, and the leakage power consumption of the first voltage terminal can be reduced, and the voltage maintenance time of the second node N2 can be extended.

[0113] In the embodiment of the present disclosure, the first reset control signal Reset1 can be an independent signal independent of other control signals of the pixel driving circuit PDC (for example, the light emitting control signal EM, the first scanning signal, the gate reset control signal ResetN, etc.), or it can multiplex the control signals of other pixel driving circuit rows (for example, multiplexing the first scanning signal or the gate reset control signal ResetN of other pixel driving circuit rows), or multiplex the control signals of this pixel driving circuit row.

[0114] In one embodiment of the present disclosure, see Figure 3-1 and Figure 3-2 The pixel driving circuit PDC further includes a second reset unit M7, and the second reset unit M7 is used to reset the fourth node N4 in the reset phase.

[0115] In some examples, the second reset unit M7 is also used to maintain a constant voltage on the second node N2 during the data writing phase; this allows the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be directly stored in the second node N2, and achieves compensation for the threshold voltage Vth and the driving power supply voltage VDD, thereby improving the uniformity of the display panel PNL.

[0116] Optionally, the second reset unit M7 is configured to apply a second initialization voltage Vinit2 to a fourth node N4 in response to a second reset control signal Reset2. Specifically, a first terminal of the second reset unit is electrically connected to a second initialization voltage terminal for applying the second initialization voltage Vinit2, a control terminal of the second reset unit is electrically connected to a second reset control signal terminal for applying the second reset control signal Reset2, and a second terminal of the second reset unit is electrically connected to the fourth node N4. When driving the pixel driving circuit PDC, the second reset control signal Reset2 can be applied to the pixel driving circuit PDC during a reset phase or a data writing phase, thereby applying the second initialization voltage Vinit2 to the fourth node N4.

[0117] In an example, in both the reset phase and the data writing phase, the second reset control signal Reset2 is applied to the pixel driving circuit PDC so that the second initialization voltage Vinit2 is applied to the fourth node N4.

[0118] Alternatively, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 、 Figure 15 、 Figure 17 and Figure 19 The second reset unit M7 may include one or more second reset transistors T7, and the second reset transistor T7 may be a low-temperature polysilicon transistor or a metal oxide transistor.

[0119] For example, see Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 13 The second reset unit M7 may include a second reset transistor T7, and the second reset transistor T7 is a metal oxide transistor.

[0120] For another example, see Figure 15 、 Figure 17 and Figure 19 The second reset unit M7 may include a second reset transistor T7, and the second reset transistor T7 is a low temperature polysilicon transistor.

[0121] In one embodiment of the present disclosure, the second reset unit M7 has one or more second reset transistors T7, and the second light-emitting control unit M6 has one or more second light-emitting control transistors T6; the transistor type of the second reset transistor T7 is opposite to the transistor type of the second light-emitting control transistor T6; the second reset control signal Reset2 and the light-emitting control signal EM are the same control signal.

[0122] In one embodiment of the present disclosure, the second reset unit M7 has one or more second reset transistors T7, and the threshold compensation unit M2 has one or more threshold compensation transistors T2; the transistor type of the second reset transistor T7 is the same as the transistor type of the threshold compensation transistor T2; the second reset control signal Reset2 and the gate reset control signal ResetN are the same control signal.

[0123] In the embodiment of the present disclosure, the second reset control signal Reset2 can be an independent signal independent of other control signals of the pixel driving circuit PDC (for example, the light emitting control signal EM, the first scanning signal, the gate reset control signal ResetN, etc.), or it can multiplex the control signals of other pixel driving circuit rows (for example, multiplexing the first scanning signal or the gate reset control signal ResetN of other pixel driving circuit rows), or multiplex the control signals of the current pixel driving circuit row (for example, multiplexing the light emitting control signal EM of the current pixel driving circuit row).

[0124] As follows, the structure, principle and driving method of the pixel driving circuit PDC provided by the embodiment of the present disclosure are exemplarily described by taking multiple embodiments as examples.

[0125] Figure 4 FIG. 4 is an equivalent circuit diagram of a pixel driving circuit PDC in some exemplary embodiments of the present disclosure. Figure 5 for Figure 4 A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0126] See also Figure 4 In some exemplary embodiments, the pixel driving circuit PDC includes:

[0127] a driving transistor T3, which is a metal oxide transistor; a first electrode of the driving transistor T3 is electrically connected to the third node N3, a second electrode of the driving transistor T3 is electrically connected to the first node N1, a bottom gate of the driving transistor T3 is electrically connected to the third node N3, and a top gate of the driving transistor T3 is electrically connected to the second node N2;

[0128] The threshold compensation transistor T2 (serving as the threshold compensation unit M2) is a metal oxide transistor; a first electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, a second electrode of the threshold compensation transistor T2 is electrically connected to the second node N2, and a bottom gate of the threshold compensation transistor T2 and a top gate of the threshold compensation transistor T2 are both electrically connected to a gate reset control signal terminal for applying a gate reset control signal ResetN;

[0129] The data writing transistor T4 (serving as the data writing unit M4) is a low-temperature polysilicon transistor; a first electrode of the data writing transistor T4 is electrically connected to a data voltage terminal for loading a data voltage Vdata, and a second electrode of the data writing transistor T4 is electrically connected to a third node N3; a bottom gate of the data writing transistor T4 and a top gate of the data writing transistor T4 are both electrically connected to a first scanning signal terminal for loading a first scanning signal;

[0130] Two first light emission control transistors T5 (serving as a first light emission control unit M5), wherein a first electrode of the first first light emission control transistor T5 is electrically connected to a driving power supply voltage terminal for applying a driving power supply voltage VDD, a second electrode of the first first light emission control transistor T5 is mutually connected to a first electrode of the second first light emission control transistor T5, and a second electrode of the second first light emission control transistor T5 is electrically connected to a first node N1; gates of the two first light emission control transistors T5 are electrically connected to a light emission control signal terminal for applying a light emission control signal EM; both first light emission control transistors T5 are low-temperature polysilicon transistors;

[0131] a second light-emitting control transistor T6 (serving as the second light-emitting control unit M6), which is a low-temperature polysilicon transistor; a first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, a second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and a gate of the second light-emitting control transistor T6 is electrically connected to a light-emitting control signal terminal for applying a light-emitting control signal EM;

[0132] Two first reset transistors T1 (serving as a first reset unit M1), wherein a first electrode of the first first reset transistor T1 is electrically connected to a driving power supply voltage terminal for applying a driving power supply voltage VDD (serving as a first voltage V1), a second electrode of the first first reset transistor T1 is mutually connected to a first electrode of the second first reset transistor T1, and a second electrode of the second first reset transistor T1 is electrically connected to a first node N1; gates of the two first reset transistors T1 are electrically connected to a first reset control signal terminal for applying a first reset control signal Reset1; and both first reset transistors T1 are low-temperature polysilicon transistors;

[0133] The second reset transistor T7 (serving as the second reset unit M7) is a metal oxide transistor. A first electrode of the second reset transistor T7 is electrically connected to a second initialization voltage terminal for applying a second initialization voltage Vinit2. A second electrode of the second reset transistor T7 is electrically connected to a fourth node N4. A gate of the second reset transistor T7 is electrically connected to a second reset control signal terminal for applying a second reset control signal Reset2. The second reset control signal Reset2 and the light-emission control signal EM share the same signal. When the signal is at a high level, the second reset transistor T7 is turned on. When the signal is at a high level, the first and second light-emission control transistors T5 and T6 are turned on. In other words, the gates of the second reset transistor T7, the first and second light-emission control transistors T5, and T6 are all electrically connected to the light-emission control signal terminal for applying the light-emission control signal EM.

[0134] See also Figure 5 ,Should Figure 4 The pixel driving circuit PDC of the exemplary embodiment may be driven by the following driving method:

[0135] During the reset phase P1, the pixel driver circuit PDC is supplied with a gate reset control signal ResetN (high level), a first reset control signal Reset1 (low level), and a second reset control signal Reset2 (high level). This turns on the first reset transistor T1, the threshold compensation transistor T2, and the second reset transistor T7. The voltage at the second node N2 becomes the driving power supply voltage VDD, and the voltage at the fourth node N4 becomes the second initialization voltage Vinit2, turning on the driving transistor T3. The first scan signal is high and the emission control signal EM is high, turning off the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0136] In the data writing phase P2 following the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first scanning signal (low level), and a second reset control signal Reset2 (high level). The second reset transistor T7 is turned on, causing the voltage of the fourth node N4 to remain at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, causing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is at a high level, and the emission control signal EM is at a high level. This causes the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 to be turned off.

[0137] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is low. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0138] In this Figure 4 In an exemplary embodiment, the second reset control signal terminal and the light emitting control signal terminal may be the same signal terminal, for example, the same signal line, which can reduce the number of signal lines on the display panel PNL.

[0139] Optional, see Figure 5 , the first reset control signal Reset1 corresponding to one pixel driving circuit row and the first scanning signal corresponding to another pixel driving circuit row can reuse the same signal. For example, the first reset control signal Reset1 corresponding to the nth pixel driving circuit row can reuse the same signal as the first scanning signal corresponding to the nxth pixel driving circuit row, where x is a positive integer. For example, when x is 1, the first scanning signal of the previous pixel driving circuit row and the first reset control signal Reset1 of the current pixel driving circuit row are the same signal, for example, they can be loaded on the same row-toward trace; when a low-level signal is loaded on the row-toward trace, the pixel driving circuit PDC of the current pixel driving circuit row enters the reset phase and the pixel driving circuit PDC of the previous pixel driving circuit row enters the data writing phase.

[0140] Figure 6 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 7 for Figure 6 A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0141] See also Figure 6 , Figure 6 The pixel driving circuit PDC in the exemplary embodiment is Figure 4 The pixel driving circuit PDC in the exemplary embodiment is basically the same, except that the first voltage V1 is the first initialization voltage Vinit1 instead of the driving power supply voltage VDD. Figure 7 ,Should Figure 6 The driving method of the pixel driving circuit PDC in the exemplary embodiment is Figure 4 The driving methods of the pixel driving circuit PDC in the exemplary embodiments are substantially the same. During the reset phase P1, the voltage at the second node N2 is the first initialization voltage Vinit1, and the voltage at the fourth node N4 is the second initialization voltage Vinit2. During the data writing phase P2, the voltage at the second node N2 is Vdata+Vth, and the voltage at the fourth node N4 is the second initialization voltage Vinit2. During the light-emitting phase P3, the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2, and the voltage at the fourth node N4 is VDD.

[0142] and Figure 4 The exemplary embodiment is similar, in Figure 6 In the pixel driving circuit PDC of the exemplary embodiment, the light emitting control signal EM and the RS threshold compensation transistor T2 are the same control signal, for example, loaded on the same row-direction trace.

[0143] and Figure 4 Similar to the exemplary embodiment, application Figure 6 The display panel PNL of the pixel driving circuit PDC of the exemplary embodiment can multiplex the first scan signal and the first reset control signal Reset1 between different pixel driving circuit rows, for example, the first scan signal of the nxth pixel driving circuit row is multiplexed into the first reset control signal Reset1 of the nth pixel driving circuit row.

[0144] Figure 8 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 9 For the present disclosure Figure 8 A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0145] See also Figure 8 and Figure 9 ,Should Figure 8 The pixel driving circuit PDC in the exemplary embodiment is Figure 4 The pixel driving circuit PDC in the exemplary embodiment is basically the same, except that the second reset control signal Reset2 and the gate reset control signal ResetN are the same control signal, for example, loaded on the same row line. Figure 9 ,Should Figure 8 In the exemplary embodiment, the driving method of the pixel driving circuit PDC is as follows:

[0146] During the reset phase P1, the pixel driver circuit PDC is supplied with a gate reset control signal ResetN (high level), a first reset control signal Reset1 (low level), and a second reset control signal Reset2 (high level). This turns on the first reset transistor T1, the threshold compensation transistor T2, and the second reset transistor T7. The voltage at the second node N2 becomes the driving power supply voltage VDD, and the voltage at the fourth node N4 becomes the second initialization voltage Vinit2, turning on the driving transistor T3. The first scan signal is high and the emission control signal EM is high, turning off the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0147] In the data writing phase P2 following the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first scanning signal (low level), and a second reset control signal Reset2 (high level). The second reset transistor T7 is turned on, causing the voltage of the fourth node N4 to remain at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, causing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is at a high level, and the emission control signal EM is at a high level. This causes the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 to be turned off.

[0148] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is low. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0149] and Figure 4 Similar to the exemplary embodiment, application Figure 8 The display panel PNL of the pixel driving circuit PDC of the exemplary embodiment can multiplex the first scan signal and the first reset control signal Reset1 between different pixel driving circuit rows, for example, the first scan signal of the nxth pixel driving circuit row is multiplexed into the first reset control signal Reset1 of the nth pixel driving circuit row.

[0150] Figure 10 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 11 For the present disclosure Figure 10 In an exemplary embodiment, a driving timing diagram of a pixel driving circuit PDC is shown. Figure 12 For the present disclosure Figure 10 In an exemplary embodiment, another driving timing diagram of the pixel driving circuit PDC is shown.

[0151] See also Figure 10 、 Figure 11 and Figure 12 ,Should Figure 10 The pixel driving circuit PDC in the exemplary embodiment is Figure 4 The pixel driving circuit PDC in the exemplary embodiment is basically the same, with two differences: the second end of the first reset unit is connected to the second node N2, and the first voltage V1 loaded on the first end of the first reset unit is the first initialization voltage Vinit1.

[0152] and Figure 4 Similar to the exemplary embodiment, the Figure 10 In the pixel driving circuit PDC of the exemplary embodiment, the second reset control signal Reset2 and the light emitting control signal EM are the same control signal, for example, loaded on the same row trace.

[0153] and Figure 4 Similar to the exemplary embodiment, application Figure 10 The display panel PNL of the pixel driving circuit PDC of the exemplary embodiment can multiplex the first scan signal and the first reset control signal Reset1 between different pixel driving circuit rows, for example, the first scan signal of the nxth pixel driving circuit row is multiplexed into the first reset control signal Reset1 of the nth pixel driving circuit row.

[0154] In one embodiment of the present disclosure, see Figure 11 ,Should Figure 10 In the exemplary embodiment, the driving method of the pixel driving circuit PDC is Figure 4 The driving methods of the pixel driving circuit PDC in the exemplary embodiments are basically the same.

[0155] In the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first reset control signal Reset1 (low level), and a second reset control signal Reset2 (high level). This turns on the first reset transistor T1, the threshold compensation transistor T2, and the second reset transistor T7. The voltage at the second node N2 becomes the first initialization voltage Vinit1, and the voltage at the fourth node N4 becomes the second initialization voltage Vinit2. The driving transistor T3 is turned on. The first scanning signal is high and the emission control signal EM is high. This turns off the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0156] In the data writing phase P2 following the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first scanning signal (low level), and a second reset control signal Reset2 (high level). The second reset transistor T7 is turned on, causing the voltage of the fourth node N4 to remain at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, causing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is at a high level, and the emission control signal EM is at a high level. This causes the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 to be turned off.

[0157] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is low. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0158] In another embodiment of the present disclosure, see Figure 12 ,Should Figure 10 In the exemplary embodiment, the driving method of the pixel driving circuit PDC is Figure 4 The driving methods of the pixel driving circuit PDC in the exemplary embodiments are basically the same, with the main difference being that the gate reset control signal ResetN may be at a low level in the reset phase P1 , and the threshold compensation transistor T2 may remain off in the reset phase P1 .

[0159] In the reset phase P1, the pixel driving circuit PDC is supplied with a first reset control signal Reset1 (low level) and a second reset control signal Reset2 (high level). This turns on the first reset transistor T1 and the second reset transistor T7, and the voltage of the second node N2 becomes the first initialization voltage Vinit1 and the voltage of the fourth node N4 becomes the second initialization voltage Vinit2. The driving transistor T3 is turned on. The first scanning signal is high, the emission control signal EM is high, and the gate reset control signal ResetN is low. This turns off the threshold compensation transistor T2, the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0160] In the data writing phase P2 following the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first scanning signal (low level), and a second reset control signal Reset2 (high level). The second reset transistor T7 is turned on, causing the voltage of the fourth node N4 to remain at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, causing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is at a high level, and the emission control signal EM is at a high level. This causes the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 to be turned off.

[0161] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is low. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0162] Figure 13 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 14 For the present disclosure Figure 13A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0163] See also Figure 13 、 Figure 14 ,Should Figure 13 The pixel driving circuit PDC in the exemplary embodiment is Figure 4 The pixel driving circuit PDC in the exemplary embodiment is basically the same, and the difference lies in the configuration of the first reset unit M1: the first reset unit M1 includes a first reset transistor T1, and the first reset transistor T1 is a metal oxide transistor, and the second electrode of the first reset transistor T1 is electrically connected to the second node N2.

[0164] and Figure 4 Similar to the exemplary embodiment, the Figure 13 In the pixel driving circuit PDC of the exemplary embodiment, the second reset control signal Reset2 and the light emitting control signal EM are the same control signal, for example, loaded on the same row trace.

[0165] Should Figure 13 In an exemplary embodiment, the driving method may be as follows:

[0166] In the reset phase P1, the pixel driving circuit PDC is supplied with a first reset control signal Reset1 (high level) and a second reset control signal Reset2 (high level). This turns on the first reset transistor T1 and the second reset transistor T7, and the voltage of the second node N2 becomes the first initialization voltage Vinit1 and the voltage of the fourth node N4 becomes the second initialization voltage Vinit2. The driving transistor T3 is turned on. The first scanning signal is high, the emission control signal EM is high, and the gate reset control signal ResetN is low. This turns off the threshold compensation transistor T2, the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0167] In the data writing phase P2 following the reset phase P1, the pixel driving circuit PDC is supplied with a gate reset control signal ResetN (high level), a first scanning signal (low level), and a second reset control signal Reset2 (high level). The second reset transistor T7 is turned on, maintaining the voltage of the fourth node N4 at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, writing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is low and the emission control signal EM is high, turning off the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6.

[0168] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is low. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0169] In one example, see Figure 14 , the first reset control signal Reset1 corresponding to one pixel driving circuit row and the gate reset control signal ResetN corresponding to another pixel driving circuit row can reuse the same signal. For example, the first reset control signal Reset1 corresponding to the nth pixel driving circuit row can reuse the same signal as the gate reset control signal ResetN corresponding to the nxth pixel driving circuit row, where x is a positive integer. For example, when x is 1, the gate reset control signal ResetN of the previous pixel driving circuit row and the first reset control signal Reset1 of the current pixel driving circuit row are the same signal, for example, they can be loaded on the same row-toward trace; when a high-level signal is loaded on the row-toward trace, the pixel driving circuit PDC of the current pixel driving circuit row enters the reset phase and the pixel driving circuit PDC of the previous pixel driving circuit row enters the data writing phase.

[0170] Figure 15 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 16 For the present disclosure Figure 15 A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0171] See also Figure 15 、 Figure 16 ,Should Figure 15 The pixel driving circuit PDC in the exemplary embodiment is Figure 4The pixel driving circuit PDC in the exemplary embodiment is basically the same, the difference lies in the setting of the second reset unit M7: the second reset unit M7 includes a second reset transistor T7, and the second reset transistor T7 is a low-temperature polysilicon transistor. The second reset control signal Reset2 loaded on the gate of the second reset transistor T7 is no longer the same signal as the light-emitting control signal EM, but an independent signal.

[0172] Should Figure 15 In an exemplary embodiment, the driving method may be as follows:

[0173] During the reset phase P1, the pixel driving circuit PDC is supplied with a first reset control signal Reset1 (low level), a second reset control signal Reset2 (low level), and a gate reset control signal ResetN (high level). This turns on the first reset transistor T1, the threshold compensation transistor T2, and the second reset transistor T7. The voltage at the second node N2 becomes the driving power supply voltage VDD, and the voltage at the fourth node N4 becomes the second initialization voltage Vinit2, turning on the driving transistor T3. The first scan signal is high, and the emission control signal EM is high. This turns off the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0174] In the data writing phase P2 following the reset phase P1, the gate reset control signal ResetN (high level), the second reset control signal Reset2 (low level), and the first scan signal (low level) are applied to the pixel driving circuit PDC. The second reset transistor T7 is turned on, so that the voltage of the fourth node N4 remains at the second initialization voltage Vinit2. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 are written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The first reset control signal Reset1 is high and the emission control signal EM is high, which turns off the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6.

[0175] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is VDD+Vdata+Vth-Vinit2. Thus, the driving transistor T3 outputs a driving current under the control of the second node N2, compensating for variations in the driving power supply voltage VDD and the threshold voltage Vth. The light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is high. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0176] In one example, with Figure 4 Similar to the exemplary embodiment, application Figure 15 The display panel PNL of the pixel driving circuit PDC of the exemplary embodiment can multiplex the first scan signal and the first reset control signal Reset1 between different pixel driving circuit rows, for example, the first scan signal of the nxth pixel driving circuit row is multiplexed into the first reset control signal Reset1 of the nth pixel driving circuit row.

[0177] In one example, see Figure 16 , the gate reset control signal ResetN and the second reset control signal Reset2 are inverted control signals.

[0178] In one example, the display panel PNL is provided with a first row-oriented trace for applying a gate reset control signal ResetN, and a second row-oriented trace for applying a second reset control signal Reset2. The first row-oriented trace and the second row-oriented trace driving the same row of pixel driver circuits are connected via an inverter. In this way, a single gate driver circuit can be used to simultaneously provide the gate reset control signal ResetN and the second reset control signal Reset2, thereby reducing the bezel of the display panel PNL and reducing power consumption.

[0179] Figure 17 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 18 For the present disclosure Figure 17 A driving timing diagram of a pixel driving circuit PDC in an exemplary embodiment.

[0180] See also Figure 17 、 Figure 18 ,Should Figure 17The pixel driving circuit PDC in the exemplary embodiment is Figure 4 The pixel driving circuits PDC in the exemplary embodiments are substantially identical, differing in the configuration of the second reset unit M7: the second reset unit M7 includes a second reset transistor T7, which is a low-temperature polysilicon transistor. The second reset control signal Reset2 applied to the gate of the second reset transistor T7 and the first reset control signal Reset1 applied to the gate of the first reset transistor T1 are the same control signal. In other words, the gates of the second reset transistor T7 and the first reset transistor T1 can be connected to the same control signal terminal, thereby reducing the number of control signals and row-direction traces on the display panel PNL.

[0181] See also Figure 18 ,Should Figure 17 In an exemplary embodiment, the driving method may be as follows:

[0182] During the reset phase P1, the pixel driving circuit PDC is supplied with a first reset control signal Reset1 (low level), a second reset control signal Reset2 (low level), and a gate reset control signal ResetN (high level). This turns on the first reset transistor T1, the threshold compensation transistor T2, and the second reset transistor T7. The voltage at the second node N2 becomes the driving power supply voltage VDD, and the voltage at the fourth node N4 becomes the second initialization voltage Vinit2, turning on the driving transistor T3. The first scan signal is high, and the emission control signal EM is high. This turns off the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6.

[0183] In the data writing phase P2 following the reset phase P1, the gate reset control signal ResetN (high level) and the first scanning signal (low level) are applied to the pixel driving circuit PDC. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, causing the data voltage Vdata and the threshold voltage Vth of the driving transistor T3 to be written to the second node N2. The voltage of the second node N2 is Vdata + Vth. The voltage of the fourth node N4 is adaptively adjusted due to the coupling effect. The first reset control signal Reset1 is low, the second reset control signal Reset2 is low, and the emission control signal EM is high. This turns off the first reset transistor T1, the second reset transistor T7, the first emission control transistor T5, and the second emission control transistor T6.

[0184] During the light-emitting phase P3 following the data writing phase P2, a light-emitting control signal EM (low level) is applied to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The voltage at the fourth node N4 is the driving power supply voltage VDD, and the voltage at the second node N2 is adaptively adjusted due to coupling. Consequently, the driving transistor T3 outputs a driving current under the control of the second node N2, and the light-emitting element LD emits light under the driving current. The gate reset control signal ResetN is low, the first reset control signal Reset1 is high, the first scan signal is high, and the second reset control signal Reset2 is high. This turns off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7.

[0185] In one example, with Figure 4 Similar to the exemplary embodiment, application Figure 17 The display panel PNL of the pixel driving circuit PDC of the exemplary embodiment can multiplex the first scan signal and the first reset control signal Reset1 between different pixel driving circuit rows, for example, the first scan signal of the nxth pixel driving circuit row is multiplexed into the first reset control signal Reset1 of the nth pixel driving circuit row.

[0186] Figure 19 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit PDC in some other exemplary embodiments of the present disclosure. Figure 19 The pixel driving circuit PDC in the exemplary embodiment is Figure 17 The pixel driving circuit PDC in the exemplary embodiment is basically the same, and the difference lies in the configuration of the first reset unit M1: the first voltage V1 loaded on the first terminal of the first reset unit is the first initialization voltage Vinit1. Figure 19 The driving method of the exemplary embodiment, Figure 17 The driving methods of the exemplary embodiments are basically the same.

[0187] In one embodiment of the present disclosure, see Figure 20 The display panel PNL includes a base substrate SBT, a driving layer DRL and a pixel layer PXL which are stacked in sequence; wherein the driving layer DRL is provided with a pixel driving circuit PDC, and the pixel layer PXL is provided with a light emitting element LD as a sub-pixel PX.

[0188] In one example, see Figure 20The sub-pixels PX include sub-pixels PX of multiple different colors. For example, the sub-pixels PX include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The colors of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are different. For example, the first sub-pixel PX1 is a red sub-pixel, the second sub-pixel PX2 is a green sub-pixel, and the third sub-pixel PX3 is a blue sub-pixel.

[0189] In one embodiment of the present disclosure, the configurations of the pixel driving circuits PDC on the display panel PNL are the same, for example, they are connected to the same power supply voltage and control signal, and the sizes of the same transistors in the pixel driving circuits PDC are also the same.

[0190] In other embodiments of the present disclosure, the pixel driving circuit PDC on the display panel PNL can adjust local parameters according to actual needs, such as adjusting the connected initialization voltage (e.g., the first initialization voltage Vinit1, the second initialization voltage Vinit2), the capacitance value of the storage capacitor Cst, the aspect ratio of the driving transistor T3, etc.

[0191] For example, on the display panel PNL, at least two pixel driving circuits PDC are connected to first initialization voltages Vinit1 having different voltage values.

[0192] For another example, on the display panel PNL, at least two pixel driving circuits PDC are connected to second initialization voltages Vinit2 with different voltage values.

[0193] For another example, on the display panel PNL, the storage capacitors Cst of at least two pixel driving circuits PDC have different capacitance values.

[0194] For another example, on the display panel PNL, the driving transistors T3 of at least two pixel driving circuits PDC have different width-to-length ratios.

[0195] In the embodiment of the present disclosure, for the sake of convenience, the pixel driving circuit PDC that drives the first sub-pixel PX1 may be referred to as the first pixel driving circuit PDC1, the pixel driving circuit PDC that drives the second sub-pixel PX2 may be referred to as the second pixel driving circuit PDC2, and the pixel driving circuit PDC that drives the third sub-pixel PX3 may be referred to as the third pixel driving circuit PDC3.

[0196] As an example, the voltage values ​​of the first initialization voltage Vinit1 connected to the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are different, or the voltage values ​​of the first initialization voltage Vinit1 connected to the first pixel driving circuit PDC1 and the third pixel driving circuit PDC3 are different, or the voltage values ​​of the first initialization voltage Vinit1 connected to the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are different, or the voltage values ​​of the first initialization voltage Vinit1 connected to the first pixel driving circuit PDC1, the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are all different.

[0197] As another example, the voltage values ​​of the second initialization voltage Vinit2 connected to the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are different, or the voltage values ​​of the second initialization voltage Vinit2 connected to the first pixel driving circuit PDC1 and the third pixel driving circuit PDC3 are different, or the voltage values ​​of the second initialization voltage Vinit2 connected to the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are different, or the voltage values ​​of the second initialization voltage Vinit2 connected to the first pixel driving circuit PDC1, the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are all different.

[0198] As another example, the capacitance values ​​of the storage capacitors Cst of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are different, or the capacitance values ​​of the storage capacitors Cst of the first pixel driving circuit PDC1 and the third pixel driving circuit PDC3 are different, or the capacitance values ​​of the storage capacitors Cst of the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are different, or the capacitance values ​​of the storage capacitors Cst of the first pixel driving circuit PDC1, the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are all different.

[0199] As another example, the aspect ratios of the driving transistors T3 of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are different, or the aspect ratios of the driving transistors T3 of the first pixel driving circuit PDC1 and the third pixel driving circuit PDC3 are different, or the aspect ratios of the driving transistors T3 of the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are different, or the aspect ratios of the driving transistors T3 of the first pixel driving circuit PDC1, the second pixel driving circuit PDC2 and the third pixel driving circuit PDC3 are all different.

[0200] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel driving circuit, comprising: a driving transistor connected to the first node and the third node, and configured to control the magnitude of the driving current under the control of the voltage on the second node; The driving transistor is a metal oxide transistor; a data writing unit, configured to load a data voltage onto the third node in response to a first scanning signal; a threshold compensation unit, configured to enable electrical conduction between the second node and the first node in response to a gate reset control signal; a first light emitting control unit, configured to load a driving power supply voltage to the first node in response to a light emitting control signal; a second light emitting control unit, configured to enable electrical conduction between the third node and the fourth node in response to the light emitting control signal; a storage capacitor connected to the second node and the fourth node; The fourth node is used to connect the light emitting element.

2. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit also includes a first reset unit; the first end of the first reset unit is used to load a first voltage, the second end of the first reset unit is directly or indirectly connected to the second node, and the control end of the first reset unit is used to respond to a first reset control signal to be turned on and enable the first voltage to be directly or indirectly loaded to the second node.

3. The pixel driving circuit according to claim 2, wherein: The second end of the first reset unit is electrically connected to the first node or the second node.

4. The pixel driving circuit according to claim 2, wherein: The first voltage is a first initialization voltage or a driving power supply voltage.

5. The pixel driving circuit according to claim 2, wherein: The first reset unit includes a plurality of first reset transistors connected in series, and the first reset transistors are low-temperature polysilicon transistors; or the first reset unit includes one first reset transistor, and the first reset transistor is a metal oxide transistor.

6. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit also includes a second reset unit; the first end of the second reset unit is used to load a second initialization voltage, the second end of the second reset unit is electrically connected to the fourth node, and the control end of the second reset unit is used to be turned on in response to a second reset control signal.

7. The pixel driving circuit according to claim 6, wherein: The second reset unit has one or more second reset transistors; the second reset transistors are low-temperature polysilicon transistors, and the gates of the second reset transistors are used to load a second reset control signal.

8. The pixel driving circuit according to claim 6, wherein: The second reset unit has one or more second reset transistors, and the second light-emitting control unit has one or more second light-emitting control transistors; the transistor type of the second reset transistor is opposite to the transistor type of the second light-emitting control transistor; the second reset control signal and the light-emitting control signal are the same control signal.

9. The pixel driving circuit according to claim 6, wherein: The second reset unit includes one or more second reset transistors, and the threshold compensation unit includes one or more threshold compensation transistors; the transistor type of the second reset transistor is the same as the transistor type of the threshold compensation transistor; The second reset control signal and the gate reset control signal are the same control signal.

10. The pixel driving circuit according to any one of claims 1 to 9, wherein: The driving transistor includes a bottom gate of the driving transistor and a top gate of the driving transistor. The bottom gate of the driving transistor is electrically connected to the third node, and the top gate of the driving transistor is electrically connected to the second node.

11. The pixel driving circuit according to any one of claims 1 to 9, wherein: The data writing unit includes a data writing transistor, and the data writing transistor has a top gate and a bottom gate; the bottom gate and the top gate of the data writing transistor are both used to load the first scanning signal.

12. The pixel driving circuit according to any one of claims 1 to 9, wherein: The threshold compensation unit includes a threshold compensation transistor, and the threshold compensation transistor has a top gate and a bottom gate; the bottom gate and the top gate of the threshold compensation transistor are both used to load a gate reset control signal.

13. The pixel driving circuit according to any one of claims 1 to 9, wherein: The first light emitting control unit includes a plurality of first light emitting control transistors connected in series, and a gate of each of the first light emitting control transistors is used to load the light emitting control signal.

14. A driving method for the pixel driving circuit according to any one of claims 1 to 13, comprising: In the data writing phase, the first scanning signal and the gate reset control signal are applied to the pixel driving circuit so that the data voltage is written into the second node; In the light emitting stage, a light emitting control signal is applied to the pixel driving circuit, so that the pixel driving circuit outputs a driving current to the light emitting element according to the voltage on the second node. 15 . A display panel comprising display units arranged in an array, wherein the display units comprise the pixel driving circuit according to claim 1 and a light-emitting element driven by the pixel driving circuit.

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