Sintering packaging method for SiC power module

Abstract

The invention discloses a SiC power module sintering packaging method, and relates to the technical field of power module packaging, and the method comprises the steps: sequentially carrying out the ultrasonic cleaning, plasma activation and drying of a SiC chip and a ceramic substrate, and obtaining an activated ceramic substrate and a SiC chip; the surfaces of the activated ceramic substrate and the SiC chip are spin-coated with nano-silver paste, and a nano-porous silver layer is formed through pre-curing and low-temperature sintering; aligning the graphene / nano-porous silver composite layer chip with the ceramic substrate, performing segmented pressure sintering in a vacuum sintering furnace, and outputting a SiC power module; the SiC power module is subjected to epoxy resin packaging glue coating, ultraviolet light curing and annealing treatment, internal stress is eliminated, and the corrosion resistance is enhanced; and screening a SiC power module, performing XRD and SEM detection, coating a high-temperature-resistant silica gel sealing layer, performing curing, and outputting a finished product. Through the epoxy resin packaging adhesive coating and thermal-acoustic combined annealing technology, the residual stress of the packaging interface is released, the service life of the SiC power module is prolonged, and the adaptability of the SiC power module is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power module packaging, and in particular to a sintering packaging method for a SiC power module. Background Art

[0002] Silicon carbide (SiC) power modules are widely used in power electronics, aerospace, and new energy vehicles due to their high voltage resistance, low conduction loss, and high-temperature stability. However, traditional SiC power module packaging methods primarily rely on high-lead solder or eutectic soldering techniques. These methods are prone to interface diffusion, thermal fatigue, and electromigration in high-temperature environments, resulting in reduced reliability of the packaging layer. Furthermore, traditional packaging processes result in high thermal resistance at the solder interface, which limits the heat dissipation performance of SiC power modules and affects their long-term stable operation. Therefore, improving the packaging quality and interface stability of SiC power modules and reducing interface thermal resistance have become important research directions.

[0003] Currently, nanosilver sintering technology is considered an ideal alternative to traditional high-lead solder due to its low-temperature sintering, high thermal conductivity, and excellent interfacial bonding ability. However, existing nanosilver sintering processes still face several challenges, such as the formation of defects in the nanosilver layer, limited interfacial bonding, and poor long-term thermal stability. Furthermore, the recrystallization of particles and the porosity of the sintered layer during the sintering process are difficult to precisely control, affecting packaging quality. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a SiC power module sintering packaging method to solve the problems of insufficient interface bonding strength, high thermal resistance and poor long-term thermal stability during the SiC power module packaging process.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for sintering and packaging a SiC power module, comprising: sequentially subjecting a SiC chip and a ceramic substrate to ultrasonic cleaning, plasma activation, and drying to obtain an activated ceramic substrate and a SiC chip;

[0008] The activated ceramic substrate and SiC chip surface are spin-coated with nano-silver paste, and a nano-porous silver layer is formed through pre-curing and low-temperature sintering.

[0009] On the surface of the nanoporous silver layer, a single layer of graphene is grown by plasma-enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite layer chip;

[0010] After aligning the graphene / nanoporous silver composite layer chip with the ceramic substrate, it is subjected to segmented pressure sintering in a vacuum sintering furnace to produce a SiC power module;

[0011] The SiC power module is coated with epoxy resin encapsulation glue, UV-cured and annealed to eliminate internal stress and enhance corrosion resistance;

[0012] Place the SiC power module in a high and low temperature cycle test chamber for thermal cycle testing;

[0013] After screening SiC power modules and undergoing XRD and SEM testing, they are coated with a high-temperature resistant silicone sealing layer and cured before being output as finished products.

[0014] As a preferred solution of the SiC power module sintering and packaging method of the present invention, wherein: the pre-curing and low-temperature sintering to form the nanoporous silver layer are specifically performed as follows:

[0015] The activated SiC chip and ceramic substrate are fixed on an automatic spin coater and spin-coated, and then placed in an automatic heating device for pre-curing;

[0016] After pre-curing, the nanoparticles are sintered in a vacuum sintering furnace at a low temperature to partially fuse the nanosilver particles and form a nanoporous silver layer.

[0017] During the sintering process, microscopic images are collected through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

[0018] As a preferred solution of the SiC power module sintering and packaging method of the present invention, wherein: the single-layer graphene is grown by plasma enhanced chemical vapor deposition, and the specific steps are as follows:

[0019] An oxygen-free environment is established under high-purity argon purge, the substrate is heated, and a bias voltage is applied to adsorb the carbon source;

[0020] Using adaptive plasma density to control the graphene growth environment;

[0021] By regulating the hydrogen / methane flow ratio and nickel atomic beam injection, the graphene monolayer grows uniformly, obtaining a graphene / nanoporous silver composite layer chip.

[0022] As a preferred solution of the SiC power module sintering packaging method of the present invention, the epoxy resin packaging glue coating, UV curing and annealing treatment are specifically performed as follows:

[0023] The surface of the SiC power module is electrostatically sprayed with epoxy resin encapsulation glue, and the encapsulation glue is internally cured using multi-band ultraviolet light;

[0024] Thermal-acoustic combined annealing is used to release the interface residual stress through temperature gradient and ultrasonic oscillation.

[0025] As a preferred solution of the SiC power module sintering and packaging method of the present invention, the ultrasonic cleaning, plasma activation and drying treatment utilizes an ultrasonic cleaning method to remove surface oil stains, particulate contaminants and plasma treatment.

[0026] As a preferred solution of the SiC power module sintering packaging method described in the present invention, the thermal cycling test refers to a test that evaluates the structural stability, electrical performance changes and fatigue life of the SiC power module under temperature stress by repeatedly cycling between high and low temperature extreme environments.

[0027] As a preferred solution of the SiC power module sintering packaging method described in the present invention, the thermal cycling test refers to a test that evaluates the structural stability, electrical performance changes and fatigue life of the SiC power module under temperature stress by repeatedly cycling between high and low temperature extreme environments.

[0028] As a preferred solution of the SiC power module sintering and packaging method of the present invention, the XRD detection is used to analyze the crystal structure and phase composition of the SiC power module, while the SEM detection is used to observe its micromorphology, interface bonding and defect distribution to ensure the structural integrity and reliability of the material.

[0029] In a second aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the SiC power module sintering packaging method as described in the first aspect of the present invention is implemented.

[0030] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, any step of the SiC power module sintering packaging method as described in the first aspect of the present invention is implemented.

[0031] The beneficial effects of the present invention are as follows: by optimizing the packaging process of the SiC power module, a single layer of graphene is deposited on the surface of the nanoporous silver layer, thereby improving the interface bonding strength and thermal conductivity; by combining plasma activation with spin coating of nanosilver slurry, the nanosilver layer forms a uniform and dense porous structure during the low-temperature sintering process, thereby reducing the porosity of the sintered layer; through a segmented pressure sintering process, electromagnetic assistance and ultrasonic pre-pressing are used to achieve precise control of sintering densification, reduce the generation of interface microcracks, and effectively release the residual stress of the packaging interface through epoxy resin packaging glue coating and thermal-acoustic combined annealing technology, thereby improving the service life and environmental adaptability of the SiC power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a flow chart of the SiC power module sintering and packaging method in Example 1.

[0034] Figure 2 Schematic diagram of the process for forming the nanoporous silver layer in Example 1.

[0035] Figure 3 Schematic diagram of the single-layer graphene growth process in Example 1.

[0036] Figure 4 Schematic diagram of the epoxy resin encapsulation and curing process in Example 1. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0039] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0040] Example 1, reference Figures 1 to 4 This embodiment provides a SiC power module sintering packaging method, comprising the following steps:

[0041] S1. The SiC chip and the ceramic substrate are sequentially subjected to ultrasonic cleaning, plasma activation and drying treatment to obtain an activated ceramic substrate and a SiC chip.

[0042] Furthermore, the SiC chip and ceramic substrate are placed separately in dedicated polytetrafluoroethylene (PTFE) trays to prevent contact and cross-contamination. The surfaces are pre-rinsed with ultrapure deionized water (DI water) to remove loose particles. A cleaning solution consisting of 70% isopropyl alcohol (IPA) and 30% DI water is used. This ratio removes organic contaminants while protecting the SiC chip and ceramic substrate surfaces. The temperature is maintained at around 30°C to improve cleaning efficiency.

[0043] Specifically, set the ultrasonic cleaning parameters, use a 40kHz ultrasonic cleaning machine, set the output power to 200W according to the volume of the cleaning tank , calculate the ultrasonic energy density I, the expression is:

[0044] ;

[0045] Among them, the output power , tank volume is 2L, then the ultrasonic energy density .

[0046] The cleaning time is set to 15 minutes to ensure sufficient ultrasonic action time to generate a large number of uniform, tiny cavitation bubbles and effectively remove surface contaminants. The pretreated SiC chip and ceramic substrate are placed in the cleaning tank, and the ultrasonic cleaning device is turned on to maintain uniform temperature and liquid circulation in the tank. After cleaning, they are thoroughly rinsed with high-purity deionized water to remove residual cleaning fluid and dissolved contaminants. Preliminary testing of some samples can be performed using a surface roughness tester or contact angle meter to verify that surface contaminants are reduced and the contact angle is lowered (surface energy is increased) after cleaning. Plasma treatment further removes trace organic residues and atomic-level contamination, while significantly increasing the surface energy of the SiC chip and ceramic substrate, improving the wettability of subsequent metal slurries.

[0047] The ultrasonically cleaned and rinsed SiC chips and ceramic substrates were placed in a pre-cleaned vacuum plasma treatment chamber, ensuring that the samples were firmly fixed and the surface was facing upward. 5% oxygen was added to Argon pure gas. Oxygen helps to further oxidize and remove organic residues without introducing an excessively thick oxide layer.

[0048] The working pressure was set to 0.2 Torr, the RF power was 100 W for excitation, and the activation time was set to 5 minutes. Under plasma excitation, ions bombarded the sample surface, causing the surface atoms to rearrange and break the organic bonds.

[0049] The activation effect can be verified using the Young equation, which is expressed as follows:

[0050] ;

[0051] in, is the solid-gas interface energy, is the solid-liquid interfacial energy, is the surface tension of the liquid, is the contact angle.

[0052] After activation, the measured contact angle decreases, indicating an increase in surface energy, thereby improving subsequent slurry wettability. Online spectral detection is configured to monitor the concentration of active species in the plasma in real time to ensure process stability. After data acquisition, the RF power and activation time are adjusted according to the PID control algorithm. After the activation time expires, the RF power is turned off and the sample is quickly removed from the chamber to prevent environmental contamination from reattaching to the sample surface.

[0053] After plasma activation, the newly activated SiC chip and ceramic substrate are immediately placed in a clean room with N2 protection to prevent impurities in the air from adhering again.

[0054] Specifically, infrared (IR) radiation drying equipment is used, and preliminary drying is performed under the protection of N2 flow. The sample is then transferred to a precision temperature-controlled drying oven, where a circulating fan is used to ensure uniform temperature. PID control is applied to monitor the drying oven temperature in real time to ensure temperature stability. The PID control formula is the same as above, ensuring that the drying temperature error is less than ±2°C. An infrared humidity sensor is used to detect the sample surface to confirm that the residual moisture is less than 5ppm. Contact angle measurement can also confirm that the surface has a high surface energy (i.e., low contact angle) after drying, laying a good foundation for subsequent spin coating of nanosilver paste. After drying, the sample is immediately placed in a clean storage box and stored in a drying cabinet to avoid adsorption of moisture and organic matter from the air.

[0055] The best practices feature clear operational procedures, defined parameters, and rigorous monitoring. They also employ cross-disciplinary technologies such as PID closed-loop control, online spectral detection, and infrared humidity monitoring. These not only significantly improve cleaning and activation, but also provide a high-quality foundation for subsequent sintering and packaging. The refined process flow and high degree of automation ensure effective surface activation and low contamination, laying a solid foundation for high-reliability packaging of SiC power modules.

[0056] S2. Spin-coating nanosilver paste on the surface of the activated ceramic substrate and the SiC chip, and forming a nanoporous silver layer through pre-curing and low-temperature sintering.

[0057] Furthermore, the activated SiC chip and the ceramic substrate are fixed on an automatic spin coater and spin-coated, and then placed in an automatic heating device for pre-curing.

[0058] Among them, the automatic spin coater uses a single model, and the preset speed is the set value to ensure that the slurry is evenly stressed during spin coating. When preparing the nanosilver slurry, high-purity nanosilver particles (particle size of about 20nm) are selected and mixed with acetone and an appropriate amount of organic binder (such as polyvinyl pyrrolidone, PVP) in a fixed ratio. After stirring evenly, it is filtered to a pore size of 0.2µm to ensure the uniformity of the slurry. To ensure the stability of the thickness of the slurry each time it is applied, the spin coater is pre-calibrated for the coating amount. When the spin coating process begins, the slurry is evenly distributed at a low speed, and then quickly increased to the preset speed, such as continuous rotation for 15 seconds, to ensure that the slurry forms a uniform thin film under the action of centrifugal force. After spin coating, the initial thickness of the silver paste layer is detected using an online laser thickness detector, and the data is recorded for subsequent process control.

[0059] After pre-curing, the nanoparticles are sintered in a vacuum sintering furnace at a low temperature to partially fuse the nanosilver particles and form a nanoporous silver layer.

[0060] Specifically, the spin-coated workpiece is immediately sent to an automatic heating pre-curing device, and the temperature is set to 80°C, and the holding time is 120 seconds to promote the volatilization of the solvent and the preliminary curing of the silver paste layer. During the pre-curing process, an infrared temperature sensor is used to monitor the surface temperature of the sample in real time to ensure uniform temperature and avoid local overheating or insufficient temperature. After the pre-curing is completed, the weight change of the workpiece is detected by micro-weighing to ensure that the solvent volatilization reaches more than 95%. The pre-cured workpiece is placed in a vacuum sintering furnace, and the vacuum degree, temperature and sintering time are set. At low temperatures, the temperature and the slow release effect of residual organic matter are used to promote the partial fusion of nanosilver particles in the solid state to form a porous structure with fine pores. During the sintering process, an online high-resolution optical monitoring system is used to collect microscopic image data of the silver layer as a basis for subsequent model regulation.

[0061] Furthermore, during the sintering process, microscopic images are collected through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

[0062] To optimize the microstructure of the silver layer, an innovative formula was designed that integrates spin-coating, pre-curing, and sintering parameters. This formula aims to predict and control the quality index Q of the final nanoporous silver layer in real time (a value ranging from 0 to 1, with 1 indicating optimal low porosity and high thermal conductivity). The expression is as follows:

[0063] ;

[0064] in, It is an evaluation index of the silver layer quality, and its value range is from 0 to 1. The larger the value, the lower the porosity of the silver layer, the better the interface bonding and the better the thermal conductivity. is the pre-curing time, which is 120 seconds in this example. is the actual rotation speed during the spin coating process, For the The ideal speed to obtain the best uniformity of the silver layer in each stage, The diffusion inhibition coefficient during spin coating is used to control the effect of actual rotation speed deviating from the ideal value. is the temperature sensitivity coefficient, which is used to describe the effect of the deviation between the sintering temperature and the ideal sintering temperature on the quality of the silver layer. is the actual sintering temperature, which is 150℃ in this example. The ideal temperature for obtaining the best silver layer sintering effect is determined by preliminary experiments, for example, 145°C. is the total number of process segments, indicating the optimal number of speed control stages considered in the spin coating process, which depends on the actual process requirements. is the process segment number index variable, is the integration variable Small strain.

[0065] During the pre-curing time, the comprehensive quality evaluation of the silver layer is obtained by weighted integration of the exponential decay function of the ideal speed deviation and the normalized function of the temperature deviation at each stage. .like If it is close to 1, it means that the entire process parameters are in the optimal state; if If the value is less than 0.8, it indicates parameter deviation and requires adjustment of the spin coating speed or sintering temperature. The model uses an integral averaging method to ensure data stability and combines it with online monitoring data for real-time feedback control.

[0066] After sintering, the workpiece is automatically taken out of the vacuum furnace and the microstructure of the silver layer is tested by scanning electron microscopy (SEM) and X-ray diffraction (XRD) to verify whether it meets the requirements of low porosity and uniform density. According to the test results, the parameters in the formula (such as 、 、 and ideal speed and temperature ), to achieve process optimization for the next batch of workpieces.

[0067] S3. Growing a single layer of graphene on the surface of the nanoporous silver layer by plasma enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite layer chip.

[0068] Plasma-enhanced chemical vapor deposition (PECVD) is a technology that uses plasma to excite reactive gases (such as CH4 / H2) to generate active free radicals, enabling the growth of high-quality graphene at low temperatures. Its core is to control the plasma density and energy distribution through electromagnetic fields, reducing the energy barrier for carbon source decomposition and promoting the uniform nucleation and directional growth of single-layer graphene.

[0069] Furthermore, an oxygen-free environment is established under high-purity argon purge, the substrate is heated and a bias voltage is applied to adsorb the carbon source;

[0070] Optimally, establishing an oxygen-free environment under a high-purity argon purge, heating the substrate, and applying a bias voltage to adsorb the carbon source effectively removes oxygen and impurities from the growth environment, improving carbon source utilization and preventing oxidation defects in the graphene layer. This ensures high graphene crystallinity and integrity while enhancing the interfacial bonding between the graphene and nanoporous silver layers, thereby improving the stability of the composite structure. Furthermore, applying a bias voltage promotes directional adsorption and uniform distribution of the carbon source, further optimizing the graphene deposition process and providing a material foundation for the preparation of high-quality, low-defect graphene / nanoporous silver composite layers.

[0071] Using adaptive plasma density to control the graphene growth environment;

[0072] Under argon protection, a biased carbon source is adsorbed and plasma is excited, allowing hydrogen plasma to etch the amorphous carbon layer and inhibit the formation of polycrystalline graphene. Simultaneously, methane dissociates into carbon radicals in the plasma, which preferentially adsorb onto lattice defect sites induced by the nickel atom beam, achieving the preferred orientation growth of single-layer graphene. This adaptive control eliminates the uneven graphene thickness caused by temperature gradients or uneven gas diffusion in traditional fixed-parameter processes, thereby reducing defect density.

[0073] A real-time feedback system dynamically adjusts plasma power, gas flow ratio (H2 / CH4), and bias voltage parameters to maintain an optimal match between plasma density and activity within the reaction chamber. For example, optical emission spectroscopy (OES) is used to monitor characteristic plasma spectral lines (such as CⅡ426.7nm), and a PID algorithm is used to dynamically adjust power to ensure a balance between graphene growth rate and defect rate.

[0074] Adaptive plasma density control (APDC) uses a microwave source (e.g., frequency f=2.45 GHz) to excite methane plasma, monitors the plasma density in real time, and dynamically adjusts the power based on the feedback To maintain the best growth environment, the expression is as follows:

[0075] ;

[0076] in, is the plasma density during the growth process, is the initial plasma density, is the initial plasma density of the reaction, is the plasma power adjustment coefficient, which is used to determine the sensitivity of plasma density to power changes. is the real-time plasma power, is the currently applied plasma power, is the expected plasma power, is the optimized target power, is the electron energy sensitivity coefficient, which is used to describe the effect of electron energy deviating from the optimal value. is the current electron energy, is the energy distribution of electrons in the reaction zone, is the optimal electron energy, which is the optimal electron energy value to ensure the high-quality growth of single-layer graphene.

[0077] To ensure plasma stability during plasma-enhanced chemical vapor deposition (PECVD), and to improve the uniformity and continuity of graphene monolayer growth, the researchers controlled the hydrogen / methane flow ratio and injected nickel atomic beams, allowing for rapid cooling under high-purity argon protection to achieve uniform growth of the graphene monolayer, resulting in a graphene / nanoporous silver composite layer chip. Dynamic power regulation and feedback control enabled real-time stabilization of the plasma density.

[0078] It should be noted that in plasma-enhanced chemical vapor deposition, the plasma density is easily affected by factors such as the reaction gas flow rate and pressure fluctuations, resulting in uneven graphene growth. This solution actively suppresses density fluctuations through closed-loop feedback (monitoring to regulation). Power regulation coefficient Accurately match the sensitivity of power changes to density to avoid local overheating or underactivation, ensure the continuity of the graphene lattice, and the current electron energy Deviation hour, The term triggers a compensation mechanism, suppressing the generation of non-stoichiometric ratios or defect states and improving the sp² hybridization degree of single-layer graphene.

[0079] By quantifying the control parameters through mathematical models, process repeatability and controllability are achieved. The formula converts the abstract plasma state into measurable physical quantities (power, electron energy), providing a theoretical basis for process optimization. and , can quickly adapt to different reaction chamber or substrate conditions, shortening the R&D cycle. The hydrogen / methane (H2 / CH4) flow ratio is controlled, and nickel atomic beam injection is introduced. Rapid cooling under high-purity argon protection enables uniform growth of single-layer graphene. By controlling the H2 / CH4 ratio, the carbon source concentration and reducing environment are optimized. Methane, as a carbon source, needs to be cracked in a hydrogen-rich environment to avoid carbon deposition. Properly reducing the H2 ratio can inhibit side reactions (such as the complete decomposition of CH4 into C and H2) and reduce amorphous carbon deposition. Excessive H2 dilutes the reactants, while too low a level can lead to uncontrolled graphene layer growth. Dynamically adjusting the flow ratio achieves a trade-off between rate and quality.

[0080] Nickel atom beam implantation provides catalytic active sites and guides graphene nucleation.

[0081] Among them, nickel is a typical catalyst that can reduce the energy barrier for graphene nucleation and promote uniform nucleation. Nickel atoms adsorb on the substrate surface, guiding the orderly arrangement of carbon atoms and reducing the density of grain boundaries. Nickel atoms combine with unsaturated bonds to passivate edge defects, improve carrier mobility, lock the single-layer structure through rapid cooling, and inhibit interlayer diffusion. At high temperatures, graphene easily stacks to form multiple layers. Rapid cooling freezes the single-layer structure and combines with the template effect of the nickel atom beam to achieve a single-layer coverage rate of >95%. Slow cooling can easily lead to lattice distortion, while rapid cooling retains an atomically smooth interface and enhances carrier transport efficiency. Adaptive plasma density control ensures that the graphene layer uniformly covers the nanoporous silver layer, avoiding interfacial thermal resistance caused by local poor contact.

[0082] By optimizing Matching the work function of the silver layer improves the ohmic contact between graphene and silver, reducing the device's on-resistance. The uniform graphene layer significantly increases the module's thermal conductivity, mitigating heat accumulation in SiC devices caused by high-frequency switching. The mechanical interlocking structure of low-defect-density graphene and nanoporous silver withstands high- and low-temperature cycling tests, meeting automotive-grade reliability requirements.

[0083] The most advanced approach combines adaptive plasma density control (APDC) with nickel-catalyzed synergistic growth, solving the challenge of uniform nucleation of monolayer graphene on complex substrates. This "dynamic feedback control + multi-physics field collaboration" approach achieves full-chain optimization from atomic-scale growth to macro-module performance, demonstrating the deep integration of precision manufacturing and materials science.

[0084] S4. After aligning the graphene / nanoporous silver composite layer chip with the ceramic substrate, perform segmented pressure sintering in a vacuum sintering furnace to output a SiC power module.

[0085] Furthermore, segmented pressure sintering in a vacuum sintering furnace refers to segmented pressure sintering through electromagnetic assistance and ultrasonic pre-pressing to optimize the densification of the nanoporous silver layer. Laser interferometry technology is used to perform high-precision alignment of the graphene / nanoporous silver composite layer chip and the ceramic substrate, and electrostatic adsorption technology is used to achieve temporary fixation, avoiding traditional mechanical alignment errors and improving interface uniformity. In a vacuum sintering chamber, the interface oxide layer is removed by dynamic control using an Ar / H2 atmosphere, and the temperature is maintained at 450°C for 10 minutes to activate the surface and improve the diffusion capacity of the sintering interface.

[0086] By using electromagnetic assistance and ultrasonic pre-pressing technology to perform segmented pressure sintering, the densification process of nanoporous silver is optimized to achieve high-strength interface connection.

[0087] Among them, the staged pressure sintering, for example, the initial low-pressure diffusion stage (T1=500°C, P1=0.5MPa, t1=15min) promotes the surface migration of silver nanoparticles through low-temperature and low-pressure diffusion to ensure good interface bonding; the stress-relieving medium-temperature sintering stage (T2=750°C, P2=2MPa, t2=20min) adopts pulsed current sintering technology (PCS) to activate the interface diffusion between graphene and silver and reduce thermal stress accumulation; the high-temperature densification sintering stage (T3=850°C, P3=5MPa, t3=10min) applies high pressure to increase density, and eliminates micropores through ultrasonic oscillation to ensure interface stability.

[0088] A nonlinear cooling curve is used to control the thermal stress release of SiC power modules and prevent interface cracking.

[0089] For example, the nonlinear cooling curve is 850°C→600°C: cooling at 5°C / min to reduce thermal shock; 600°C→300°C: gradually releasing the interface residual stress at 2°C / min; 300°C→room temperature: natural cooling under nitrogen protection to improve interface reliability.

[0090] Nano-X-ray computed tomography is used to evaluate the sintering interface microstructure to ensure that there are no significant holes or cracks; tensile shear tests are used to verify the bonding strength to ensure that the standards are met, ultimately outputting high-stability SiC power modules.

[0091] S5. Apply epoxy resin encapsulation glue to the SiC power module, perform UV curing and annealing treatment to eliminate internal stress and enhance corrosion resistance.

[0092] Furthermore, the SiC power module surface is electrostatically sprayed with epoxy encapsulant, which is then cured internally using multi-band UV light. In a vacuum sintering furnace, O2+Ar plasma is used to remove contaminants from the SiC module surface, improving its compatibility. A high-voltage electrostatic field is used to atomize the epoxy resin and then spray it onto the SiC module surface, forming a uniform coating.

[0093] Multi-band UV light (UVA and UVC combination) ensures full curing of the encapsulant and reduces stress gradients. Initial exposure promotes rapid crosslinking of the surface layer to avoid solvent residue. Deep curing uses high-penetration UV light to complete internal crosslinking of the colloid and enhance adhesion strength.

[0094] Thermal-acoustic combined annealing is used to release the interface residual stress through temperature gradient and ultrasonic oscillation.

[0095] The step-by-step temperature annealing is, for example, stage 1 (T1=80°C, t1=30min), the low-temperature stage promotes colloid flow and improves interfacial wettability; stage 2 (T2=150°C, t2=60min), the medium-temperature stage triggers cross-linking network structure optimization and releases stress; stage 3 (T3=200°C, t3=20min), the high-temperature stage improves weather resistance and enhances crack resistance.

[0096] This promotes microstructural rearrangement, reduces stress concentration areas, and improves interface reliability. A sol-gel process forms a SiO2 nano-protective layer on the surface of the encapsulation layer, enhancing corrosion resistance. Accelerated aging testing in a humidity environment ensures the long-term stability of the encapsulation layer, ultimately resulting in a highly reliable SiC power module.

[0097] S6. Place the SiC power module in a high and low temperature cycle test chamber for thermal cycle testing.

[0098] Furthermore, before thermal cycling testing, the SiC power module must be in a standardized state to ensure accurate and repeatable test results. Absolute ethanol and plasma cleaning techniques are used to remove contaminants from the module surface to prevent contamination from affecting thermal conductivity during testing. The module's on-resistance is measured using the four-probe method, and an LCR meter is used to record parasitic inductance and capacitance as baseline values.

[0099] A nonlinear temperature cycling mode with gradient temperature control and isothermal hold is used to improve thermal stress uniformity and simulate actual operating environments. Based on the SiC power module's operating environment, a cycling range of -55°C to 200°C is set to cover extreme temperature variations. A nonlinear rate curve is used to reduce stress concentration caused by thermal shock. The highest and lowest temperatures are maintained for 15 minutes each to ensure the material fully responds to thermal expansion and contraction.

[0100] Thermal cycling testing involves repeatedly cycling between extreme high and low temperatures to evaluate the structural stability, electrical performance changes, and fatigue life of SiC power modules under thermal stress. During the thermal cycling process, the temperature gradient, stress distribution, and key parameter changes within the SiC power module are monitored in real time. Fiber optic sensors are embedded within the packaging layer to monitor internal thermal stress changes. During the test, a high-resolution infrared thermal imager records the module surface temperature distribution and identifies areas of potential thermal stress concentration.

[0101] The standard test setting is, for example, 1000 cycles, and module lifespan is determined in advance by monitoring electrical parameter drift. Finite element simulation is used to calculate the stress distribution of the SiC solder joints. After returning to room temperature, electrical parameters are measured again to confirm whether there are transient failures. Initial data is compared with post-test data. If the on-resistance, parasitic inductance, and capacitance change by more than 20%, the module is considered failed; otherwise, the test passes.

[0102] S7. After screening the SiC power modules and conducting XRD and SEM tests, they are coated with a high-temperature resistant silicone sealing layer and cured to produce the finished product.

[0103] Furthermore, the SiC power module is placed in an X-ray diffractometer (XRD), and the Cu-Kα radiation and scanning angle range are set to obtain the diffraction spectrum of the SiC material. According to the Bragg formula:

[0104] ;

[0105] in, is the diffraction order, is the interplanar spacing, The diffraction angle is calculated to determine the lattice parameters of SiC, confirm whether there are impurities or defects, and ensure the integrity of the material structure. is the wavelength.

[0106] SiC power module samples that passed XRD screening were placed in a scanning electron microscope (SEM). Secondary electron imaging (SE) was used to observe the surface morphology at a selected accelerating voltage, and backscattered electron imaging (BSE) was used to analyze the material's compositional distribution. The thickness of the interface bonding layer was measured to ensure the absence of cracks, voids, or severe defects, thereby improving the long-term stability of the device.

[0107] SiC power modules that pass XRD and SEM screening are placed in a clean, dust-free environment and evenly coated with a high-temperature-resistant silicone layer (PDMS, polydimethylsiloxane) using an automatic coating machine. A controllable flow nozzle ensures that the silicone coating evenly covers the module surface, improving the module's resistance to moisture and heat and dielectric strength.

[0108] After coating, it is placed in a constant temperature oven for two-step curing.

[0109] For example, the two-step curing process involves a low-temperature pre-curing step at 80°C for one hour to promote solvent evaporation and prevent residual bubbles. The second step involves a high-temperature cross-linking curing step at 150°C for two hours, utilizing thermal cross-linking to enhance high-temperature resistance and improve interface stability. After curing, the SiC power module's sealing layer thickness is measured, and its reliability is verified through high- and low-temperature cycling testing. Finally, qualified products are screened and shipped as finished products.

[0110] The best ones, through XRD+SEM combined screening, precise silicone coating control, and thermal cross-linking curing optimization, effectively improve the sealing, temperature resistance and long-term stability of the SiC power module, reduce the interface stress, and improve the weather resistance and electrical insulation capability.

[0111] This embodiment also provides a computer device suitable for the SiC power module sintering packaging method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the SiC power module sintering packaging method proposed in the above embodiment.

[0112] The computer device may be a terminal, comprising a processor, memory, a communication interface, a display, and an input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system and computer programs. The internal memory provides an environment for the operating system and computer programs stored in the non-volatile storage media. The communication interface of the computer device is used to communicate with external terminals via wired or wireless communication. Wireless communication may be achieved via Wi-Fi, a carrier network, NFC (near-field communication), or other technologies. The display of the computer device may be a liquid crystal display or an electronic ink display. The input device may be a touchscreen overlay on the display, buttons, a trackball, or a touchpad on the computer device housing, or an external keyboard, touchpad, or mouse.

[0113] This embodiment also provides a storage medium having a computer program stored thereon. When the program is executed by a processor, the method for sintering and packaging a SiC power module as proposed in the above embodiment is implemented. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0114] In summary, the present invention optimizes the packaging process of the SiC power module and deposits a single layer of graphene on the surface of the nanoporous silver layer, thereby improving the interface bonding strength and thermal conductivity. A combination of plasma activation and nanosilver slurry spin coating is adopted to form a uniform and dense porous structure of the nanosilver layer during the low-temperature sintering process, thereby reducing the porosity of the sintered layer. Through a segmented pressure sintering process, electromagnetic assistance and ultrasonic pre-pressing are utilized to achieve precise control of sintering densification, reduce the generation of interface microcracks, and effectively release the residual stress of the packaging interface through epoxy resin encapsulation glue coating and thermal-acoustic combined annealing technology, thereby improving the service life and environmental adaptability of the SiC power module.

[0115] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A SiC power module sintering packaging method, characterized by: include, The SiC chip and the ceramic substrate are sequentially subjected to ultrasonic cleaning, plasma activation and drying to obtain an activated ceramic substrate and a SiC chip; The activated ceramic substrate and SiC chip surface are spin-coated with nano-silver paste, and a nano-porous silver layer is formed through pre-curing and low-temperature sintering. On the surface of the nanoporous silver layer, a single layer of graphene is grown by plasma-enhanced chemical vapor deposition to obtain a graphene / nanoporous silver composite layer chip; After aligning the graphene / nanoporous silver composite layer chip with the ceramic substrate, it is subjected to segmented pressure sintering in a vacuum sintering furnace to produce a SiC power module; Apply epoxy resin encapsulation glue, UV curing and annealing to SiC power modules to eliminate internal stress and enhance corrosion resistance; Place the SiC power module in a high and low temperature cycle test chamber for thermal cycle testing; After screening SiC power modules and undergoing XRD and SEM testing, they are coated with a high-temperature resistant silicone sealing layer and cured before being output as finished products.

2. The SiC power module sintering and packaging method according to claim 1, wherein: The pre-curing and low-temperature sintering to form the nanoporous silver layer are specifically performed as follows: The activated SiC chip and ceramic substrate are fixed on an automatic spin coater and spin-coated, and then placed in an automatic heating device for pre-curing; After pre-curing, the nanoparticles are sintered in a vacuum sintering furnace at a low temperature to partially fuse the nanosilver particles and form a nanoporous silver layer. During the sintering process, microscopic images are collected through online high-resolution optical monitoring, and a mathematical model is established to evaluate the quality of the silver layer in real time.

3. The SiC power module sintering and packaging method according to claim 1, wherein: The specific steps of growing a single layer of graphene by plasma enhanced chemical vapor deposition are as follows: An oxygen-free environment is established under high-purity argon purge, the substrate is heated, and a bias voltage is applied to adsorb the carbon source; Using adaptive plasma density to control the graphene growth environment; By regulating the hydrogen / methane flow ratio and nickel atomic beam injection, the graphene monolayer grows uniformly, obtaining a graphene / nanoporous silver composite layer chip.

4. The SiC power module sintering and packaging method according to claim 1, wherein: The specific steps of epoxy resin encapsulation adhesive coating, UV curing and annealing are as follows: The surface of the SiC power module is electrostatically sprayed with epoxy resin encapsulation glue, and the encapsulation glue is internally cured using multi-band ultraviolet light; Thermal-acoustic combined annealing is used to release the interface residual stress through temperature gradient and ultrasonic oscillation.

5. The SiC power module sintering and packaging method according to claim 1, wherein: The ultrasonic cleaning, plasma activation and drying treatment utilizes an ultrasonic cleaning method to remove surface oil stains, particulate pollutants and plasma treatment.

6. The SiC power module sintering and packaging method according to claim 1, wherein: The segmented pressure sintering in the vacuum sintering furnace refers to segmented pressure sintering through electromagnetic assistance and ultrasonic pre-pressing, which is used to optimize the densification of the nanoporous silver layer.

7. The SiC power module sintering and packaging method according to claim 1, wherein: The thermal cycle test is a test that evaluates the structural stability, electrical performance changes, and fatigue life of SiC power modules under temperature stress by repeatedly cycling between high and low temperature extreme environments.

8. The SiC power module sintering and packaging method according to claim 1, wherein: The XRD test is used to analyze the crystal structure and phase composition of the SiC power module, while the SEM test is used to observe its micromorphology, interface bonding and defect distribution.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the SiC power module sintering packaging method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the SiC power module sintering packaging method according to any one of claims 1 to 8 are implemented.

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