Low-jitter injection-locked phase-locked loop based on multiphase injection

Abstract

The invention relates to the technical field of radio frequency integrated circuits, and particularly provides a low-jitter injection locking phase-locked loop based on multiphase injection, which comprises an injection locking path unit, a locking unit and an injection locking ring oscillator, the injection locking path unit can generate a multi-phase injection signal and a complementary injection signal according to the received reference signal; the injection locking ring oscillator receives the multi-phase injection signal and the complementary injection signal and then generates an oscillation signal; and then the locking unit locks the injection locking phase-locked loop according to the generated oscillation signal. According to the invention, the injection locking path unit generates the multi-phase injection signal and the complementary injection signal, so that the injection locking ring oscillator is subjected to multi-phase direct injection and cross coupling complementary injection, and the multi-phase direct injection can reduce the jitter of the phase-locked loop based on the ring oscillator. And phase deviation generated by multi-phase direct injection is eliminated through cross coupling complementary injection, so that the injection intensity is further improved, and the noise suppression bandwidth is effectively expanded.

Description

Technical Field

[0001] The present application relates to the technical field of radio frequency integrated circuits, and in particular to a low-jitter injection-locked phase-locked loop based on multi-phase injection. Background Art

[0002] A phase-locked loop (PLL) is a sophisticated electronic control system whose core function is to automatically and precisely track and lock the phase and frequency of an output signal to an input reference signal. It continuously compares the phase difference between the input signal and the output signal, converting this difference into an error voltage. This error is then processed by a loop filter to control the output frequency of a voltage-controlled oscillator, thus forming a closed feedback loop. The ultimate goal is to reduce the phase error to near zero, achieving high synchronization of the output and input signals in frequency and phase. Due to this characteristic, PLLs are widely used in frequency synthesis, clock recovery, modulation and demodulation, and various electronic systems requiring high-precision clock synchronization.

[0003] In system-on-chip (SoC) design, phase-locked loops (PLLs) based on ring oscillators are highly favored due to their significant advantages: compared to LC oscillator-based PLLs, they offer a wider frequency tuning range (accommodating multi-band requirements), an extremely compact circuit structure (saving area and reducing cost), and the ability to naturally output multiphase clocks (e.g., quadrature signals, crucial for high-speed serial interfaces and clock distribution networks). However, their inherently poor phase noise and jitter performance present a key bottleneck. This high jitter significantly increases the timing uncertainty of the clock signal, making it difficult to meet the performance requirements of applications with extremely stringent timing accuracy and noise requirements, such as high-speed ADC / DAC sampling clocks and millimeter-wave communications. Therefore, despite their significant advantages in area and integration, phase noise and jitter issues remain a major constraint limiting the widespread adoption of ring oscillator PLLs in high-performance applications.

[0004] Therefore, effectively improving the phase noise suppression capability and jitter performance of the ring oscillator-based phase-locked loop to overcome its inherent defects and fully unleash its application potential in wide tuning range, small area and multi-phase output is a key technical challenge that urgently needs to be solved by technicians in this field. Summary of the Invention

[0005] To address the above problems, the present application provides a low-jitter injection-locked phase-locked loop based on multi-phase injection, which not only reduces the jitter of the phase-locked loop based on the ring oscillator, but also improves the phase noise suppression capability of the phase-locked loop based on the ring oscillator.

[0006] To achieve the purpose of this application, this application provides the following technical solutions: The present application provides a low-jitter injection-locked phase-locked loop based on multi-phase injection, comprising: an injection-locked path unit and an injection-locked phase-locked loop; The injection locked phase locked loop comprises a locking unit and an injection locked ring oscillator, wherein the input end of the injection locked ring oscillator is connected to the output end of the locking unit and the output end of the injection locked path unit; The input end of the locking unit is connected to the output end of the injection locked ring oscillator; The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal, wherein the injection signal includes a multi-phase injection signal and a complementary injection signal; The injection-locked ring oscillator is configured to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit; The locking unit is configured to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal, wherein the first signal is used to lock the injection-locked phase-locked loop.

[0007] Furthermore, the injection locking path unit includes a pulse generator, a phase shifter and a complementary injection unit; The input end of the pulse generator is connected to the reference signal, and the output end is connected to the input end of the phase shifter, the input end of the complementary injection unit and the input end of the injection locked ring oscillator; The output end of the phase shifter and the output end of the complementary injection unit are both connected to the input end of the injection locked ring oscillator; The multi-phase injection signal includes a first phase-shifted injection signal, a second phase-shifted injection signal and a third phase-shifted injection signal; The pulse generator is used to receive a reference signal and generate a first phase-shifted injection signal based on the reference signal; The phase shifter is configured to receive the first phase-shifted injection signal and generate the second phase-shifted injection signal and the third phase-shifted injection signal based on the first phase-shifted injection signal; The complementary injection unit is configured to receive the first phase-shifted injection signal and generate the complementary injection signal based on the first phase-shifted injection signal.

[0008] Furthermore, in the multi-phase injection signal, the phase shifts of the first phase-shifted injection signal, the second phase-shifted injection signal, and the third phase-shifted injection signal are 60°, 120°, and 180°, respectively.

[0009] Furthermore, the pulse generator includes an AND gate, a first NOT gate and a variable delay unit; The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal; The input end of the first NOT gate is connected to the output end of the variable delay unit; The second input end of the AND gate is connected to the output end of the first NOT gate; The AND gate is configured to receive the reference signal and the signal output by the first NOT gate, and generate the first phase-shifted injection signal based on the reference signal and the signal output by the first NOT gate.

[0010] Further, the phase shifter includes a polyphase filter and a dual Gilbert unit; The polyphase filter includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor; One end of the first resistor is commonly connected to the positive input end of the polyphase filter and one end of the first capacitor, and the other end of the first resistor is commonly connected to one end of the second resistor, one end of the second capacitor, and one end of the seventh capacitor; The other end of the second resistor is connected to one end of the eighth capacitor and the first output end of the polyphase filter; One end of the third resistor and one end of the third capacitor are both grounded, and the other end is commonly connected to the other end of the first capacitor, one end of the fourth resistor, and one end of the fourth capacitor; The other end of the fourth resistor is commonly connected to the other end of the second capacitor and the second output end of the polyphase filter; One end of the fifth resistor and one end of the fifth capacitor are both grounded, and the other end is commonly connected to the other end of the third capacitor, one end of the sixth resistor, and one end of the sixth capacitor; The other end of the sixth resistor is commonly connected to the other end of the fourth capacitor and the third output end of the polyphase filter; One end of the seventh resistor is commonly connected to the other end of the seventh capacitor and the negative input end of the polyphase filter, and the other end of the seventh resistor is commonly connected to the other end of the fifth capacitor, the other end of the eighth capacitor, and one end of the eighth resistor; The other end of the eighth resistor is commonly connected to the other end of the sixth capacitor and the fourth output end of the polyphase filter; The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the polyphase filter are connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the dual Gilbert unit respectively.

[0011] Furthermore, the dual Gilbert unit includes a ninth resistor, a tenth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. A first input terminal of the dual Gilbert unit is commonly connected to the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor, a second input terminal is commonly connected to the gates of the eighteenth NMOS transistor and the fifteenth NMOS transistor, a third input terminal is commonly connected to the gates of the eleventh NMOS transistor and the fourteenth NMOS transistor, a fourth input terminal is connected to the gates of the sixteenth NMOS transistor and the seventeenth NMOS transistor, a first output terminal is commonly connected to the drains of the eleventh NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor, and the seventeenth NMOS transistor, and one end of the ninth resistor, and a second output terminal is commonly connected to the drains of the twelfth NMOS transistor, the fourteenth NMOS transistor, the sixteenth NMOS transistor, and the eighteenth NMOS transistor, and one end of the tenth resistor; The other end of the ninth resistor and the other end of the tenth resistor are both connected to a power supply; The gates of the first NMOS transistor and the second NMOS transistor are both connected to a fixed bias voltage; The drain of the first NMOS transistor is commonly connected to the sources of the seventh NMOS transistor and the eighth NMOS transistor; the drain of the second NMOS transistor is commonly connected to the sources of the ninth NMOS transistor and the tenth NMOS transistor; The drain of the seventh NMOS transistor is commonly connected to the sources of the eleventh NMOS transistor and the twelfth NMOS transistor; the drain of the eighth NMOS transistor is commonly connected to the sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor; the drain of the ninth NMOS transistor is commonly connected to the sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor; and the drain of the tenth NMOS transistor is commonly connected to the sources of the seventeenth NMOS transistor and the eighteenth NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, and the drain is commonly connected to the gate of the seventh NMOS transistor and the source of the first PMOS transistor; the gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor, and the drain is commonly connected to the gate of the eighth NMOS transistor and the source of the second PMOS transistor; the drains of the first PMOS transistor and the second PMOS transistor are connected; The gate of the fifth NMOS transistor is connected to the gate of the third PMOS transistor, and the drain is commonly connected to the gate of the ninth NMOS transistor and the source of the third PMOS transistor; the gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain is commonly connected to the gate of the tenth NMOS transistor and the source of the fourth PMOS transistor; the drain of the third PMOS transistor is connected to the drain of the fourth PMOS transistor; Sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all grounded.

[0012] Furthermore, the complementary injection unit includes a second NOT gate and a transmission gate; The input ends of the second NOT gate and the transmission gate are both connected to the output end of the pulse generator; The output ends of the second NOT gate and the transmission gate are connected to the first output end and the second output end of the complementary injection unit respectively; The second NOT gate is configured to receive the first phase-shifted injection signal and generate a first complementary injection signal based on the first phase-shifted injection signal; The transmission gate is configured to receive the first phase-shifted injection signal and generate a second complementary injection signal based on the first phase-shifted injection signal.

[0013] Furthermore, the injection-locked ring oscillator includes three injection tubes and three differential delay units, and the injection tubes are NMOS tubes; The first input terminal and the second input terminal of the first differential delay unit are connected to the first output terminal and the second output terminal of the third differential delay unit, respectively; the first input terminal and the second input terminal of the second differential delay unit are connected to the first output terminal and the second output terminal of the first differential delay unit, respectively; the first input terminal and the second input terminal of the third differential delay unit are connected to the first output terminal and the second output terminal of the second differential delay unit, respectively; The gate of the first injection tube is connected to the output end of the pulse generator, and the drain and source are connected to the first output end and the second output end of the first differential delay unit respectively; the gate of the second injection tube is connected to the first output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the second differential delay unit respectively; the gate of the third injection tube is connected to the second output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the third differential delay unit respectively; The third input terminal and the fourth input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal; The first injection tube, the second injection tube and the third injection tube are used to receive the first phase-shifted injection signal, the second phase-shifted injection signal and the third phase-shifted injection signal respectively.

[0014] Furthermore, the second differential delay unit includes a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; The first input terminal of the second differential delay unit is commonly connected to the gates of the 20th NMOS transistor and the 6th PMOS transistor, the second input terminal is commonly connected to the gates of the 19th NMOS transistor and the 5th PMOS transistor, the first output terminal is commonly connected to the drains of the 20th NMOS transistor, the 6th PMOS transistor, the second injection transistor, the 24th NMOS transistor, and the 10th PMOS transistor, and the gates of the 22nd NMOS transistor and the 8th PMOS transistor, and the second output terminal is commonly connected to the drains of the 19th NMOS transistor, the 5th PMOS transistor, the 22nd NMOS transistor, and the 8th PMOS transistor, the gates of the 24th NMOS transistor and the 10th PMOS transistor, and the source of the second injection transistor; The gates of the seventh PMOS transistor and the ninth PMOS transistor are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal; The gates of the twenty-first NMOS transistor and the twenty-third NMOS transistor are both connected to the fourth input terminal of the second differential delay unit, for receiving the second complementary injection signal; The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the drain of the twenty-first NMOS transistor is connected to the source of the twenty-second NMOS transistor; and the drain of the twenty-third NMOS transistor is connected to the source of the twenty-fourth NMOS transistor. The sources of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the ninth PMOS transistor are all connected to a power supply; Sources of the nineteenth NMOS transistor, the twentieth NMOS transistor, the twenty-first NMOS transistor, and the twenty-third NMOS transistor are all grounded.

[0015] Furthermore, the locking unit includes a sub-sampling loop unit, a frequency-locked loop unit, a loop filter and a buffer; The input end of the loop filter is connected to the output end of the sub-sampling loop unit and the output end of the frequency-locked loop unit, and the output end is connected to the input end of the injection-locked ring oscillator; The loop filter is configured to receive a current signal and generate the control voltage signal based on the current signal, the current signal including a first current signal and a second current signal, the first current signal and the second current signal being current signals output by the sub-sampling loop unit and the frequency-locked loop unit, respectively; the control voltage signal including a first control voltage signal and a second control voltage signal, the first control voltage signal being generated based on the first current signal, and the second control voltage signal being generated based on the second current signal; The input end of the buffer is connected to the output end of the injection locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain a second oscillation signal; The frequency-locked loop unit includes a frequency divider, a phase frequency detector, and a charge pump; the input end of the frequency divider is connected to the output end of the buffer; the first input end of the phase frequency detector is connected to the output end of the frequency divider, and the second input end is connected to the reference signal; the input end of the charge pump is connected to the output end of the phase frequency detector, and the output end is connected to the input end of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal; The sub-sampling loop unit includes a sub-sampling phase detector and a transconductance module; a first input end of the sub-sampling phase detector is connected to a reference signal, and a second input end is connected to an output end of the buffer; an input end of the transconductance module is connected to an output end of the sub-sampling phase detector, and an output end is connected to the loop filter; the sub-sampling loop unit is used to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

[0016] Beneficial effects: The present application generates a multi-phase injection signal and a complementary injection signal through an injection-locked path unit, thereby performing multi-phase direct injection and cross-coupled complementary injection on an injection-locked ring oscillator. The multi-phase direct injection can reduce the jitter of a phase-locked loop based on a ring oscillator, and then multi-path injection is performed through cross-coupled complementary injection, thereby eliminating the phase offset caused by the multi-phase direct injection, further improving the injection strength, and effectively expanding the noise suppression bandwidth of the phase-locked loop based on the ring oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not limit the present application. Figure 1 A schematic diagram of the structure of a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application; Figure 3 A circuit diagram of a pulse generator for a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application; Figure 4 A schematic diagram of signal injection into a phase shifter and an injection-locked ring oscillator of a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application; Figure 5 A circuit diagram of a polyphase filter of a low-jitter injection-locked phase-locked loop based on polyphase injection provided in an embodiment of the present application; Figure 6 A circuit structure diagram of a dual Gilbert unit of a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application; Figure 7 This is a circuit structure diagram of a second differential delay unit of a ring oscillator of a low-jitter injection-locked phase-locked loop based on multi-phase injection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features; and in the description of this application, unless otherwise specified, "plurality" means two or more.

[0020] A low-jitter injection-locked phase-locked loop based on multi-phase injection according to an embodiment of the present application includes: an injection-locked path unit and an injection-locked phase-locked loop; The injection locked phase locked loop comprises a locking unit and an injection locked ring oscillator, wherein the input end of the injection locked ring oscillator is connected to the output end of the locking unit and the output end of the injection locked path unit; The input end of the locking unit is connected to the output end of the injection locked ring oscillator; The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal, wherein the injection signal includes a multi-phase injection signal and a complementary injection signal; The injection-locked ring oscillator is configured to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit; The locking unit is configured to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal, wherein the first signal is used to lock the injection-locked phase-locked loop.

[0021] The technical solution of the present invention is described below with reference to the embodiments shown in the accompanying drawings: like Figure 1 As shown, a low-jitter injection-locked phase-locked loop based on multi-phase injection includes an injection-locked path unit 11 and an injection-locked phase-locked loop 12; The injection-locked phase-locked loop 12 comprises a locking unit 121 and an injection-locked ring oscillator 122, wherein the input end of the injection-locked ring oscillator 122 is connected to the output end of the locking unit 121 and the output end of the injection-locked path unit 11; The input end of the locking unit 121 is connected to the output end of the injection locked ring oscillator 122; The injection locking path unit 11 is used to receive a reference signal and generate an injection signal based on the reference signal, wherein the injection signal includes a multi-phase injection signal and a complementary injection signal; The injection-locked ring oscillator 122 is configured to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is the control voltage signal output by the locking unit 121; The locking unit 121 is configured to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal, where the first signal is used to lock the injection-locked phase-locked loop 12 .

[0022] It should be noted that phase noise and jitter are both major factors limiting the widespread application of ring oscillator phase-locked loops in high-performance applications. Therefore, both issues need to be addressed simultaneously to enable ring oscillator phase-locked loops to be applied in wide tuning ranges, small footprints, and multi-phase outputs. Therefore, the injection-locked path unit of the present invention not only improves the jitter performance of the ring oscillator phase-locked loop through multi-phase injection, but also performs multipath injection by simultaneously utilizing direct injection and cross-coupled complementary injection. The injection of complementary injection signals eliminates the phase offset of direct injection, thereby further increasing the injection strength and expanding the noise suppression bandwidth.

[0023] In the embodiments of this application, Figure 2 As shown, the injection locking path unit includes a pulse generator, a phase shifter and a complementary injection unit; The input end of the pulse generator is connected to the reference signal, and the output end is connected to the input end of the phase shifter, the input end of the complementary injection unit and the input end of the injection locked ring oscillator; The output end of the phase shifter and the output end of the complementary injection unit are both connected to the input end of the injection locked ring oscillator; The multi-phase injection signal includes a first phase-shifted injection signal, a second phase-shifted injection signal and a third phase-shifted injection signal; The pulse generator is used to receive a reference signal and generate a first phase-shifted injection signal based on the reference signal; The phase shifter is configured to receive the first phase-shifted injection signal and generate the second phase-shifted injection signal and the third phase-shifted injection signal based on the first phase-shifted injection signal; The complementary injection unit is configured to receive the first phase-shifted injection signal and generate the complementary injection signal based on the first phase-shifted injection signal.

[0024] It can be understood that the pulse generator generates a first phase-shifted injection signal based on the reference signal, uses the first phase-shifted injection signal as the initial signal, and generates a second phase-shifted injection signal and a third phase-shifted injection signal after processing by the phase shifter. The first phase-shifted injection signal, the second phase-shifted injection signal, and the third phase-shifted injection signal correspond to the three differential delay units of the injection-locked ring oscillator, respectively, thereby performing multi-phase direct injection into the injection-locked ring oscillator. The first phase-shifted injection signal is passed through the complementary injection unit to generate a complementary injection signal, which is used for subsequent cross-coupled complementary injection into the injection-locked ring oscillator.

[0025] In this embodiment, in the multi-phase injection signal, the phase shifts of the first phase-shifted injection signal, the second phase-shifted injection signal, and the third phase-shifted injection signal are 60°, 120°, and 180°, respectively.

[0026] It is understood that since this embodiment uses a three-stage ring oscillator, the output phase shift difference of each differential delay unit in the three-stage ring oscillator is 60° to meet oscillation conditions. Therefore, the phase shift of the multi-phase injection signal should correspond to the output phase shift of each differential delay unit in the three-stage ring oscillator to achieve a good injection effect.

[0027] In this embodiment, if Figure 3 As shown, the pulse generator includes an AND gate, a first NOT gate and a variable delay unit; The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal; The input end of the first NOT gate is connected to the output end of the variable delay unit; The second input end of the AND gate is connected to the output end of the first NOT gate; The AND gate is configured to receive the reference signal and the signal output by the first NOT gate, and generate the first phase-shifted injection signal based on the reference signal and the signal output by the first NOT gate.

[0028] It is understandable that the pulse generator uses an AND gate, a variable delay unit, and a first NOT gate to form a narrow pulse generation circuit. The reference signal is delayed by the variable delay unit, flipped by the NOT gate, and then input into the AND gate together with the original reference signal. The logical AND is used to generate a Pul_60 narrow pulse, that is, a 60° phase-shifted pulse. The variable delay unit uses a transistor-level delay unit design to achieve precise adjustable delay. If its delay is , then the narrow pulse width of the AND gate output is also , the pulse signal serves as the initial injection signal, that is, the first phase-shifted injection signal.

[0029] In this embodiment, if Figure 4 As shown, the phase shifter includes a polyphase filter and a dual Gilbert unit; like Figure 5 As shown, the polyphase filter includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8; One end of the first resistor R1 is commonly connected to the positive input terminal VIN+ of the polyphase filter and one end of the first capacitor C1, and the other end is commonly connected to one end of the second resistor R2, one end of the second capacitor C2, and one end of the seventh capacitor C7; The other end of the second resistor R2 is connected to one end of the eighth capacitor C8 and the first output terminal VI- of the polyphase filter; One end of the third resistor R3 and one end of the third capacitor C3 are both grounded, and the other end is commonly connected to the other end of the first capacitor C1, one end of the fourth resistor R4, and one end of the fourth capacitor C4; The other end of the fourth resistor R4 is commonly connected to the other end of the second capacitor C2 and the second output terminal VQ+ of the polyphase filter; One end of the fifth resistor R5 and one end of the fifth capacitor C5 are both grounded, and the other end is commonly connected to the other end of the third capacitor C3, one end of the sixth resistor R6, and one end of the sixth capacitor C6; The other end of the sixth resistor R6 is commonly connected to the other end of the fourth capacitor C4 and the third output terminal VI+ of the polyphase filter; One end of the seventh resistor R7 is commonly connected to the other end of the seventh capacitor C7 and the negative input terminal VIN- of the polyphase filter, and the other end is commonly connected to the other end of the fifth capacitor C5, the other end of the eighth capacitor C8, and one end of the eighth resistor R8; The other end of the eighth resistor R8, the other end of the sixth capacitor C6 and the fourth output end of the polyphase filter are commonly connected to VQ-; The first output terminal VI-, the second output terminal VQ+, the third output terminal VI+ and the fourth output terminal VQ- of the polyphase filter are connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the dual Gilbert unit respectively.

[0030] It can be understood that the input signals of the first input terminal VIN+ and the second input terminal VIN- of the polyphase filter are a pair of differential inverted signals, that is, the first input terminal VIN+ of the polyphase filter is connected to the Pul_60 signal, and the second input terminal is connected to the inverted signal of Pul_60.

[0031] like Figure 6 As shown, the dual Gilbert unit includes a ninth resistor R9, a tenth resistor R10, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The first input terminal I- of the dual Gilbert unit is commonly connected to the gates of the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13, the second input terminal Q+ is commonly connected to the gates of the eighteenth NMOS transistor N18 and the fifteenth NMOS transistor N15, the third input terminal I+ is commonly connected to the gates of the eleventh NMOS transistor N11 and the fourteenth NMOS transistor N14, the fourth input terminal Q- is connected to the gates of the sixteenth NMOS transistor N16 and the seventeenth NMOS transistor N17, and the first output terminal The second output terminal is commonly connected to the drains of the eleventh NMOS transistor N11, the thirteenth NMOS transistor N13, the fifteenth NMOS transistor N15, and the seventeenth NMOS transistor N17, and one end of the ninth resistor R9. Commonly connected to the drains of the twelfth NMOS transistor N12, the fourteenth NMOS transistor N14, the sixteenth NMOS transistor N16, and the eighteenth NMOS transistor N18, and one end of the tenth resistor R10; The other end of the ninth resistor R9 and the other end of the tenth resistor R10 are both connected to a power supply; The gates of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to a fixed bias voltage; The drain of the first NMOS transistor N1 is commonly connected to the sources of the seventh NMOS transistor N7 and the eighth NMOS transistor N8; the drain of the second NMOS transistor N2 is commonly connected to the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10; The drain of the seventh NMOS transistor N7 is commonly connected to the sources of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12; the drain of the eighth NMOS transistor N8 is commonly connected to the sources of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14; the drain of the ninth NMOS transistor N9 is commonly connected to the sources of the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16; the drain of the tenth NMOS transistor N10 is commonly connected to the sources of the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18; The gate of the third NMOS transistor N3 is connected to the gate of the first PMOS transistor P1, and the drain is commonly connected to the gate of the seventh NMOS transistor N7 and the source of the first PMOS transistor P1; the gate of the fourth NMOS transistor N4 is connected to the gate of the second PMOS transistor P2, and the drain is commonly connected to the gate of the eighth NMOS transistor N8 and the source of the second PMOS transistor P2; the drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected; The gate of the fifth NMOS transistor N5 is connected to the gate of the third PMOS transistor P3, and the drain is commonly connected to the gate of the ninth NMOS transistor N9 and the source of the third PMOS transistor P3; the gate of the sixth NMOS transistor N6 is connected to the gate of the fourth PMOS transistor P4, and the drain is commonly connected to the gate of the tenth NMOS transistor N10 and the source of the fourth PMOS transistor P4; the drain of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4; Sources of the first NMOS transistor N1 , the second NMOS transistor N2 , the third NMOS transistor N3 , the fourth NMOS transistor N4 , the fifth NMOS transistor N5 , and the sixth NMOS transistor N6 are all grounded.

[0032] It is understandable that, combined with Figure 5 and Figure 6As shown, the polyphase filter's first output terminal VI-, second output terminal VQ+, third output terminal VI+, and fourth output terminal VQ- are connected to the first input terminal I-, second input terminal Q+, third input terminal I+, and fourth input terminal Q- of the dual Gilbert unit, respectively. The phase shifter comprises a polyphase filter and a current vector synthesizer. The polyphase filter employs four RC networks, each generating a fixed delay, to filter and phase modulate Pul_60, generating multi-phase pulse signals. The current vector synthesizer, based on a dual Gilbert unit design, vector-adds the RC-filtered multi-phase pulse signals to generate Pul_120 (120° phase shift) and Pul_180 (180° phase shift) pulse signals, which are used with Pul_60 for subsequent multi-phase direct injection. The dual Gilbert unit comprises a first Gilbert unit and a second Gilbert unit. The first Gilbert unit outputs the Pul_120 signal at its output terminal VOUT+, while the second Gilbert unit outputs the Pul_180 signal at its output terminal VOUT+.

[0033] In this embodiment, if Figure 2 As shown, the complementary injection unit includes a second NOT gate and a transmission gate; The input ends of the second NOT gate and the transmission gate are both connected to the output end of the pulse generator; The output ends of the second NOT gate and the transmission gate are connected to the first output end and the second output end of the complementary injection unit respectively; The second NOT gate is configured to receive the first phase-shifted injection signal and generate a first complementary injection signal based on the first phase-shifted injection signal; The transmission gate is configured to receive the first phase-shifted injection signal and generate a second complementary injection signal based on the first phase-shifted injection signal.

[0034] It can be understood that after the transmission gate of the complementary injection unit receives the initial signal Pul_60, it outputs the first complementary injection signal INJ_P; after the second NOT gate of the complementary injection unit receives the initial signal Pul_60, it outputs the second complementary injection signal INJ_N; INJ_N and INJ_P are complementary injection signals, that is, a pair of inverted pulse signals, the signal of the Pul_60 signal after being transmitted through the transmission gate is in phase with the Pul_60 signal, and the signal of the Pul_60 signal after being output by the inverter is in phase with the Pul_60 signal, thus forming a pair of complementary injection signals for subsequent cross-coupled complementary injection.

[0035] In this embodiment, the injection-locked ring oscillator includes three injection tubes and three differential delay units, and the injection tubes are NMOS tubes; The first input terminal and the second input terminal of the first differential delay unit are connected to the first output terminal and the second output terminal of the third differential delay unit, respectively; the first input terminal and the second input terminal of the second differential delay unit are connected to the first output terminal and the second output terminal of the first differential delay unit, respectively; the first input terminal and the second input terminal of the third differential delay unit are connected to the first output terminal and the second output terminal of the second differential delay unit, respectively; The gate of the first injection tube is connected to the output end of the pulse generator, and the drain and source are connected to the first output end and the second output end of the first differential delay unit respectively; the gate of the second injection tube is connected to the first output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the second differential delay unit respectively; the gate of the third injection tube is connected to the second output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the third differential delay unit respectively; The third input terminal and the fourth input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal; The first injection tube, the second injection tube and the third injection tube are used to receive the first phase-shifted injection signal, the second phase-shifted injection signal and the third phase-shifted injection signal respectively.

[0036] It is understandable that if Figure 4 As shown, the injection-locked ring oscillator consists of three stages of differential delay units and three injection tubes. The CK0 and CK180 signals are the inputs to the first-stage delay unit, indicating that the phases of the signals entering the first-stage delay unit are 0° and 180°; the CK60 and CK240 signals are the inputs to the second-stage delay unit, indicating that the phases of the signals entering the second-stage delay unit are 60° and 240°; the CK120 and CK300 signals are the inputs to the third-stage delay unit, indicating that the phases of the signals entering the third-stage delay unit are 120° and 300°. The injection port of the injection tube corresponding to the first-stage differential delay unit is INJ3, which is used to receive the Pul_180 signal; the injection port corresponding to the second-stage differential delay unit is INJ1, which is used to receive the Pul_60 signal; and the injection port corresponding to the third-stage differential delay unit is INJ2, which is used to receive the Pul_120 signal. The delay calculation formula for each stage of the delay unit is: ; in, Delay for each level of delay unit, is the frequency of the oscillator. The clock period of the oscillator can be obtained according to the frequency of the oscillator. The calculation formula is: ; in, is the frequency of the oscillator, is the cycle time of the oscillator, so the total delay of the three stages is The phase shift of each differential delay unit is 60°, meeting the ring oscillator oscillation conditions. An injection tube is connected in parallel to the output of each differential delay unit, and the gate of each injection tube is controlled by the connected multi-phase injection signal. For example, the multi-phase injection signal connected to the gate of the injection tube connected in parallel to the output of a differential delay unit is the first phase-shifted injection signal. The phase shift of each differential delay unit corresponds to the phase shift of the connected multi-phase injection signal. When the injection tube is turned on, it changes the current distribution of the differential pair, adjusts the phase of the oscillator, and eliminates accumulated jitter. The use of three injection points avoids the degradation of reference spurious signals caused by using large injection tubes.

[0037] In this embodiment, if Figure 7 As shown, the second differential delay unit includes a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a twenty-third NMOS transistor N23, a twenty-fourth NMOS transistor N24, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9 and a tenth PMOS transistor P10; The first input terminal of the second differential delay unit is commonly connected to the gates of the 20th NMOS transistor N20 and the sixth PMOS transistor P6, the second input terminal is commonly connected to the gates of the 19th NMOS transistor N19 and the fifth PMOS transistor P5, the first output terminal is commonly connected to the drains of the 20th NMOS transistor N20, the sixth PMOS transistor P6, the second injection transistor, the 24th NMOS transistor N24, the tenth PMOS transistor P10, and the gates of the 22nd NMOS transistor N22 and the eighth PMOS transistor P8, and the second output terminal is commonly connected to the drains of the 19th NMOS transistor N19, the fifth PMOS transistor P5, the 22nd NMOS transistor N22, the eighth PMOS transistor P8, the gates of the 24th NMOS transistor N24 and the tenth PMOS transistor P10, and the source of the second injection transistor; The gates of the seventh PMOS transistor P7 and the ninth PMOS transistor P9 are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal; The gates of the twenty-first NMOS transistor N21 and the twenty-third NMOS transistor N23 are both connected to the fourth input terminal of the second differential delay unit, for receiving the second complementary injection signal; The drain of the seventh PMOS transistor P7 is connected to the source of the eighth PMOS transistor P8; the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10; the drain of the twenty-first NMOS transistor N21 is connected to the source of the twenty-second NMOS transistor N22; and the drain of the twenty-third NMOS transistor N23 is connected to the source of the twenty-fourth NMOS transistor N24. The sources of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the ninth PMOS transistor P9 are all connected to a power supply; Sources of the nineteenth NMOS transistor N19 , the twentieth NMOS transistor N20 , the twenty-first NMOS transistor N21 , and the twenty-third NMOS transistor N23 are all grounded.

[0038] It is understandable that if Figure 7 As shown, the injection terminal of the multi-phase injection signal of each differential delay unit is the gate of the corresponding injection transistor. In the second differential delay unit, in addition to using the Pul_60 signal to inject the second differential delay unit's injection terminal INJ1, that is, the gate of the first injection transistor N0, INJ_N and INJ_P are also used to perform cross-coupled complementary injection on the second differential delay unit, thereby eliminating the phase offset caused by direct injection and multi-phase injection, and expanding the noise suppression bandwidth of the ring oscillator-based phase-locked loop.

[0039] Furthermore, it is understandable that Figure 7 As shown, after direct injection of Pul_60, if in the rising edge half of the Pul_60 pulse, the current will flow from the first output end of the second differential delay unit to the second output end. At this time, the first injection tube N0 provides an additional pull-down path, thereby accelerating the discharge process, so that the zero crossing point of the oscillation signal arrives early. Since the present application performs cross-coupling complementary injection through complementary injection signals INJ_N and INJ_P, when the voltage of the second output end rises from GND, that is, the ground end, to VDD / 2, that is, half the power supply voltage, the current will flow from VDD to the first output end through the inverter A composed of the twenty-third NMOS tube N23, the twenty-fourth NMOS tube N24, the ninth PMOS tube P9 and the tenth PMOS tube P10. At the same time, the current will flow from the second output end to the ground through the inverter B composed of the twenty-first NMOS tube N21, the twenty-second NMOS tube N22, the seventh PMOS tube P7, and the eighth PMOS tube P8, thereby generating current negative feedback and slowing down the edge conversion rate of the oscillation signal.

[0040] Similarly, if the voltage at the first output terminal is lower than the voltage at the second output terminal during the falling half of the Pul_60 pulse, the current in the N0 tube reverses, slowing down the edge rise speed of the oscillation signal. Since the present application uses cross-coupled complementary injection signals INJ_N and INJ_P, when the voltage at the second output terminal rises from half the power supply voltage VDD / 2 to the power supply voltage VDD, current will flow from the first output terminal to ground through inverter A, and at the same time, current will flow from VDD to the second output terminal through inverter B, thereby generating current positive feedback and accelerating the edge conversion rate of the oscillation signal.

[0041] Since direct injection and complementary injection have opposite effects on the edge conversion rate of the oscillation signal, complementary injection offsets the phase shift of the oscillation signal caused by direct injection. At the same time, complementary injection increases the injection points, thereby improving the injection intensity and thus improving the injection locking range, that is, the noise suppression bandwidth.

[0042] In this embodiment, if Figure 2 As shown, the locking unit includes a sub-sampling loop unit, a frequency-locked loop unit, a loop filter and a buffer; The input end of the loop filter is connected to the output end of the sub-sampling loop unit and the output end of the frequency-locked loop unit, and the output end is connected to the input end of the injection-locked ring oscillator; The loop filter is configured to receive a current signal and generate the control voltage signal based on the current signal, the current signal including a first current signal and a second current signal, the first current signal and the second current signal being current signals output by the sub-sampling loop unit and the frequency-locked loop unit, respectively; the control voltage signal including a first control voltage signal and a second control voltage signal, the first control voltage signal being generated based on the first current signal, and the second control voltage signal being generated based on the second current signal; The input end of the buffer is connected to the output end of the injection locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain a second oscillation signal; The frequency-locked loop unit includes a frequency divider, a phase frequency detector, and a charge pump; the input end of the frequency divider is connected to the output end of the buffer; the first input end of the phase frequency detector is connected to the output end of the frequency divider, and the second input end is connected to the reference signal; the input end of the charge pump is connected to the output end of the phase frequency detector, and the output end is connected to the input end of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal; The sub-sampling loop unit includes a sub-sampling phase detector and a transconductance module; a first input end of the sub-sampling phase detector is connected to a reference signal, and a second input end is connected to an output end of the buffer; an input end of the transconductance module is connected to an output end of the sub-sampling phase detector, and an output end is connected to the loop filter; the sub-sampling loop unit is used to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

[0043] It can be understood that the subsampling loop and the frequency-locked loop are used to complete the phase and frequency locking of the phase-locked loop respectively. The frequency-locked loop works first to complete the frequency locking. After the frequency is locked, the frequency-locked loop stops working and the subsampling loop starts phase tracking, eventually locking the phase-locked loop based on the ring oscillator.

[0044] The phase frequency detector in the frequency locked loop uses a traditional three-state PFD with dead zone. The phase frequency detector detects the phase difference between the reference signal and the divider output signal. Greater than the oscillator frequency after N division ,Right now At this time, the PFD outputs an "advanced" pulse to control the charge pump to inject current. At this time, the PFD outputs a "hysteresis" pulse to control the charge pump to extract current. The charge pump adopts a current steering type design, and the output current The control voltage is generated by integrating the third-order RC loop filter , Adjust the oscillation frequency of the injection-locked ring oscillator until , complete frequency locking, the loop bandwidth should be designed to be 1 / 10~1 / 20 of the reference frequency to balance the locking time and stability. After the frequency is locked, the sub-sampling loop starts to work. The sub-sampling phase detector in the sub-sampling loop uses the low-frequency reference signal to sub-sample the high-frequency oscillator output signal, and converts the phase error between the reference signal and the oscillator output into a voltage signal , which contains phase error information The current signal is converted into a current signal by the transconductance module, and then a smooth control voltage signal is generated by the third-order loop filter. , precisely adjusting the phase of the oscillator's output signal to ensure phase lock. This embodiment utilizes multiphase and multipath injection techniques to improve injection strength, expand noise suppression bandwidth, and effectively suppress jitter. It also utilizes a subsampling phase-locked loop structure to further reduce phase noise. This provides a technical solution for the application of ring oscillators in millimeter-wave communications and high-speed data conversion systems that require high clock accuracy and low jitter.

[0045] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0046] The above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit them. The present application is not limited to the precise structures described above and illustrated in the accompanying drawings, and it cannot be assumed that the specific implementation of the present application is limited to these descriptions. For those skilled in the art of the present application, any changes and modifications made without departing from the concept of the present application should be deemed to fall within the scope of protection of the present application.

Claims

1. A low-jitter injection-locked phase-locked loop based on multi-phase injection, characterized in that: It includes an injection-locked path unit and an injection-locked phase-locked loop; The injection locked phase locked loop comprises a locking unit and an injection locked ring oscillator, wherein the input end of the injection locked ring oscillator is connected to the output end of the locking unit and the output end of the injection locked path unit; The input end of the locking unit is connected to the output end of the injection locked ring oscillator; The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal, wherein the injection signal includes a multi-phase injection signal and a complementary injection signal; The injection-locked ring oscillator is configured to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit; The locking unit is configured to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal, wherein the first signal is used to lock the injection-locked phase-locked loop.

2. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 1, characterized in that: The injection locking path unit includes a pulse generator, a phase shifter and a complementary injection unit; The input end of the pulse generator is connected to the reference signal, and the output end is connected to the input end of the phase shifter, the input end of the complementary injection unit and the input end of the injection locked ring oscillator; The output end of the phase shifter and the output end of the complementary injection unit are both connected to the input end of the injection locked ring oscillator; The multi-phase injection signal includes a first phase-shifted injection signal, a second phase-shifted injection signal and a third phase-shifted injection signal; The pulse generator is used to receive a reference signal and generate a first phase-shifted injection signal based on the reference signal; The phase shifter is configured to receive the first phase-shifted injection signal and generate the second phase-shifted injection signal and the third phase-shifted injection signal based on the first phase-shifted injection signal; The complementary injection unit is configured to receive the first phase-shifted injection signal and generate the complementary injection signal based on the first phase-shifted injection signal.

3. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 2, characterized in that: In the multi-phase injection signal, the phase shifts of the first phase-shifted injection signal, the second phase-shifted injection signal, and the third phase-shifted injection signal are 60°, 120°, and 180°, respectively.

4. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 3, characterized in that: The pulse generator includes an AND gate, a first NOT gate and a variable delay unit; The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal; The input end of the first NOT gate is connected to the output end of the variable delay unit; The second input end of the AND gate is connected to the output end of the first NOT gate; The AND gate is configured to receive the reference signal and the signal output by the first NOT gate, and generate the first phase-shifted injection signal based on the reference signal and the signal output by the first NOT gate.

5. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 4, characterized in that: The phase shifter includes a polyphase filter and a dual Gilbert unit; The polyphase filter includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor; One end of the first resistor is commonly connected to the positive input end of the polyphase filter and one end of the first capacitor, and the other end of the first resistor is commonly connected to one end of the second resistor, one end of the second capacitor, and one end of the seventh capacitor; The other end of the second resistor is connected to one end of the eighth capacitor and the first output end of the polyphase filter; One end of the third resistor and one end of the third capacitor are both grounded, and the other end is commonly connected to the other end of the first capacitor, one end of the fourth resistor, and one end of the fourth capacitor; The other end of the fourth resistor is commonly connected to the other end of the second capacitor and the second output end of the polyphase filter; One end of the fifth resistor and one end of the fifth capacitor are both grounded, and the other end is commonly connected to the other end of the third capacitor, one end of the sixth resistor, and one end of the sixth capacitor; The other end of the sixth resistor is commonly connected to the other end of the fourth capacitor and the third output end of the polyphase filter; One end of the seventh resistor is commonly connected to the other end of the seventh capacitor and the negative input end of the polyphase filter, and the other end of the seventh resistor is commonly connected to the other end of the fifth capacitor, the other end of the eighth capacitor, and one end of the eighth resistor; The other end of the eighth resistor is commonly connected to the other end of the sixth capacitor and the fourth output end of the polyphase filter; The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the polyphase filter are connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the dual Gilbert unit respectively.

6. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 5, characterized in that: The dual Gilbert unit includes a ninth resistor, a tenth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; A first input terminal of the dual Gilbert unit is commonly connected to the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor, a second input terminal is commonly connected to the gates of the eighteenth NMOS transistor and the fifteenth NMOS transistor, a third input terminal is commonly connected to the gates of the eleventh NMOS transistor and the fourteenth NMOS transistor, a fourth input terminal is connected to the gates of the sixteenth NMOS transistor and the seventeenth NMOS transistor, a first output terminal is commonly connected to the drains of the eleventh NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor, and the seventeenth NMOS transistor, and one end of the ninth resistor, and a second output terminal is commonly connected to the drains of the twelfth NMOS transistor, the fourteenth NMOS transistor, the sixteenth NMOS transistor, and the eighteenth NMOS transistor, and one end of the tenth resistor; The other end of the ninth resistor and the other end of the tenth resistor are both connected to a power supply; The gates of the first NMOS transistor and the second NMOS transistor are both connected to a fixed bias voltage; The drain of the first NMOS transistor is commonly connected to the sources of the seventh NMOS transistor and the eighth NMOS transistor; the drain of the second NMOS transistor is commonly connected to the sources of the ninth NMOS transistor and the tenth NMOS transistor; The drain of the seventh NMOS transistor is commonly connected to the sources of the eleventh NMOS transistor and the twelfth NMOS transistor; the drain of the eighth NMOS transistor is commonly connected to the sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor; the drain of the ninth NMOS transistor is commonly connected to the sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor; and the drain of the tenth NMOS transistor is commonly connected to the sources of the seventeenth NMOS transistor and the eighteenth NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, and the drain is commonly connected to the gate of the seventh NMOS transistor and the source of the first PMOS transistor; the gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor, and the drain is commonly connected to the gate of the eighth NMOS transistor and the source of the second PMOS transistor; the drains of the first PMOS transistor and the second PMOS transistor are connected; The gate of the fifth NMOS transistor is connected to the gate of the third PMOS transistor, and the drain is commonly connected to the gate of the ninth NMOS transistor and the source of the third PMOS transistor; the gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain is commonly connected to the gate of the tenth NMOS transistor and the source of the fourth PMOS transistor; the drain of the third PMOS transistor is connected to the drain of the fourth PMOS transistor; Sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all grounded.

7. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 6, characterized in that: The complementary injection unit includes a second NOT gate and a transmission gate; The input ends of the second NOT gate and the transmission gate are both connected to the output end of the pulse generator; The output ends of the second NOT gate and the transmission gate are connected to the first output end and the second output end of the complementary injection unit respectively; The second NOT gate is configured to receive the first phase-shifted injection signal and generate a first complementary injection signal based on the first phase-shifted injection signal; The transmission gate is configured to receive the first phase-shifted injection signal and generate a second complementary injection signal based on the first phase-shifted injection signal.

8. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 7, characterized in that: The injection-locked ring oscillator includes three injection tubes and three differential delay units, wherein the injection tubes are NMOS tubes; The first input terminal and the second input terminal of the first differential delay unit are connected to the first output terminal and the second output terminal of the third differential delay unit respectively; the first input terminal and the second input terminal of the second differential delay unit are connected to the first output terminal and the second output terminal of the first differential delay unit respectively; The first input terminal and the second input terminal of the third differential delay unit are connected to the first output terminal and the second output terminal of the second differential delay unit respectively; The gate of the first injection tube is connected to the output end of the pulse generator, and the drain and source are connected to the first output end and the second output end of the first differential delay unit respectively; the gate of the second injection tube is connected to the first output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the second differential delay unit respectively; the gate of the third injection tube is connected to the second output end of the dual Gilbert unit, and the drain and source are connected to the first output end and the second output end of the third differential delay unit respectively; The third input terminal and the fourth input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal; The first injection tube, the second injection tube and the third injection tube are used to receive the first phase-shifted injection signal, the second phase-shifted injection signal and the third phase-shifted injection signal respectively.

9. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 8, characterized in that: The second differential delay unit includes a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; The first input terminal of the second differential delay unit is commonly connected to the gates of the 20th NMOS transistor and the 6th PMOS transistor, the second input terminal is commonly connected to the gates of the 19th NMOS transistor and the 5th PMOS transistor, the first output terminal is commonly connected to the drains of the 20th NMOS transistor, the 6th PMOS transistor, the second injection transistor, the 24th NMOS transistor, and the 10th PMOS transistor, and the gates of the 22nd NMOS transistor and the 8th PMOS transistor, and the second output terminal is commonly connected to the drains of the 19th NMOS transistor, the 5th PMOS transistor, the 22nd NMOS transistor, and the 8th PMOS transistor, the gates of the 24th NMOS transistor and the 10th PMOS transistor, and the source of the second injection transistor; The gates of the seventh PMOS transistor and the ninth PMOS transistor are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal; The gates of the twenty-first NMOS transistor and the twenty-third NMOS transistor are both connected to the fourth input terminal of the second differential delay unit, for receiving the second complementary injection signal; The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the drain of the twenty-first NMOS transistor is connected to the source of the twenty-second NMOS transistor; and the drain of the twenty-third NMOS transistor is connected to the source of the twenty-fourth NMOS transistor. The sources of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the ninth PMOS transistor are all connected to a power supply; Sources of the nineteenth NMOS transistor, the twentieth NMOS transistor, the twenty-first NMOS transistor, and the twenty-third NMOS transistor are all grounded.

10. The low-jitter injection-locked phase-locked loop based on multi-phase injection according to claim 1, characterized in that: The locking unit includes a sub-sampling loop unit, a frequency-locked loop unit, a loop filter and a buffer; The input end of the loop filter is connected to the output end of the sub-sampling loop unit and the output end of the frequency-locked loop unit, and the output end is connected to the input end of the injection-locked ring oscillator; The loop filter is configured to receive a current signal and generate the control voltage signal based on the current signal, the current signal including a first current signal and a second current signal, the first current signal and the second current signal being current signals output by the sub-sampling loop unit and the frequency-locked loop unit, respectively; the control voltage signal including a first control voltage signal and a second control voltage signal, the first control voltage signal being generated based on the first current signal, and the second control voltage signal being generated based on the second current signal; The input end of the buffer is connected to the output end of the injection locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain a second oscillation signal; The frequency-locked loop unit includes a frequency divider, a phase frequency detector, and a charge pump; the input end of the frequency divider is connected to the output end of the buffer; the first input end of the phase frequency detector is connected to the output end of the frequency divider, and the second input end is connected to the reference signal; the input end of the charge pump is connected to the output end of the phase frequency detector, and the output end is connected to the input end of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal; The sub-sampling loop unit includes a sub-sampling phase detector and a transconductance module; the first input end of the sub-sampling phase detector is connected to the reference signal, and the second input end is connected to the output end of the buffer; the input end of the transconductance module is connected to the output end of the sub-sampling phase detector, and the output end is connected to the loop filter; The sub-sampling loop unit is configured to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

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