Photovoltaic cell multi-junction laminated structure deposition process

Abstract

The invention relates to the technical field of deposition processes, in particular to a photovoltaic cell multi-junction laminated structure deposition process which comprises the following steps: generating an amorphous silicon nitride transition layer with the thickness of 50nm on the surface of a flexible polyimide substrate through plasma enhanced chemical vapor deposition; alGaAs / GaAs gradient alloy layers are alternately grown in combination with MBE and PLD, the Al content is 0-30%, the layer thickness of each layer is 10 nm, and five levels are achieved in total; a p-type GaInP layer is grown through MOCVD (Metal Organic Chemical Vapor Deposition), the thickness is 300nm, and the SiH4 / DEZn flow ratio is dynamically adjusted through a mass flow controller to realize longitudinal doping gradient. Through technical collaboration and cross-scale regulation and control, flexible substrate pretreatment, an amorphous transition layer, a gradient buffer layer and strain compensation design are adopted, dynamic adaptation of crystal lattices and thermal expansion coefficients is achieved, in-situ spectral feedback and dynamic doping are introduced, current matching and spectral response are optimized, a nano-structure and interface atomic-scale stitching are combined, and the thermal expansion coefficient of the crystal lattices is improved. Compared with a traditional scheme, the solar cell has the advantages of high efficiency, flexibility and low cost.

Description

Technical Field

[0001] The present invention relates to the technical field of deposition processes, and in particular to a deposition process for a multi-junction stacked structure of a photovoltaic cell. Background Art

[0002] The photovoltaic cell stacked structure is a design that stacks different semiconductor material layers to broaden the spectral absorption range. Each layer of material has a specific bandgap energy and absorbs different wavelengths of sunlight (such as short wave, medium wave, and long wave). Through synergistic action, more photons are converted into electrical energy, thereby significantly improving the overall conversion efficiency of the cell. This structure usually adopts a multi-junction design, and each sub-cell is electrically interconnected through a tunnel junction or interface engineering, ultimately forming an efficient energy collection system. The deposition process is the core manufacturing technology for preparing the stacked structure. Semiconductor materials are grown or deposited layer by layer on the substrate by physical or chemical methods. Its goal is to precisely control The composition, thickness, crystal quality, and interface characteristics of each layer of material must be controlled to ensure the matching and synergy of the optoelectronic performance of each sub-cell. The process must address key issues such as lattice matching, stress control, and interface defect suppression, which directly affect the efficiency and reliability of the cell. Moreover, the design of the stacked structure depends on the implementation capabilities of the deposition process. The process must convert the theoretical energy band design into actual material stacking, such as alleviating lattice mismatch through gradient buffer layers and optimizing spectral absorption through quantum dots or superlattices. The precision of the deposition technology determines the interface quality, carrier transport efficiency, and structural stability of each sub-cell, and is the core bridge for the transition of stacked cells from design to application.

[0003] Generally, traditional processes mostly use rigid substrates and single epitaxial technology, which makes it difficult to solve the compatibility problem between flexible substrates and multi-material systems. Lattice mismatch leads to interface defects and stress accumulation, reducing carrier lifetime; the current matching of each sub-battery relies on static design and cannot dynamically respond to spectral changes; complex process steps lead to high costs, low yields, and it is difficult to achieve uniform deposition over large areas.

[0004] Based on this, the present invention provides a photovoltaic cell multi-junction stacking structure deposition process to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of the present invention is to provide a photovoltaic cell multi-junction stacking structure deposition process for solving the problems mentioned in the background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] The present invention proposes a photovoltaic cell multi-junction stacking structure deposition process, comprising the following steps:

[0008] S1. Generate a 50nm thick amorphous silicon nitride transition layer on the surface of a flexible polyimide substrate by plasma-enhanced chemical vapor deposition;

[0009] S2. AlGaAs / GaAs gradient alloy layers were grown alternately by MBE and PLD, with an Al content of 0→30% and a layer thickness of 10 nm per level for a total of five levels.

[0010] S3. Grow a p-type GaInP layer with a thickness of 300 nm by MOCVD. Dynamically adjust the SiH4 / DEZn flow ratio using a mass flow controller to achieve a longitudinal doping gradient. The Si concentration is 1×10 17 →5×10 18 cm -3 ;

[0011] S4. Deposition of a 2 nm AlN layer using ALD with TMA and NH3 as precursors for 20 cycles at 250°C.

[0012] S5. At 350℃, plasma-assisted MOCVD was used to alternately deposit n + -GaAs (Si doped, 5×10 19 cm -3 ) / p + -GaInNAs superlattice structure, period number 10;

[0013] S6. Pore formation by nanoimprinting and selective wet etching (H3PO4:H2O2 = 1:10) with a template period of 500 nm, followed by MBE filling of InGaAs quantum dots.

[0014] S7. Based on real-time photoluminescence spectral feedback, dynamically adjust the gas flow rate of the MOCVD chamber partitions to grow an InGaAs layer with an In composition gradient, with a thickness of 200-250nm;

[0015] S8. Hydrogen radical assisted annealing was performed in an AsH3 atmosphere at a pressure of 10 Pa, a temperature of 400°C, and an annealing time of 5 min;

[0016] S9. After rapid thermal annealing at 600℃ / 30s in N2 atmosphere, ALD deposition of Al2O3 (5nm) and PECVD deposition of SiN x (50nm).

[0017] Preferably, the implementation steps of step S1 are:

[0018] S1.1. Use an ultrasonic cleaner to clean the substrate in a mixture of acetone and isopropanol for 10 minutes each, set the cleaning temperature to 60°C, blow dry with nitrogen, and place in a vacuum chamber;

[0019] S1.2. Using plasma-enhanced chemical vapor deposition equipment, set the RF power to 300W, the chamber pressure to 50Pa, the SiH4 flow rate to 20sccm, the NH3 flow rate to 200sccm, the deposition temperature to 250°C, and the deposition time to 30 minutes to generate a 50nm amorphous silicon nitride layer;

[0020] S1.3. Plasma treatment was performed in an argon atmosphere with a power of 150 W, a treatment time of 5 minutes, and an argon flow rate of 100 sccm to increase the surface dangling bond density to 1×10 15 cm -2 .

[0021] Preferably, the implementation steps of step S2 are:

[0022] S2.1. MBE growth of the initial GaAs layer. The substrate temperature in the molecular beam epitaxy equipment was set to 580°C and the As4 beam pressure was 1×10 -5 Torr, Ga beam rate 0.5 ML / s, growth of 10 nm undoped GaAs layer;

[0023] S2.2. PLD deposition of AlGaAs gradient layers. The pulsed laser deposition equipment uses a KrF excimer laser with a wavelength of 248 nm, an energy density of 2 J / cm², and a frequency of 10 Hz. The target material is an AlGaAs alloy with a 10% Al content. After growing a 10 nm layer, the target material is switched to a 20% Al content, and the target material is gradually increased to 30%.

[0024] S2.3. Interlayer annealing integration: After each level of AlGaAs deposition, in-situ annealing is performed in the MBE chamber at 450°C for 2 minutes with an argon pressure of 1×10 -2 Torr, eliminate interface defects.

[0025] Preferably, the implementation steps of step S3 are:

[0026] Preheat the MOCVD chamber by heating the substrate to 650°C, introducing H2 carrier gas at a flow rate of 5000 sccm and a chamber pressure of 100 mbar, and stabilizing for 5 minutes.

[0027] S3.2. Gradient-doped GaInP growth: TMGa flow rate of 10 sccm, TMIn flow rate of 5 sccm, PH3 flow rate of 200 sccm, SiH4 flow rate linearly increased from 0.1 sccm to 5 sccm, DEZn flow rate decreased from 5 sccm to 0.5 sccm, growth rate 0.3 nm / s, total thickness 300 nm.

[0028] S3.3. In-situ doping concentration calibration: monitor the resistivity with an online four-probe tester and adjust the SiH4 to DEZn flow ratio to ensure a longitudinal doping gradient of 1×1017 to 5×10 18 cm -3 .

[0029] Preferably, the implementation steps of step S4 are:

[0030] S4.1. ALD precursor pulses were performed using an atomic layer deposition system with a TMA pulse time of 0.1 s, an NH3 pulse time of 0.2 s, a purge time of 20 s, and 20 cycles.

[0031] S4.2. Low-temperature deposition of AlN layer: deposition temperature 250°C, chamber pressure 0.1 Torr, single-cycle growth rate 0.1 nm / cycle, total thickness 2 nm;

[0032] S4.3. Scan the interface defects and use in-situ atomic force microscopy to detect the surface roughness and ensure that the Ra value is less than 0.2 nm.

[0033] Preferably, the implementation steps of step S5 are:

[0034] S5.1. Start the plasma-assisted MOCVD process, setting the reaction chamber temperature to 350°C, pressure to 50 mbar, RF power to 150 W, and H2 carrier gas flow rate to 3000 sccm.

[0035] S5.2.n + -GaAs layer deposition, TMGa flow rate 15sccm, AsH3 flow rate 200sccm, SiH4 flow rate 50sccm, growth rate 0.5nm / s, thickness 2nm, doping concentration 5×10 19 cm -3 ;

[0036] S5.3.p + -GaInNAs layer deposition, switch to TMIn flow 8 sccm, TMGa flow 10 sccm, AsH3 flow 150 sccm, N2 plasma flow 5 sccm, growth rate 0.4 nm / s, thickness 3 nm, N content 2%;

[0037] S5.4. For periodic stacking of the superlattice, repeat steps S5.2 and S5.3 10 times, with a total number of cycles of 10 and an interlayer purge time of 30 seconds.

[0038] Preferably, the implementation steps of step S6 are:

[0039] S6.1. Nanoimprint template preparation using a SiO2 hard template with a period of 500 nm, an imprint pressure of 10 MPa, a temperature of 180°C, and an imprint time of 5 min.

[0040] S6.2. Wet-etch the openings using an etchant consisting of H₃PO₄ and H₂O₂ in a volume ratio of 1:10 at 25°C for 30 seconds to form nanopores with a depth of 100 nm.

[0041] S6.3. MBE quantum dot filling, substrate temperature 480 °C, In beam rate 0.3 ML / s, Ga beam rate 0.2 ML / s, As4 beam pressure 5×10 -6 Torr, growing InGaAs quantum dots with a diameter of 8nm.

[0042] Preferably, the implementation steps of step S7 are:

[0043] S7.1. Real-time spectral monitoring, using an integrated fiber optic spectrometer to collect photoluminescence signals in real time, with a wavelength range of 800–1200 nm and a sampling interval of 1 second.

[0044] S7.2. Dynamically control the gas flow in zones. Divide the MOCVD chamber into five zones and adjust the TMIn flow rate to 8-12 sccm, the TMGa flow rate to 10-15 sccm, and the growth rate to 0.3-0.6 nm / s, respectively, based on spectral feedback.

[0045] S7.3. InGaAs gradient layer growth with a total thickness of 200-250nm, the In composition gradually changes from 53% to 58%, and the composition fluctuation within the layer is less than 0.5%.

[0046] Preferably, the implementation steps of step S8 are:

[0047] S8.1. Use a microwave plasma generator with a power of 500 W and a H2 flow rate of 100 sccm to generate a hydrogen radical concentration of 1×10 18 cm -3 ;

[0048] S8.2. Interface atomic etching and reconstruction, in an AsH3 atmosphere, pressure 10 Pa, temperature 400°C, annealing time 5 min, etch rate 2 nm / min;

[0049] S8.3. After annealing, use an ellipsometer to measure the interface roughness and ensure that the Ra value is less than 0.2 nm.

[0050] Preferably, the implementation steps of step S9 are:

[0051] S9.1. Rapid thermal annealing in N2 atmosphere, heating rate 50°C / s, peak temperature 600°C, hold time 30 s, cooling rate 20°C / s;

[0052] S9.2. ALD deposition of Al2O3 using TMA and H2O precursors at 200°C, 50 cycles, 0.1 nm monolayer thickness, 5 nm total thickness.

[0053] S9.3. PECVD Deposition of SiN x , using RF power 400W, SiH4 flow 50sccm, NH3 flow 200sccm, deposition temperature 300℃, pressure 100Pa, thickness 50nm;

[0054] S9.4. Stress distribution test: Use an X-ray diffractometer to measure the residual stress of the laminate, and control the compressive stress to be within the range of -1.2 GPa to the tensile stress of +0.8 GPa.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] The process of the present invention achieves dynamic adaptation of the lattice and thermal expansion coefficient through technical collaboration and cross-scale regulation, adopts flexible substrate pretreatment and amorphous transition layer, gradient buffer layer and strain compensation design, introduces in-situ spectral feedback and dynamic doping, optimizes current matching and spectral response, combines nanostructure and atomic-level interface stitching, improves light absorption efficiency and interface stability, and has the advantages of high efficiency, flexibility and low cost compared with traditional solutions. DETAILED DESCRIPTION

[0057] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0058] The present invention proposes a photovoltaic cell multi-junction stacking structure deposition process, comprising the following steps:

[0059] S1. Generate a 50nm thick amorphous silicon nitride transition layer on the surface of a flexible polyimide substrate by plasma-enhanced chemical vapor deposition;

[0060] It should be noted that the implementation steps of step S1 are:

[0061] S1.1. Use an ultrasonic cleaner to clean the substrate in a mixture of acetone and isopropanol for 10 minutes each, set the cleaning temperature to 60°C, blow dry with nitrogen, and place in a vacuum chamber;

[0062] S1.2. Using plasma-enhanced chemical vapor deposition equipment, set the RF power to 300W, the chamber pressure to 50Pa, the SiH4 flow rate to 20sccm, the NH3 flow rate to 200sccm, the deposition temperature to 250°C, and the deposition time to 30 minutes to generate a 50nm amorphous silicon nitride layer;

[0063] S1.3. Plasma treatment was performed in an argon atmosphere with a power of 150 W, a treatment time of 5 minutes, and an argon flow rate of 100 sccm to increase the surface dangling bond density to 1×10 15 cm -2 ;

[0064] S2. AlGaAs / GaAs gradient alloy layers were grown alternately by MBE and PLD, with an Al content of 0→30% and a layer thickness of 10 nm per level for a total of five levels.

[0065] It should be noted that the implementation steps of step S2 are:

[0066] S2.1. MBE growth of the initial GaAs layer. The substrate temperature in the molecular beam epitaxy equipment was set to 580°C and the As4 beam pressure was 1×10 -5 Torr, Ga beam rate 0.5 ML / s, growth of 10 nm undoped GaAs layer;

[0067] S2.2. PLD deposition of AlGaAs gradient layers. The pulsed laser deposition equipment uses a KrF excimer laser with a wavelength of 248 nm, an energy density of 2 J / cm², and a frequency of 10 Hz. The target material is an AlGaAs alloy with a 10% Al content. After growing a 10 nm layer, the target material is switched to a 20% Al content, and the target material is gradually increased to 30%.

[0068] S2.3. Interlayer annealing integration: After each level of AlGaAs deposition, in-situ annealing is performed in the MBE chamber at 450°C for 2 minutes with an argon pressure of 1×10 -2 Torr, eliminates interface defects;

[0069] Through this step, the lattice constant of the AlGaAs buffer layer at the end of step S2 (Al: 30%) is 5.66Å, and the lattice constant of the GaInP layer at step S3 (In: 52%) is 5.65Å, with a matching error of <0.2%, ensuring low dislocation density epitaxy (<10 6 cm -2 ), the residual compressive stress of -0.3 GPa introduced by PLD in step S2 is converted into an increase in the built-in electric field strength through the carrier concentration difference formed by the gradient doping in step S3;

[0070] S3. Grow a p-type GaInP layer with a thickness of 300 nm by MOCVD. Dynamically adjust the SiH4 / DEZn flow ratio using a mass flow controller to achieve a longitudinal doping gradient. The Si concentration is 1×10 17 →5×10 18 cm -3 ;

[0071] It should be noted that the implementation steps of step S3 are:

[0072] Preheat the MOCVD chamber by heating the substrate to 650°C, introducing H2 carrier gas at a flow rate of 5000 sccm and a chamber pressure of 100 mbar, and stabilizing for 5 minutes.

[0073] S3.2. Gradient-doped GaInP growth: TMGa flow rate of 10 sccm, TMIn flow rate of 5 sccm, PH3 flow rate of 200 sccm, SiH4 flow rate linearly increased from 0.1 sccm to 5 sccm, DEZn flow rate decreased from 5 sccm to 0.5 sccm, growth rate 0.3 nm / s, total thickness 300 nm.

[0074] S3.3. In-situ doping concentration calibration: monitor the resistivity with an online four-probe tester and adjust the SiH4 to DEZn flow ratio to ensure a longitudinal doping gradient of 1×10 17 to 5×10 18 cm -3 ;

[0075] Through this step, the GaInP layer in step S3 has a local lattice expansion of +0.4% due to the In composition gradient of 52%-55%. The AlN layer in step S4 has a high elastic modulus of 300GPa and applies a reverse stress of +0.35GPa at the nanoscale to balance the lattice distortion. The diffusion tendency of the Zn doping interface in step S3 is suppressed by the AlN barrier layer, and the steepness of the interface doping concentration gradient is improved.

[0076] S4. Deposition of a 2 nm AlN layer using ALD with TMA and NH3 as precursors for 20 cycles at 250°C.

[0077] It should be noted that the implementation steps of step S4 are:

[0078] S4.1. ALD precursor pulses were performed using an atomic layer deposition system with a TMA pulse time of 0.1 s, an NH3 pulse time of 0.2 s, a purge time of 20 s, and 20 cycles.

[0079] S4.2. Low-temperature deposition of AlN layer: deposition temperature 250°C, chamber pressure 0.1 Torr, single-cycle growth rate 0.1 nm / cycle, total thickness 2 nm;

[0080] S4.3. Scan the interface for defects and examine the surface roughness using in-situ atomic force microscopy to ensure that the Ra value is less than 0.2 nm.

[0081] Through this step, the thermal conductivity of the AlN layer in step S4 (285W / m·K) reduces the heat transfer from the bottom layer to the tunnel junction area, making the deposition temperature in step S5 150°C lower than that of the conventional process, suppressing the thermal migration and segregation of the N element in GaInNAs (N distribution uniformity >95%). The insulating properties of AlN are bypassed by the quantum tunneling effect (tunneling probability >80%) of the superlattice tunneling barrier (thickness 2nm), maintaining the longitudinal resistivity <10 -3 Ω·cm;

[0082] S5. At 350℃, plasma-assisted MOCVD was used to alternately deposit n + -GaAs (Si doped, 5×10 19 cm -3 ) / p + -GaInNAs superlattice structure, period number 10;

[0083] It should be noted that the implementation steps of step S5 are:

[0084] S5.1. Start the plasma-assisted MOCVD process, setting the reaction chamber temperature to 350°C, pressure to 50 mbar, RF power to 150 W, and H2 carrier gas flow rate to 3000 sccm.

[0085] S5.2.n + -GaAs layer deposition, TMGa flow rate 15sccm, AsH3 flow rate 200sccm, SiH4 flow rate 50sccm, growth rate 0.5nm / s, thickness 2nm, doping concentration 5×10 19 cm -3 ;

[0086] S5.3.p + -GaInNAs layer deposition, switch to TMIn flow 8 sccm, TMGa flow 10 sccm, AsH3 flow 150 sccm, N2 plasma flow 5 sccm, growth rate 0.4 nm / s, thickness 3 nm, N content 2%;

[0087] S5.4. Superlattice periodic stacking, repeat steps S5.2 and S5.3 10 times, total number of cycles 10, interlayer purge time 30 seconds;

[0088] Through this step, n in the superlattice of step S5 +The GaAs layer is used as an etch stop layer (etching selectivity > 100:1) to ensure consistent hole depth (±5nm). The band gap of the GaInNAs (1.2eV) in step S5 and the energy level of the quantum dots (1.0eV) in step S6 form a cascade absorption, which improves the separation efficiency of photogenerated carriers by 22%.

[0089] S6. Pore formation by nanoimprinting and selective wet etching (H3PO4:H2O2 = 1:10) with a template period of 500 nm, followed by MBE filling of InGaAs quantum dots.

[0090] It should be noted that the implementation steps of step S6 are:

[0091] S6.1. Nanoimprint template preparation using a SiO2 hard template with a period of 500 nm, an imprint pressure of 10 MPa, a temperature of 180°C, and an imprint time of 5 min.

[0092] S6.2. Wet-etch the openings using an etchant consisting of H₃PO₄ and H₂O₂ in a volume ratio of 1:10 at 25°C for 30 seconds to form nanopores with a depth of 100 nm.

[0093] S6.3. MBE quantum dot filling, substrate temperature 480 °C, In beam rate 0.3 ML / s, Ga beam rate 0.2 ML / s, As4 beam pressure 5×10 -6 Torr, growing InGaAs quantum dots, 8 nm in diameter;

[0094] Through this step, the photoluminescence peak position (wavelength 950nm-1100nm) of the quantum dots in step S6 is captured in real time by the spectral sensor, driving the In component in S7 to adjust to a higher value to compensate for the weak absorption of long-wave light by the underlying sub-cell. The scattering angle distribution (±30°) of the nanochannel in step S6 is fed back to the thickness control method in step S7 through optical path simulation to optimize the matching of the optical path and the carrier transport path.

[0095] S7. Based on real-time photoluminescence spectral feedback, dynamically adjust the gas flow rate of the MOCVD chamber partitions to grow an InGaAs layer with an In composition gradient, with a thickness of 200-250nm;

[0096] It should be noted that the implementation steps of step S7 are:

[0097] S7.1. Real-time spectral monitoring, using an integrated fiber optic spectrometer to collect photoluminescence signals in real time, with a wavelength range of 800–1200 nm and a sampling interval of 1 second.

[0098] S7.2. Dynamically control the gas flow in zones. Divide the MOCVD chamber into five zones and adjust the TMIn flow rate to 8-12 sccm, the TMGa flow rate to 10-15 sccm, and the growth rate to 0.3-0.6 nm / s, respectively, based on spectral feedback.

[0099] S7.3. Growth of graded InGaAs layers, total thickness 200-250 nm, with an In composition gradient from 53% to 58%, and intralayer composition fluctuations less than 0.5%;

[0100] Through this step, the interface roughness (Ra 0.3-0.8 nm) caused by the dynamic adjustment in step S7 is selectively etched by HRAA (etching rate 2 nm / min in the raised area and 0.9 nm / min in the recessed area), achieving atomic-level flatness (Ra < 0.2 nm). The In composition gradient in step S7 is reconstructed by AsH3 atmosphere to form an As-In bond density gradient (5 × 10 14 →1×10 15 cm -2 ), the interface state density is reduced to <1×10 11 cm -2 eV -1 ;

[0101] S8. Hydrogen radical assisted annealing was performed in an AsH3 atmosphere at a pressure of 10 Pa, a temperature of 400°C, and an annealing time of 5 min;

[0102] It should be noted that the implementation steps of step S8 are:

[0103] S8.1. Use a microwave plasma generator with a power of 500 W and a H2 flow rate of 100 sccm to generate a hydrogen radical concentration of 1×10 18 cm -3 ;

[0104] S8.2. Interface atomic etching and reconstruction, in an AsH3 atmosphere, pressure 10 Pa, temperature 400°C, annealing time 5 min, etch rate 2 nm / min;

[0105] S8.3. After annealing, measure the interface roughness using an ellipsometer to ensure that the Ra value is less than 0.2 nm.

[0106] Through this step, the atomic-level interface of step S8 expands synchronously in RTA (CTE matching error <0.5%), avoiding interlayer delamination caused by thermal stress, and the residual hydrogen radicals in step S8 (concentration -1×10 18 cm -3 ) are captured by the Al2O3 layer, forming H-Si / O defect passivation centers, and the bulk defect density is reduced to <1×10 15 cm -3, the As-In bonding network reconstructed in step S8 and SiN x The refractive index gradient of the membrane (1.65→2.05) synergistically optimizes the optical coupling efficiency of the S6 nanochannel;

[0107] S9. After rapid thermal annealing at 600℃ / 30s in N2 atmosphere, ALD deposition of Al2O3 (5nm) and PECVD deposition of SiN x (50nm);

[0108] It should be noted that the implementation steps of step S9 are:

[0109] S9.1. Rapid thermal annealing in N2 atmosphere, heating rate 50°C / s, peak temperature 600°C, hold time 30 s, cooling rate 20°C / s;

[0110] S9.2. ALD deposition of Al2O3 using TMA and H2O precursors at 200°C, 50 cycles, 0.1 nm monolayer thickness, 5 nm total thickness.

[0111] S9.3. PECVD Deposition of SiN x , using RF power 400W, SiH4 flow 50sccm, NH3 flow 200sccm, deposition temperature 300℃, pressure 100Pa, thickness 50nm;

[0112] S9.4. Stress distribution testing: Use an X-ray diffractometer to measure the residual stress of the laminate, controlling the compressive stress to be within the range of -1.2 GPa to the tensile stress of +0.8 GPa.

[0113] The performance of the deposition process for the multi-junction stacked structure of the photovoltaic cell of the present invention was verified. The experimental steps included:

[0114] a1. Sample preparation: Select three sets of laminated samples (10 x 10 mm²) from steps S9.1 to S9.3, ensuring the surface is free of contamination.

[0115] a2. X-ray diffractometer calibration: A standard Si (111) crystal was used to calibrate the instrument to an angle accuracy of ±0.001°, and a Cu-Kα radiation source (λ = 0.154 nm) was set. The scanning angle range was 20°-80°, with a step size of 0.02°.

[0116] a3. Stress measurement: XRDω scans were performed on five points on the surface of each sample group, and residual stress was calculated using the lattice distortion formula Δd / d0 = -(σ / E)(1+ν), where E = 70 GPa (laminate equivalent modulus) and ν = 0.3;

[0117] a4. Mechanical integrity test: Use a scanning electron microscope (SEM, accelerating voltage 5kV) to observe whether there is any delamination or cracking in the cross section;

[0118] It should also be noted that the specific testing standards are:

[0119] b1. Residual stress qualified range: -1.2GPa≤σ≤+0.8GPa;

[0120] b2. No visible cracks or peeling at the interlayer interface (SEM resolution 1nm);

[0121] b3. The range of the three-point measurement value is less than 0.3GPa;

[0122] Set up a control group without performing the stress compensation in step S9.4 and record the test data, as shown in Table 1:

[0123] Table 1 Key performance parameters of samples

[0124] Sample number Average residual stress (GPa) SEM interface observation results Stress distribution extremes (GPa) Mechanical integrity assessment Sample 1 -0.9 Continuous interface without cracks 0.20 Qualified (curvature radius > 2m) Sample 2 +0.5 Continuous interface without cracks 0.18 Qualified (curvature radius > 2m) Sample 3 -1.0 Continuous interface without cracks 0.25 Qualified (curvature radius > 2m) control group -1.5 Interlaminar delamination and microcracks 0.45 Failure (curvature radius < 0.5m)

[0125] As shown in Table 1, the process results of the present invention are verified:

[0126] It can be seen that the average residual stresses of the three groups of samples measured by X-ray diffraction were -0.9GPa, +0.5GPa, and -1.0GPa, respectively, which were all within the control range. SEM cross-sectional observations showed that the interfaces of each layer were continuous, without cracks or delamination, and the stress distribution uniformity met the standards. The maximum range of the five-point measurement was 0.25GPa, while the curvature radius of the control group was <0.5m, with obvious interlayer warping and local cracks. Therefore, through the combined use of XRD and SEM, cross-layer stress balance control was effectively achieved.

[0127] In summary, the present invention adopts flexible substrate pretreatment and amorphous transition layer, gradient buffer layer and strain compensation design to achieve dynamic adaptation of lattice and thermal expansion coefficient, introduces in-situ spectral feedback and dynamic doping, optimizes current matching and spectral response, combines nanostructure and atomic-level stitching of interfaces, improves light absorption efficiency and interface stability, and has the advantages of high efficiency, flexibility and low cost compared with traditional solutions.

[0128] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0129] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A photovoltaic cell multi-junction stacking structure deposition process, characterized in that: The following steps are involved: S1. Generate a 50nm thick amorphous silicon nitride transition layer on the surface of a flexible polyimide substrate by plasma-enhanced chemical vapor deposition; S2. AlGaAs / GaAs gradient alloy layers were grown alternately by MBE and PLD, with an Al content of 0→30% and a layer thickness of 10 nm per level for a total of five levels. S3. Grow a p-type GaInP layer with a thickness of 300 nm by MOCVD. Dynamically adjust the SiH4 / DEZn flow ratio using a mass flow controller to achieve a longitudinal doping gradient. The Si concentration is 1×10 17 →5×10 18 cm -3 ; S4. Deposition of a 2 nm AlN layer using ALD with TMA and NH3 as precursors for 20 cycles at 250°C. S5. At 350℃, plasma-assisted MOCVD was used to alternately deposit n + -GaAs / p + -GaInNAs superlattice structure, period number 10; S6. Pore formation by nanoimprinting and selective wet etching (H3PO4:H2O2 = 1:10) with a template period of 500 nm, followed by MBE filling of InGaAs quantum dots. S7. Based on real-time photoluminescence spectral feedback, dynamically adjust the gas flow rate of the MOCVD chamber partitions to grow an InGaAs layer with an In composition gradient, with a thickness of 200-250nm; S8. Hydrogen radical assisted annealing was performed in an AsH3 atmosphere at a pressure of 10 Pa, a temperature of 400°C, and an annealing time of 5 min; S9. After rapid thermal annealing at 600℃ / 30s in N2 atmosphere, ALD deposition of Al2O3 (5nm) and PECVD deposition of SiN x (50nm).

2. A photovoltaic cell multi-junction stacking structure deposition process according to claim 1, characterized in that: The implementation steps of step S1 are: S1.

1. Use an ultrasonic cleaner to clean the substrate in a mixture of acetone and isopropanol for 10 minutes each, set the cleaning temperature to 60°C, blow dry with nitrogen, and place in a vacuum chamber; S1.

2. Using plasma-enhanced chemical vapor deposition equipment, set the RF power to 300W, the chamber pressure to 50Pa, the SiH4 flow rate to 20sccm, the NH3 flow rate to 200sccm, the deposition temperature to 250°C, and the deposition time to 30 minutes to generate a 50nm amorphous silicon nitride layer; S1.

3. Plasma treatment was performed in an argon atmosphere with a power of 150 W, a treatment time of 5 minutes, and an argon flow rate of 100 sccm to increase the surface dangling bond density to 1×10 15 cm -2 .

3. A photovoltaic cell multi-junction stacking structure deposition process according to claim 2, characterized in that: The implementation steps of step S2 are: S2.

1. MBE growth of the initial GaAs layer. The substrate temperature in the molecular beam epitaxy equipment was set to 580°C and the As4 beam pressure was 1×10 -5 Torr, Ga beam rate 0.5ML / s, growth of 10nm undoped GaAs layer; S2.

2. PLD deposition of AlGaAs gradient layers. The pulsed laser deposition equipment uses a KrF excimer laser with a wavelength of 248 nm, an energy density of 2 J / cm², and a frequency of 10 Hz. The target material is an AlGaAs alloy with a 10% Al content. After growing a 10 nm layer, the target material is switched to a 20% Al content, and the target material is gradually increased to 30%. S2.

3. Interlayer annealing integration: After each level of AlGaAs deposition, in-situ annealing is performed in the MBE chamber at 450°C for 2 minutes with an argon pressure of 1×10 -2 Torr, eliminate interface defects.

4. A photovoltaic cell multi-junction stacking structure deposition process according to claim 3, characterized in that: The implementation steps of step S3 are: Preheat the MOCVD chamber by heating the substrate to 650°C, introducing H2 carrier gas at a flow rate of 5000 sccm and a chamber pressure of 100 mbar, and stabilize for 5 minutes. S3.

2. Gradient-doped GaInP growth: TMGa flow rate of 10 sccm, TMIn flow rate of 5 sccm, PH3 flow rate of 200 sccm, SiH4 flow rate linearly increased from 0.1 sccm to 5 sccm, DEZn flow rate decreased from 5 sccm to 0.5 sccm, growth rate 0.3 nm / s, total thickness 300 nm. S3.

3. In-situ doping concentration calibration: monitor the resistivity with an online four-probe tester and adjust the SiH4 to DEZn flow ratio to ensure a longitudinal doping gradient of 1×10 17 to 5×10 18 cm -3 .

5. The photovoltaic cell multi-junction stacking structure deposition process according to claim 4, characterized in that: The implementation steps of step S4 are: S4.

1. ALD precursor pulses were performed using an atomic layer deposition system with a TMA pulse time of 0.1 s, an NH3 pulse time of 0.2 s, a purge time of 20 s, and 20 cycles. S4.

2. Low-temperature deposition of AlN layer: deposition temperature 250°C, chamber pressure 0.1 Torr, single-cycle growth rate 0.1 nm / cycle, total thickness 2 nm; S4.

3. Scan the interface defects and use in-situ atomic force microscopy to detect the surface roughness and ensure that the Ra value is less than 0.2 nm.

6. The photovoltaic cell multi-junction stacking structure deposition process according to claim 5, characterized in that: The implementation steps of step S5 are: S5.

1. Start the plasma-assisted MOCVD process, setting the reaction chamber temperature to 350°C, pressure to 50 mbar, RF power to 150 W, and H2 carrier gas flow rate to 3000 sccm. S5.2.n + -GaAs layer deposition, TMGa flow rate 15sccm, AsH3 flow rate 200sccm, SiH4 flow rate 50sccm, growth rate 0.5nm / s, thickness 2nm, doping concentration 5×10 19 cm -3 ; S5.3.p + -GaInNAs layer deposition, switch to TMIn flow 8 sccm, TMGa flow 10 sccm, AsH3 flow 150 sccm, N2 plasma flow 5 sccm, growth rate 0.4 nm / s, thickness 3 nm, N content 2%; S5.

4. For periodic stacking of the superlattice, repeat steps S5.2 and S5.3 10 times, with a total number of cycles of 10 and an interlayer purge time of 30 seconds.

7. A photovoltaic cell multi-junction stacking structure deposition process according to claim 6, characterized in that: The implementation steps of step S6 are: S6.

1. Nanoimprint template preparation using a SiO2 hard template with a period of 500 nm, an imprint pressure of 10 MPa, a temperature of 180°C, and an imprint time of 5 min. S6.

2. Wet-etch the openings using an etchant consisting of H₃PO₄ and H₂O₂ in a volume ratio of 1:10 at 25°C for 30 seconds to form nanopores with a depth of 100 nm. S6.

3. MBE quantum dot filling, substrate temperature 480 °C, In beam rate 0.3 ML / s, Ga beam rate 0.2 ML / s, As4 beam pressure 5×10 -6 Torr, growing InGaAs quantum dots with a diameter of 8nm.

8. The photovoltaic cell multi-junction stacking structure deposition process according to claim 7, characterized in that: The implementation steps of step S7 are: S7.

1. Real-time spectral monitoring, using an integrated fiber optic spectrometer to collect photoluminescence signals in real time, with a wavelength range of 800–1200 nm and a sampling interval of 1 second. S7.

2. Dynamically control the gas flow in zones. Divide the MOCVD chamber into five zones and adjust the TMIn flow rate to 8-12 sccm, the TMGa flow rate to 10-15 sccm, and the growth rate to 0.3-0.6 nm / s, respectively, based on spectral feedback. S7.

3. InGaAs gradient layer growth with a total thickness of 200-250nm, the In composition gradually changes from 53% to 58%, and the composition fluctuation within the layer is less than 0.5%.

9. The photovoltaic cell multi-junction stacking structure deposition process according to claim 8, characterized in that: The implementation steps of step S8 are: S8.

1. Use a microwave plasma generator with a power of 500 W and a H2 flow rate of 100 sccm to generate a hydrogen radical concentration of 1×10 18 cm -3 ; S8.

2. Interface atomic etching and reconstruction, in an AsH3 atmosphere, pressure 10 Pa, temperature 400°C, annealing time 5 min, etch rate 2 nm / min; S8.

3. After annealing, use an ellipsometer to measure the interface roughness and ensure that the Ra value is less than 0.2 nm.

10. The photovoltaic cell multi-junction stacking structure deposition process according to claim 9, characterized in that: The implementation steps of step S9 are: S9.

1. Rapid thermal annealing in N2 atmosphere, heating rate 50°C / s, peak temperature 600°C, hold time 30 s, cooling rate 20°C / s; S9.

2. ALD deposition of Al2O3 using TMA and H2O precursors at 200°C, 50 cycles, 0.1 nm monolayer thickness, 5 nm total thickness. S9.

3. PECVD Deposition of SiN x , using RF power 400W, SiH4 flow 50sccm, NH3 flow 200sccm, deposition temperature 300℃, pressure 100Pa, thickness 50nm; S9.

4. Stress distribution test: Use an X-ray diffractometer to measure the residual stress of the laminate, and control the compressive stress to be within the range of -1.2 GPa to the tensile stress of +0.8 GPa.