Low-power-consumption clock delay method and system

Abstract

The invention relates to a low-power-consumption clock delay method and system in the technical field of integrated circuits, and the method comprises the following steps: carrying out the phase alignment of a counting clock signal and a to-be-delayed clock signal based on the counting clock signal, and generating a first phase clock alignment signal and a second phase clock alignment signal; extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal; splitting the clock rising edge information and the clock falling edge information to obtain a first pulse filtering signal and a second pulse filtering signal; performing coarse delay on the first pulse filtering signal and the second pulse filtering signal in sequence, and performing signal synthesis processing after coarse delay to obtain a coarse delay clock signal; and performing fine delay on the coarse delay clock signal based on the digital time converter to obtain a fine delay clock signal, thereby solving the problem that the existing delay technology cannot simultaneously realize high delay precision and large dynamic range under the condition of low power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power clock delay method and system. Background Art

[0002] With the continuous development of communication technology, the market has increasingly stringent requirements for clocks. For example, in fields such as communications, finance, and scientific research, high-resolution time synchronization technology is the cornerstone of normal system operation. High-resolution, low-power, and large dynamic range clock delay technology is the foundation of this technology.

[0003] However, since the delay circuit used in the existing clock delay is composed of multiple delay units, if it wants to achieve high delay accuracy, it means that the delay adjustment step of the delay unit needs to be shorter, and then more delay units are used to achieve it. However, due to the requirements of chip layout area and power consumption, the number of delay units is limited. Therefore, the delay circuit used in the existing clock delay is difficult to achieve a large dynamic range under the premise of high delay accuracy; similarly, when the clock delay technology meets the large dynamic range, it means that a longer time delay is required, and its time delay also depends on the generation of the delay unit. Therefore, it is also limited by the chip layout area and power consumption. The number of delay units is limited, and it is necessary to increase the delay time of a single delay unit to achieve a large delay range, which reduces the delay resolution.

[0004] Therefore, based on the above, existing delay technology needs to rely on lengthening the delay link to achieve both high delay accuracy and large dynamic range, but lengthening the delay link leads to greater power consumption and chip area. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a low-power clock delay method and system, which solves the problem that the existing delay technology cannot achieve high delay accuracy and large dynamic range at the same time with low power consumption.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] A low-power clock delay method comprises the following steps:

[0008] Performing phase alignment on the counting clock signal and the clock signal to be delayed based on the counting clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal;

[0009] Extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal;

[0010] Separating clock rising edge information and clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal, and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal;

[0011] performing coarse delay on the first pulse filtered signal and the second pulse filtered signal in sequence, and synthesizing the coarsely delayed first pulse filtered signal and the second pulse filtered signal to obtain a coarse delayed clock signal;

[0012] The coarse-delayed clock signal is finely delayed based on a digital-to-time converter to obtain a fine-delayed clock signal.

[0013] Optionally, performing a coarse delay on the first pulse filtered signal includes the following steps:

[0014] Setting a delay configuration code, triggering the counting clock signal to reset and start counting each time the first pulse filtering signal sends a pulse filtering signal;

[0015] Every time the count value of the counting clock signal reaches the delay configuration code, the counting clock signal stops counting and outputs a set signal corresponding to the first pulse filtering signal.

[0016] Optionally, performing a coarse delay on the second pulse filtered signal comprises the following steps:

[0017] When the second pulse filtering signal sends a pulse filtering signal, the counting clock signal is triggered to reset and start counting;

[0018] Every time the count value of the counting clock signal reaches the delay configuration code, the counting clock signal stops counting and outputs a reset signal corresponding to the second pulse filtering signal.

[0019] Optionally, performing fine delay on the coarse-delay clock signal based on a digital-to-time converter comprises the following steps:

[0020] A control word of the digital-to-time converter is set, and the coarse-delayed clock signal is delayed based on the control word to obtain a fine-delayed clock signal.

[0021] Optionally, performing phase alignment on the counting clock signal and the clock signal to be delayed based on the counting clock signal includes the following steps:

[0022] Setting a counting clock signal, and resampling the delayed clock signal using the counting clock signal to obtain a first phase clock alignment signal and a second phase clock alignment signal;

[0023] The first phase clock alignment signal and the second phase clock alignment signal are inverse signals to each other, and the first phase clock alignment signal and the clock signal to be delayed are in the same direction.

[0024] Optionally, extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal includes the following steps:

[0025] Performing reverse processing on the counting clock signal to obtain a counting clock reverse signal;

[0026] Resampling the first phase clock alignment signal by the counting clock inverse signal to generate a first phase clock resampled signal whose phase difference from the first phase clock alignment signal is half a clock period of the counting clock signal;

[0027] A pulse signal carrying clock edge information is generated based on the first phase clock alignment signal and the first phase clock resampling signal.

[0028] Optionally, splitting the clock rising edge information and the clock falling edge information includes the following steps:

[0029] Using the first phase clock alignment signal to filter out falling edge pulse information in the pulse signal to obtain a first pulse filtered signal;

[0030] The second phase clock alignment signal is used to filter out rising edge pulse information in the pulse signal to obtain a second pulse filtered signal.

[0031] A low-power clock delay system, which implements any one of the low-power clock delay methods described above, comprising a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit, and a digital time conversion circuit;

[0032] The clock synchronization circuit is used to phase-align the counting clock signal with the clock signal to be delayed based on the counting clock signal, and generate a first phase clock alignment signal and a second phase clock alignment signal;

[0033] The clock edge generating circuit is used to extract rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal;

[0034] The clock edge separation circuit is used to separate the clock rising edge information and the clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal;

[0035] The pulse delay circuit is used to sequentially perform coarse delay on the first pulse filtered signal and the second pulse filtered signal;

[0036] The RS trigger circuit is used to synthesize the first pulse filtered signal and the second pulse filtered signal after coarse delay to obtain a coarse delayed clock signal;

[0037] The digital time conversion circuit is used to perform fine delay on the coarse delayed clock signal based on a digital time converter to obtain a fine delayed clock signal.

[0038] Optionally, the pulse delay circuit includes a first pulse delayer and a second pulse delayer;

[0039] The first pulse delayer receives the first pulse filter signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a set signal;

[0040] The second pulse delayer receives the second pulse filter signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a reset signal.

[0041] Optionally, the clock edge generating circuit includes a D flip-flop and an XOR logic gate;

[0042] The D flip-flop receives a counting clock inversion signal obtained by inverting the counting clock signal and a first phase clock alignment signal sent by the clock synchronization circuit, and outputs a first phase clock resampling signal;

[0043] The XOR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

[0044] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0045] The present application sets a counting clock signal and uses the counting function of the counting clock signal to perform coarse delay processing on the clock signal to be delayed, so that the clock signal to be delayed reaches a delay of microseconds or even milliseconds; at the same time, on the basis of the coarse delay, the coarse delayed clock signal is finely delayed by a digital time converter, so that the delay effect reaches the picosecond level, thereby achieving the precision control of the delay by combining coarse delay with fine delay; on the other hand, since the present invention only needs to configure a counting clock signal and a digital time converter to achieve high delay accuracy, there is no need to increase the number of delay units to improve the high delay accuracy, so the power consumption overhead of the delay system can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 A low-power clock delay method proposed in the first embodiment;

[0048] Figure 2 This is a circuit schematic diagram of a low-power clock delay proposed in the first and second embodiments;

[0049] Figure 3 This is an example diagram of the working waveform during the coarse delay proposed in this embodiment. DETAILED DESCRIPTION

[0050] The present invention will be further described in detail below with reference to the examples. The following examples are intended to explain the present invention but the present invention is not limited to the following examples.

[0051] Example 1

[0052] like Figure 1 and Figure 2 As shown, a low-power clock delay method includes the following steps: based on a counting clock signal, a counting clock signal is phase-aligned with a clock signal to be delayed, generating a first phase clock alignment signal and a second phase clock alignment signal to eliminate the phase difference between the counting clock signal and the clock signal to be delayed, specifically including the following steps: setting a counting clock signal, and resampling the clock signal to be delayed by the counting clock signal to obtain a first phase clock alignment signal and a second phase clock alignment signal; wherein the first phase clock alignment signal and the second phase clock alignment signal are inverse signals of each other, and the first phase clock alignment signal and the clock signal to be delayed are in the same direction.

[0053] Since the phase error between the clock signal to be delayed CLK_IN and the counting clock signal is uncertain, and the present application implements the coarse delay based on counting the counting clock signal CLKP, it is necessary to first perform phase alignment on the signal to be delayed CLK_IN through the counting clock, that is, it is necessary to first eliminate the uncertain phase difference between the counting clock CLKP and the clock signal to be delayed CLK_IN to avoid delay control errors.

[0054] Therefore, the present application uses the counting clock signal CLKP to implement resampling of the delayed clock signal CLK_IN in the clock synchronization circuit, and generates a first phase clock alignment signal CLK_INP_D1 and a second phase clock alignment signal CLK_INN_D1 aligned with the clock edge of the counting clock signal CLKP for processing by subsequent circuits.

[0055] Specifically, a D flip-flop based on rising edge triggering is set in the clock synchronization circuit, and the edge triggering function of the D flip-flop is used to realize resampling (ie, the output signal of the D flip-flop is updated at the rising edge of the trigger clock), such as Figure 3 As shown, it can be seen that the clock edge variation relationship between the counting clock signal CLKP formed after the delayed clock signal is resampled by the D flip-flop and the first phase clock alignment signal CLK_INP_D1 and the second phase clock alignment signal CLK_INN_D1 is formed.

[0056] After obtaining the first phase clock alignment signal CLK_INP_D1 and the second phase clock alignment signal CLK_INN_D1, the rising edge information and the falling edge information of the first phase clock alignment signal are extracted to obtain a pulse signal, which specifically includes the following steps: reverse processing the counting clock signal to obtain a counting clock reverse signal; resampling the first phase clock alignment signal through the counting clock reverse signal to generate a first phase clock resampling signal that differs from the first phase clock alignment signal by half a counting clock signal clock cycle; based on the first phase clock alignment signal and the first phase clock resampling signal, a pulse signal carrying clock edge information is generated.

[0057] Specifically, since in clock delay, a clock needs to be delayed, which is actually to delay the clock edge position. Therefore, it is necessary to extract the clock edge information, and then delay the extracted clock edge information to achieve clock delay. Therefore, the present application sets a D flip-flop in the clock edge generation circuit, and uses the D flip-flop to generate a first phase clock resampling signal CLK_INP_D2 that differs from the first phase clock alignment signal CLK_INP_D1 by half a clock cycle of the counting clock signal CLKP, and then sends the first phase clock alignment signal CLK_INP_D1 and the first phase clock resampling signal CLK_INP_D2 to the exclusive OR logic gate input to generate a pulse signal CLK_INP_XOR carrying the clock edge information. The formed pulse signal CLK_INP_XOR is as follows: Figure 3 shown.

[0058] Among them, it should be noted that the pulse width of the obtained pulse signal CLK_INP_XOR is half the cycle width of the counting clock signal CLKP. This is because this embodiment generates coarse delay based on high-frequency clock counting, and the counter uses rising edge triggering. Therefore, the counter reset signals RST_S and RST_R must release the reset before the arrival of the first counting clock edge after the rising edge of the reset pulse (that is, RST_S and RST_R need to be pulled low before the arrival of the first counting edge after the rising edge of the reset pulse). Therefore, the reset pulse signal width needs to be less than 1 CLKP cycle. Based on this, the falling edge of the counting clock signal CLKP clock is used for processing in this application, so as to realize a pulse signal CLK_INP_XOR with a pulse width of half the cycle width of the counting clock signal CLKP.

[0059] After obtaining the pulse signal CLK_INP_XOR, the clock rising edge information and the clock falling edge information are split based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal to obtain the first pulse filtered signal and the second pulse filtered signal. Specifically, the first phase clock alignment signal is used to filter out the falling edge pulse information in the pulse signal to obtain the first pulse filtered signal; the second phase clock alignment signal is used to filter out the rising edge pulse information in the pulse signal to obtain the second pulse filtered signal.

[0060] In this embodiment, the clock rising edge information and the clock falling edge information are split by a clock delay separation circuit. Specifically, two AND logic gates are set in the clock delay separation circuit, and the first phase clock alignment signal CLK_INP_D1 is used to filter out the falling edge pulse information of the pulse signal CLK_INP_XOR to obtain a first pulse filtered signal RST_S containing only rising edge information. The second phase clock alignment signal CLK_INN_D1 is used to filter out the rising edge pulse information of the pulse signal CLK_INP_XOR to obtain a second pulse filtered signal RST_R containing only falling edge information. Their waveforms are as follows: Figure 3 As shown in RST_S and RST_R.

[0061] Furthermore, the first pulse filtered signal and the second pulse filtered signal are coarsely delayed in sequence, and the coarsely delayed first pulse filtered signal and the second pulse filtered signal are synthesized to obtain a coarse delayed clock signal.

[0062] Among them, the first pulse filtering signal is coarsely delayed, including the following steps: setting a delay configuration code, triggering the counting clock signal to reset and start counting every time the first pulse filtering signal sends a pulse filtering signal; each time the count value of the counting clock signal reaches the delay configuration code once, the counting clock signal stops counting and outputs a set signal corresponding to the first pulse filtering signal.

[0063] The second pulse filtering signal is coarsely delayed, including the following steps: each time the second pulse filtering signal sends a pulse filtering signal, the counting clock signal is triggered to reset and start counting; each time the count value of the counting clock signal reaches a delay configuration code, the counting clock signal stops counting and outputs a reset signal corresponding to the second pulse filtering signal.

[0064] This embodiment implements coarse delay through a pulse delay circuit. Specifically, the pulse delayer in the pulse delay circuit delays the input first pulse filtered signal RST_S containing rising edge information and the second pulse filtered signal RST_R containing falling edge information, so that the output set signal SET is the signal after the first pulse filtered signal RST_S is delayed. The delay size is DELAY_CFG×T CLKP , where T CLKP is a clock cycle of the counting clock signal CLKP, and DELAY_CFG is the delay configuration code; similarly, the output reset signal RESET is the signal after the second pulse filtered signal RST_R is delayed, and its delay size is DELAY_CFG×T CLKP , where TCLKP is one CLKP clock cycle.

[0065] More specifically, the rising edge information of the input reset pulse is delayed, and the delay size is controlled by the delay configuration code DELAY_CFG. The implementation is based on a counter. The counter is reset by the RST signal, and the reset pulse width is half the cycle width of CLKP. The counter starts counting from 0 at reset. When the counter count value is equal to the delay configuration code DELAY_CFG, the counter stops counting. At this time, the pulse delayer outputs a pulse signal. The rising edge of the pulse signal and the rising edge signal of the input first pulse filtered signal RST_S / second pulse filtered signal RST_R differ by DELAY_CFG CLKP clock cycles, thereby realizing a controllable delay function.

[0066] After obtaining the first pulse filtered signal RST_S and the second pulse filtered signal RST_R, the input set signal SET and reset signal RESET are clock synthesized, that is, the set signal SET generates a high level of the output clock, and the reset signal RESET generates a low level of the output clock, thereby synthesizing the two input pulse signals into a coarse delayed clock signal for output, and the rising edge of the coarse delayed clock signal is aligned with the rising edge of the set signal SET, and the falling edge of the coarse delayed clock signal is aligned with the falling edge of the reset signal RESET.

[0067] Finally, the coarse-delayed clock signal is finely delayed based on the digital time converter to obtain a fine-delayed clock signal. Specifically, the following steps are included: setting the control word of the digital time converter, and delaying the coarse-delayed clock signal based on the control word to obtain the fine-delayed clock signal with high resolution and large delay range that is ultimately required to be output.

[0068] This produces a precise delay on the input clock signal, and the output clock is the signal after the input clock is precisely delayed. The delay size is DTC_CFG×T DTC , where T DTC is the delay resolution of the digital time converter, DTC_CFG is the control word of the digital time converter, and the delay accuracy of the time-to-digital converter can be achieved within 1ps.

[0069] Based on the above scheme, the present application divides the clock delay into two parts, namely coarse delay and fine delay. The coarse delay is based on the counting of the counting clock signal CLKP, and its delay control resolution is one cycle of the counting clock signal CLKP clock, which is recorded as T CLKP , which is usually in the order of microseconds or even milliseconds; the fine delay is based on the digital time converter, and its delay control resolution is the resolution of 1 digital time converter, recorded as T DTC , which is usually in the order of picoseconds.

[0070] During delay, use T CLKP T DTC Normalized, that is, N T DTC The time length is equal to 1 T CLKP (T CLKP =N×T DTC ), by configuring the coarse delay control code DELAY_CFG and the fine delay control code DTC_CFG, the final delay time that can be achieved is T delay = DELAY_CFG × T CLKP + DTC_CFG×T DTC .

[0071] The clock signal CLKP is 312.5MHz, that is, T CLKP Taking 3.2ns as an example, the full range of the digital time converter is 3.2ns. The digital time converter selects 8-bit control, that is, 256 delays, and the time resolution of the digital time converter is 3.2ns÷256 = 12.5ps. To achieve a delay of 10.0000625us, you can configure DELAY_CFG to 3125 and DTC_CFG to 5 to achieve this delay requirement.

[0072] In traditional delay circuits, in order to achieve high-resolution delay, the delay step size of the delay unit is small. At this time, in order to achieve a larger delay range, the number of delay units needs to be increased. Each delay unit will generate power consumption overhead, so the power consumption will also increase linearly with the increase of the delay range. However, the present application uses a combination of coarse delay and fine delay to achieve high delay accuracy and a large delay adjustment range without increasing power consumption.

[0073] Example 2

[0074] like Figure 2 As shown, a low-power clock delay system includes a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit and a digital time conversion circuit;

[0075] a clock synchronization circuit, configured to perform phase alignment on the counting clock signal and the clock signal to be delayed based on the counting clock signal, and generate a first phase clock alignment signal and a second phase clock alignment signal, so as to eliminate a phase difference between the counting clock signal and the clock signal to be delayed;

[0076] A clock edge generating circuit, configured to extract rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal;

[0077] A clock edge separation circuit is used to separate the clock rising edge information and the clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal;

[0078] A pulse delay circuit, configured to sequentially coarsely delay the first pulse filtered signal and the second pulse filtered signal;

[0079] An RS trigger circuit is used to synthesize the first pulse filtered signal and the second pulse filtered signal after coarse delay to obtain a coarse delayed clock signal;

[0080] The digital time conversion circuit is used for finely delaying the coarse delay clock signal based on the digital time converter to obtain a fine delay clock signal.

[0081] Among them, the pulse delay circuit includes a first pulse delayer and a second pulse delayer; the first pulse delayer receives the first pulse filtering signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a set signal; the second pulse delayer receives the second pulse filtering signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a reset signal.

[0082] The clock edge generation circuit includes a D flip-flop and an exclusive OR logic gate; the D flip-flop receives a counting clock inversion signal obtained by inverting the counting clock signal and a first phase clock alignment signal sent by the clock synchronization circuit, and outputs a first phase clock resampling signal; the exclusive OR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

[0083] Since the low-power clock delay system of this embodiment implements the low-power clock delay method shown in the first embodiment, it will not be repeated here.

[0084] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form or substance. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention. These improvements and supplements should also be regarded as the scope of protection of the present invention. Any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the spirit and scope of the present invention by using the technical content disclosed above are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A low-power clock delay method, characterized in that: The following steps are involved: Performing phase alignment on the counting clock signal and the clock signal to be delayed based on the counting clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal; Extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal; Separating clock rising edge information and clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal, and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal; performing coarse delay on the first pulse filtered signal and the second pulse filtered signal in sequence, and synthesizing the coarsely delayed first pulse filtered signal and the second pulse filtered signal to obtain a coarse delayed clock signal; The coarse-delayed clock signal is finely delayed based on a digital-to-time converter to obtain a fine-delayed clock signal.

2. A low-power clock delay method according to claim 1, characterized in that: The method of performing a coarse delay on the first pulse filtered signal comprises the following steps: Setting a delay configuration code, triggering the counting clock signal to reset and start counting each time the first pulse filtering signal sends a pulse filtering signal; Every time the count value of the counting clock signal reaches the delay configuration code, the counting clock signal stops counting and outputs a set signal corresponding to the first pulse filtering signal.

3. A low-power clock delay method according to claim 2, characterized in that: The method of performing a coarse delay on the second pulse filtered signal comprises the following steps: When the second pulse filtering signal sends a pulse filtering signal, the counting clock signal is triggered to reset and start counting; Every time the count value of the counting clock signal reaches the delay configuration code, the counting clock signal stops counting and outputs a reset signal corresponding to the second pulse filtering signal.

4. A low-power clock delay method according to any one of claims 1 to 3, characterized in that: Finely delaying the coarse-delay clock signal based on a digital-to-time converter includes the following steps: A control word of the digital-to-time converter is set, and the coarse-delayed clock signal is delayed based on the control word to obtain a fine-delayed clock signal.

5. A low-power clock delay method according to claim 4, characterized in that: Phase-aligning the counting clock signal with the clock signal to be delayed based on the counting clock signal includes the following steps: Setting a counting clock signal, and resampling the delayed clock signal using the counting clock signal to obtain a first phase clock alignment signal and a second phase clock alignment signal; The first phase clock alignment signal and the second phase clock alignment signal are inverse signals to each other, and the first phase clock alignment signal and the clock signal to be delayed are in the same direction.

6. A low-power clock delay method according to claim 4, characterized in that: Extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal includes the following steps: Performing reverse processing on the counting clock signal to obtain a counting clock reverse signal; Resampling the first phase clock alignment signal by the counting clock inverse signal to generate a first phase clock resampled signal whose phase difference from the first phase clock alignment signal is half a clock period of the counting clock signal; A pulse signal carrying clock edge information is generated based on the first phase clock alignment signal and the first phase clock resampling signal.

7. A low-power clock delay method according to claim 4, characterized in that: The separation of clock rising edge information and clock falling edge information includes the following steps: Using the first phase clock alignment signal to filter out falling edge pulse information in the pulse signal to obtain a first pulse filtered signal; The second phase clock alignment signal is used to filter out rising edge pulse information in the pulse signal to obtain a second pulse filtered signal.

8. A low-power clock delay system, characterized in that: The low-power clock delay system implements the low-power clock delay method according to any one of claims 1 to 7, comprising a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit, and a digital time conversion circuit; The clock synchronization circuit is used to phase-align the counting clock signal with the clock signal to be delayed based on the counting clock signal, and generate a first phase clock alignment signal and a second phase clock alignment signal; The clock edge generating circuit is used to extract rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal; The clock edge separation circuit is used to separate the clock rising edge information and the clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal; The pulse delay circuit is used to sequentially perform coarse delay on the first pulse filtered signal and the second pulse filtered signal; The RS trigger circuit is used to synthesize the first pulse filtered signal and the second pulse filtered signal after coarse delay to obtain a coarse delayed clock signal; The digital time conversion circuit is used to perform fine delay on the coarse delayed clock signal based on a digital time converter to obtain a fine delayed clock signal.

9. The low-power clock delay system according to claim 8, characterized in that: The pulse delay circuit includes a first pulse delayer and a second pulse delayer; The first pulse delayer receives the first pulse filter signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a set signal; The second pulse delayer receives the second pulse filter signal, the counting clock signal and the set delay configuration code sent by the clock edge separation circuit, and outputs a reset signal.

10. The low-power clock delay system according to claim 8, characterized in that: The clock edge generating circuit includes a D flip-flop and an XOR logic gate; The D flip-flop receives a counting clock inversion signal obtained by inverting the counting clock signal and a first phase clock alignment signal sent by the clock synchronization circuit, and outputs a first phase clock resampling signal; The XOR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

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