Multi-level control chip channel management method and device

Abstract

The invention relates to the technical field of chip control management, in particular to a multi-level control chip channel management method and device.Firstly, a BMC analyzes an operation instruction sent by a user and sends a packaged internal instruction message to a master control MCU chip; after the MCU verifies that the message is complete, a target FPGA is determined based on the packaged internal instruction message, and then an operation code and a target identifier are sent to the target FPGA in a first instruction message mode; and finally, the target FPGA analyzes the first instruction message after receiving the first instruction message, extracts the operation code and the target identifier, searches a local SoC control interface mapping relation according to the target identifier, and drives a corresponding pin according to the operation code and the local SoC control interface mapping relation. When the SoC chip is added, only a new FPGA + SoC needs to be expanded on an existing FPGA or added to a new block. The master control MCU chip can be connected with the newly-added FPGA only by adding a small number of UART channels or multiplexing an existing bus, and expansion is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip control management, and in particular to a multi-level control chip channel management method and device. Background Art

[0002] For scenarios such as AI inference, edge computing, and high-density data centers, server designs are increasingly integrating a large number of SoCs (such as ARM SoCs, AI accelerator SoCs, and storage controller SoCs). These SoCs often require independent or grouped control operations such as power management, status monitoring, firmware updates, and debug interfaces. Challenges presented by large-scale I / O control include: 1. Exploding interface complexity: If each SoC's multiple control I / Os (such as Power Enable, Reset, I2C / SPI / SMBus, JTAG / SWD, and GPIO) are individually connected to a central management system (such as a BMC), the backplane design becomes extremely complex, requiring a large number of cables, reducing reliability, and dramatically increasing costs. 2. Overloaded BMCs: The BMC must manage and drive a vast number of point-to-point interfaces, incurring significant overhead in handling concurrent requests, making it a performance bottleneck and a single point of failure. 3. Poor scalability: Adding new SoCs requires modifications to the BMC's interface, driver, and board layout, limiting flexibility. 4. Long-distance transmission of control signals: Long traces can lead to reduced signal integrity, noise interference, and increased latency. 5. Difficulty managing hot swapping and partitioning: It is difficult to power on / off and isolate physical blocks or functional modules. To overcome these issues, current solutions include single bus extensions (such as I2C / SPI), daisy chaining, multiple BMCs or management nodes, and using FPGAs as simple logic extensions or bridges. However, existing solutions still have the following limitations: Single bus extensions (such as I2C / SPI): When there are many nodes, the bus load is high, conflicts increase, reliability decreases, address conflict management becomes complex, and speed may be insufficient. Daisy chaining: Faults easily propagate, latency increases with chain length, and locating problematic nodes is difficult. Multiple BMCs or management nodes: The architecture is complex, the cost is higher, and upper-layer coordination mechanisms are required. Using FPGAs as simple logic extensions or bridges fails to fully utilize the computing and intelligence advantages of FPGAs, and the master control node (such as the BMC) still needs to directly manage a large number of low-level details. Summary of the Invention

[0003] The purpose of the present invention is to provide a multi-level control chip channel management method and device, which fully utilizes the advantages of FPGA, has a simple structure and strong scalability.

[0004] To achieve the above objectives, the present invention provides a multi-level control chip channel management method, the method comprising:

[0005] Step S1: The user sends an operation instruction to the baseboard management controller (BMC) of the server;

[0006] Step S2: The BMC parses the operation instruction and sends the packaged internal instruction message to the main control MCU chip;

[0007] Step S3: After the master control MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message;

[0008] Step S4: After receiving the first instruction message, the target FPGA parses it, extracts the operation code and the target identifier, searches for the local SoC control interface mapping relationship based on the target identifier, and drives the corresponding pin according to the local SoC control interface mapping relationship based on the operation code.

[0009] Optionally, the method further includes:

[0010] After the target FPGA drives the corresponding pin, it generates a response message and sends it back to the main control MCU chip through the UART channel;

[0011] The master MCU chip receives the response messages from each target FPGA and aggregates or directly transmits the response messages to generate final status information, and feeds back the final status information to the user through the remote management interface and sends it back to the BMC through the UART channel.

[0012] After receiving the final status information, the BMC updates an internal status database.

[0013] Optionally, after the master control MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and the target identifier to the target FPGA in the form of a first instruction message, specifically including:

[0014] Step S31: The main control MCU chip receives the encapsulated internal command message sent by the BMC through the UART channel and verifies whether the encapsulated internal command message is complete. If the verification is incomplete, the encapsulated internal command message is discarded and a request is made to resend it. If the verification is complete, "Step S32" is executed;

[0015] Step S32: The main control MCU chip parses the encapsulated internal instruction message to obtain the operation code and target identifier, and searches for the corresponding target FPGA according to the control domain-agent FPGA mapping table based on the target identifier, and then sends the operation code and the target identifier to the target FPGA in the form of the first instruction message.

[0016] Optionally, the BMC parses the operation instruction and sends the encapsulated internal instruction message to the main control MCU chip, specifically including:

[0017] The BMC parses the operation instruction and verifies whether the operation permission and SoC ID are valid in the global scope of the system; if not, the process ends; if valid, an internal instruction message is generated, and the internal instruction message is encapsulated according to the instruction format, and the encapsulated internal instruction message is sent to the main control MCU chip through the UART serial communication protocol.

[0018] Optionally, the user sends an operation instruction to a baseboard management controller (BMC) of the server, specifically including:

[0019] The user sends an operation instruction to the server's baseboard management controller (BMC) through the remote management interface.

[0020] The present invention also provides a multi-level control chip channel management device, the device comprising:

[0021] A baseboard management controller (BMC), a main control MCU chip, at least one FPGA, and a blade board; the baseboard management controller (BMC), the main control MCU chip, and each FPGA are connected via a UART channel; the blade board is connected to each FPGA respectively; and multiple SoC chips are provided on the blade board;

[0022] The baseboard management controller (BMC) is used to receive operation instructions input by the user, parse the operation instructions, and send the packaged internal instruction message to the main control MCU chip;

[0023] The main control MCU chip is used to receive and verify the integrity of the encapsulated internal command message sent by the BMC, determine the target FPGA based on the encapsulated internal command message, and then send the operation code and target identifier to the target FPGA in the form of a first command message;

[0024] The target FPGA is used to parse the first instruction message after receiving it, extract the operation code and the target identifier, and search for the local SoC control interface mapping relationship according to the target identifier, and drive the corresponding pin on the blade board according to the local SoC control interface mapping relationship according to the operation code.

[0025] Optionally, the device further comprises:

[0026] At least one switch is connected to the baseboard management controller BMC respectively, and is used to provide a network.

[0027] Optionally, the device further comprises:

[0028] A power board including multiple power supplies is connected to the baseboard management controller BMC and the main control MCU chip respectively to provide electrical energy.

[0029] Optionally, after the target FPGA is used to drive the corresponding pin, it generates a response message and sends it back to the main control MCU chip through the UART channel;

[0030] The main control MCU chip is also used to receive the response messages from each target FPGA and aggregate or directly transmit the response messages to generate final status information, and feed back the final status information to the user through the remote management interface, and send it back to the BMC through the UART channel.

[0031] The BMC is further configured to update an internal status database after receiving the final status information.

[0032] Optionally, the device further comprises:

[0033] The signal input display device is connected to the main control MCU chip and is used to input user operation instructions and / or display the final status information.

[0034] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0035] The present invention provides a multi-level control chip channel management method and device. First, the user sends an operation instruction to the server's baseboard management controller (BMC); second, the BMC parses the operation instruction and sends a packaged internal instruction message to the main control MCU chip; then, after the main control MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message; finally, after receiving the first instruction message, the target FPGA parses it, extracts the operation code and target identifier, and searches for the local SoC control interface mapping relationship based on the target identifier, and drives the corresponding pin according to the local SoC control interface mapping relationship based on the operation code. When adding an SoC chip, the present invention only needs to expand on the existing FPGA or add a new FPGA+SoC to a new block, and register the new range to the new FPGA ID in the mapping table of the main control MCU chip. The main control MCU chip only needs to add a small number of UART channels or reuse the existing bus to connect to the newly added FPGA to achieve expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 This is a structural diagram of a multi-level control chip channel management device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] The purpose of the present invention is to provide a multi-level control chip channel management method and device, which fully utilizes the advantages of FPGA, has a simple structure and strong scalability.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Example 1

[0042] like Figure 1 As shown, the present invention discloses a multi-level control chip channel management device, the device comprising:

[0043] A baseboard management controller (BMC), a main control MCU chip, at least one FPGA, and a blade board; the baseboard management controller (BMC), the main control MCU chip, and each FPGA are connected via a UART channel; the blade board is connected to each FPGA respectively; and multiple SoC chips are provided on the blade board.

[0044] The baseboard management controller BMC is used to receive operation instructions input by the user, parse the operation instructions, and send the packaged internal instruction message to the main control MCU chip; the main control MCU chip is used to receive and verify that the packaged internal instruction message sent by the BMC is complete, determine the target FPGA based on the packaged internal instruction message, and then send the operation code and target identifier to the target FPGA in the form of a first instruction message; the target FPGA is used to parse the first instruction message after receiving it, extract the operation code and target identifier, and search for the local SoC control interface mapping relationship according to the target identifier, and drive the corresponding pins on the blade board according to the local SoC control interface mapping relationship according to the operation code.

[0045] In this application, the baseboard management controller BMC is set with 2 USB interfaces, 2 RJ45 interfaces and 1 HDMI interface. The above is just an example. The specific number of each interface is set according to actual needs and is not limited here.

[0046] In this application, multiple FPGAs and master MCU chips can be set on multiple small base boards or on a large base board. Preferably, they are set on a large base board to facilitate subsequent direct unified management.

[0047] As an optional embodiment, the apparatus of the present invention further includes: at least one switch, each connected to a baseboard management controller (BMC) for providing a network. This application uses two switches, switch A and switch B, as an example. Switch A and switch B are both connected to the BMC via UART and Ethernet to provide a network to the BMC.

[0048] As an optional embodiment, the apparatus of the present invention further includes a power board comprising multiple power supplies, each connected to a baseboard management controller (BMC) and a main control MCU chip, for providing power to the BMC and the main control MCU chip. The power supplies may also be connected to multiple FPGAs for providing power to the FPGAs. The power board of the present invention can generate a 12V main power supply to provide power to the BMC and to the main control MCU chip via a power management bus (PMBUS).

[0049] As an optional implementation, after the target FPGA drives the corresponding pins, it generates a response message and sends it back to the master MCU chip via the UART channel. The master MCU chip is also responsible for receiving the response messages from each target FPGA and aggregating or directly transparently transmitting them to generate final status information. This final status information is then fed back to the user via the remote management interface and sent back to the BMC via the UART channel. The BMC is also responsible for updating its internal status database after receiving the final status information. After the operation is completed, the final status can also be fed back to the user to inform them whether the final operation was successful.

[0050] The remote management interface disclosed in the present application may be at least one of Redfish API, IPMI and Web GUI. Redfish API is a modern standard interface based on RESTful architecture, used to manage and monitor data center infrastructure such as servers, storage, and network equipment. It was developed by DMTF to provide a more efficient, flexible and standardized way of hardware management. IPMI (Intelligent Platform Management Interface) is an open standard hardware management interface specification for out-of-band management and monitoring of computer systems. IPMI commands allow administrators to remotely manage server hardware over the network, even if the server operating system crashes or is not running. Web GUI (Graphical User Interface) is a visual interactive interface presented by a web browser, where users can interact with web applications through input devices such as a mouse and keyboard. It is different from the command line interface and uses graphical elements (such as icons, buttons, forms, etc.) to simplify operations and enhance user experience.

[0051] As an optional embodiment, the device of the present invention also includes: a signal input and display device, which is connected to the main control MCU chip and is used to input user operation instructions and / or display the final status information; specifically, the signal input and display device can be a UID button / indicator light, a power button & power indicator light, an operating keyboard and a display, etc., which can be set according to actual needs and will not be discussed in detail here.

[0052] As an optional implementation, the temperature sensor of the present invention can also be set on the blade plate to detect the temperature. Other sensors can also be set on the blade plate as inputs. The specific settings can be made according to actual needs.

[0053] The BMC of the present invention only processes abstract instructions and global IDs, the MCU is responsible for routing and partition management, and the FPGA is responsible for specific signal driving and hardware adaptation, thereby realizing layered processing.

[0054] The FPGA of the present invention can realize multiple SoC control tasks in parallel processing areas at the same time.

[0055] When adding an SoC chip, the present invention only requires expanding the existing FPGA (or connector support) or adding a new FPGA+SoC in a new block, and registering the new range to the new FPGA ID in the mapping table of the main control MCU chip. The main control MCU chip only needs to add a few UART channels or reuse the existing bus to connect to the newly added FPGA to achieve expansion.

[0056] When adding a new SoC model or control requirement, the present invention generally only requires updating the FPGA logic without changing the BMC and MCU core logic.

[0057] Example 2

[0058] The present invention also discloses a multi-level control chip channel management method, the method comprising:

[0059] Step S1: The user issues an operation instruction to the baseboard management controller (BMC) of the server. Specifically, the user issues the operation instruction to the baseboard management controller (BMC) of the server through the remote management interface. The operation instruction includes the operation authority and SoCID, for example: Power Off SoC#1.

[0060] Step S2: The BMC parses the operation instruction and sends the encapsulated internal instruction message to the main control MCU chip. Specifically, the BMC parses the operation instruction and verifies whether the operation permission and SoC ID are valid within the system; if not, the process ends; if valid, the BMC generates an internal instruction message, encapsulates the internal instruction message according to the instruction format, and sends the encapsulated internal instruction message to the main control MCU chip via the UART serial communication protocol. Specifically, the BMC sends the encapsulated internal instruction message to the main control MCU chip via the UART serial communication protocol through a hardware interface via a single physical line (RX / TX).

[0061] The encapsulated internal instruction message contains: an operation code and a target identifier, and may also include transmission parameters and a check procedure. Among them, the operation code (Opcode) is used to define the operation type (for example, Opcode = 0x01, 0x01 means power off). The target identifier (Target ID) represents the globally unique SoC chip identifier (for example, Target ID = 0x0001, 0x0001 represents SoC number 1). Transmission parameters include delay time, status query command, etc. The check procedure is used to ensure the integrity of the instruction, and the check procedure uses CRC16+CRC32 algorithms for verification.

[0062] Step S3: After the master MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message, which specifically includes:

[0063] Step S31: The main control MCU chip receives the encapsulated internal command message sent by the BMC through the UART channel, and verifies whether the encapsulated internal command message is complete. If the verification is incomplete, the encapsulated internal command message is discarded and a request is made to resend it. If the verification is complete, "Step S32" is executed; specifically, if there is data loss or incorrect check bit in the message, it means that the message verification is incomplete.

[0064] Step S32: The master MCU chip parses the encapsulated internal instruction message to obtain an operation code and a target identifier, and searches for the corresponding target FPGA according to the control domain-proxy FPGA mapping table based on the target identifier, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message; the control domain-proxy FPGA mapping table of the present invention is stored in the internal Flash or EEPROM of the master MCU chip, and the control domain-proxy FPGA mapping table is preset in the internal Flash or EEPROM of the master MCU chip in advance, and is also updated in real time according to data changes.

[0065] Example of the control domain-proxy FPGA mapping table structure:

[0066]

[0067] The main control MCU chip searches the control domain-proxy FPGA mapping table based on the target identifier Target ID = 0x0001. Since 0x0001-0x0008 belong to FPGA #0, it determines that this SoC belongs to the management scope of FPGA #0 (Channel 0). Therefore, it will send the first command message to FPGA #0 instead of FPGA 1.

[0068] Step S4: After receiving the first instruction message, the target FPGA parses it, extracts the opcode and target identifier, searches for the local SoC control interface mapping relationship based on the target identifier, and drives the corresponding pins according to the opcode and the local SoC control interface mapping relationship. For example, the local SoC control interface mapping relationship corresponds to a specific set of pins in the FPGAIO Bank for SoC#1. The target FPGA may also monitor the power-off status signal (such as PGD) of SoC#1 through its ADC or GPIO, and save the status in an internal register or feed it back to the MCU / BMC. The target FPGA can also manage the signals required by multiple SoCs in the area simultaneously or nearly simultaneously, with a high degree of parallelism.

[0069] Step S5: After the target FPGA drives the pin, it generates a response message and sends it back to the main control MCU chip through the UART channel; the response message includes the target SoC status and / or execution result; the target SoC status is, for example, powered off; the execution result includes success or failure.

[0070] Step S6: The master MCU chip receives the response messages from each target FPGA and aggregates or directly transmits them to generate final status information. It then feeds the final status information back to the user through the remote management interface and sends it back to the BMC through the UART channel. Direct transmission can include information such as timestamps and original instruction IDs.

[0071] Step S7: After receiving the final status information, the BMC updates the internal status database; the final status information is such as "SoC#1 is powered off successfully".

[0072] Step S8: The master MCU chip receives the encapsulated internal command message sent by the BMC through the UART channel, modifies it and / or transmits it transparently, and then sends it to the target FPGA through another UART channel. The forwarding protocol should be consistent between the master MCU chip and all FPGAs.

[0073] The above method can also be applied to the following solutions, such as pulling down a specific GPIO (Power Enable) pin for SoC#1; writing a specific shutdown command register to the power management IC (PMIC) on SoC#1 through an I2C controller (built into the FPGA logic), etc. The details are not described one by one.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0075] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A multi-level control chip channel management method, characterized in that: The method comprises: Step S1: The user sends an operation instruction to the baseboard management controller (BMC) of the server; Step S2: The BMC parses the operation instruction and sends the packaged internal instruction message to the main control MCU chip; Step S3: After the master control MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message; Step S4: After receiving the first instruction message, the target FPGA parses it, extracts the operation code and the target identifier, searches for the local SoC control interface mapping relationship based on the target identifier, and drives the corresponding pin according to the local SoC control interface mapping relationship based on the operation code.

2. The multi-level control chip channel management method according to claim 1, characterized in that: The method further comprises: After the target FPGA drives the corresponding pin, it generates a response message and sends it back to the main control MCU chip through the UART channel; The master MCU chip receives the response messages from each target FPGA and aggregates or directly transmits the response messages to generate final status information, and feeds back the final status information to the user through the remote management interface and sends it back to the BMC through the UART channel. After receiving the final status information, the BMC updates an internal status database.

3. The multi-level control chip channel management method according to claim 1, characterized in that: After the master control MCU chip verifies that the packaged internal instruction message is complete, it determines the target FPGA based on the packaged internal instruction message, and then sends the operation code and target identifier to the target FPGA in the form of a first instruction message, specifically including: Step S31: The main control MCU chip receives the encapsulated internal command message sent by the BMC through the UART channel and verifies whether the encapsulated internal command message is complete. If the verification is incomplete, the encapsulated internal command message is discarded and a retransmission request is made; if the verification is complete, "step S32" is executed; Step S32: The main control MCU chip parses the encapsulated internal instruction message to obtain the operation code and target identifier, and searches for the corresponding target FPGA according to the control domain-agent FPGA mapping table based on the target identifier, and then sends the operation code and the target identifier to the target FPGA in the form of the first instruction message.

4. The multi-level control chip channel management method according to claim 1, characterized in that: The BMC parses the operation instruction and sends the packaged internal instruction message to the main control MCU chip, specifically including: The BMC parses the operation instruction and verifies whether the operation permission and SoC ID are valid in the global scope of the system; if not, the process ends; if valid, an internal instruction message is generated, and the internal instruction message is encapsulated according to the instruction format, and the encapsulated internal instruction message is sent to the main control MCU chip.

5. The multi-level control chip channel management method according to claim 1, characterized in that: The user sends an operation instruction to the baseboard management controller BMC of the server, specifically including: The user sends an operation instruction to the server's baseboard management controller (BMC) through the remote management interface.

6. A multi-level control chip channel management device, characterized in that: The device comprises: A baseboard management controller (BMC), a main control MCU chip, at least one FPGA, and a blade board; the baseboard management controller (BMC), the main control MCU chip, and each FPGA are connected via a UART channel; the blade board is connected to each FPGA respectively; and multiple SoC chips are provided on the blade board; The baseboard management controller (BMC) is used to receive operation instructions input by the user, parse the operation instructions, and send the packaged internal instruction message to the main control MCU chip; The main control MCU chip is used to receive and verify the integrity of the encapsulated internal command message sent by the BMC, determine the target FPGA based on the encapsulated internal command message, and then send the operation code and target identifier to the target FPGA in the form of a first command message; The target FPGA is used to parse the first instruction message after receiving it, extract the operation code and the target identifier, and search for the local SoC control interface mapping relationship according to the target identifier, and drive the corresponding pin on the blade board according to the local SoC control interface mapping relationship according to the operation code.

7. The multi-level control chip channel management device according to claim 6, characterized in that: The device further comprises: At least one switch is connected to the baseboard management controller BMC respectively, and is used to provide a network.

8. The multi-level control chip channel management device according to claim 6, characterized in that: The device further comprises: A power board including multiple power supplies is connected to the baseboard management controller BMC and the main control MCU chip respectively to provide electrical energy.

9. The multi-level control chip channel management device according to claim 6, characterized in that: The target FPGA is used to drive the corresponding pin and generate a response message and send it back to the main control MCU chip through the UART channel; The main control MCU chip is also used to receive the response messages from each target FPGA and aggregate or directly transmit the response messages to generate final status information, and feed back the final status information to the user through the remote management interface, and send it back to the BMC through the UART channel. The BMC is further configured to update an internal status database after receiving the final status information.

10. The multi-level control chip channel management device according to claim 9, characterized in that: The device further comprises: The signal input display device is connected to the main control MCU chip and is used to input user operation instructions and / or display the final status information.

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