Semiconductor structure and forming method thereof
By setting a stress adjustment layer on the conductive material layer, the problem of warping of multi-layer wafer stacking is solved, and the flatness and yield of the wafer stack are improved.
Patent Information
- Application Number
- CN202510772231.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-10
- Publication Date
- 2025-09-16
AI Technical Summary
In semiconductor manufacturing, multi-layer wafer stacking leads to warping problems, especially when the warping value exceeds 500μm after the conductive material layer is covered, affecting the normal progress of subsequent processing.
A first stress adjustment layer is provided on the conductive material layer to cover its edge and improve the warping of the wafer stack by applying a compressive stress opposite to the warping direction. The second and third stress adjustment layers are combined to further improve the flatness.
It effectively improves the warpage of the wafer stack, ensures that it can enter the exposure/etching machine for operation, and improves the flatness and yield of the wafer stack.
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Figure CN120657022A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] In the field of semiconductor manufacturing and advanced packaging, wafer-on-wafer (WoW) is a three-dimensional integration technology that forms a high-density interconnected structure by directly stacking and bonding multiple wafers vertically. This structure is one of the key technologies to break the limitations of Moore's Law and achieves coordinated optimization of semiconductor device performance, power consumption and area through 3D integration.
[0003] Currently, in the WoW structure, the vertical stacking of multiple wafers causes wafer warping. Especially as the number of wafer stacking layers increases, the degree of warping also accumulates and increases, thereby affecting the normal progress of subsequent processing of the WoW structure.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention
[0005] In view of this, a semiconductor structure and a method for forming the same are provided. The semiconductor structure can improve the warping degree of the wafer stack and improve the flatness of the wafer stack by disposing a first stress adjustment layer on the conductive material layer.
[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.
[0007] According to one aspect of the present disclosure, there is provided a semiconductor structure, comprising:
[0008] A wafer stack, the wafer stack comprising a bottom wafer and at least one wafer sequentially stacked on the bottom wafer along a first direction, each wafer comprising a bonding pad, two adjacent wafers being bonded to each other via the bonding pads, the first direction being a direction perpendicular to a surface of the bottom wafer;
[0009] a conductive material layer covering a side of the wafer stack away from the bottom wafer;
[0010] A first stress adjustment layer is located on a side of the conductive material layer away from the wafer stack, and the first stress adjustment layer at least covers an edge of the conductive material layer.
[0011] In an exemplary embodiment of the present disclosure, the orthographic projection of the first stress adjustment layer on the surface of the underlying wafer coincides with the orthographic projection of the conductive material layer on the surface of the underlying wafer, and the thickness of the central area of the first stress adjustment layer is less than the thickness of the edge area.
[0012] In an exemplary embodiment of the present disclosure, the orthographic projection of the first stress adjustment layer on the conductive material layer exposes the central area of the conductive material layer, and the orthographic projection of the first stress adjustment layer on the surface of the conductive material layer coincides with the edge of the surface of the conductive material layer.
[0013] In an exemplary embodiment of the present disclosure, the first stress adjustment layer includes a plurality of first sub-stress layers, an array of the first sub-stress layers is arranged on a surface of the conductive material layer away from the underlying wafer, and at least part of the first sub-stress layers is distributed on the edge of the conductive material layer.
[0014] In an exemplary embodiment of the present disclosure, the structure also includes a second stress adjustment layer, which is located on a side of the bottom wafer away from the conductive material layer. In the first direction, the stress direction applied to the wafer stack by the second stress adjustment layer and the first stress adjustment layer is the same.
[0015] In an exemplary embodiment of the present disclosure, the thickness of the second stress adjustment layer is less than the thickness of the first stress adjustment layer; the edge of the orthographic projection of the second stress adjustment layer on the surface of the underlying wafer is located within the edge of the orthographic projection of the first stress adjustment layer on the surface of the underlying wafer.
[0016] In an exemplary embodiment of the present disclosure, a thickness of a central region of the second stress adjustment layer is smaller than a thickness of an edge region thereof.
[0017] In an exemplary embodiment of the present disclosure, the structure further includes a third stress adjustment layer, the third stress adjustment layer is located between the bottom wafer and the second stress adjustment layer, and the third stress adjustment layer includes a metal material.
[0018] In an exemplary embodiment of the present disclosure, the thickness of the third stress adjustment layer is greater than the thickness of the second stress adjustment layer; and the thickness of the third stress adjustment layer is less than the thickness of the conductive material layer.
[0019] In an exemplary embodiment of the present disclosure, the second stress adjustment layer covers a bottom surface and side surfaces of the third stress adjustment layer.
[0020] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:
[0021] Providing a wafer stack, the wafer stack comprising a bottom wafer and at least one wafer sequentially stacked on the bottom wafer along a first direction, each wafer comprising a bonding pad, two adjacent wafers being bonded to each other via the bonding pads, wherein the first direction is a direction perpendicular to a surface of the bottom wafer;
[0022] forming a conductive material layer on a surface of the wafer stack;
[0023] A first stress adjustment layer is deposited on a side of the conductive material layer away from the bottom wafer, wherein the first stress adjustment layer at least covers an edge of the conductive material layer.
[0024] The semiconductor structure provided by the present disclosure forms a conductive material layer on a wafer stack to provide a structural foundation for electrical connection between the wafer stack and other device structures. However, due to the thin thickness of the wafer itself, warping may occur. In particular, after multiple wafers are stacked to form a wafer stack, the accumulated warping may cause the warping value of the wafer stack to reach 400μm. After the conductive material layer is formed on the wafer stack, the conductive material layer causes the metal volume on the wafer stack to be uneven, resulting in an increase in the warping of the wafer stack. The warping value of the wafer stack may exceed 500μm, which makes it impossible for the wafer stack to enter the exposure / etching machine for operation. Therefore, the semiconductor structure provided by the present disclosure forms a first stress adjustment layer on the conductive material layer. The first stress adjustment layer covers at least the edge of the conductive material layer. The first stress adjustment layer can generate compressive stress in the opposite direction of the warping of the wafer stack, thereby improving the warping of the wafer stack and improving the flatness of the wafer stack, allowing the wafer stack to enter the exposure / etching machine for operation.
[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0027] Figure 1 It is a schematic structural diagram of a wafer stack in the prior art in an exemplary embodiment of the present disclosure.
[0028] Figure 2 Schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
[0029] Figure 3 Schematic cross-sectional view of a first stress adjustment layer in an exemplary embodiment of the present disclosure.
[0030] Figure 4 Schematic diagram of the structure of the central area and edge area of a first stress adjustment layer in an exemplary embodiment of the present disclosure.
[0031] Figure 5 Schematic diagram of the structure of a first stress adjustment layer in an exemplary embodiment of the present disclosure.
[0032] Figure 6 Schematic diagram of the structure of another first stress adjustment layer in an exemplary embodiment of the present disclosure.
[0033] Figure 7 Schematic diagram of another semiconductor structure in an exemplary embodiment of the present disclosure.
[0034] Figure 8 Schematic diagram of the structure of a second stress adjustment layer in an exemplary embodiment of the present disclosure.
[0035] Figure 9 Schematic diagram of another semiconductor structure in an exemplary embodiment of the present disclosure.
[0036] Figure 10 The present invention is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0037] Figure 11 Schematic diagram of the structure of a wafer stack in an exemplary embodiment of the present disclosure.
[0038] Figure 12 Schematic diagram of the structure of a conductive material layer in an exemplary embodiment of the present disclosure.
[0039] Figure 13 Schematic diagram of the structure of a patterned photoresist layer in an exemplary embodiment of the present disclosure.
[0040] Figure 14 Schematic diagram of the structure of a conductive interconnect layer in an exemplary embodiment of the present disclosure.
[0041] Figure 15 Schematic diagram of the structure of a dielectric layer in an exemplary embodiment of the present disclosure.
[0042] The description of the accompanying drawings is as follows:
[0043] 100, wafer stack; 110, bottom wafer; 120, wafer; 121, solder pad; 200, conductive material layer; 310, first stress adjustment layer; 311, first sub-stress layer; 320, second stress adjustment layer; 330, third stress adjustment layer; 400, patterned photoresist layer; 500, solder pad; 600, dielectric layer; X, first direction; A, warpage value; a, central area of the first stress adjustment layer; b, edge area of the first stress adjustment layer. DETAILED DESCRIPTION
[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0045] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.
[0046] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.
[0047] In related technologies, the WoW structure is to align two or more wafers face to face or back to back, and achieve electrical connection through hybrid bonding or microbumps. This structure can reduce the wafer interconnection spacing and the signal transmission distance, thereby reducing signal delay and device power consumption, and thus improving device performance.
[0048] At present, the thickness of the wafer is usually below 20μm. Due to the small thickness of the wafer, a single-layer wafer has a certain warpage value, such as Figure 1As shown, after multiple layers of wafers 120 are stacked to form a wafer stacking structure, the degree of warping is aggravated. For example, when the number of stacked layers of wafers 120 reaches 8 or more, the warping value A of the wafer stacking structure will reach 400μm, especially after the conductive material layer is covered on the wafer 120. Since the covering of the conductive material layer will cause the metal volume on the wafer stacking structure to be uneven, the cumulative degree of the warping value A of the wafer stacking structure will be increased. The warping value A of the wafer stacking structure will reach more than 500μm, resulting in the wafer stacking structure being unable to enter the exposure / etching machine normally for operation.
[0049] Based on this, the present disclosure provides a semiconductor structure, such as Figure 2 As shown, the semiconductor structure includes: a wafer stack 100 , a conductive material layer 200 and a first stress adjustment layer 310 .
[0050] Among them, the wafer stack 100 includes a bottom wafer 110 and at least one wafer 120 stacked on the bottom wafer 110 in sequence along a first direction X, each wafer 120 includes a bonding pad 121, and two adjacent wafers 120 are bonded to each other through the bonding pad 121, and the first direction X is a direction perpendicular to the surface of the bottom wafer 110; the conductive material layer 200 covers the side of the wafer stack 100 away from the bottom wafer 110; the first stress adjustment layer 310 is located on the side of the conductive material layer 200 away from the wafer stack 100, and the first stress adjustment layer 310 covers at least the edge of the conductive material layer 200.
[0051] The semiconductor structure provided by the present disclosure forms a conductive material layer 200 on the wafer stack 100 to provide a structural basis for forming an electrical connection between the wafer stack 100 and other device structures. However, due to the thin thickness of the wafer 120 itself, warping may occur. In particular, after multiple wafers 120 are stacked to form the wafer stack 100, the warping value of the wafer stack 100 may reach 400 μm due to warping accumulation. After the conductive material layer 200 is formed on the wafer stack 100, the conductive material layer 200 makes the metal volume on the wafer stack 100 uneven, resulting in an aggravated warping of the wafer stack 100. The warpage value will exceed 500μm, which will cause the wafer stack 100 to be unable to enter the exposure / etching machine for operation. Therefore, the semiconductor structure provided by the present invention forms a first stress adjustment layer 310 on the conductive material layer 200. The first stress adjustment layer 310 at least covers the edge of the conductive material layer 200. The first stress adjustment layer 310 can generate a compressive stress opposite to the warping direction of the wafer stack 100, thereby improving the warping of the wafer stack 100 and improving the flatness of the wafer stack 100, so that the wafer stack 100 can enter the exposure / etching machine for operation, thereby improving the yield of the wafer stack 100.
[0052] The following describes in detail the various parts of the semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:
[0053] In the embodiments provided herein, wafer 120 may be a silicon wafer, such as single crystal silicon, polycrystalline silicon, or silicon germanium (GeSi); a compound semiconductor wafer, such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or indium phosphide (InP); or a silicon-on-insulator (SOI). The specific type of wafer 120 may be selected based on the actual design requirements of the semiconductor structure and is not specifically limited in this disclosure.
[0054] In the embodiments provided in the present disclosure, Figure 2 As shown, the structure includes a wafer stack 100 , wherein the wafer stack 100 includes a bottom wafer 110 and at least one wafer 120 stacked on the bottom wafer 110 in sequence along a first direction X, where the first direction X is a direction perpendicular to the surface of the bottom wafer 110 .
[0055] The bottom wafer 110 and the wafer 120 stacked on the bottom wafer 110 can be of the same or different types. For example, when the bottom wafer 110 and the wafer 120 stacked on the bottom wafer 110 are of different types, the bottom wafer 110 can be a bare wafer or a logic chip wafer, and the wafer 120 stacked on the bottom wafer 110 can be a logic chip wafer or a memory wafer, etc. The bottom wafer 110 can provide mechanical support for the upper wafer 120 to ensure the effectiveness and reliability of the electrical interconnection of the multiple layers of wafers 120. Both the bottom wafer 110 and the wafer 120 can be memory wafers.
[0056] The number of wafers 120 stacked on the bottom wafer 110 is at least one, and can be, for example, one, two, three, five, seven, or even more. The number of wafers 120 stacked can be determined based on the actual number of bonding layers required for the device. Furthermore, to improve device integration and ensure device performance, the number of wafers 120 stacked is typically 8 or more.
[0057] Among them, such as Figure 2 As shown, each wafer 120 includes a bonding pad 121, and two adjacent wafers 120 are bonded to each other via the bonding pads 121 to form metal interconnects between the wafers 120. In addition, when the bonding pads 121 are bonded, the dielectric material layer between the two adjacent wafers 120 is also bonded simultaneously to reduce the interconnection spacing and improve the integration of the device.
[0058] Among them, the dielectric material layer can be made of materials such as silicon oxide (SiO2), and the surface of the silicon oxide layer between the two adjacent wafers 120 is mechanically connected through the chemical bond Si-O-Si. Of course, when the dielectric material layer is made of other materials, chemical bonds can also be formed on the surface of the dielectric material layer between the two adjacent wafers 120 to achieve mixed bonding between the adjacent wafers 120.
[0059] In addition, a bonding stress adjustment layer can be provided between two adjacent wafers 120 to avoid the phenomenon of increased warping of the wafer 120 during the bonding process. The bonding stress adjustment layer can be made of materials such as silicon oxide (SiO2) and silicon nitride (Si3N4), and the material can be selected and adjusted according to the stress type required for the bonding stress adjustment layer. In addition, the bonding stress adjustment layer can be provided on each layer of wafer 120, or only on part of the wafer 120, or can be provided on a single wafer 120.
[0060] In some embodiments, as Figure 2 As shown, the thickness of the bottom wafer 110 can be greater than the thickness of the wafer 120 stacked thereon. When the wafer 120 is stacked on the bottom wafer 110, the bottom wafer 110 has a certain anti-warping ability to improve the warping phenomenon of the wafer stack 100 to at least a certain extent.
[0061] In some embodiments, an epitaxial layer can also be formed on the side of the bottom wafer 110 facing away from the conductive material layer 200. The epitaxial layer can be used to increase the thickness of the bottom wafer 110, thereby improving the warping resistance of the bottom wafer 110, thereby improving the warping phenomenon of the wafer stack 100 at least to a certain extent.
[0062] In the embodiments provided in the present disclosure, Figure 2 As shown, the structure includes a conductive material layer 200, which covers the side of the wafer stack 100 away from the bottom wafer 110. The conductive material layer 200 can realize electrical interconnection between the wafer stack 100 and external device structures.
[0063] The conductive material layer 200 can be made of a metal material, for example, it can be one or more of aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), etc., and its thickness can be 0.1μm to 3μm. The thickness of the conductive material layer 200 can be selected according to the specific material selected and the design of the device structure. For example, in some device structures, when cobalt is used to realize metal interconnection, the thickness of the cobalt layer can be 5nm to 20nm. Taking into account the cost and performance balance of metal interconnection, the conductive material layer 200 provided in the present disclosure is made of aluminum (Al), but it should be understood that when the conductive material layer 200 is made of other types of metal materials, the first stress adjustment layer 310 can be adaptively adjusted, which is also within the scope of protection of the present disclosure.
[0064] In the embodiments provided in the present disclosure, Figure 2 As shown, the structure includes a first stress adjustment layer 310 . The first stress adjustment layer 310 is located on a side of the conductive material layer 200 away from the wafer stack 100 , and the first stress adjustment layer 310 at least covers the edge of the conductive material layer 200 .
[0065] According to the warping direction of the wafer stack 100 , the first stress adjustment layer 310 can provide the wafer stack 100 with stress opposite to the warping direction thereof, thereby improving the warping degree of the wafer stack 100 and thereby improving the flatness of the wafer stack 100 .
[0066] The first stress adjustment layer 310 can be made of materials such as silicon oxide (SiO2) or silicon hydroxide (SiOH), and can be formed on the conductive material layer 200 by one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation (Thermal Oxidation), and sol-gel (Sol-Gel). The formation process of the first stress adjustment layer 310 can be determined according to the selection of its specific material, and this disclosure does not make any specific limitations.
[0067] In some embodiments, the orthographic projection of the first stress adjustment layer 310 on the surface of the bottom wafer 110 coincides with the orthographic projection of the conductive material layer 200 on the surface of the bottom wafer 110, i.e., the first stress adjustment layer 310 covers the surface of the conductive material layer 200. Forming the first stress adjustment layer 310 on the conductive material layer 200 can effectively improve the warpage of the wafer stack 100, particularly the phenomenon of increased warpage of the wafer stack 100 due to coverage by the conductive material layer 200, thereby improving the flatness of the wafer stack 100.
[0068] In some specific embodiments, Figure 3 As shown, since the warping degree of the edge area of the wafer stack 100 is often greater than that of the central area, in order to effectively improve the warping phenomenon of the edge area of the wafer stack 100, the thickness of the central area of the first stress adjustment layer 310 can be less than the thickness of the edge area. When improving the warping problem of the wafer stack 100, the adverse effects of the thickness of the device caused by the first stress adjustment layer 310 can also be improved.
[0069] Furthermore, when the center thickness of the first stress adjustment layer 310 is less than the edge thickness, the thickness of the first stress adjustment layer 310 can be gradually thickened from the center to the edge of the first stress adjustment layer 310 to facilitate process manufacturing while ensuring the uniformity of the first stress adjustment layer 310 and avoiding the appearance of a stepped structure on the surface of the first stress adjustment layer 310, which would result in uneven stress provided by the first stress adjustment layer 310 to the conductive material layer 200 and the wafer stack 100.
[0070] It should be noted that when the conductive material layer 200 is subsequently etched, the first stress adjustment layer 310 can serve as a hard mask; after the conductive material layer 200 is etched, the remaining first stress adjustment layer 310 can serve as a dielectric layer to provide isolation and insulation for the device.
[0071] It should be noted that in this disclosure, Figure 4 As shown, taking the first stress adjustment layer 310 as an example, the first stress adjustment layer 310 includes a central region a and an edge region b, wherein the edge region b is disposed around the central region a and is adjacent to the central region a. The edge of the central region a is concentric with the edge of the first stress adjustment layer 310, and the diameter of the orthographic projection of the central region a on the surface of the underlying wafer 110 is at least 80% of the diameter of the orthographic projection of the first stress adjustment layer 310 on the surface of the underlying wafer 110. Furthermore, the divisions of the edge and central regions of the conductive material layer 200, the edge and central regions of the wafer stack 100, and the edge and central regions of the second stress adjustment layer 320 are the same or substantially the same as those of the first stress adjustment layer 310 and are not listed here one by one.
[0072] In some embodiments, as Figure 5As shown, the orthographic projection of the first stress adjustment layer 310 on the conductive material layer 200 exposes the central area of the conductive material layer 200, and the orthographic projection of the first stress adjustment layer 310 on the surface of the conductive material layer 200 coincides with the edge of the surface of the conductive material layer 200. Since the warping degree of the edge area of the wafer stack 100 is greater than the warping degree of the central area, by setting the first stress adjustment layer 310 at least in the edge area of the conductive material layer 200, the warping degree of the edge area of the wafer stack 100 can be effectively improved to improve the flatness of the wafer stack 100. In addition, since the first stress adjustment layer 310 exposes the central area of the conductive material layer 200, that is, the first stress adjustment layer 310 is only located in the edge area of the conductive material layer 200, when etching the structure, the conductive material layer 200 can be directly etched, which can simplify the formation process of the solder pad.
[0073] In some specific embodiments, Figure 5 As shown, the positive projection of the first stress adjustment layer 310 on the conductive material layer 200 can be in the shape of a ring or a quasi-ring, and the edge of the first stress adjustment layer 310 is flush with the edge of the conductive material layer 200. By covering the edge position of the conductive material layer 200 with the first stress adjustment layer 310, the first stress adjustment layer 310 applies stress opposite to the warping direction to the edge area of the wafer stack 100, which can effectively improve the warping degree at the edge position of the wafer stack 100.
[0074] Among them, when the first stress adjustment layer 310 has a ring structure, the area of the orthographic projection of the first stress adjustment layer 310 on the surface of the conductive material layer 200 can be 30% to 80% of the surface area of the conductive material layer 200, for example, it can be 30%, 40%, 50%, 60%, 70% or 80%.
[0075] In some embodiments, as Figure 6 As shown, the first stress adjustment layer 310 includes multiple first sub-stress layers 311. The first sub-stress layers 311 are arranged in an array on the side of the conductive material layer 200 away from the bottom wafer 110, and at least a portion of the first sub-stress layers 311 are distributed on the edge of the conductive material layer 200. By distributing multiple first sub-stress layers 311 at intervals on the conductive material layer 200, the multiple first sub-stress layers 311 can collaboratively adjust the warpage of the wafer stack 100. At the same time, when the warpage of the wafer stack 100 is uneven, the thickness and area of the first sub-stress layers 311 can be adjusted to ensure consistent improvement in the warpage of the wafer stack 100, thereby improving the uniformity and flatness of the wafer stack 100. It should be noted that the area of the first sub-stress layer 311 refers to the contact area between the first sub-stress layer 311 and the conductive material layer 200.
[0076] In some specific embodiments, a plurality of first sub-stressor layers 311 may be arranged at the edge region of the conductive material layer 200, and a distance may exist between two adjacent first sub-stressor layers 311. Figure 6 As shown, to improve the uniformity of the stress provided by the first stress adjustment layer 310 to the conductive material layer 200, the spacing between the multiple first sub-stress layers 311 is equal. For example, the first sub-stress layers 311 can be arc-shaped, with each first sub-stress layer 311 having the same arc and length, and the multiple first sub-stress layers 311 are distributed in a mirror-image manner at the edge region of the conductive material layer 200. Of course, the structure and arrangement of the multiple first sub-stress layers 311 in the above embodiment are merely exemplary, and the structure and arrangement of the multiple first sub-stress layers 311 can be adaptively adjusted according to the specific requirements of stress adjustment.
[0077] In the embodiments provided in the present disclosure, Figure 7 As shown, the structure further includes a second stress adjustment layer 320, which is located on the side of the bottom wafer 110 away from the conductive material layer 200. In the first direction X, the second stress adjustment layer 320 and the first stress adjustment layer 310 exert stress on the wafer stack 100 in the same direction. By jointly applying stress in the same direction to the wafer stack 100 by the first stress adjustment layer 310 and the second stress adjustment layer 320, the warpage of the wafer stack 100 can be further reduced, and the flatness of the wafer stack 100 can be further improved.
[0078] Among them, since the first stress adjustment layer 310 and the second stress adjustment layer 320 are distributed on both sides of the wafer stack 100, for the warping of the wafer stack 100, if the first stress adjustment layer 310 applies compressive stress to the wafer stack 100, the second stress adjustment layer 320 applies tensile stress to the wafer stack 100; if the first stress adjustment layer 310 applies tensile stress to the wafer stack 100, the second stress adjustment layer 320 applies compressive stress to the wafer stack 100.
[0079] The second stress adjustment layer 320 can be made of materials such as silicon nitride (Si3N4) or metal, and can be formed on the underlying wafer 110 using one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation (Thermal Oxidation), and sol-gel (Sol-Gel). The formation process of the second stress adjustment layer 320 can be determined according to the selection of its specific material, and this disclosure does not make any specific limitations.
[0080] In some embodiments, in order to prevent the wafer stack 100 from warping or bending in the opposite direction, the thickness of the second stress adjustment layer 320 can be less than the thickness of the first stress adjustment layer 310. On the one hand, the second stress adjustment layer 320 can provide support for the wafer stack 100. On the other hand, the second stress adjustment layer 320 can also assist the first stress adjustment layer 310 in improving the warping of the wafer stack 100.
[0081] In some specific embodiments, Figure 7 As shown, when the second stress adjustment layer 320 is made of silicon nitride (Si3N4), the orthographic projection of the second stress adjustment layer 320 on the surface of the underlying wafer 110 coincides with the orthographic projection of the first stress adjustment layer 310 on the surface of the underlying wafer 110. The second stress adjustment layer 320 is arranged on the side of the underlying wafer 110 away from the conductive material layer 200. It can provide tensile stress for the wafer stack 100, thereby cooperating with the first stress adjustment layer 310 to further improve the warping of the wafer stack 100, and achieve the purpose of balance and uniformity of stress adjustment of the wafer stack 100 by the first stress adjustment layer 310 and the second stress adjustment layer 320, which can effectively improve the warping of the wafer stack 100 and prevent reverse warping.
[0082] In some specific embodiments, Figure 8 As shown, when the second stress adjustment layer 320 is made of a metal material (such as aluminum or copper), the edge of the orthographic projection of the second stress adjustment layer 320 on the surface of the bottom wafer 110 is located within the edge of the orthographic projection of the first stress adjustment layer 310 on the surface of the bottom wafer 110, that is, the surface area of the second stress adjustment layer 320 is smaller than the surface area of the first stress adjustment layer 310. The second stress adjustment layer 320 can be used to offset the uneven metal volume caused by the conductive material layer 200 covering the wafer stack 100, thereby improving the phenomenon of increased warping of the wafer stack 100. In addition, after the conductive material layer 200 is subsequently etched, since the surface area of the second stress adjustment layer 320 is smaller than the surface area of the first stress adjustment layer 310, the reverse warping phenomenon caused by the second stress adjustment layer 320 on the wafer stack 100 is avoided. It should be noted that the surface area of the first stress adjustment layer 310 refers to the contact area between the first stress adjustment layer 310 and the conductive material layer 200. The surface area of the second stress adjustment layer 320 is the contact area between the second stress adjustment layer 320 and the underlying wafer 110 .
[0083] In some embodiments, since the degree of warping in the edge area of the wafer stack 100 is often greater than that in the central area, in order to effectively improve the warping phenomenon in the edge area of the wafer stack 100, the thickness of the central area of the second stress adjustment layer 320 can be less than the thickness of the edge area, and the cross-sectional shape of the second stress adjustment layer 320 can be the same as or similar to the cross-sectional shape of the first stress adjustment layer 310. When improving the warping problem of the wafer stack 100, the adverse effect of the thickness of the device caused by the second stress adjustment layer 320 can also be improved.
[0084] Furthermore, when the center thickness of the second stress adjustment layer 320 is less than the edge thickness, the thickness of the second stress adjustment layer 320 can be gradually thickened from the center to the edge of the second stress adjustment layer 320 to facilitate process manufacturing while ensuring the uniformity of the second stress adjustment layer 320 and avoiding the appearance of a stepped structure on the surface of the second stress adjustment layer 320, which would result in uneven stress provided by the second stress adjustment layer 320 to the wafer stack 100.
[0085] In the embodiments provided in the present disclosure, Figure 9 As shown, the structure also includes a third stress adjustment layer 330, which is located between the bottom wafer 110 and the second stress adjustment layer 320. The third stress adjustment layer 330 can be used to offset the stress applied by part of the conductive material layer 200 to the wafer stack 100, thereby improving the phenomenon that the warping degree of the wafer stack 100 is aggravated due to the coverage of the conductive material layer 200.
[0086] The third stress adjustment layer 330 includes a metal material, and the third stress adjustment layer 330 can be made of the same metal material as the second stress adjustment layer 320. For example, the third stress adjustment layer 330 can include one or more materials such as aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), and molybdenum (Mo). The third stress material layer is made of a metal material that has thermal conductivity. Because the third stress adjustment layer 330 is disposed on the side of the bottom wafer 110 facing away from the conductive material layer 200, the third stress adjustment layer 330 can also perform thermal management for the wafer stack 100 and dissipate heat from the wafer stack 100.
[0087] In some specific embodiments, to enhance the effect of the third stress-regulating layer 330 on improving the warpage of the wafer stack 100, and in particular to enhance the effect of the third stress-regulating layer 330 on offsetting the stress applied by the third stress-regulating layer 330 to the conductive material layer 200, the material of the third stress-regulating layer 330 may be the same as that of the conductive material layer 200. For example, when the conductive material layer 200 is aluminum (Al), the third stress-regulating layer 330 may also be aluminum (Al). In some specific embodiments, the material of the third stress-regulating layer 330 may be different from that of the conductive material layer 200. For example, when the conductive material layer 200 is aluminum (Al), the third stress-regulating layer 330 may be copper (Cu), to further enhance the thermal management performance of the third stress-regulating layer 330 on the wafer stack 100.
[0088] In some embodiments, the thickness of the third stress adjustment layer 330 is less than the thickness of the conductive material layer 200. The smaller thickness of the third stress adjustment layer 330 can increase the metal amount of the wafer stack 100 and match the metal amount of the conductive material layer 200, thereby improving the phenomenon of aggravated wafer warping caused by the uneven metal volume generated after the conductive material layer 200 covers the wafer stack 100. In addition, since the third stress adjustment layer 330 and the second stress adjustment layer 320 improve the wafer warping at the same time, the thickness of the third stress adjustment layer 330 is smaller, which can avoid reverse warping of the wafer stack 100.
[0089] In some embodiments, to provide protection and insulation for the third stress adjustment layer 330, the second stress adjustment layer 320 may cover the bottom and side surfaces of the third stress adjustment layer 330, with the top surface of the third stress adjustment layer 330 being aligned with the surface of the bottom wafer 110. The bottom surface of the third stress adjustment layer 330 refers to the side of the third stress adjustment layer 330 that is away from the bottom wafer 110. By simultaneously providing the second stress adjustment layer 320 and the third stress adjustment layer 330 on the bottom wafer 110, the warpage of the wafer stack 100 can be simultaneously improved by the second stress adjustment layer 320 and the third stress adjustment layer 330. Furthermore, the second stress adjustment layer 320 can provide protection and insulation for the third stress adjustment layer 330, thereby ensuring the integrity of the third stress adjustment layer 330 and facilitating effective thermal management of the wafer stack 100 by the third stress adjustment layer 330.
[0090] In some embodiments, the thickness of the third stress adjustment layer 330 is greater than the thickness of the second stress adjustment layer 320, and the thickness of the second stress adjustment layer 320 is less than the thickness of the first stress adjustment layer 310. Through the synergistic effect of the first stress adjustment layer 310, the second stress adjustment layer 320 and the third stress adjustment layer 330, the warping of the wafer stack 100 itself and the phenomenon of aggravated warping of the wafer stack 100 after being covered by the conductive material layer 200 can be effectively improved, so as to further improve the flatness of the wafer stack 100 and the conductive material layer 200, improve the subsequent processing accuracy of the structure, and thereby improve the performance of the structure.
[0091] In the present disclosure, in the subsequent process, the conductive material layer 200 is etched into a metal pad, thereby reducing the amount of metal above the wafer stack 100. To prevent reverse warping, the contact area between the third stress adjustment layer 330 and the underlying wafer 110 can be made smaller than the contact area between the conductive material layer 200 and the wafer 120, ensuring that the wafer stack 100 after etching still has a good degree of warping.
[0092] In the present disclosure, a first stress adjustment layer 310 is provided on the conductive material layer 200. At least one of the second stress adjustment layer 320 and the third stress adjustment layer 330 acts in conjunction with the first stress adjustment layer 310 on the wafer stack 100. For example, the structure may include the first stress adjustment layer 310 alone; or the structure may include both the first stress adjustment layer 310 and the second stress adjustment layer 320; or the structure may include both the first stress adjustment layer 310 and the third stress adjustment layer 330; or the structure may include both the first stress adjustment layer 310, the second stress adjustment layer 320, and the third stress adjustment layer 330. The above embodiments can be adaptively selected and implemented according to the specific structure of the wafer stack 100, and parameters such as the materials and thicknesses of the first stress adjustment layer 310, the second stress adjustment layer 320, and the third stress adjustment layer 330 can be adaptively adjusted according to the actual design requirements of the semiconductor structure and the layout of the three layers.
[0093] The present disclosure provides a method for forming a semiconductor structure, which is used to form the semiconductor structure provided by any of the above embodiments, such as Figure 10 As shown, the forming method includes: steps S10 to S30.
[0094] Wherein, step S10: providing a wafer stack, the wafer stack including a bottom wafer and at least one wafer sequentially stacked on the bottom wafer along a first direction, each wafer including a bonding pad, two adjacent wafers being bonded to each other via the bonding pads, and the first direction being a direction perpendicular to a surface of the bottom wafer;
[0095] Step S20: forming a conductive material layer on the surface of the wafer stack;
[0096] Step S30: depositing a first stress adjustment layer on a side of the conductive material layer away from the bottom wafer, wherein the first stress adjustment layer at least covers an edge of the conductive material layer.
[0097] The present disclosure provides a method for forming a semiconductor structure. This method can improve the warping degree of the wafer stack and improve the flatness of the wafer stack by depositing a first stress adjustment layer on the side of the conductive material layer away from the underlying wafer, thereby providing a better structural foundation for subsequent wafer stacking process processing.
[0098] The following is a detailed description of the various steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:
[0099] The specific structure of the wafer stack and the conductive material layer can refer to the embodiment of the semiconductor structure described above. In step S10, Figure 11 As shown, a wafer stack 100 is provided; in step S20, as shown Figure 12 As shown, a conductive material layer 200 is formed on the surface of the wafer stack 100; in step S30, as shown in FIG. Figure 2 As shown, a first stress adjustment layer 310 is deposited on a side of the conductive material layer 200 away from the bottom wafer 110 , and the first stress adjustment layer 310 at least covers the edge of the conductive material layer 200 .
[0100] In the embodiment provided by the present disclosure, after step S30, as Figure 7 As shown, the method also includes: forming a second stress adjustment layer 320 on the side of the bottom wafer 110 facing away from the conductive material layer 200, and the edge of the orthographic projection of the second stress adjustment layer 320 on the surface of the bottom wafer 110 is located within the edge of the orthographic projection of the first stress adjustment layer 310 on the surface of the bottom wafer 110.
[0101] The method forms a first stress adjustment layer 310 and a second stress adjustment layer 320 in the structure at the same time. The second stress adjustment layer 320 and the first stress adjustment layer 310 apply stress in the same direction to the wafer stack 100 structure. The second stress adjustment layer 320 cooperates with the first stress adjustment layer 310 to further improve the warping degree of the wafer stack 100 and further improve the flatness of the wafer stack 100.
[0102] In the embodiment provided by the present disclosure, after step S30, as Figure 9 As shown, the method may further include: forming a third stress adjustment layer 330 on a side of the bottom wafer 110 facing away from the conductive material layer 200, the third stress adjustment layer 330 including a metal material; forming a second stress adjustment layer 320 on a side of the third stress adjustment layer 330 facing away from the bottom wafer 110, the second stress adjustment layer 320 covering both side surfaces of the third stress adjustment layer 330.
[0103] This method forms a first stress adjustment layer 310, a second stress adjustment layer 320 and a third stress adjustment layer 330 in the structure at the same time. Through the synergistic effect of the three, the warping degree of the wafer stack 100 is improved, the flatness of the wafer stack 100 is improved, and a better structural foundation is provided for subsequent processes. In addition, the formed third stress adjustment layer 330 can also provide heat dissipation for the wafer stack 100, thereby improving the structural performance.
[0104] In the embodiment provided by the present disclosure, after step S30, the method may further include: Figure 13 As shown, a patterned photoresist layer 400 is formed on the first stress adjustment layer 310; Figure 14 As shown, the conductive material layer 200 is patterned using the patterned photoresist layer 400 to form a pad 500, wherein the orthographic projection of the etched first stress adjustment layer 310 on the surface of the bottom wafer 110 coincides with the orthographic projection of the pad 500 on the surface of the bottom wafer 110; Figure 15 As shown, a dielectric material layer is formed on the etched first stress adjustment layer 310. The etched first stress adjustment layer 310 and the dielectric material layer together constitute a dielectric layer 600. The dielectric material layer is made of the same material as the first stress adjustment layer 310. The dielectric layer 600 is etched to form a solder bump receiving hole corresponding to the solder pad 500. The solder bump receiving hole is filled to form a solder bump connected to the solder pad 500.
[0105] After forming solder bumps connected to the pads 500 , the wafer stack 100 can be connected to other device structures through the solder bumps. For example, the wafer stack 100 can be connected to a substrate through the solder bumps to form a semiconductor device.
[0106] This method utilizes the first stress-regulating layer 310 as a hard mask during etching of the conductive material layer 200. In subsequent processes, the first stress-regulating layer 310 can serve as part of the dielectric layer 600, providing insulation for the semiconductor structure. This eliminates the need for additional process steps to remove the first stress-regulating layer 310, reducing process complexity. After forming the first stress-regulating layer 310, the warpage of the wafer stack 100 can be reduced from 500 μm to below 350 μm, enabling smooth entry into the exposure / etching machine.
[0107] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.
[0108] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.
Claims
1. A semiconductor structure, characterized in that include: A wafer stack, the wafer stack comprising a bottom wafer and at least one wafer sequentially stacked on the bottom wafer along a first direction, each wafer comprising a bonding pad, two adjacent wafers being bonded to each other via the bonding pads, the first direction being a direction perpendicular to a surface of the bottom wafer; a conductive material layer covering a side of the wafer stack away from the bottom wafer; A first stress adjustment layer is located on a side of the conductive material layer away from the wafer stack, and the first stress adjustment layer at least covers an edge of the conductive material layer.
2. The semiconductor structure according to claim 1, wherein: The orthographic projection of the first stress adjustment layer on the surface of the bottom wafer coincides with the orthographic projection of the conductive material layer on the surface of the bottom wafer, and the thickness of the central region of the first stress adjustment layer is smaller than the thickness of the edge region.
3. The semiconductor structure according to claim 1, wherein: The orthographic projection of the first stress adjustment layer on the conductive material layer exposes the central area of the conductive material layer, and the orthographic projection of the first stress adjustment layer on the surface of the conductive material layer coincides with an edge of the surface of the conductive material layer.
4. The semiconductor structure according to claim 1, wherein: The first stress adjustment layer includes a plurality of first sub-stress layers, which are arrayed on a surface of the conductive material layer away from the bottom wafer, and at least part of the first sub-stress layers are distributed on the edge of the conductive material layer.
5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The structure also includes a second stress adjustment layer, which is located on a side of the bottom wafer away from the conductive material layer. In the first direction, the second stress adjustment layer and the first stress adjustment layer exert stress on the wafer stack in the same direction.
6. The semiconductor structure according to claim 5, wherein: The thickness of the second stress adjustment layer is less than that of the first stress adjustment layer; the edge of the orthographic projection of the second stress adjustment layer on the surface of the underlying wafer is located within the edge of the orthographic projection of the first stress adjustment layer on the surface of the underlying wafer.
7. The semiconductor structure according to claim 6, wherein: The thickness of the central region of the second stress adjustment layer is smaller than the thickness of the edge region.
8. The semiconductor structure according to claim 6 or 7, characterized in that: The structure further includes a third stress adjustment layer, the third stress adjustment layer being located between the bottom wafer and the second stress adjustment layer, and the third stress adjustment layer comprising a metal material.
9. The semiconductor structure according to claim 8, wherein: The thickness of the third stress adjustment layer is greater than that of the second stress adjustment layer; and the thickness of the third stress adjustment layer is less than that of the conductive material layer.
10. The semiconductor structure according to claim 8, wherein: The second stress adjustment layer covers a bottom surface and side surfaces of the third stress adjustment layer.
11. A method for forming a semiconductor structure, characterized in that: include: Providing a wafer stack, the wafer stack comprising a bottom wafer and at least one wafer sequentially stacked on the bottom wafer along a first direction, each wafer comprising a bonding pad, two adjacent wafers being bonded to each other via the bonding pads, wherein the first direction is a direction perpendicular to a surface of the bottom wafer; forming a conductive material layer on a surface of the wafer stack; A first stress adjustment layer is deposited on a side of the conductive material layer away from the bottom wafer, wherein the first stress adjustment layer at least covers an edge of the conductive material layer.
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CN121204645A