Full-temperature-zone polynomial digital temperature compensation method and system based on SOI chip

Abstract

The invention relates to the technical field of semiconductors, and discloses a full-temperature-zone polynomial digital temperature compensation method and system based on an SOI chip, and the method comprises the steps: obtaining the temperature frequency data of a preset temperature zone of a target SOI chip, fitting a full-temperature-zone curve, extracting a critical point of the temperature zone, dividing a segmented compensation interval according to the critical point, and obtaining the temperature frequency data of the preset temperature zone of the target SOI chip; the method comprises the following steps: calculating frequency drift amounts under different voltages to construct a full-automatic test framework, acquiring an environment temperature parameter and an instantaneous temperature value by using the framework, analyzing a temperature compensation vector of a segmented compensation interval, further monitoring a signal frequency interval output by a chip, extracting a phase noise parameter, calculating a frequency offset error amount with a preset value, and calculating the frequency offset error amount. And analyzing an error source, optimizing a polynomial compensation order, and collecting temperature drift suppression data to generate a full temperature region compensation report. According to the invention, the performance stability of the chip in a complex environment can be improved.

Description

Technical Field

[0001] The present invention relates to a full-temperature-range polynomial digital temperature compensation method and system based on an SOI chip, belonging to the technical field of semiconductors. Background Art

[0002] SOI chips are semiconductor devices made by growing a single-crystal silicon thin film on an insulating layer. They offer advantages such as low power consumption, high radiation resistance, and high-temperature resistance, making them widely used in aerospace, automotive electronics, and other fields. However, the temperature characteristics of SOI chips are affected by nonlinearities across the entire temperature range (e.g., -55°C to 125°C). The output parameters of modules such as their internal oscillators and ADCs drift with temperature, resulting in reduced accuracy.

[0003] Currently, temperature compensation often uses piecewise linear fitting or table lookup methods, correcting chip outputs using calibration data from fixed temperature points. However, these methods struggle to cover nonlinear variations across the entire temperature range and rely on large amounts of calibration data. This leads to issues such as insufficient compensation accuracy, high storage resource usage, and poor real-time performance. Compensation failure is particularly common at extreme temperatures, impacting system reliability. Therefore, a full-temperature range polynomial digital temperature compensation method based on SOI chips is needed. By dynamically fitting the temperature-parameter curve, high-precision adaptive compensation is achieved to improve chip performance and stability in complex environments. Summary of the Invention

[0004] The present invention provides a full-temperature-range polynomial digital temperature compensation method and system based on an SOI chip, the main purpose of which is to improve the performance stability of the chip in complex environments.

[0005] To achieve the above objectives, the present invention provides a full-temperature range polynomial digital temperature compensation method based on an SOI chip, comprising: Acquire temperature-frequency data of a target SOI chip within a preset temperature range, fit a full-temperature-range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract temperature-range critical points in the full-temperature-range curve; Based on the temperature zone critical points, the full temperature zone curve is divided into segmented compensation intervals, the frequency drift of the segmented compensation intervals under different operating voltages is calculated, and based on the frequency drift, a fully automatic test architecture corresponding to the target SOI chip is constructed; Based on the fully automatic test architecture, collecting the ambient temperature parameters corresponding to the target SOI chip, collecting the instantaneous temperature values ​​in the ambient temperature parameters, and analyzing the temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values; Based on the temperature compensation amount, monitoring the signal frequency interval output by the target SOI chip, extracting the phase noise parameter in the signal frequency interval, and calculating the frequency offset error between the phase noise parameter and a preset design value; Analyze the error source corresponding to the frequency offset error, optimize the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain the optimized compensation order, collect temperature drift suppression data of the optimized compensation order during execution, and generate a full-temperature zone compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

[0006] Optionally, fitting a full-temperature range curve corresponding to the target SOI chip based on the temperature-frequency data includes: Identifying a set of temperature points in the temperature-frequency data; Querying the temperature characteristic index corresponding to the temperature point set; extracting frequency response parameters corresponding to the target SOI chip based on the temperature characteristic index; Performing curve simulation on the frequency response parameters to obtain an initial temperature curve; Performing full-range temperature calibration on the initial temperature curve to generate a full-temperature range curve.

[0007] Optionally, the calculating the frequency drift of the segmented compensation interval under different operating voltages includes: The frequency drift of the segmented compensation interval under different operating voltages is calculated using the following formula: ; in, Indicates the frequency drift of the segmented compensation interval under different operating voltages, Indicates the sequence number of the segmented compensation interval, Indicates the serial number of the operating voltage, represents the total number of temperature sampling points within the segmented compensation interval, Indicates the number index of temperature sampling points, Indicates the Temperature sampling points The corresponding actual measurement frequency, It represents the frequency average of all temperature sampling points in the i-th segment compensation interval, and Respectively represent the lowest temperature value and the highest temperature value of the i-th segment compensation interval, Indicates the total number of voltage sampling points corresponding to the working voltage, Indicates the number index of voltage sampling points, represents the jth operating voltage, Indicates the average voltage of all operating voltages.

[0008] Optionally, constructing a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift includes: Analyzing the drift spectrum characteristics corresponding to the frequency drift amount; Analyzing the key test frequency band corresponding to the drift spectrum characteristics; Configuring a programming stimulus source corresponding to the key test frequency band; generating a test signal sequence driven by the programming stimulus source; According to the test signal sequence, a fully automatic test architecture corresponding to the target SOI chip is constructed.

[0009] Optionally, collecting the ambient temperature parameters corresponding to the target SOI chip based on the fully automatic test architecture includes: Obtaining the real-time running status of the fully automatic test architecture when it is running; Analyzing the temperature distribution gradient corresponding to the real-time operating state; Determining a heat-sensitive area corresponding to the target SOI chip based on the temperature distribution gradient; Setting the temperature point sampling frequency corresponding to the heat-sensitive area; Based on the temperature point sampling frequency, the ambient temperature parameters corresponding to the target SOI chip are collected

[0010] Optionally, analyzing the temperature compensation vector corresponding to the segmented compensation interval based on the instantaneous temperature value includes: Mapping the instantaneous temperature values ​​along the time axis and the interval axis to generate a temperature distribution matrix; Analyzing the slope variation interval corresponding to the temperature distribution matrix; Based on the slope change interval, marking the compensation feature nodes in the temperature distribution matrix; Querying the node compensation sequence corresponding to the compensation feature node; Based on the node compensation sequence, the temperature compensation vector corresponding to the segmented compensation interval is analyzed.

[0011] Optionally, monitoring a frequency interval of a signal output by the target SOI chip based on the temperature compensation amount includes: adjusting a bias voltage parameter corresponding to the target SOI chip according to the temperature compensation amount; Based on the bias voltage parameter, collecting the real-time signal frequency output by the target SOI chip; Analyzing the fluctuation range corresponding to the real-time signal frequency; According to the fluctuation range, a dynamic threshold corresponding to the target SOI chip is set; Based on the dynamic threshold, a frequency interval of a signal output by the target SOI chip is monitored.

[0012] Optionally, calculating a frequency offset error between the phase noise parameter and a preset design value includes: The frequency deviation error between the phase noise parameter and the preset design value is calculated using the following formula: ; in, Indicates the frequency deviation error between the phase noise parameter and the preset design value, Indicates the total number of frequency offset points in phase noise analysis, Indicates the number index corresponding to the frequency offset point, Indicates the The phase noise parameters of the target SOI chip output signal actually collected at the frequency offset point are: Indicates the At each frequency offset point, the design target value of the phase noise is preset.

[0013] Optionally, optimizing the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain the optimized compensation order includes: Analyze the order distribution profile corresponding to the error source; querying the dominant order component in the order distribution profile; generating an order optimization weight corresponding to the dominant order component; determining an order increment corresponding to the dominant error component based on the order optimization weight; Based on the order increment, the polynomial compensation order corresponding to the target SOI chip is optimized to obtain an optimized compensation order.

[0014] In order to solve the above problems, the present invention also provides a full-temperature range polynomial digital temperature compensation system based on an SOI chip, the system comprising: A critical point extraction module is used to obtain temperature-frequency data of a target SOI chip within a preset temperature range, fit a full temperature range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract the temperature range critical points in the full temperature range curve; An architecture construction module is used to divide the full temperature range curve into segmented compensation intervals based on the temperature zone critical points, calculate the frequency drift of the segmented compensation intervals under different operating voltages, and build a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift; a vector parsing module, configured to collect, based on the fully automatic test architecture, ambient temperature parameters corresponding to the target SOI chip, collect instantaneous temperature values ​​from the ambient temperature parameters, and parse temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values; an error calculation module, configured to monitor the signal frequency interval output by the target SOI chip based on the temperature compensation amount, extract a phase noise parameter in the signal frequency interval, and calculate a frequency offset error between the phase noise parameter and a preset design value; A report generation module is used to analyze the error source corresponding to the frequency offset error, optimize the polynomial compensation order corresponding to the target SOI chip based on the error source, obtain the optimized compensation order, collect temperature drift suppression data of the optimized compensation order during execution, and generate a full-temperature zone compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

[0015] Compared with the problems described in the background technology, the present invention can accurately capture the nonlinear change characteristics of chip temperature-frequency by acquiring the temperature-frequency data of the target SOI chip within the preset temperature range, provide data support for the polynomial curve fitting of the full temperature range, and then realize the scientific definition of the segmented compensation interval by dividing the temperature zone critical point, effectively improving the accuracy and adaptability of temperature compensation. The present invention divides the segmented compensation interval in the full temperature range curve based on the temperature zone critical point, and can decompose the nonlinear temperature characteristics into multiple approximate linear or low-order nonlinear sub-intervals, so that the temperature-frequency relationship in each interval is easier to model and compensate, effectively reducing the complexity and calculation amount of polynomial fitting, and providing a structured framework for realizing high-precision full temperature range dynamic compensation. Furthermore, the present invention collects the ambient temperature parameters corresponding to the target SOI chip based on the fully automatic test architecture, and can use the automation and precision of the architecture to achieve high-precision full temperature range dynamic compensation. Accuracy, real-time and continuous acquisition of temperature data of each segment in the full temperature zone test, providing an accurate temperature benchmark for frequency drift analysis, helping to explore the chip temperature-performance correlation law, and improving the adaptability and reliability of the full temperature zone compensation strategy. Furthermore, the present invention monitors the signal frequency range output by the target SOI chip based on the temperature compensation amount, and can verify the correction effect of the compensation algorithm on the frequency drift in real time, accurately locate the frequency deviation error that still exists after compensation, and provide data support for the dynamic optimization of compensation parameters, and ultimately improve the frequency output stability of the chip in a complex temperature environment. Finally, by analyzing the error source corresponding to the frequency deviation error, the present invention can accurately locate the problems in the chip design, manufacturing or testing links, and clarify whether the error is caused by insufficient temperature compensation strategy, hardware circuit noise or process deviation, thereby improving the chip signal quality and frequency stability and ensuring system-level application performance. Therefore, a full-temperature zone polynomial digital temperature compensation method and system based on SOI chip provided in an embodiment of the present invention can improve the performance stability of the chip in a complex environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic flow chart of a full-temperature-range polynomial digital temperature compensation method based on an SOI chip provided in one embodiment of the present invention; Figure 2 A schematic diagram of a fully automatic test architecture for a full-temperature-range polynomial digital temperature compensation method based on an SOI chip provided by one embodiment of the present invention; Figure 3 A schematic diagram of a module for implementing a full-temperature-range polynomial digital temperature compensation system based on an SOI chip provided in one embodiment of the present invention.

[0017] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0018] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] The embodiment of the present application provides a full-temperature-range polynomial digital temperature compensation method based on an SOI chip. The execution subject of the full-temperature-range polynomial digital temperature compensation method based on an SOI chip includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided in the embodiment of the present application. In other words, the full-temperature-range polynomial digital temperature compensation method based on an SOI chip can be executed by software or hardware installed on a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0020] Example 1: Reference Figure 1 FIG. 1 is a flow chart of a full-temperature-range polynomial digital temperature compensation method based on an SOI chip according to an embodiment of the present invention. In this embodiment, the full-temperature-range polynomial digital temperature compensation method based on an SOI chip includes: S1. Obtain temperature-frequency data of a target SOI chip within a preset temperature range, fit a full-temperature-range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract temperature-range critical points in the full-temperature-range curve.

[0021] By acquiring the temperature-frequency data of the target SOI chip within a preset temperature range, the present invention can accurately capture the nonlinear change characteristics of the chip temperature-frequency, provide data support for polynomial curve fitting in the entire temperature range, and then realize the scientific definition of the segmented compensation interval by dividing the temperature zone critical points, thereby effectively improving the accuracy and adaptability of temperature compensation.

[0022] Among them, the target SOI chip refers to a specific SOI chip selected as the compensation object during the temperature compensation process. Different SOI chips have different temperature characteristics due to differences in manufacturing processes, internal structures, etc. For example, in a certain aerospace project, a specific model of SOI chip is selected to meet harsh environmental requirements. It will be the core object of temperature compensation work. Temperature compensation can ensure that the chip operates stably in the project equipment; the preset temperature range refers to a pre-set temperature range that covers the possible working environment of the target SOI chip. The setting of this range requires comprehensive consideration of the chip's actual application scenarios. For example, for SOI chips in automotive engine control systems, the engine compartment operating temperature may fluctuate between -40°C and 150°C. Therefore, the preset temperature range can be set to -40°C to 150°C to ensure the chip's performance under all temperature conditions. The temperature-frequency data refers to the frequency data corresponding to the target SOI chip at different temperatures. The output frequency of modules such as the chip's internal oscillator will vary with temperature. For example, an SOI chip used in industrial automation equipment may have an oscillator output frequency of 10MHz at 25°C. When the temperature rises to 80°C, the frequency may drift to 10.05MHz. Collecting this frequency data at different temperature nodes can provide a key basis for subsequent temperature compensation. Optionally, obtaining the temperature-frequency data of the target SOI chip within the preset temperature range can be achieved using infrared thermal imaging methods, such as using a FLIRA655sc infrared thermal imager to simultaneously capture the chip surface temperature distribution and operating frequency signal, and then obtain the temperature-frequency data through time series correlation analysis.

[0023] Furthermore, the present invention fits the full-temperature zone curve corresponding to the target SOI chip based on the temperature-frequency data, and can characterize the nonlinear relationship between chip temperature and frequency in the form of a mathematical model, and convert discrete data into a continuous and computable curve model, which facilitates the precise positioning of temperature zone critical points and nonlinear characteristics, and provides a quantitative basis for the subsequent segmented compensation interval division.

[0024] Among them, the full temperature range curve refers to the precise temperature-frequency relationship curve generated after the initial temperature curve is subjected to full-domain temperature calibration. It corrects and optimizes the initial curve by comprehensively considering the characteristics of all temperature points in the full temperature range, calibration errors, and factors affecting the actual working environment of the chip. For example, the error of the correction curve at the temperature boundary is corrected to make the curve more accurately reflect the temperature-frequency change relationship of the chip in the full temperature range of -55°C to 125°C, providing a reliable basis for temperature compensation.

[0025] As an embodiment of the present invention, fitting the full temperature range curve corresponding to the target SOI chip based on the temperature-frequency data includes: identifying a temperature point set in the temperature-frequency data; querying a temperature characteristic index corresponding to the temperature point set; extracting frequency response parameters corresponding to the target SOI chip based on the temperature characteristic index; performing curve simulation on the frequency response parameters to obtain an initial temperature curve; and performing global temperature calibration on the initial temperature curve to generate a full temperature range curve.

[0026] Among them, the temperature point set refers to a series of representative temperature value sets selected from the temperature-frequency data. When obtaining the temperature-frequency data of the target SOI chip, a large amount of discrete temperature data will be obtained, from which key temperature values ​​are screened to form a point set. For example, in the temperature range of -55℃ to 125℃, temperature points such as -55℃, -20℃, 0℃, 25℃, 80℃, and 125℃ are selected. These points can cover the change trend of the entire temperature range and serve as basic data nodes for subsequent analysis; the temperature characteristic index refers to a quantitative indicator that describes the characteristics of the temperature point set, which is used to characterize the degree of influence of different temperature points on chip performance. It comprehensively considers factors such as the temperature change gradient and the sensitivity to the key parameters of the chip. For example, between 25℃ and 80℃, the chip frequency changes significantly for every 1℃ increase in temperature. The temperature characteristic index of this interval may be higher, reflecting that this temperature segment has a significant impact on chip performance; the frequency response parameter refers to the frequency output corresponding to the target SOI chip under a specific temperature characteristic index. Characteristic parameters, these parameters include frequency value, frequency drift, frequency stability and other indicators. For example, when the temperature characteristic index shows that the chip frequency in a certain temperature range is susceptible to interference, the corresponding frequency response parameters will show a larger frequency fluctuation range. These parameters can be used to intuitively understand the frequency output performance of the chip at different temperatures; the initial temperature curve refers to the temperature-frequency relationship curve obtained by preliminary curve simulation based on the frequency response parameters. It uses a mathematical model to preliminarily fit the frequency change trend of the chip at different temperatures. Although it has not been finely calibrated, it can show a general trend. For example, the frequency response parameters are fitted using the least squares method to obtain a curve that can preliminarily reflect the relationship between temperature and frequency.

[0027] Furthermore, the identification of the temperature point set in the temperature-frequency data can be achieved through a peak detection algorithm, such as: using the find_peaks function in Python's SciPy library combined with a sliding window technology to screen key temperature turning points, thereby obtaining a temperature point set; the query of the temperature characteristic index corresponding to the temperature point set can be achieved through a statistical feature analysis method, such as: calculating the mean, variance, skewness and kurtosis of the temperature point set based on the Pandas data framework, constructing a multidimensional feature vector, thereby obtaining a temperature characteristic index; the extraction of the frequency response parameters corresponding to the target SOI chip can be achieved through frequency domain signal processing technology, such as: using MATLAB The tfestimate function of AB performs Fourier transform on the temperature-frequency data, extracts the amplitude-frequency characteristic and the phase-frequency characteristic parameters, and thus obtains the frequency response parameters; the curve simulation of the frequency response parameters can be achieved through a nonlinear regression modeling method, such as: using the Gaussian mixture model of OriginPro software to fit the frequency-temperature scatter data, generating the optimal fit equation, and thus obtaining the initial temperature curve; the global temperature calibration of the initial temperature curve can be achieved through an adaptive optimization algorithm, such as: adjusting the curve parameters based on the genetic algorithm, combining the PID control module of NILabVIEW to iteratively correct the temperature zone boundary error, and thus obtaining the full temperature zone curve.

[0028] By extracting the temperature zone critical points in the full-temperature zone curve, the present invention can accurately locate the nonlinear mutation nodes of the chip temperature characteristics, providing a key basis for the scientific division of the segmented compensation intervals, making the temperature-frequency characteristics in each compensation interval closer to linearity or low-order nonlinearity, and improving the accuracy of full-temperature zone compensation and system reliability.

[0029] Among them, the temperature zone critical point refers to the key node in the full temperature zone curve that characterizes the significant change in the chip temperature characteristics, which is usually the curve slope mutation point, extreme point or nonlinear characteristic inflection point. These points reflect the turning characteristics of the internal physical mechanism of the chip with temperature changes. For example, the full temperature zone curve of a certain SOI chip has a sudden increase in slope at 80°C, indicating that the drift rate of the chip frequency with increasing temperature is significantly accelerated after this temperature point. This 80°C becomes the critical point of the temperature zone segment, which is used to define the application range of different compensation strategies to ensure that the temperature compensation algorithm adapts to the changes in chip characteristics. Optionally, the extraction of the temperature zone critical point in the full temperature zone curve can be achieved by derivative extreme value analysis, such as: using MATLAB's diff and findpeaks functions to calculate the first-order derivative of the curve and locate the extreme point where the derivative is zero, thereby obtaining the temperature zone critical point.

[0030] S2. Based on the temperature zone critical points, divide the full temperature zone curve into segmented compensation intervals, calculate the frequency drift of the segmented compensation intervals under different operating voltages, and build a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift.

[0031] The present invention divides the full temperature range curve into segmented compensation intervals based on the critical points of the temperature zones, and can decompose the nonlinear temperature characteristics into multiple approximately linear or low-order nonlinear sub-intervals, making the temperature-frequency relationship in each interval easier to model and compensate, effectively reducing the complexity and calculation amount of polynomial fitting, and providing a structured framework for achieving high-precision full temperature range dynamic compensation.

[0032] Among them, the segmented compensation interval refers to dividing the full temperature zone curve into several temperature sub-intervals with the critical point of the temperature zone as the boundary. The temperature-frequency characteristics of the chip in each interval are approximately linear or present a low-order nonlinear law. For example, the full temperature zone curve of a certain SOI chip has critical points at -55℃~25℃, 25℃~80℃, and 80℃~125℃, and is divided into three segmented compensation intervals accordingly. Each interval is compensated using polynomials of different orders to ensure that the frequency drift in each temperature zone can be accurately fitted and avoid compensation errors caused by unified modeling of the full temperature zone. Optionally, the segmented compensation intervals in the segmented compensation intervals of the full temperature zone curve can be implemented through a hidden Markov model, such as: using the hmmlearn library to train the state transition probability matrix, and decoding the most likely state transition node through the Viterbi algorithm to obtain the segmented compensation intervals.

[0033] Furthermore, by calculating the frequency drift of the segmented compensation interval under different operating voltages, the present invention can comprehensively analyze the cross-influence of voltage and temperature on the chip frequency, reveal the parameter drift law under the coupling of multiple physical fields, and provide data support for constructing a compensation model that considers the voltage dimension, thereby ensuring the performance stability of the chip within the entire voltage-temperature range.

[0034] Different operating voltages refer to the various supply voltages that a target SOI chip may encounter during actual operation. These voltages vary depending on application scenarios, affecting the chip's temperature characteristics and frequency output. For example, a SOI chip used in automotive electronics may face different operating voltages in the vehicle system, including a 12V battery (normally 13.8V), a voltage drop during startup (e.g., 9V), or power ripple interference (±0.5V fluctuation). Frequency drift must be tested at 9V, 12V, and 14V voltages across the full temperature range of -55°C to 125°C to cover actual operating conditions. Frequency drift refers to the deviation of the chip frequency from the reference state due to different operating voltages within the segmented compensation range. For example, in a segmented compensation range, the frequency is 100MHz at the standard voltage. When the voltage is changed, the frequency changes to 98MHz. The 2MHz difference is the frequency drift, which measures the impact of voltage on frequency.

[0035] As an embodiment of the present invention, the calculating of the frequency drift of the segmented compensation interval under different operating voltages includes: The frequency drift of the segmented compensation interval under different operating voltages is calculated using the following formula: ; in, Indicates the frequency drift of the segmented compensation interval under different operating voltages, Indicates the sequence number of the segmented compensation interval, Indicates the serial number of the operating voltage, represents the total number of temperature sampling points within the segmented compensation interval, Indicates the number index of temperature sampling points, Indicates the Temperature sampling points The corresponding actual measurement frequency, It represents the frequency average of all temperature sampling points in the i-th segment compensation interval, and Respectively represent the lowest temperature value and the highest temperature value of the i-th segment compensation interval, Indicates the total number of voltage sampling points corresponding to the working voltage, Indicates the number index of voltage sampling points, represents the jth operating voltage, Indicates the average voltage of all operating voltages.

[0036] In detail, the temperature sampling point refers to a discrete temperature value selected according to certain rules within the temperature range of the segmented compensation interval. For example, assuming that the temperature of the segmented compensation interval is -20°C to 40°C, a point is selected every 5°C, such as -20°C, -15°C, 0°C, etc. These temperature points selected for testing and data collection are temperature sampling points, which are used to analyze the impact of temperature on frequency; the actual measured frequency refers to the actual output frequency of the chip obtained by actual testing means (such as a frequency meter) at a specific temperature sampling point and a specific operating voltage. For example, when the temperature sampling point is 25°C and the operating voltage is 3.3V, the chip output frequency measured by a frequency meter is 120MHz. , this 120MHz is the actual measured frequency, reflecting the actual working frequency performance of the chip; the frequency average value refers to the value obtained by adding the actual measured frequencies corresponding to all temperature sampling points in the i-th segmented compensation interval and dividing it by the total number of temperature sampling points. For example, a segmented compensation interval has 5 temperature sampling points, and the corresponding frequencies are 110MHz, 112MHz, 108MHz, 115MHz, and 105MHz respectively. The sum of the two points and the division by 5 gives 110MHz, which is the frequency average value of the interval, reflecting the average level of the frequency in the interval; the voltage sampling point refers to the value selected when studying the influence of different working voltages. Several discrete voltage values ​​are taken. For example, to study the impact of voltage on chip frequency, representative voltage values ​​such as 1.8V, 2.5V, 3.3V, and 5V are selected. Each selected voltage is a voltage sampling point, which is used to comprehensively analyze the impact of voltage changes. The voltage average value refers to the mean value obtained by adding the voltage values ​​of all selected working voltage sampling points and dividing it by the total number of voltage sampling points. For example, three voltage sampling points are selected, namely 3V, 3.2V, and 2.8V. The sum (3+3.2+2.8=9) is divided by 3 to obtain 3V. This 3V is the voltage average value, which can be used as a reference for the overall voltage level.

[0037] Based on the frequency drift, the present invention constructs a fully automatic test architecture corresponding to the target SOI chip, which can accurately capture the frequency characteristics of the chip under different voltage and temperature segments, automatically schedule the test process, cover the full working condition compensation range, and dynamically adapt to chip parameter fluctuations through an automated closed loop, thereby improving test efficiency and compensation accuracy.

[0038] Among them, the fully automatic test architecture refers to a system framework that integrates parsing, analysis, configuration, generation and other links to realize automated testing of the target SOI chip. It covers hardware (such as programming stimulus source, signal acquisition equipment, etc.) and software (control logic, data analysis algorithm, etc.), and can automatically execute the test process and collect and process data. For example, the constructed architecture can automatically configure the stimulus source according to the drift spectrum, send the test signal sequence, collect the chip output and analyze it, and complete the full process of automated testing.

[0039] As an embodiment of the present invention, the fully automatic test architecture corresponding to the target SOI chip is constructed based on the frequency drift amount, including: parsing the drift spectrum characteristics corresponding to the frequency drift amount; analyzing the key test frequency band corresponding to the drift spectrum characteristics; configuring a programming excitation source corresponding to the key test frequency band; generating a test signal sequence driven by the programming excitation source; and constructing the fully automatic test architecture corresponding to the target SOI chip according to the test signal sequence.

[0040] Among them, the drift spectrum characteristics refer to the spectrum performance reflecting the frequency drift law and characteristics obtained after the frequency drift amount is spectrally analyzed. It presents the distribution of drift on different frequency components by performing Fourier transform and other processing on the frequency drift data, such as which frequency bands the drift energy is concentrated in, the drift amplitude of each frequency band, etc. For example, when the temperature of the chip changes, the frequency drift spectrum may have a larger amplitude in the low frequency band, showing specific drift spectrum characteristics; the key test frequency band refers to the frequency range that is critical for evaluating chip performance and analyzing the impact of frequency drift based on the drift spectrum characteristics. These frequency bands contain information that can reflect the essential characteristics of chip frequency drift, such as the frequency range with drastic drift changes and plays a key role in the chip function. For example, it is found from the drift spectrum that the drift in the 10MHz-50MHz frequency band has a great impact on the chip communication function, and this frequency band becomes the key test frequency band; The programmable excitation source refers to a device or module that can set output parameters (such as frequency, amplitude, waveform, etc.) through programming to generate specific test signals. It can accurately output excitation signals corresponding to key test frequency bands according to test requirements and provide input for the test chip. For example, to test the key frequency band of 20MHz-30MHz, the programmable excitation source can be set to output sinusoidal wave signals of different frequencies and amplitudes within the frequency band and input them into the chip; the test signal sequence refers to a series of ordered test signal sets generated by the programmable excitation source according to test requirements, which contains signals at different times and with different parameters (frequency, amplitude, etc.) and is used to comprehensively test the response of the chip under various working conditions. For example, a 20MHz, 1V amplitude signal is output first, followed by a 25MHz, 1.2V amplitude signal, and then a 30MHz, 0.8V amplitude signal. These signals arranged in sequence constitute a test signal sequence.

[0041] Furthermore, the analysis of the drift spectrum characteristics corresponding to the frequency drift amount can be achieved through the fast Fourier transform method, such as: using MATLAB's fft function to perform spectrum analysis on the time domain drift signal, extracting the amplitude spectrum and phase spectrum characteristic parameters, thereby obtaining the drift spectrum characteristics; the analysis of the key test frequency band corresponding to the drift spectrum characteristics can be achieved through the energy concentration evaluation method, such as: calculating the power spectrum density based on Python's scipy.signal library, determining the main energy distribution interval by setting the energy ratio threshold, thereby obtaining the key test frequency band; the configuration of the programmed excitation source corresponding to the key test frequency band can be achieved through digital signal synthesis technology, such as: using Keysight The 33600A series waveform generator is configured to set multi-band composite excitation parameters through SCPI commands, thereby obtaining a programmed excitation source. The test signal sequence driven by the programmed excitation source can be generated through a multi-channel time-domain interleaving method, such as using the LabVIEW waveform generation toolkit to create a pseudo-random binary sequence with time stamp information, thereby obtaining a test signal sequence. The construction of a fully automatic test architecture corresponding to the target SOI chip can be achieved through a modular integrated design method, such as integrating a signal generator, an acquisition card, and a switch matrix based on a PXIe platform, and automating the process through TestStand test management software, thereby obtaining a fully automatic test architecture.

[0042] Specifically, to further understand the implementation architecture of the fully automatic test system in this application, please refer to Figure 2 The provided structural block diagram of the fully automatic test architecture presents the various components of the system and their connection relationships. In the present invention, this block diagram is used to demonstrate the hardware construction logic of the fully automatic test system, such as how high-precision pressure controllers, high and low temperature test chambers, sensors and other equipment work together, and how the GPIB bus realizes data transmission and control. Among them, each module (such as the high-precision pressure controller provides a specific pressure environment, and the high and low temperature test chamber simulates temperature conditions) corresponds to a different functional link in the test process, and jointly supports full-condition testing of the target SOI chip, etc. It does not limit the equipment adaptation adjustments that may occur due to scenario differences in actual applications, and is only used to present the basic architecture relationship.

[0043] S3. Based on the fully automatic test architecture, collect the ambient temperature parameters corresponding to the target SOI chip, collect the instantaneous temperature values ​​in the ambient temperature parameters, and analyze the temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values.

[0044] The present invention is based on the fully automatic test architecture to collect the ambient temperature parameters corresponding to the target SOI chip. With the help of the automation and accuracy of the architecture, it can obtain the temperature data of each segment in the full-temperature zone test in real time and continuously, providing an accurate temperature benchmark for frequency drift analysis, helping to explore the chip temperature-performance correlation law, and improving the adaptability and reliability of the full-temperature zone compensation strategy.

[0045] Among them, the ambient temperature parameters refer to the quantitative expression of the test environment temperature of the target SOI chip, including the temperature value of the heat-sensitive area and the surrounding environment of the chip, the temperature change rate, the temperature fluctuation amplitude and other data. It is collected at a set sampling frequency and is used to analyze the impact of ambient temperature on chip performance (such as frequency drift). It is a key input for building a chip temperature-performance model. For example, the temperature of the heat-sensitive area of ​​the chip at a certain moment is 25°C, and the temperature change rate is 0.5°C / s. These data are the ambient temperature parameters.

[0046] As an embodiment of the present invention, the ambient temperature parameters corresponding to the target SOI chip are collected based on the fully automatic test architecture, including: obtaining the real-time operating status of the fully automatic test architecture when it is running; analyzing the temperature distribution gradient corresponding to the real-time operating status; determining the thermal sensitive area corresponding to the target SOI chip based on the temperature distribution gradient; setting the temperature point sampling frequency corresponding to the thermal sensitive area; and collecting the ambient temperature parameters corresponding to the target SOI chip based on the temperature point sampling frequency.

[0047] The real-time operating status refers to the various operating characteristics and parameters presented by the fully automated test architecture at the moment it executes chip testing tasks, covering the operating mode of hardware devices, the execution progress of software programs, the rate and status of data exchange, etc. For example, the output frequency of the signal generator in the test architecture, the operating gain of the power amplifier, the cache occupancy rate of the data acquisition module, and the current step of the test process (such as the stimulus signal transmission stage or the response signal acquisition stage) constitute the real-time operating status. The temperature distribution gradient refers to a quantitative description of the rate and direction of temperature change within the fully automated test architecture or the related test environment space during operation, reflecting the temperature variation at different locations and different test stages. It analyzes the temperature values ​​of different areas (such as the chip periphery, test fixture, signal transmission path, etc.) and calculates the ratio of the temperature difference between adjacent locations to the distance to obtain the speed and trend of temperature change. For example, in a chip test chamber, if the temperature increases by 2°C per centimeter from the chamber wall to the chip surface, there will be a temperature distribution gradient of 2°C / cm in that direction. The heat-sensitive area refers to the target SOI chip determined based on the temperature distribution gradient analysis. In the chip and test environment, there are specific areas that are extremely sensitive to temperature changes and where temperature fluctuations will significantly affect the chip performance and test results. A slight change in the temperature of these areas may cause obvious changes in chip characteristics such as frequency drift. For example, the active device array area of ​​the chip, or the area near the high-speed signal transmission line closely connected to the chip, due to factors such as heat conduction and heat radiation, temperature changes have a great impact on the electrical performance of the chip, which is the heat-sensitive area; the temperature point sampling frequency refers to the number of times the temperature of a determined heat-sensitive area is collected per unit time, which is used to accurately capture the dynamic changes in the temperature of the heat-sensitive area. It is set according to the severity of the temperature fluctuation in the heat-sensitive area and the test requirements. The more frequent the fluctuation and the more critical the impact on the test results, the higher the sampling frequency. For example, for the heat-sensitive area of ​​the chip power module with rapidly changing temperature, the temperature is set to be collected 10 times per second, that is, the temperature point sampling frequency is 10Hz, to record the temperature change process in detail.

[0048] Furthermore, obtaining the real-time operating status of the fully automatic test architecture during operation can be achieved through an embedded system monitoring method, such as using the built-in FPGA module of the NI CompactRIO controller to collect voltage and current timing data of each test node, thereby obtaining the real-time operating status; analyzing the temperature distribution gradient corresponding to the real-time operating status can be achieved through an infrared thermal imaging processing method, such as using FLIR ResearchIR Max software to perform gradient calculations on the chip surface thermal map, extracting isothermal distribution features, and thus obtaining the temperature distribution gradient; determining the heat-sensitive area corresponding to the target SOI chip can be achieved through a thermal resistance network modeling method, such as establishing a three-dimensional thermal model based on ANSYS Icepak, identifying temperature-sensitive nodes through heat flux density simulation, and thus obtaining the heat-sensitive area; setting the temperature point sampling frequency corresponding to the heat-sensitive area can be achieved through a Nyquist sampling theorem derivation method, such as calculating the minimum sampling interval based on the thermal time constant and configuring a multi-channel polling strategy using the Keithley 3706A system switch matrix to obtain the temperature point sampling frequency; and collecting the ambient temperature parameters corresponding to the target SOI chip can be achieved through distributed sensor network technology, such as deploying Honeywell The HTU21D digital temperature and humidity sensor array uses the Modbus protocol to synchronously read multi-location measurement values ​​to obtain ambient temperature parameters.

[0049] By collecting the instantaneous temperature values ​​in the current ambient temperature parameters, the present invention can accurately capture the real-time temperature transients of the chip working environment, provide an instant temperature benchmark for dynamically matching the segmented compensation interval, ensure that the compensation vector is synchronized with the current temperature characteristics in real time, and optimize the temperature prediction model to improve the real-time and accuracy of compensation in the entire temperature zone.

[0050] Among them, the instantaneous temperature value refers to the real-time temperature data measured by the temperature acquisition equipment on the target SOI chip environment or heat-sensitive area at a specific moment, reflecting the temperature state at that moment. For example, during the chip test process, when the temperature of the incubator rises rapidly from 25°C to 80°C, the 72.3°C captured by the temperature sensor at the 10th second is the instantaneous temperature value at that moment, which can accurately reflect the real-time state of the dynamic temperature change and provide a key basis for real-time temperature compensation. Optionally, the acquisition of the instantaneous temperature value in the ambient temperature parameter can be achieved through thermocouple fast response technology, such as: using Omega K-type thermocouple with NI 9213 acquisition module to achieve millisecond-level temperature sampling, thereby obtaining the instantaneous temperature value.

[0051] The present invention analyzes the temperature compensation vector corresponding to the segmented compensation interval based on the instantaneous temperature value, can accurately match the current compensation interval of the chip according to the real-time temperature, quickly generate an adaptive compensation parameter combination, realize dynamic response and real-time correction of temperature drift, reduce compensation errors under extreme temperatures, and ensure the performance stability of the chip in a dynamic temperature environment.

[0052] Among them, the temperature compensation vector refers to a multidimensional parameter vector parsed for the current segmented compensation interval based on the node compensation sequence and used to correct the chip frequency output. The vector usually contains elements such as polynomial coefficients, offsets, and weight factors. For example, [0.0018, 0.12, -2.8, 1.05] corresponds to the coefficients and correction factors of the quadratic polynomial compensation model. This vector directly drives the hardware compensation circuit or digital algorithm to make the chip output frequency approach the ideal value at the current temperature, thereby realizing dynamic temperature compensation.

[0053] As an embodiment of the present invention, the method of parsing the temperature compensation vector corresponding to the segmented compensation interval based on the instantaneous temperature value includes: mapping the instantaneous temperature value along the time axis and the interval axis to generate a temperature distribution matrix; analyzing the slope change interval corresponding to the temperature distribution matrix; marking the compensation feature nodes in the temperature distribution matrix based on the slope change interval; querying the node compensation sequence corresponding to the compensation feature node; and parsing the temperature compensation vector corresponding to the segmented compensation interval based on the node compensation sequence.

[0054] The temperature distribution matrix refers to a matrix generated by two-dimensionally arranging instantaneous temperature values ​​in the time dimension (such as continuous sampling points at 0.1 second intervals) and the interval dimension (such as -55°C to 125°C divided into 20 segmented compensation intervals). For example, 21 temperature values ​​are collected at 0.5 second intervals within 10 seconds, and each value corresponds to a segmented interval, forming a 21×20 matrix. The matrix elements represent the temperature values ​​in a specific interval at a specific moment. This matrix is ​​used to capture the spatiotemporal characteristics of temperature variations, providing a structured data foundation for subsequent analysis. The slope change interval refers to the temperature range in the temperature distribution matrix where the rate of change (i.e., slope) of adjacent temperature values ​​changes significantly. For example, the frequency drift of an SOI chip in the 25°C to 50°C range is 0.5 ppm for every 1°C increase in temperature, while the drift rate changes to 1.2 ppm in the 50°C to 80°C range. The boundary point between these two intervals (e.g., 50°C) is the slope change point. The interval containing such a change point is called the slope change interval. Identifying this interval helps locate the region where the temperature characteristic changes suddenly. The compensation feature node refers to the characteristic point in the temperature distribution matrix marked based on the slope change interval that is critical for temperature compensation. For example, nodes marked at the inflection point of the full-temperature curve (e.g., the critical point where the temperature characteristic changes from linear to nonlinear) or the extreme point (e.g., the temperature point corresponding to the maximum frequency drift). These nodes are the hubs connecting the temperature distribution and the compensation strategy, and their location and characteristics directly determine the subsequent selection of compensation parameters. The node compensation sequence refers to a predefined sequence of compensation parameter combinations that corresponds one-to-one with the compensation feature node. Each sequence contains a set of compensation parameters (such as polynomial coefficients, gain factors, etc.) for a specific node. For example, when the characteristic node corresponds to 80°C (the critical point of a certain segmented interval), its compensation sequence may be {quadratic term coefficient 0.002, linear term coefficient 0.15, constant term -3.2}, which is used to construct the frequency compensation formula for this temperature point. The sequence is generated through historical data training or theoretical calculations and stored in the compensation algorithm library.

[0055] Furthermore, the mapping of the instantaneous temperature values ​​along the time axis and the interval axis can be achieved by a thermal topology reconstruction method, such as using FLIR Tools+ The SDK maps multi-sensor data to the surface of the chip three-dimensional model, generates a spatial temperature matrix through bilinear interpolation, and thus obtains a temperature distribution matrix; the analysis of the slope change interval corresponding to the temperature distribution matrix can be achieved through a gradient field calculation method, such as: performing a two-dimensional difference operation on the matrix data based on the gradient function of MATLAB, and automatically dividing the change interval by setting a slope threshold, thereby obtaining the slope change interval; the marking of the compensation feature nodes in the temperature distribution matrix can be achieved through a clustering center recognition algorithm, such as: using the K-means++ algorithm to perform cluster analysis on the hot node data, extracting the center point coordinates of each category, thereby obtaining the compensation feature nodes; the query of the node compensation sequence corresponding to the compensation feature node can be achieved through a graph theory shortest path method, such as: using the Dijkstra algorithm to construct a node association graph, calculating the optimal compensation path to generate a time series queue, thereby obtaining a node compensation sequence; the analysis of the temperature compensation vector corresponding to the segmented compensation interval can be achieved through a segmented polynomial regression method, such as: applying the fitlm function of MATLAB to independently fit a second-order compensation function for each interval, extracting coefficients to generate multiple compensation vectors, thereby obtaining a temperature compensation vector.

[0056] S4. Based on the temperature compensation amount, monitor the signal frequency interval output by the target SOI chip, extract the phase noise parameter in the signal frequency interval, and calculate the frequency offset error between the phase noise parameter and a preset design value.

[0057] Based on the temperature compensation amount, the present invention monitors the signal frequency range output by the target SOI chip, verifies the correction effect of the compensation algorithm on the frequency drift in real time, accurately locates the frequency offset error that still exists after compensation, provides data support for the dynamic optimization of the compensation parameters, and ultimately improves the frequency output stability of the chip in a complex temperature environment.

[0058] The signal frequency interval refers to the reasonable range within which the output frequency of the target SOI chip should be within under the dynamic threshold constraint. For example, when the dynamic threshold is set to 99.980MHz to 100.020MHz, the signal frequency interval is this closed interval. By continuously monitoring this interval, it can be determined whether the chip maintains a stable working state after temperature compensation. The narrower the interval, the higher the temperature compensation accuracy, providing reliability assurance for the chip's application in high-precision systems (such as communications and radar).

[0059] As an embodiment of the present invention, monitoring the frequency range of the signal output by the target SOI chip based on the temperature compensation amount includes: adjusting a bias voltage parameter corresponding to the target SOI chip according to the temperature compensation amount; collecting the real-time signal frequency output by the target SOI chip based on the bias voltage parameter; analyzing the fluctuation range corresponding to the real-time signal frequency; setting a dynamic threshold corresponding to the target SOI chip based on the fluctuation range; and monitoring the frequency range of the signal output by the target SOI chip based on the dynamic threshold.

[0060] Among them, the bias voltage parameter refers to the voltage value used to adjust the operating point of the internal circuit of the SOI chip. By dynamically adjusting this parameter through the temperature compensation amount, the electrical characteristics of the chip can be changed to offset the temperature drift. For example, when the temperature compensation amount shows that the frequency stability needs to be improved, the bias voltage is fine-tuned from the default 1.2V to 1.25V, and the frequency output characteristics of the chip at the current temperature are optimized by changing the threshold voltage or gain of the transistor; the real-time signal frequency refers to the actual output frequency of the electrical signal of the target SOI chip after adjusting the bias voltage, which is collected in real time by a high-frequency counter or spectrum analyzer. For example, when the temperature is 85°C and the bias voltage is adjusted to 1.25V, the clock signal frequency output by the chip is 99.987MHz. This value reflects the actual working state of the chip under the current temperature and compensation conditions, and is the core indicator for evaluating the effectiveness of compensation; the fluctuation range refers to the real-time signal The maximum frequency variation within a certain time window is usually expressed as peak-to-peak value or standard deviation. For example, if the chip frequency fluctuates between 99.985MHz and 99.992MHz within 10 seconds, the fluctuation range is 7kHz. This indicator quantifies the stability of the frequency after temperature compensation and reflects the compensation algorithm's ability to suppress random noise and slight temperature changes. The smaller the fluctuation range, the better the compensation effect. The dynamic threshold is a boundary value adaptively set according to the frequency fluctuation range to determine whether the frequency is abnormal. For example, if the standard deviation calculated based on historical fluctuation data is ±3kHz, the dynamic threshold can be set to ±5kHz of the mean (reserving a safety margin). When the real-time frequency exceeds this threshold (such as reaching 100.003MHz), an alarm is triggered or the compensation parameters are readjusted. The threshold automatically updates with the ambient temperature and fluctuation characteristics to avoid misjudgment of fixed thresholds at extreme temperatures.

[0061] Furthermore, adjusting the bias voltage parameters corresponding to the target SOI chip can be achieved through an adaptive voltage regulation algorithm, such as using TI's DAC7741 digital-to-analog converter in conjunction with a PID control loop to dynamically adjust the supply voltage based on real-time frequency feedback, thereby obtaining the bias voltage parameters; the real-time signal frequency output by the target SOI chip can be acquired through high-speed frequency counting technology, such as using Keysight The 53230A frequency counter captures the output signal edge at a 1 MHz sampling rate and calculates the instantaneous frequency using the equal-precision measurement principle, thereby obtaining the real-time signal frequency. Analyzing the fluctuation range corresponding to the real-time signal frequency can be achieved using statistical process control methods, such as calculating the 3σ control limits of the frequency data using Minitab software and automatically identifying abnormal fluctuations exceeding the ±1.5% tolerance band, thereby obtaining the fluctuation range. Setting the dynamic threshold corresponding to the target SOI chip can be achieved using a moving window extreme value detection method, such as using Python's Pandas library to rollingly calculate the maximum and minimum frequency values ​​of the most recent 100 sampling cycles and generating an adaptive threshold with a safety factor of 1.2, thereby obtaining the dynamic threshold. Monitoring the signal frequency range output by the target SOI chip can be achieved using a spectrum waterfall analysis method, such as using an R&S FSW spectrum analyzer to continuously record time-frequency characteristics and automatically marking the upper and lower boundaries of the frequency distribution using the peak hold function, thereby obtaining the signal frequency range.

[0062] By extracting the phase noise parameters in the signal frequency range, the present invention can accurately evaluate the impact of temperature compensation on the signal phase stability, identify the phase distortion characteristics in the high-frequency band to optimize the compensation algorithm, and provide a basis for optimizing phase characteristics for the application of chips in high-precision scenarios such as communications and radar.

[0063] Among them, the phase noise parameter refers to a quantitative indicator that measures the random fluctuations in the frequency phase of a signal, and is used to characterize the degree to which the signal deviates from an ideal sine wave in the frequency domain. It is usually expressed as the single-sideband phase noise power spectral density (such as dBc / Hz) at a specified frequency offset. For example, at a carrier frequency of 100MHz, the phase noise parameter of a certain SOI chip at a 10kHz offset is -110dBc / Hz, which means that the noise power at 10kHz near this frequency point is 110 decibels lower than the carrier power. This parameter reflects the phase stability of the signal after temperature compensation and is a key indicator for evaluating chip performance in scenarios such as high-frequency communications and precision clocks. Optionally, the extraction of the phase noise parameter in the signal frequency range can be achieved through a digital signal processing algorithm, such as: performing a windowed FFT transform on the acquired signal based on the pwelch function of MATLAB, extracting the phase noise curve with an offset of 10kHz to 1MHz by calculating the single-sideband power spectrum, and thus obtaining the phase noise parameter.

[0064] Furthermore, the present invention can accurately locate the deviation between the actual phase characteristics of the chip and the design target by calculating the frequency offset error between the phase noise parameter and the preset design value, providing a quantitative basis for the optimization of the compensation algorithm, ensuring that the phase stability meets the requirements of high-precision scenarios, and continuously improving the signal spectrum purity and system-level phase consistency, laying a reliability foundation for phase-sensitive application scenarios such as communications and radar.

[0065] The preset design value refers to the theoretical value of a performance indicator pre-set based on the application scenario requirements during the target SOI chip development phase. It serves as a benchmark for evaluating whether the chip's actual output meets the standard. For example, the preset design value for chips used in 5G communication base stations requires that the phase noise at a 10GHz carrier frequency and a 100kHz offset be no higher than -120dBc / Hz. This value is determined by the system's requirements for signal spectrum purity and clock synchronization accuracy. The preset design value typically includes multiple sets of parameter thresholds for various temperature zones and voltages, which are used to compare the measured phase noise parameters during testing to determine whether the chip meets design expectations. The frequency offset error is a quantitative indicator used to measure the degree of difference between the actual phase noise parameters and the preset design value. It integrates the phase noise deviation at each frequency offset point and reflects the overall deviation of the chip output signal phase noise from the design target. For example, after testing at multiple frequency offset points, a FE of 0.15 calculated by substituting it into the formula means that the actual phase noise deviates to a certain extent from the design value. A smaller value indicates closer proximity to the design target.

[0066] As an embodiment of the present invention, the calculating the frequency offset error between the phase noise parameter and a preset design value includes: The frequency deviation error between the phase noise parameter and the preset design value is calculated using the following formula: ; in, Indicates the frequency deviation error between the phase noise parameter and the preset design value, Indicates the total number of frequency offset points in phase noise analysis, Indicates the number index corresponding to the frequency offset point, Indicates the The phase noise parameters of the target SOI chip output signal actually collected at the frequency offset point are: Indicates the At each frequency offset point, the design target value of the phase noise is preset.

[0067] In detail, the frequency offset point refers to a number of specific frequency positions deviated from the carrier selected based on the carrier frequency in the phase noise analysis. These points are used to detect the phase noise conditions at different offset distances and comprehensively evaluate the signal quality. For example, for a 100MHz carrier frequency, 1kHz, 10kHz, 100kHz, etc. are selected as frequency offset points, and the phase noise at each point is tested to understand the noise characteristics of the signal at different frequency offsets; the phase noise parameter refers to a parameter that characterizes the degree of random fluctuation of the signal phase, reflecting the signal frequency stability and spectral purity. It is usually presented in the form of single-sideband power spectral density (such as dBc / Hz) at a specific frequency offset point. For example, at a frequency offset point of 10kHz, the phase noise parameter of a chip signal is measured to be -90dBc / Hz. , indicating that the noise power at this offset point is 90 decibels lower than the carrier power. The smaller the value, the lower the noise and the higher the signal quality. The design target value refers to the ideal value of the phase noise at each frequency offset point that is pre-set according to application requirements during the chip R&D and design phase, which serves as a reference for measuring whether the actual performance meets the standard. For example, when designing a communication chip, the phase noise design target value at the 10kHz offset point is required to be -95dBc / Hz. If the actual test is close to this value, it means that the chip phase noise performance meets the design expectations and is conducive to ensuring the communication quality of the system.

[0068] S5. Analyze the error source corresponding to the frequency offset error; based on the error source, optimize the polynomial compensation order corresponding to the target SOI chip to obtain an optimized compensation order; collect temperature drift suppression data during execution of the optimized compensation order; and generate a full-temperature range compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

[0069] By analyzing the error source corresponding to the frequency offset error, the present invention can accurately locate problems in chip design, manufacturing or testing, and clarify whether the error is caused by insufficient temperature compensation strategy, hardware circuit noise or process deviation, thereby improving chip signal quality and frequency stability and ensuring system-level application performance.

[0070] Among them, the error sources refer to various factors that cause the frequency deviation error, covering aspects such as chip design, manufacturing, testing and use environment. For example, the compensation algorithm does not fully cover the entire temperature range during chip design, the transistor process deviation during manufacturing causes parameter drift, the temperature sampling accuracy is insufficient during testing, or the power supply voltage fluctuation affects the signal output during use. These factors will cause the actual phase noise to deviate from the preset value, and need to be checked one by one to optimize performance. Optionally, the analysis of the error source corresponding to the frequency deviation error can be achieved through the error contribution decomposition method, such as: using the variance analysis module (ANOVA) of Minitab software to perform factor significance tests on multiple groups of test data, identify the contribution weights of variables such as temperature and voltage, and thus obtain the error source.

[0071] Furthermore, based on the error source, the present invention optimizes the polynomial compensation order corresponding to the target SOI chip to obtain an optimized compensation order, which can accurately adapt to the error characteristics introduced by the chip due to design, manufacturing and other links, and can make the compensation strategy more in line with the actual performance of the chip, helping to explore the potential performance boundaries of the chip, and laying a solid foundation for subsequent iterative design and stable application.

[0072] Among them, the optimized compensation order refers to the new polynomial compensation order obtained by analyzing the source of error, adjusting the order distribution, determining the dominant order component, setting the optimization weight and order increment, etc. It can more accurately adapt to the chip error characteristics and improve the compensation effect. For example, the original compensation order is 3rd order, which becomes 5th order after optimization. The new 5th order compensation order can more comprehensively cover the error source and effectively reduce the frequency deviation error.

[0073] As an embodiment of the present invention, optimizing the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain the optimized compensation order includes: analyzing the order distribution profile corresponding to the error source; querying the dominant order component in the order distribution profile; generating an order optimization weight corresponding to the dominant order component; determining the order increment corresponding to the dominant error component based on the order optimization weight; and optimizing the polynomial compensation order corresponding to the target SOI chip based on the order increment to obtain the optimized compensation order.

[0074] Among them, the order distribution profile refers to the distribution of polynomial compensation orders in different error impact dimensions after analyzing the error sources. It covers information such as the proportion of each order's contribution to the error and the distribution trend, which is used to clarify which orders play a key role in the error composition. For example, by analyzing the source of temperature drift error, it is found that the 1st and 3rd order compensation terms have a significant impact on the error, while the 2nd order has a smaller impact. The statistical results of sorting out the proportions and action trends of these orders are the order distribution profile; the dominant order component refers to the polynomial compensation order component that has a major impact on the error, which is screened out from the order distribution profile. These order components account for a large proportion in the error composition and are the objects that need to be focused on when optimizing the compensation order. For example, in the order distribution, if the error corresponding to the 3rd order compensation term accounts for 60% of the total error, far exceeding other orders, then the 3rd order compensation term is the dominant order component. The order optimization weight refers to the weight coefficient set for adjusting the dominant order component, which is determined according to the degree of influence of the dominant order component on the error and the optimization requirements, and is used to quantify the adjustment strength of each order component in the optimization process. For example, for the third-order term in the dominant order component, an optimization weight of 0.8 is assigned according to its error contribution and chip performance requirements, which is higher than the weights of other secondary order components, so that the optimization resources are more focused on the key order; the order increment refers to the numerical change in the polynomial compensation order corresponding to the dominant error component based on the order optimization weight. It is used to increase or adjust the number of orders on the basis of the original order to adapt to the error compensation requirements. For example, the original polynomial compensation order is 5th order. After analyzing the source of the error, it is determined that the dominant order component needs to be increased by 2 orders to optimize the compensation effect. The increased 2 orders are the order increment.

[0075] Furthermore, the analysis of the order distribution profile corresponding to the error source can be achieved through a power spectral density decomposition method, such as: using MATLAB's pwelch function to perform frequency domain analysis on the error sequence, and determining the energy proportion of each order through harmonic peak detection, thereby obtaining an order distribution profile; the query of the dominant order component in the order distribution profile can be achieved through an envelope spectrum peak detection method, such as: demodulating the frequency deviation signal based on MATLAB's envelope function, and identifying significant order components with an amplitude exceeding 30% of the total energy through FFT spectrum analysis, thereby obtaining the dominant order component; the generation of the order optimization weight corresponding to the dominant order component can be achieved through a contribution factor weighting method, such as: The entropy weight method is used to calculate the information entropy value of each order component, and a normalized weight coefficient of 0.1 to 0.9 is automatically assigned according to the entropy ratio to obtain the order optimization weight; the determination of the order increment corresponding to the dominant error component can be achieved by a gradient descent optimization method, such as: using the TensorFlow framework to construct a polynomial regression model, and calculating the sensitivity gradient of each order coefficient to the error by automatic differentiation, so as to obtain the order increment; the optimization of the polynomial compensation order corresponding to the target SOI chip can be achieved by the Akaike Information Criterion evaluation method, such as: using the glmulti package of R language to perform multi-order model fitting, and selecting the optimal complexity compensation model with the smallest AIC value to obtain the optimized compensation order.

[0076] By collecting the temperature drift suppression data during the execution of the optimized compensation order, the present invention can accurately verify the actual suppression effect of the compensation model on temperature drift. By quantifying the compensation residuals in different temperature zones, it provides data support for model iteration, ensuring that the compensation strategy continues to match the chip's temperature drift characteristics, and helping to improve the chip's full-temperature frequency stability and the robustness of the compensation strategy.

[0077] Among them, the temperature drift suppression data refers to various quantitative indicators collected during the execution of the optimized compensation order to measure the temperature drift compensation effect, covering data such as frequency drift at different temperature points, error comparison before and after compensation, phase noise change, etc. For example, in the temperature range of -40°C to 125°C, the deviation value between the actual frequency and the ideal frequency after chip compensation, as well as the corresponding phase noise parameters, are recorded at intervals of 10°C. These data constitute temperature drift suppression data, which are used to evaluate the ability of the optimized compensation order to suppress temperature drift. Optionally, the temperature drift suppression data collected during the execution of the optimized compensation order can be achieved through a high-precision temperature-frequency synchronous sampling method, such as using a Keysight 34972A data acquisition instrument to synchronously record the chip junction temperature (via infrared temperature measurement) and the output frequency (via a frequency counter), establish a temperature-frequency drift characteristic curve, and thus obtain temperature drift suppression data.

[0078] Furthermore, the present invention generates a full-temperature zone compensation report corresponding to the target SOI chip based on the temperature drift suppression data, and can systematically integrate the compensation effect data of each temperature zone, and visualize the correlation between temperature-frequency drift-compensation effect, thereby providing an intuitive basis for chip design optimization and application selection, and building a data support system for chip full-temperature domain performance improvement and reliability evaluation.

[0079] The full-temperature compensation report refers to a document that systematically analyzes the compensation effect of a target SOI chip over the full temperature operating range (e.g., -55°C to 125°C) by integrating temperature drift suppression data. The report includes measured frequency drift values ​​for each temperature zone, error comparisons before and after compensation, phase noise indicators, and an evaluation of the effectiveness of the optimized compensation order. The report is often presented in the form of charts (e.g., temperature-zone-frequency deviation curves and compensation residual heat maps) combined with text descriptions. For example, one report shows that after compensation, the frequency deviation of the chip at 85°C is reduced from ±20ppm to ±3ppm, and the phase noise is improved by 15dBc / Hz, intuitively demonstrating the effectiveness of the full-temperature compensation strategy. Optionally, generating the full-temperature compensation report for the target SOI chip can be implemented using the LabVIEW test report toolkit, such as using NI DIAdem software to automatically integrate temperature scan data, frequency stability analysis, and compensation effect evaluation to generate a comprehensive report containing key parameter tables and trend charts, thereby obtaining the full-temperature compensation report.

[0080] Compared with the problems described in the background technology, the present invention can accurately capture the nonlinear change characteristics of chip temperature-frequency by acquiring the temperature-frequency data of the target SOI chip within the preset temperature range, provide data support for the polynomial curve fitting of the full temperature range, and then realize the scientific definition of the segmented compensation interval by dividing the temperature zone critical point, effectively improving the accuracy and adaptability of temperature compensation. The present invention divides the segmented compensation interval in the full temperature range curve based on the temperature zone critical point, and can decompose the nonlinear temperature characteristics into multiple approximate linear or low-order nonlinear sub-intervals, so that the temperature-frequency relationship in each interval is easier to model and compensate, effectively reducing the complexity and calculation amount of polynomial fitting, and providing a structured framework for realizing high-precision full temperature range dynamic compensation. Furthermore, the present invention collects the ambient temperature parameters corresponding to the target SOI chip based on the fully automatic test architecture, and can use the automation and precision of the architecture to achieve high-precision full temperature range dynamic compensation. Accuracy, real-time and continuous acquisition of temperature data of each segment in the full temperature zone test, providing an accurate temperature benchmark for frequency drift analysis, helping to explore the chip temperature-performance correlation law, and improving the adaptability and reliability of the full temperature zone compensation strategy. Furthermore, the present invention monitors the signal frequency range output by the target SOI chip based on the temperature compensation amount, and can verify the correction effect of the compensation algorithm on the frequency drift in real time, accurately locate the frequency deviation error that still exists after compensation, and provide data support for the dynamic optimization of compensation parameters, and ultimately improve the frequency output stability of the chip in a complex temperature environment. Finally, by analyzing the error source corresponding to the frequency deviation error, the present invention can accurately locate the problems in the chip design, manufacturing or testing links, and clarify whether the error is caused by insufficient temperature compensation strategy, hardware circuit noise or process deviation, thereby improving the chip signal quality and frequency stability and ensuring system-level application performance. Therefore, a full-temperature zone polynomial digital temperature compensation method and system based on SOI chip provided in an embodiment of the present invention can improve the performance stability of the chip in a complex environment.

[0081] Example 2: like Figure 3 FIG. 1 is a functional module diagram of a full-temperature-range polynomial digital temperature compensation system based on an SOI chip according to the present invention.

[0082] The full-temperature-range polynomial digital temperature compensation system 200 based on an SOI chip described in the present invention can be installed in an electronic device. Depending on the functionality implemented, the full-temperature-range polynomial digital temperature compensation system based on an SOI chip can include a critical point extraction module 201, an architecture construction module 202, a vector analysis module 203, an error calculation module 204, and a report generation module 205. The modules described in the present invention, also referred to as units, refer to a series of computer program segments that can be executed by an electronic device processor and can perform fixed functions, and are stored in the memory of the electronic device.

[0083] In the embodiment of the present invention, the functions of each module / unit are as follows: The critical point extraction module 201 is used to obtain temperature-frequency data of a target SOI chip within a preset temperature range, fit a full temperature range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract the temperature range critical points in the full temperature range curve; The architecture construction module 202 is configured to divide the full temperature range curve into segmented compensation intervals based on the temperature zone critical points, calculate the frequency drift of the segmented compensation intervals under different operating voltages, and construct a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift; The vector parsing module 203 is configured to collect, based on the fully automatic test architecture, the ambient temperature parameters corresponding to the target SOI chip, collect instantaneous temperature values ​​from the ambient temperature parameters, and parse the temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values; The error calculation module 204 is configured to monitor the signal frequency interval output by the target SOI chip based on the temperature compensation amount, extract the phase noise parameter in the signal frequency interval, and calculate the frequency offset error between the phase noise parameter and a preset design value; The report generation module 205 is used to analyze the error source corresponding to the frequency offset error, optimize the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain an optimized compensation order, collect temperature drift suppression data of the optimized compensation order during execution, and generate a full-temperature range compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

[0084] In detail, the modules in the full-temperature-range polynomial digital temperature compensation system 200 based on SOI chip in the embodiment of the present invention are used in the same manner as above. Figure 1 The same technical means as the full-temperature-range polynomial digital temperature compensation method based on SOI chip described in , and can produce the same technical effects, will not be repeated here.

[0085] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A full-temperature range polynomial digital temperature compensation method based on SOI chip, characterized in that: The method comprises: Acquire temperature-frequency data of a target SOI chip within a preset temperature range, fit a full-temperature-range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract temperature-range critical points in the full-temperature-range curve; Based on the temperature zone critical points, the full temperature zone curve is divided into segmented compensation intervals, the frequency drift of the segmented compensation intervals under different operating voltages is calculated, and based on the frequency drift, a fully automatic test architecture corresponding to the target SOI chip is constructed; Based on the fully automatic test architecture, collecting the ambient temperature parameters corresponding to the target SOI chip, collecting the instantaneous temperature values ​​in the ambient temperature parameters, and analyzing the temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values; Based on the temperature compensation amount, monitoring the signal frequency interval output by the target SOI chip, extracting the phase noise parameter in the signal frequency interval, and calculating the frequency offset error between the phase noise parameter and a preset design value; Analyze the error source corresponding to the frequency offset error, optimize the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain the optimized compensation order, collect temperature drift suppression data of the optimized compensation order during execution, and generate a full-temperature zone compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

2. A full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The step of fitting a full temperature range curve corresponding to the target SOI chip based on the temperature-frequency data includes: Identifying a set of temperature points in the temperature-frequency data; Querying the temperature characteristic index corresponding to the temperature point set; extracting frequency response parameters corresponding to the target SOI chip based on the temperature characteristic index; Performing curve simulation on the frequency response parameters to obtain an initial temperature curve; Performing full-range temperature calibration on the initial temperature curve to generate a full-temperature range curve.

3. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The calculating the frequency drift of the segmented compensation interval under different operating voltages includes: The frequency drift of the segmented compensation interval under different operating voltages is calculated using the following formula: ； in, Indicates the frequency drift of the segmented compensation interval under different operating voltages, Indicates the sequence number of the segmented compensation interval, Indicates the serial number of the operating voltage, represents the total number of temperature sampling points within the segmented compensation interval, Indicates the number index of temperature sampling points, Indicates the Temperature sampling points The corresponding actual measurement frequency, It represents the frequency average of all temperature sampling points in the i-th segment compensation interval. and Respectively represent the lowest temperature value and the highest temperature value of the i-th segment compensation interval, Indicates the total number of voltage sampling points corresponding to the working voltage, Indicates the number index of voltage sampling points, represents the jth operating voltage, Indicates the average voltage of all operating voltages.

4. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The step of constructing a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift includes: Analyzing the drift spectrum characteristics corresponding to the frequency drift amount; Analyzing the key test frequency band corresponding to the drift spectrum characteristics; Configuring a programming stimulus source corresponding to the key test frequency band; generating a test signal sequence driven by the programming stimulus source; According to the test signal sequence, a fully automatic test architecture corresponding to the target SOI chip is constructed.

5. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The collecting of the ambient temperature parameters corresponding to the target SOI chip based on the fully automatic test architecture includes: Obtaining the real-time running status of the fully automatic test architecture when it is running; Analyzing the temperature distribution gradient corresponding to the real-time operating state; Determining a heat-sensitive area corresponding to the target SOI chip based on the temperature distribution gradient; Setting the temperature point sampling frequency corresponding to the heat-sensitive area; Based on the temperature point sampling frequency, the ambient temperature parameters corresponding to the target SOI chip are collected.

6. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The step of analyzing the temperature compensation vector corresponding to the segmented compensation interval based on the instantaneous temperature value includes: Mapping the instantaneous temperature values ​​along the time axis and the interval axis to generate a temperature distribution matrix; Analyzing the slope variation interval corresponding to the temperature distribution matrix; Based on the slope change interval, marking the compensation feature nodes in the temperature distribution matrix; Querying the node compensation sequence corresponding to the compensation feature node; Based on the node compensation sequence, the temperature compensation vector corresponding to the segmented compensation interval is analyzed.

7. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The step of monitoring the frequency range of a signal output by the target SOI chip based on the temperature compensation amount includes: adjusting a bias voltage parameter corresponding to the target SOI chip according to the temperature compensation amount; Based on the bias voltage parameter, collecting the real-time signal frequency output by the target SOI chip; Analyzing the fluctuation range corresponding to the real-time signal frequency; According to the fluctuation range, a dynamic threshold corresponding to the target SOI chip is set; Based on the dynamic threshold, a frequency interval of a signal output by the target SOI chip is monitored.

8. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: Calculating the frequency offset error between the phase noise parameter and a preset design value includes: The frequency deviation error between the phase noise parameter and the preset design value is calculated using the following formula: ； in, Indicates the frequency deviation error between the phase noise parameter and the preset design value, Indicates the total number of frequency offset points in phase noise analysis, Indicates the number index corresponding to the frequency offset point, Indicates the The phase noise parameters of the target SOI chip output signal actually collected at the frequency offset point are: Indicates the At each frequency offset point, the design target value of the phase noise is preset.

9. The full-temperature range polynomial digital temperature compensation method based on SOI chip according to claim 1, characterized in that: The step of optimizing the polynomial compensation order corresponding to the target SOI chip based on the error source to obtain the optimized compensation order includes: Analyze the order distribution profile corresponding to the error source; querying a dominant order component in the order distribution profile; generating an order optimization weight corresponding to the dominant order component; determining an order increment corresponding to the dominant error component based on the order optimization weight; Based on the order increment, the polynomial compensation order corresponding to the target SOI chip is optimized to obtain an optimized compensation order.

10. A full-temperature range polynomial digital temperature compensation system based on SOI chip, characterized in that: The system comprises: A critical point extraction module is used to obtain temperature-frequency data of a target SOI chip within a preset temperature range, fit a full temperature range curve corresponding to the target SOI chip based on the temperature-frequency data, and extract the temperature range critical points in the full temperature range curve; An architecture construction module is used to divide the full temperature range curve into segmented compensation intervals based on the temperature zone critical points, calculate the frequency drift of the segmented compensation intervals under different operating voltages, and build a fully automatic test architecture corresponding to the target SOI chip based on the frequency drift; a vector parsing module, configured to collect, based on the fully automatic test architecture, ambient temperature parameters corresponding to the target SOI chip, collect instantaneous temperature values ​​from the ambient temperature parameters, and parse temperature compensation vectors corresponding to the segmented compensation intervals based on the instantaneous temperature values; an error calculation module, configured to monitor the signal frequency interval output by the target SOI chip based on the temperature compensation amount, extract a phase noise parameter in the signal frequency interval, and calculate a frequency offset error between the phase noise parameter and a preset design value; A report generation module is used to analyze the error source corresponding to the frequency offset error, optimize the polynomial compensation order corresponding to the target SOI chip based on the error source, obtain the optimized compensation order, collect temperature drift suppression data of the optimized compensation order during execution, and generate a full-temperature zone compensation report corresponding to the target SOI chip based on the temperature drift suppression data.

Images