Multi-channel TDC signal processing board card and multi-beam laser radar signal processing system

Abstract

The invention relates to the technical field of multi-beam laser radar'low, small and slow 'target detection, in particular to a multi-channel TDC signal processing board card and a multi-beam laser radar signal processing system. According to the multichannel TDC signal processing board card, a pulse broadening circuit, a delay chain signal sampling circuit, a coding circuit, a synchronous coarse counting circuit and a data integration generation circuit are constructed based on an FPGA (Field Programmable Gate Array); the pulse broadening circuit is used for adjusting a starting moment and an ending moment of an input pulse to obtain a pulse broadening signal; the delay chain signal sampling circuit comprises a delay chain and a D trigger array; the pulse broadening signal is interpolated and delayed by a delay chain and then a thermometer code is generated by a D trigger array; the coding circuit is used for coding thermometer codes output by the D trigger array; and the synchronous coarse counter is used for triggering the data integration generation circuit, so that the data integration generation circuit integrates and outputs the coded data output by the coding circuit. According to the invention, the problem of synchronous acquisition and identification of the transmitting signal and the echo signal in the multi-beam laser radar is solved, and the time detection and measurement precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-beam laser radar "low, small, and slow" target detection, and in particular to a multi-channel TDC signal processing board and a multi-beam laser radar signal processing system. Background Art

[0002] For detecting low, small, and slow targets like drones, multi-beam lidar (LiDAR) uses the time-of-flight (ToF) ranging principle. This method determines the target's distance by measuring the time difference between the synchronous emission of a laser pulse by a laser array and the reception of the echo pulse by a single-photon avalanche diode (SPAD) array. During this process, a time-to-digital converter (TDC) acquires the ToF data, which is then combined with time-correlated single photon counting (TCSPC) technology to generate a multi-cycle photon count histogram. After data analysis and processing, the actual distance of the target from the system is determined. Subsequently, this data is combined with the servo motor's attitude information and the Global Positioning System (GPS)'s azimuth information to accurately determine the target's exact position. Therefore, the performance of multi-beam LiDAR's signal acquisition and processing directly impacts the accuracy of target positioning.

[0003] The multi-beam LiDAR system consists of an optomechanical system and a multi-beam LiDAR signal processing system. The optomechanical system utilizes components such as servo motors, a distributed laser array, and a single-photon detector array to achieve three-dimensional spatial scanning and laser signal transmission and reception. The multi-beam LiDAR signal processing system is the core control unit of the multi-beam LiDAR system, controlling the laser emission. It is also responsible for identifying and processing the laser emission signal and the echo signal received by the single-photon detector, accurately measuring the laser's time of flight and, combined with attitude information fed back by the servo motor, precisely locating the drone's target position in space.

[0004] There are two challenges in the design of multi-beam lidar signal processing systems: (1) how to accurately synchronize and identify the transmitted pulse and the echo pulse; and (2) how to accurately measure the time interval between the transmitted pulse and the echo pulse. Summary of the Invention

[0005] To address the problem of synchronous acquisition and identification of transmitted and echo signals in multi-beam lidar, the present invention proposes a multi-channel TDC signal processing board based on FPGA, which improves the time detection and measurement accuracy.

[0006] The multi-channel TDC signal processing board proposed in the present invention is based on FPGA to construct a pulse stretching circuit, a delay chain signal sampling circuit, an encoding circuit, a synchronous coarse counting circuit and a data integration generation circuit;

[0007] The pulse stretching circuit is used to adjust the start and end times of the input pulse to obtain a pulse stretching signal;

[0008] The delay chain signal sampling circuit includes a delay chain and a D flip-flop array; the pulse stretching signal is interpolated and delayed by the delay chain and then the D flip-flop array generates a thermometer code;

[0009] The encoding circuit is used to encode the thermometer code output by the D flip-flop array;

[0010] The synchronous coarse counter is used to trigger the data integration generation circuit, so that the data integration generation circuit integrates and outputs the coded data output by the coding circuit.

[0011] Preferably, the delay chain is composed of a plurality of carry lookahead chains, each carry lookahead chain being configured as a 4-bit output structure in which two sum outputs and two carry outputs are alternately combined; the D flip-flop array includes D flip-flops corresponding one-to-one to the sum outputs and carry outputs in the delay chain, each D flip-flop being used to convert a delay signal generated by the corresponding sum output or carry output into a thermometer code;

[0012] The encoding circuit includes four encoders, and the four encoders correspond one-to-one to the two sum outputs and two carry outputs in the carry lookahead chain.

[0013] Preferably, the two sum outputs and the two carry outputs in the carry lookahead chain are numbered according to the ranking, the thermometer code generated by the output with the same number in different carry lookahead chains is encoded by the encoder corresponding to the number, and the fine count codes output by each encoder are added to obtain the encoded data output by the encoding circuit.

[0014] Preferably, the encoding strategy of the encoder is: the encoder converts the acquired thermometer codes into 3-bit binary codes in groups of 7, and sets a carry flag code for each group; when all 7 thermometer codes in the group are valid codes, the carry flag code is a valid code; all carry flag codes are arranged as reference codes, and the sum of 7 multiples of the valid bits in the reference code and the decimal number of the 3-bit binary code corresponding to the "10" jump point is calculated as the detailed count code output by the encoder.

[0015] Preferably, the encoder includes a plurality of encoding units, each encoding unit first performs rearrangement encoding on the 7-bit thermometer code, and then converts the rearranged 7-bit thermometer code into a 3-bit binary code. The rearrangement encoding method of the 7-bit thermometer code includes the following steps:

[0016] S1. Set counters i and j. The initial value of counter i is the highest bit value of the 7-bit thermometer code, and the initial value of counter j is the lowest bit value of the 7-bit thermometer code. The leftmost bit of the 7-bit thermometer code is the highest bit, and the rightmost bit is the lowest bit.

[0017] S2, determine whether i is equal to j;

[0018] If yes, proceed to step S4;

[0019] If not, proceed to step S3;

[0020] S3, judging whether the jth bit of the 7-bit thermometer code from low to high is a valid bit;

[0021] If yes, update the counter j to j+1, and then return to step S2;

[0022] If not, set the i-th bit in the 7-bit thermometer code from high to low to an invalid bit, then update i to i+1, and return to step S2;

[0023] S4. Output the rearranged 7-bit thermometer code.

[0024] Preferably, the encoding rule for sum output is opposite to the encoding rule for carry output.

[0025] Preferably, it further comprises an input signal selector and a correction circuit; when the input signal selector inputs a random signal, the correction circuit calibrates the delay time of each delay unit in the delay chain using a code density calibration technology.

[0026] The present invention proposes a multi-beam lidar signal processing system, which includes a constant-ratio timing discrimination circuit and a multi-channel TDC signal processing board card corresponding to each pulse laser and single-photon detector, as well as a control core and a data integration module.

[0027] The constant-ratio timing discrimination circuit receives the transmitted pulse signal of the pulse laser and the echo pulse signal of the single-photon detector, discriminates and processes the two pulse signals, and converts them into short pulse signals that can be recognized by the FPGA; the multi-channel TDC signal processing board measures the time interval of the two pulse signals; the control core and data integration module are used for radar system communication, execution system control and data upload.

[0028] Preferably, the constant ratio timing discrimination circuit includes: a threshold discrimination part, a constant ratio discrimination signal generating part and a signal conversion part; the threshold discrimination part is used to generate a signal to enable the constant ratio discrimination signal generating part based on the comparison result of the input signal and the threshold voltage; the input signal is attenuated and delayed respectively in the constant ratio discrimination signal generating part, and the attenuated signal and the delayed signal are compared to generate a constant ratio discrimination signal, and the discrimination signal is converted into a short pulse signal that can be recognized by the FPGA through the signal conversion part.

[0029] Preferably, the constant ratio discrimination signal generating part adopts an RC circuit to attenuate the signal and adopts an LC filtering circuit to delay the signal; the signal conversion part is composed of a level converter and a differential converter.

[0030] Preferably, a random signal generator is further included to provide the TDC board with a random signal required for correction.

[0031] The advantages of the present invention are:

[0032] (1) The multi-channel TDC signal processing board proposed in this invention can fully utilize the internal resources of the FPGA to design the TDCs for the required channels on the FPGA. Furthermore, the board can be optimized based on system requirements, improving the overall performance of the TDC and achieving high-precision time-of-flight measurements. Furthermore, system control and data communication logic can be integrated into the FPGA to enable peripheral device control, data analysis, efficient board-to-board communication collaboration, and high-speed data backhaul.

[0033] (2) The present invention improves the encoding method. Through the independent distributed encoding method of the encoders, the bubbling thermometer code can be converted into a thermometer code without bubbling phenomenon, eliminating the bubbling phenomenon, improving the fine counting encoding accuracy, and further accurately measuring the time interval between the transmitted pulse and the echo pulse.

[0034] How to convert the bubbling thermometer code into a non-bubbling thermometer code, and then finally convert it into binary code as the encoding value of the fine count, that is, the output of the TDC encoder in the FPGA

[0035] (3) The present invention adopts the principle of coarse and fine combined time interpolation to measure the time interval between two input pulses, and realizes the rough counting of the time interval through the high-frequency stable system clock. The input pulse signal can be delayed in the picosecond level through the logic unit asynchronous with the clock signal in the FPGA, such as the carry chain. Multiple different delay states can be realized within one clock cycle. By accurately detecting and counting these delay states, fine measurement in the picosecond level can be realized.

[0036] (4) The multi-beam lidar signal processing system proposed in the present invention shapes the pulse signal generated when the laser emits the laser and the pulse signal generated when the single-photon detector detects the echo through a constant ratio timing discrimination circuit with pre-discrimination, and converts them into signals that can be recognized by the FPGA. Then, the time interval between the two pulses is measured through the rearranged carry coding delay chain type time-to-digital converter (TDC) with the "sum output-carry output alternating (SCSC)" architecture built inside the FPGA, thereby realizing the multi-beam lidar target detection function.

[0037] (5) The core function of the present invention is to filter and shape the signals output by the laser and the single-photon detector, and then input them into the time-to-digital converter (TDC) inside the field programmable gate array (FPGA) to measure the pulse time interval. It is suitable for ToF and FMCW laser radars. By optimizing and upgrading the existing technology, the present invention focuses on studying the impact of the bubble problem in TDC measurement on the measurement, and innovatively proposes a rearranged anti-bubble carry encoder to effectively overcome the measurement error caused by the bubble problem. After testing, this system reduces the amount of FPGA logic used while ensuring good overall performance, and has obvious advantages in multi-beam laser radars. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the multi-beam lidar signal processing system proposed in the present invention;

[0039] Figure 2 This is a schematic diagram of the constant ratio timing discrimination circuit proposed by the present invention;

[0040] Figure 3 This is a schematic diagram of the multi-channel TDC signal processing board proposed by the present invention;

[0041] Figure 4 Schematic diagram of the encoding logic for converting 7-bit-3-bit C / S thermometer code to binary code;

[0042] Figure 5 This is a diagram of the thermometer code with bubbling problem;

[0043] Figure 6 This is the flow chart of the rearrangement algorithm;

[0044] Figure 7 Schematic diagram of the structure of the rearranged anti-bubble carry encoder designed for this application;

[0045] Figure 8 This is a schematic diagram of the inconsistent random distribution of the carry chain unit delay time;

[0046] Figure 9 This is the code density correction flow chart. DETAILED DESCRIPTION

[0047] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] The multi-beam lidar signal processing system (hereinafter referred to as the signal processing system) controls the laser array to emit pulsed lasers, which are transmitted to the transmitting telescope through optical fiber and then emitted into the surrounding space. The lasers are irradiated on the surface of the detected object and reflected. The reflected lasers are collected by the receiving telescope and transmitted to the single-photon detector through optical fiber for signal detection. The signal processing system collects and processes the output signals of the laser array and the single-photon detector, and accurately measures the time interval between the two pulses, thereby obtaining the distance between the detected object and the multi-beam lidar system. Combined with the attitude information of the scanning turntable and the azimuth information of the GPS, the position of the detected object in space is accurately located.

[0049] According to the positioning principle of multi-beam laser radar, the core function of the signal processing system is to realize the processing of the pulse signal output by the laser and the single photon detector and the precise measurement of the time interval between the two pulse signals. Figure 1 As shown, it mainly includes a constant ratio timing discrimination circuit and a multi-channel TDC signal processing board corresponding to each pulse laser and single photon detector, as well as a control core and a data integration module.

[0050] In a multi-beam lidar system, 8 pulse lasers and 8 single-photon detectors are generally provided; therefore, the signal processing system of this embodiment is provided with 16 constant-ratio timing discrimination circuits and 16 multi-channel TDC signal processing boards; the pulse signal of each pulse laser or single-photon detector is processed by the corresponding constant-ratio timing discrimination circuit and then sent to the corresponding multi-channel TDC signal processing board for analysis.

[0051] In this embodiment, a multi-channel TDC (time-to-digital converter) signal processing board is based on an FPGA (field programmable gate array) architecture. A constant-ratio timing discrimination circuit implements discrimination processing of input pulse signals and converts the input pulse signals into short pulse signals that can be recognized by the FPGA. The FPGA-based multi-channel TDC signal processing board implements precise measurement of the time interval between two pulses. The control core and data integration module are used to realize radar system communication, system control, and data upload.

[0052] In this embodiment, a high-speed comparator and a level converter are used to form a Figure 2The constant ratio timing discrimination circuit with pre-discrimination shown in the figure adopts the leading edge timing discrimination principle in the pre-discrimination part. The output end of the digital-to-analog converter (DAC) is input to the positive end of the high-speed comparator U1 to set the discrimination threshold voltage in the circuit; the input signal is connected to the negative end of the high-speed comparator U1. If the input signal amplitude exceeds the threshold voltage, the positive end of the high-speed comparator U1 in the pre-discrimination circuit outputs a high level and the negative end outputs a low level, triggering the subsequent level converter U2 to output a high level, thereby enabling the constant ratio timing discrimination circuit. The constant ratio timing discrimination circuit is used to realize the discrimination conversion of the input signal. The circuit divides the input signal into two paths for parallel processing. One input signal is delayed by a fourth-order LC low-pass filter composed of inductor L1, capacitor C3, inductor L2 and capacitor C4 as a delay circuit. The other input signal is attenuated by a resistance divider ratio circuit composed of parallel capacitor C2 and resistor R3. The two delayed and attenuated signals are simultaneously input into the comparator U3 to generate a constant ratio discrimination signal, which is then input into the threshold adjustable level conversion circuit composed of level converter U4 and differential converter U5 to generate a short pulse signal that can be recognized by the FPGA.

[0053] In specific implementation, the RC delay circuit of the constant ratio timing discrimination circuit can replace the Wie delay chip or the LC delay circuit; the delay circuit composed of the delay chip is used in scenarios where high-precision signal delay and precise control of the trigger ratio are required; the RC delay circuit and the LC delay circuit work together through inductance, resistance and capacitance to achieve signal delay. Their frequency characteristics and delay performance are in the middle, which can filter out high-frequency noise and achieve precise signal delay.

[0054] The constant-fraction timing discrimination circuit receives pulse signals from lasers and single-photon detectors. The pulse signals have waveform characteristics such as standard-level digital pulses or analog signals exhibiting fast rising edges, slow falling edges, tailing, and asymmetric spikes. Essentially, the constant-fraction timing discrimination circuit uses a high-speed comparator and level shifter to implement a pre-discrimination signal discrimination circuit. It converts the pulse signals into short pulses that can be recognized by the FPGA through level comparison and conversion.

[0055] The short pulse signal converted by the constant ratio timing discrimination circuit is used as the input signal to be measured. Figure 3 The multi-channel TDC signal processing board shown in the figure is a permuted carry-coded delay chain time-to-digital converter (TDC) based on an FPGA-based "sum-carry alternating (SCSC)" architecture. It is used to measure time intervals of signals under test.

[0056] The multi-channel TDC signal processing board includes: a correction circuit, an input signal selector D1, a pulse stretching circuit, a delay chain signal sampling circuit, an encoding circuit, a synchronous coarse counting circuit, and a data integration generation circuit.

[0057] The pulse stretching circuit adjusts the start and end times of the input pulse passing through input signal selector D1, achieving pulse width stretching of the input pulse and generating a pulse stretching signal. The delay chain signal sampling circuit comprises a delay chain and a D-type flip-flop array. The pulse stretching signal is interpolated and delayed by the delay chain, and then a thermometer code is generated by the D-type flip-flop array. The delay chain length is slightly longer than one clock cycle of the pulse stretching signal. The encoding circuit encodes the thermometer code output by the D-type flip-flop array. The synchronous coarse counter triggers the data integration generation circuit, which integrates and outputs the encoded data output by the encoding circuit. The correction circuit uses code density calibration technology to calibrate the delay time of each delay unit in the delay chain.

[0058] The TDC board uses input signal selector D1 to switch input signals, realizing the switching between the signal to be tested and the random signal for calibration. When the system needs to measure the signal to be tested, the input signal selector D1 can input the signal to be tested into the TDC board for measurement; when code density histogram statistics and correction are required, the input signal selector D1 can promptly switch to the calibration random signal to realize TDC calibration.

[0059] After the signal to be measured (the short pulse signal output by the constant ratio timing discrimination circuit) is connected through the input signal selector D1, it enters the pulse stretching circuit to achieve precise adjustment of the start and end time of the input pulse, so that the pulse width of the input delay chain is stretched to be greater than a single clock cycle. Specifically, the pulse stretching circuit consists of a synchronous reset D flip-flop D2, a synchronous set D flip-flop D3 and an AND-OR gate as shown below. Figure 3 The logic shown is combined.

[0060] The pulse signal after pulse stretching circuit is input into the delay chain for picosecond delay processing, thus achieving fine interpolation of a clock cycle. The delay chain is composed of a carry lookahead chain implemented by high-speed carry logic Carry4 inside the FPGA and a D flip-flop array composed of synchronous D flip-flops. The high-speed carry logic Carry4 is configured as an "SCSC" output that alternates between Sum Out (S, sum output) and Carry Out (C, carry output). The specific connection method is as follows: Figure 3As shown in , the delay chain length is determined based on the TDC's coarse count clock period and the Carry4 unit delay in the FPGA chip, ensuring it is slightly longer than one clock period. A synchronous D-type flip-flop latches the propagation length of the stretched pulse signal in the delay chain on the rising edge of the TDC count clock, generating a fine count thermometer code.

[0061] The thermometer codes corresponding to the fine counts of C / S (Sum Out (S) and Carry Out (C)) are continuous "00001111" or "11110000" sequences, which cannot be directly used for binary calculations. In addition, since the delay chain structure does not meet the setup time requirements and the clock is skewed, the thermometer code may appear as follows during transmission. Figure 4 The bubble problem shown (red code such as "00101011") is that 01 appears multiple times at intervals. Therefore, this embodiment uses a C / S independent encoding circuit, which includes four encoders. The four encoders correspond one-to-one to the two sum outputs and two carry outputs of the carry lookahead chain (Carry4). The four encoders are denoted as S0 encoder, C0 encoder, S1 encoder, and C1 encoder.

[0062] The independent C / S encoding circuit decomposes the continuous encoding process into discrete encoding. The discrete encoding strategy allocates adjacent invalid logic units to two independent encoders. The continuous signal processed by each encoder spans a Carry4 module, which can disperse the interference caused by the bubbling phenomenon and avoid continuous bubbling phenomena occurring simultaneously in the same encoder and causing encoding errors. Thermometer code encoding is then implemented using a 7-bit to 3-bit permutation carry encoding strategy, dividing the 336-bit thermometer code with a total delay chain length into 48 encoders.

[0063] like Figure 5 The permutation carry encoding strategy for converting a 7-bit thermometer code to a 3-bit binary code is shown. A lookup table is used to store the C / S encoding logic, the number of valid bits in consecutive 7-bit thermometer codes is counted, and the corresponding number of binary codes is output. When all 7-bit thermometer codes are valid logic, the encoder generates a carry flag and then converts it into the corresponding binary code. To solve the bubbling problem, a permutation algorithm is used to rearrange the thermometer code with the bubbling problem to generate a thermometer code without the bubbling problem.

[0064] like Figure 6The rearrangement algorithm shown sets the highest and lowest bits of the thermometer code with the bubble problem to two counters, starting a bidirectional scan from there, traversing the entire delay chain. During this traversal, the encoder establishes a judgment criterion based on the logical characteristics of Sum Out and Carry Out: Sum is valid when the logic state is 0 and Carry is valid when the logic state of the thermometer code corresponding to the lower counter does not match the current valid logic state, the thermometer code corresponding to the higher counter is set to invalid logic, and the higher counter is decremented by 1. Conversely, if the logic state matches the valid logic state, the thermometer code register corresponding to the lower counter is set to valid logic, and the lower counter is incremented by 1. This bidirectional dynamic adjustment method continuously corrects the thermometer code logic, gradually correcting the thermometer code with the bubble problem to the correct one. After code correction, the carry encoding algorithm is used to convert all thermometer codes to binary code.

[0065] like Figure 7 The carry encoders shown are assigned to the corresponding encoders in the order of "SCSC" to encode and generate a 3-bit binary code and a 1-bit carry flag. Afterwards, the carry flags generated by each encoder are aggregated in the order of high and low bits to form a 12-bit carry thermometer code. A special decoding algorithm is used to decode the 12-bit carry thermometer code to generate a 4-bit total carry quantity. The value of the total carry quantity is exactly equal to the number of the rearranged anti-bubble carry encoder that does not generate a carry flag. The position of the "10" jump point and its corresponding binary code are obtained through the data selector. Finally, the value of the total carry quantity is multiplied by 7 and added to the binary code of the "10" jump point position to obtain the encoding value of the fine count.

[0066] The encoding strategy is further explained below in conjunction with specific embodiments.

[0067] Assuming the TDC coarse count clock period is set to 4ns, the Carry4 unit delay is set to 13.3ps, and the delay chain length is set to 336 bits, each sum output and carry output in the carry lookahead chain is allocated to 84 bits; each encoder in the encoding circuit is configured with 12 encoding units using a 7-bit encoding system to meet the 84-bit encoding requirement.

[0068] Each output (sum output or carry output) in each carry lookahead chain (Carry4) is converted into a 1-bit thermometer code through a D flip-flop;

[0069] Let the 1-bit thermometer code converted by the D flip-flop of the first sum output of each carry lookahead chain (Carry4) be denoted as S0 code bit, and let the S0 code bit of the first carry lookahead chain (Carry4) be denoted as S0_1;

[0070] Let the 1-bit thermometer code converted by the first carry output of each carry lookahead chain (Carry4) through the D flip-flop be denoted as code bit C0, and let the C0 code bit of the first carry lookahead chain (Carry4) be denoted as C0_1;

[0071] Let the 1-bit thermometer code converted by the D flip-flop from the second sum output of each carry lookahead chain (Carry4) be denoted as S1 code bit, and let the S1 code bit of the first carry lookahead chain (Carry4) be denoted as S1_1;

[0072] Let the 1-bit thermometer code converted by the second carry output of each carry lookahead chain (Carry4) through the D flip-flop be denoted as C1 code bit, and let the C1 code bit of the first carry lookahead chain (Carry4) be denoted as C1_1;

[0073] The S0 encoder is responsible for encoding code bits S0_1, S0_2, ..., S0_84. Each encoding unit is responsible for encoding 7 code bits, converting the 7-bit thermometer code into a 3-bit binary code. The decimal number corresponding to the 3-bit binary code is the number of valid bits of the 7-bit thermometer code. The 7-bit thermometer code is converted into a 3-bit binary code and a carry flag is added. When all 7-bit thermometer codes are valid codes, the carry flag is 1, otherwise it is 0. Thus, the S0 encoder obtains a 12-bit carry flag.

[0074] There is only one "10" transition point in the 12-bit carry flag code. Count the number of valid bits 1 in the 12-bit carry flag code to find the "10" transition point. Multiply the number of valid bits in the carry flag code by 7 and add the binary code of the "10" transition point position to obtain the detailed count code.

[0075] Assume that the 12-bit carry flag code is 111111000000, it can be seen that there are 6 valid bits 1, and the "10" jump point position is the 7th carry flag code. At this time, find the binary code of the coding unit corresponding to the 7th carry flag code, and add 6×7 to the decimal number of the binary code to obtain the detailed count code of the encoder, which is a decimal number.

[0076] Using the above method, the fine count codes of the C0 encoder, S1 encoder and C1 encoder are obtained respectively.

[0077] The fine count codes of the S0 encoder, the C0 encoder, the S1 encoder, and the C1 encoder are added together to obtain the coded data output by the coding circuit, which is the coding result of the sampling signal of the delay chain signal sampling circuit.

[0078] Due to the interaction of semiconductor manufacturing process level and dynamic environmental factors such as temperature and voltage, the actual delay of basic delay units at different positions in the carry lookahead chain (Carry4) in FPGA varies and exhibits random distribution characteristics, such as Figure 8 The non-uniform characteristics shown result in a large error in the delay time corresponding to the coding value of the fine count calculated using a fixed resolution, and a code density calibration technology needs to be used to calibrate the delay time of each delay unit.

[0079] The calibration principle of code density calibration technology is to input random pulses into the carry chain. When the random pulse propagates in the carry chain, it is affected by the inconsistent delay time of each delay unit. The number of pulses falling into each delay unit is positively correlated with the delay time. By counting the number of pulses appearing in each delay unit, the delay time of each delay unit can be estimated according to the probability distribution model.

[0080] The random pulse generation methods required during the correction process include: using an external signal generator to input a pulse signal that is asynchronous with the FPGA clock and is random relative to the FPGA's internal logic; or using an odd number of LUTs (Look-Up-Tables) within the FPGA to construct a ring oscillator to generate random pulses. This method allows for rapid input signal switching via system control commands. After the random pulses are generated, they are input into the TDC board to initiate the code density correction process. The correction formula and number of times are calculated using statistical formulas. In specific implementation, the number of corrections is set to 300,000.

[0081] The code density correction process is as follows Figure 9 As shown, when the correction signal is enabled, the ring oscillator outputs a random signal, which is directly input into the TDC board for time interval measurement. At this time, the code density histogram statistics module will use the fine count value generated by the encoder as the horizontal axis coordinate of the histogram, and control the correction times counter to accumulate 1. At the same time, the read-write controller is enabled, and the cumulative value of the horizontal axis corresponding to the fine count value is added by 1. The cumulative value is the frequency of occurrence of each fine count value, which is also the vertical coordinate of the code density histogram. When the number of corrections reaches the preset threshold, it indicates that the statistical process of the code density histogram is completed. The correction controller stores the statistical histogram data into the correction data memory. When the correction data needs to be output, the system will accurately calculate the actual fine count delay according to the preset formula, generate an accurate fine count, and trigger the synchronous coarse count circuit to generate a coarse count.

[0082] The synchronous coarse counting circuit inputs the original start and stop signals into independent D-type flip-flops respectively, latches the two signals through the rising edge of the system clock, and generates a stable coarse counting enable signal after synchronous latching. This signal controls the coarse counter to accumulate on the rising edge of the system clock, generates a coarse count (without generating counting errors), and triggers the data integration generation circuit to generate the final TDC data.

[0083] The data integration generation circuit integrates the coarse count of the synchronous coarse counter with the fine time generated by the measurement start and end signals. The circuit can choose to correct or not correct the fine count according to actual application requirements, and can adapt to the data output requirements in different measurement scenarios.

[0084] Of course, it will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, but also encompasses the same or similar structures that can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and it is intended that all variations that fall within the meaning and range of equivalents of the claims be encompassed within the present invention. Any reference signs in the claims should not be construed as limiting the claim to which they relate.

[0085] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0086] The technology, shape, and structure not described in detail in the present invention are all well-known technologies.

Claims

1. A multi-channel TDC signal processing board, characterized in that: Construct pulse stretching circuit, delay chain signal sampling circuit, encoding circuit, synchronous coarse counting circuit and data integration generation circuit based on FPGA; The pulse stretching circuit is used to adjust the start and end times of the input pulse to obtain a pulse stretching signal; The delay chain signal sampling circuit includes a delay chain and a D flip-flop array; the pulse stretching signal is interpolated and delayed by the delay chain and then the D flip-flop array generates a thermometer code; The encoding circuit is used to encode the thermometer code output by the D flip-flop array; The synchronous coarse counter is used to trigger the data integration generation circuit, so that the data integration generation circuit integrates and outputs the coded data output by the coding circuit.

2. The multi-channel TDC signal processing board according to claim 1, wherein: The delay chain is composed of multiple carry lookahead chains, each of which is configured as a 4-bit output structure with two sum outputs and two carry outputs alternately combined. The D flip-flop array includes D flip-flops corresponding one-to-one to the sum outputs and carry outputs in the delay chain, and each D flip-flop is used to convert the delay signal generated by the corresponding sum output or carry output into a thermometer code. The encoding circuit includes four encoders, and the four encoders correspond one-to-one to the two sum outputs and two carry outputs in the carry lookahead chain.

3. The multi-channel TDC signal processing board according to claim 2, wherein: The two sum outputs and the two carry outputs in the carry lookahead chain are numbered according to their ranking. The thermometer code generated by the output with the same number in different carry lookahead chains is encoded by the encoder corresponding to the number. The fine count codes output by each encoder are added together to obtain the encoded data output by the encoding circuit.

4. The multi-channel TDC signal processing board according to claim 3, wherein: The encoder's encoding strategy is as follows: the encoder converts the acquired thermometer codes into 3-bit binary codes in groups of seven, with a carry flag set for each group. When all seven thermometer codes in a group are valid, the carry flag is considered valid. All carry flags are arranged as reference codes, and the sum of seven multiples of the valid bits in the reference code and the decimal number of the 3-bit binary code corresponding to the "10" transition point is calculated as the detailed count code output by the encoder.

5. The multi-channel TDC signal processing board according to claim 4, characterized in that: The encoder includes multiple encoding units. Each encoding unit first permutes and encodes the 7-bit thermometer code, and then converts the permuted 7-bit thermometer code into a 3-bit binary code. The permutation encoding method of the 7-bit thermometer code includes the following steps: S1. Set counters i and j. The initial value of counter i is the highest bit value of the 7-bit thermometer code, and the initial value of counter j is the lowest bit value of the 7-bit thermometer code. The leftmost bit of the 7-bit thermometer code is the highest bit, and the rightmost bit is the lowest bit. S2, determine whether i is equal to j; If yes, proceed to step S4; If not, proceed to step S3; S3, judging whether the jth bit of the 7-bit thermometer code from low to high is a valid bit; If yes, update the counter j to j+1, and then return to step S2; If not, set the i-th bit in the 7-bit thermometer code from high to low to an invalid bit, then update i to i+1, and return to step S2; S4. Output the rearranged 7-bit thermometer code.

6. The multi-channel TDC signal processing board according to claim 2, wherein: The encoding rules for sum output are opposite to those for carry output.

7. The multi-channel TDC signal processing board according to claim 2, wherein: It also includes an input signal selector and a correction circuit; when the input signal selector inputs a random signal, the correction circuit uses a code density calibration technology to calibrate the delay time of each delay unit in the delay chain.

8. A multi-beam lidar signal processing system using the multi-channel TDC signal processing board according to any one of claims 1 to 6, characterized in that: It includes a constant ratio timing discrimination circuit and a multi-channel TDC signal processing board corresponding to each pulse laser and single photon detector, as well as a control core and data integration module; The constant-ratio timing discrimination circuit receives the transmitted pulse signal of the pulse laser and the echo pulse signal of the single-photon detector, discriminates and processes the two pulse signals, and converts them into short pulse signals that can be recognized by the FPGA; the multi-channel TDC signal processing board measures the time interval of the two pulse signals; the control core and data integration module are used for radar system communication, execution system control and data upload.

9. The multi-beam laser radar signal processing system according to claim 7, wherein: The constant ratio timing discrimination circuit includes: a threshold discrimination part, a constant ratio discrimination signal generation part and a signal conversion part; the threshold discrimination part is used to generate a signal to enable the constant ratio discrimination signal generation part based on the comparison result between the input signal and the threshold voltage; the input signal is attenuated and delayed respectively in the constant ratio discrimination signal generation part, and the attenuated signal and the delayed signal are compared to generate a constant ratio discrimination signal, which is converted into a short pulse signal that can be recognized by the FPGA by the signal conversion part.

10. The multi-beam laser radar signal processing system according to claim 8, wherein: The constant ratio discrimination signal generation part uses an RC circuit for signal attenuation and an LC filtering circuit for signal delay; the signal conversion part is composed of a level converter and a differential converter.

11. The multi-beam laser radar signal processing system according to claim 7, wherein: The system also includes a random signal generator for providing the random signal required for correction to the TDC board.

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