Storage and calculation integrated array based on self-rectification memristor and design method thereof

Abstract

The invention relates to the technical field of neural network hardware implementation, and particularly discloses a storage and calculation integrated array of a self-rectification memristor and a design method of the storage and calculation integrated array. Comprising word lines, bit lines and self-rectification memristors, the word lines and the bit lines are perpendicular to each other, the self-rectification memristors are located at the intersections of the word lines and the bit lines, the positive ends of the self-rectification memristors are connected with the word lines, the negative ends of the self-rectification memristors are connected with the bit lines, the storage and calculation integrated array adopts a binary calculation mode, and non-0, namely 1 data and weights are used for calculation; the self-rectification memristors in adjacent rows or adjacent columns form a weight bit, if the weight is one bit weight, the calculation unit comprises one weight bit, and if the weight is n bit weight, the calculation unit comprises n weight bits; 0 or 1 is represented by the resistance states of the memristors, each bit weight is represented by the states of the two memristors at the same time, and the resistance states of the two self-rectification memristors at the same weight bit are opposite. According to the invention, calculation errors caused by non-linear resistance value reading during analog calculation of the self-rectification memristor can be eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of neural network hardware implementation, and in particular to a storage and computing integrated array based on self-rectifying memristors and a design method thereof. Background Art

[0002] In recent years, with the widespread application of artificial intelligence (AI) at the edge (e.g., in smartphones, autonomous driving, and the Industrial Internet of Things), the "memory wall" problem in traditional computing architectures has become a core bottleneck restricting energy efficiency and real-time performance. In the von Neumann architecture, the physical separation of computing and memory units results in data transfer energy consuming 60%-80% of the total system power consumption, severely limiting the optimization of computing power and resource consumption. Computing-in-Memory (CIM) technology embeds computing logic directly into non-volatile memory arrays, leveraging the physical properties of memory cells to perform computations in situ, fundamentally eliminating data transfer overhead and being considered a revolutionary path to breaking through the "memory wall." Non-volatile memory devices include Flash, Resistive Random Access Memory (RRAM), and Ferroelectric Random Access Memory (FRAM). RRAM is considered one of the best implementations for CIM due to its low power consumption, fast switching speed, ease of large-scale integration, and compatibility with CMOS processes. RRAM, also known as a memristor, performs calculations through a cross-array structure, i.e., a structure in which word lines (WLs) and bit lines (BLs) cross vertically. The word lines are the top electrodes, and the bit lines are the bottom electrodes. There is other material at the intersection of the word lines and bit lines, forming a memristor. According to Ohm's Law and Kirchhoff's Laws, the input physical quantity (voltage or current) corresponds to the input matrix I, and the output physical quantity (current or voltage) corresponds to the output matrix O. The physical quantity (conductance or resistance) of the memristor array is the weight matrix W, so the calculation of O=W×I can be achieved. However, this crossbar array structure has a leakage current path (Sneak Path) or crosstalk problem (Crosstalk Problem). That is, when a voltage is applied across the two ends of the memristor, multiple currents passing through multiple adjacent memristors will be merged into the output path, causing errors in the read and calculation results, or devices on the leakage current path will be incorrectly erased, which will seriously affect the storage and calculation of the memristor array.There are two solutions to this problem. The most commonly used solution is to connect a memristor in series with a switching device, such as a transistor, diode, or selector. This solution can effectively suppress crosstalk, but in practical applications it will complicate the manufacturing process and increase area costs, affecting the actual performance of the integrated storage and computing chip. Therefore, memristor devices with self-rectification or self-selection characteristics have been proposed. This type of memristor can suppress crosstalk without being connected in series with other switching devices. Researching new and reliable self-rectifying memristors is crucial to solving the crosstalk problem.

[0003] The self-rectifying memristor has a normal resistance change under positive voltage, while the negative voltage shows the rectification property of the rectifier diode. The most reported mechanism of its rectification characteristic is the interface barrier effect, that is, when reverse voltage is applied, electrons need more energy to cross the barrier to achieve the rectification effect, such as Figure 1 As shown on the right, its electrical characteristics exhibit polarity and asymmetry, making them significantly affected by the stimulus applied to both ends of the device. Therefore, adjusting the memristor to a certain resistance state and applying different read voltages will produce different resistance readings. In computing models based on analog physical quantities, a large number of computational operations will accumulate errors caused by nonlinear resistance state readings, leading to errors in the final calculation results and reduced chip usability. Therefore, a new integrated storage and computing architecture design is needed to eliminate these errors. Summary of the Invention

[0004] In response to the defects of the prior art, the present invention provides a storage and computing integrated array based on self-rectifying memristors and a design method thereof, which are used to eliminate the calculation error problem caused by the nonlinear resistance readout of the self-rectifying memristors when performing analog calculations.

[0005] In order to solve the technical problem, the present invention adopts the following technical solution: a storage and computing integrated array based on self-rectifying memristors, comprising M rows of word lines, N columns of bit lines, and M*N self-rectifying memristors, where M and N are both positive integers, the word lines and the bit lines are perpendicular to each other, the self-rectifying memristors are located at the intersection of the word lines and the bit lines, the positive end of the self-rectifying memristors is connected to the word lines, and the negative end is connected to the bit lines, the input is applied from the word lines to the positive end of the self-rectifying memristors and is calculated with the weights stored in the self-rectifying memristors, and the accumulated results calculated by the self-rectifying memristors in this column are read out on the bit lines; The storage and computing integrated array adopts a binary calculation mode, using data that is either 0 or 1 and weights for calculation; In the integrated storage and computing array, self-rectifying memristors in adjacent rows or columns form a weight bit. If it is a one-bit weight, the computing unit includes one weight bit. If it is an n-bit weight, the computing unit includes n weight bits, where n is an integer greater than 1. The resistance state of the memristor is used to represent 0 or 1. Each bit weight is represented by the state of two memristors at the same time. The resistance states of the two self-rectifying memristors for the same weight bit are opposite.

[0006] Furthermore, the high resistance state of the memristor represents 0, and the low resistance state represents 1.

[0007] Furthermore, the memristors in odd-numbered rows are high bits of the weight bits, and the memristors in even-numbered rows are low bits of the weight bits. When the weight bits are 01, they represent 0, and when the weight bits are 10, they represent 1.

[0008] Furthermore, when the weight is updated, the two self-rectifying memristors with the same weight bit are simultaneously updated to opposite resistance states.

[0009] Furthermore, the input is current or voltage, and the output is voltage or current.

[0010] Furthermore, this array is used for DNN, CNN and BNN neural networks.

[0011] The present invention also discloses a design method for a storage-computation integrated array based on a self-rectifying memristor, comprising the following steps: S01. Select a self-rectifying memristor and perform electrical characteristic tests on it. The test contents include the device's on / off ratio, rectification ratio, set voltage, and reset voltage. S02. Design and train a binary neural network, which is obtained by binarizing the data and weights of an existing neural network; S03. Designing a memory-computation integrated array. As described above, the memory-computation integrated array maps the device characteristics of the self-rectifying memristor to the memory-computation integrated array, selects an array calculation method for current or voltage, selects the number of weight bits, and designs a calculation macro. S04. Write the trained weights into the integrated storage and computing array, perform erase and write operations on the self-rectifying memristor, and test the accuracy of application task recognition. If the requirements are not met, return to S02 to redesign and train the binary neural network. If the requirements are met, test the chip parameters and put it into application.

[0012] Furthermore, in step S03, the device characteristics of the self-rectifying memristor include erase voltage, maximum array expansion capability, data retention capability, device durability, read voltage used in calculation, and current or voltage values ​​of the device in high resistance state and low resistance state.

[0013] Furthermore, in step S02, the training data set includes an image data set, a video data set, and a text data set.

[0014] Furthermore, when training binary neural networks, application tasks include image recognition, video processing, and text generation.

[0015] Beneficial effects of the present invention: The present invention constructs a binary storage and computing integrated architecture design with two self-rectifying memristors as computing units, which significantly suppresses crosstalk current without the need for other switching devices in series. Compared with the traditional transistor-memristor series computing unit and array design, this method simplifies the process of neural network hardware implementation. While ensuring high precision and high efficiency in task completion, it greatly optimizes the area cost, energy efficiency and maximum computing throughput of the computing array. Combined with the smaller network scale of binary computing, it provides an efficient and low-power storage and computing integrated array design for edge computing AI devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the IV characteristic curve of the self-rectifying memristor; Figure 2 This is a schematic diagram of a memory-computation array based on self-rectifying memristors; Figure 3 This is a flow chart of the design method of a memory-computation integrated array based on self-rectifying memristors; Figure 4 It is a schematic diagram of the calculation principle of binary neural network; Figure 5 This is a schematic diagram of a self-rectifying memristor mapping binary computing unit; Figure 6 This is a schematic diagram of a self-rectifying memristor mapping multi-bit weight calculation unit; Figure 7 Schematic diagram of the binary neural network structure in Example 1; Figure 8 It is a schematic diagram of the design, mapping and calculation of the binary storage and computing architecture based on the self-rectifying memristor; Figure 9 This is an example of self-rectifying memristor device characteristics and chip performance test data. DETAILED DESCRIPTION

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0018] Example 1 This embodiment discloses a storage and computing integrated array based on self-rectifying memristors. Using memristors with self-rectifying characteristics as computing devices can significantly suppress array crosstalk. Self-rectifying memristors are generally composed of a top electrode, a resistive switching layer, a rectifying layer, and a bottom electrode. The resistive switching layer and the rectifying layer can be composed of one or more materials. The resistive switching layer realizes the resistive switching behavior of the device, that is, it is turned on or off after applying an excitation. The rectifying layer uses a potential barrier to block the generation of leakage current when reverse excitation is applied. Its IV characteristic curve is as follows: Figure 1 As shown on the right, due to the influence of the interface potential barrier, it exhibits asymmetric resistive switching behavior and nonlinear resistance values ​​under different read voltages.

[0019] like Figure 2 The storage-computing integrated array described in this embodiment includes M rows of word lines, N columns of bit lines, and M*N self-rectifying memristors, where M and N are both positive integers, the word lines and bit lines are perpendicular to each other, the self-rectifying memristor is located at the intersection of the word lines and the bit lines, the positive end of the self-rectifying memristor is connected to the word line, and the negative end is connected to the bit line. The input is applied from the word line to the positive end of the self-rectifying memristor and is calculated with the weight stored in the self-rectifying memristor, and the accumulated result calculated by the self-rectifying memristor in this column is read out on the bit line; the storage-computing integrated array adopts a binary calculation mode, using data that is neither 0 nor 1 to perform operations with the weight; and the multiplication and accumulation operation is equivalently implemented using the exclusive-OR logical operation. This effectively avoids the nonlinear resistance effect of the self-rectifying memristor. In this embodiment, the XOR operation is implemented in the memristor array. A popcount operation is required after the XOR operation. The two operations together are equivalent to a multiplication-accumulation operation. However, the popcount operation is implemented by a dedicated circuit and is classified as a peripheral circuit. This is a conventional technical means in this field and is not an innovation of this application. It will not be described in detail here.

[0020] In a storage-computing integrated array, self-rectifying memristors in adjacent rows or columns form a weight bit, and the resistance states of two self-rectifying memristors with the same weight bit are opposite. If the weight is one bit, the computing unit includes one weight bit, namely 2R; if the weight is n bits, the computing unit includes n weight bits, namely n*2R, where n is an integer greater than 1. The resistance state of the memristor is used to represent 0 or 1, with the high resistance state of the memristor representing 0 and the low resistance state representing 1. Compared to the high resistance state, a memristor in the low resistance state will have a larger current or voltage when the same voltage or current is applied, which matches the computing logic. Each bit weight is represented by the state of two memristors at the same time. In this embodiment, the memristors in odd rows are the high bit of the weight bit, and the memristors in even rows are the low bit of the weight bit. This is an artificial regulation. In other embodiments, the memristors in odd rows can also be the low bit of the weight bit, and the memristors in even rows can be the high bit of the weight bit. Then, a weight bit of 01 represents 0, and a weight bit of 10 represents 1. When the weight is updated, the two self-rectifying memristors for the same weight bit are simultaneously updated to opposite resistance states, ensuring that no intermediate states occur. Similarly, a multi-bit quantized weight is composed of n 2R computation units, each representing one weight bit.

[0021] In this embodiment, the physical quantity of the input data of the storage and computing integrated array is current or voltage, and correspondingly, the physical quantity of the output data is voltage or current, and it can be expanded to multi-core parallel computing.

[0022] In this embodiment, the array is used for DNN, CNN and BNN neural networks, and can be applied to tasks such as image recognition, video processing and text generation.

[0023] Example 2 This embodiment discloses a design scheme of a memory-computation integrated array based on self-rectifying memristors, such as Figure 3 As shown, the following steps are included: Step 1: First, select a self-rectifying memristor and perform electrical characteristic tests. These tests include the device's on / off ratio (i.e., the ratio of the current in the positive low-resistance state to the current in the positive high-resistance state when a read voltage is applied to the device), the device's rectification ratio (i.e., the ratio of the current in the positive low-resistance state to the current in the negative low-resistance state when a read voltage is applied to the device), and the set and reset voltages (i.e., the positive and negative voltages required to cause the memristor to switch resistance states).

[0024] Step 2: Use software to design and train a binary neural network. The selected binary neural network can be obtained by binarizing the data and weights of a traditional neural network. Binarization involves normalizing the neural network inputs and weights to the range [-1, 1], where data greater than 0 is set to 1 and data less than 0 is set to -1. This means that full-precision floating-point numbers are binarized to 1 bit. The training dataset can be image, video, or text datasets, and the application tasks can include image recognition, video processing, and text generation.

[0025] Step 3: Design a custom binary storage and computing architecture. Map device characteristics to the network and design, such as erase voltage, maximum array expansion capability, data retention capability, device durability, read voltage used for calculation, current or voltage values ​​in the high-resistance and low-resistance states of the device, etc. Then select the array calculation method for current or voltage, and select the number of weight bits, that is, the number of weight bits in each weight, to determine the number of computing units required for each weight. This will standardize the weight mapping attribution of the self-rectifying memristor and determine the number and scale of the computing sub-array. Finally, design the operation macro and select the peripheral circuit according to the application needs. The peripheral circuit of the operation macro is not the innovation of this application and will not be described in detail here.

[0026] Step 4: Divide the trained weights into set weight bits, write each weight bit into the array of the designed storage and computing architecture, perform erase and write operations on the self-rectifying memristor, and test the accuracy of application task recognition. If the requirements are not met, return to step 2 to redesign and train the binary neural network. If the requirements are met, test the chip parameters and put it into use.

[0027] Figure 4 The computational principle of a binary neural network is presented. The applied network architecture consists of two convolutional layers, two maximum pooling layers, and two fully connected layers, and the recognition dataset is a gesture recognition dataset.

[0028] Specifically, during the forward propagation process, the weight Q w With input Q A To scale respectively, get the scaling factor a and b ; Then substitute it into the XOR calculation, and perform the XOR operation on each bit of the weight and each bit of the input, that is, if they are the same as 0 or 1, they will get 1, and if they are different from 0 or 1, they will get 0. This corresponds to the binary calculation where the same as -1 or 1 multiplied together will get 1, and different from -1 or 1 multiplied together will get -1. Therefore, it is more friendly to hardware mapping. For the specific XOR operation, see Figure 5 , after converting to XNOR operation, it can realize the multiplication and accumulation operation similar to matrix-vector multiplication, and then through popcountThe bit counting operation calculates the number of 1s in the output, and then subtracts twice the data length to get the final calculation output result; then batch normalization is performed to converge the data distribution; finally, Sign The activation function performs binary activation.

[0029] Specifically, in the back propagation process, it is roughly the same as the traditional neural network, but when passing through the activation function layer in the reverse direction, since the binary Sign function is a discrete process and cannot be continuously derived, the straight-through estimator (STE) is used to perform reverse derivation to obtain continuous propagation. The specific formula is: , so that reverse continuous gradient derivative propagation can be achieved.

[0030] Figure 5 and Figure 6 Truth tables for mapping self-rectifying memristors into single-bit weights and multi-bit quantized weights in a binary computation network are presented. In a storage-computation integrated array, two self-rectifying memristors form a single weight bit. For a single-bit weight, the number of computational units is 2R. Similarly, for multi-bit quantized weights, the number of computational units is n*2R. The resistance state of the memristor represents 0 or 1, with a high resistance state representing 0 and a low resistance state representing 1. Each weight bit is represented by the states of two memristors simultaneously: odd-numbered rows of memristors represent the high bit of the weight bit, while even-numbered rows represent the low bit. A weight bit of 01 represents 0, while a weight bit of 10 represents 1. When the weight is updated, both memristors must be updated simultaneously to opposite resistance states to prevent any intermediate states. Similarly, a multi-bit quantized weight consists of n 2R computational units, each representing a single weight bit. Similarly, a low input voltage represents 0, while a high input voltage represents 1. The output current is 0 when it is in the high-resistance state and 1 when it is in the low-resistance state. This mapping method can also realize that adjacent columns of self-rectifying memristors are a computing unit, the input data can be current, and the output data can be voltage.

[0031] Figure 7 The neural network structure used in the embodiment is a VGG-8 network, which consists of three convolutional layers, two maximum pooling layers and two fully connected layers. The dataset used is the CIFAR-10 dataset, and the data is in the form of pictures with a size of 32×32×3 RGB color images.

[0032] Figure 8The present invention provides a schematic diagram of a binary storage and calculation integrated architecture design based on a self-rectifying memristor. This diagram only provides a schematic diagram of a single macro design and can be expanded to a parallel architecture with multiple data inputs and multiple cores for calculation. The image to be recognized is input to the word line of the self-rectifying memristor array in the form of a voltage vector after binary preprocessing. At the same time, a calculation unit consisting of two self-rectifying memristors performs an XOR operation on the data to obtain a calculation result. After being read and amplified by a readout circuit such as a sensing amplifier, an adder, and a register, an output feature map or output feature vector is obtained and input to the next level circuit. The design adopts a cross array structure to simplify the process of manufacturing and only uses two memristors to complete the calculation operation. The design shows two memristors in adjacent rows, and can also be expanded to adjacent columns of self-rectifying memristors as a calculation unit. The calculation mode can also be expanded to a current mode, that is, the input data is current and the output data is voltage. The corresponding peripheral circuit design needs to match it.

[0033] Figure 9 The device used and the chip parameters obtained are given. The design of this embodiment achieves a recognition accuracy of about 90%, with an energy efficiency of 96.5 TOPS / W and a calculation subarray area of ​​0.0095mm 2 The maximum computing throughput is 9.83969 TOPS. Compared with the traditional 2T2R computing unit storage and computing integrated frame design, it achieves optimization of energy efficiency, computing efficiency and area cost.

[0034] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A memory-computing integrated array based on self-rectifying memristors, characterized by: The invention comprises M rows of word lines, N columns of bit lines, and M*N self-rectifying memristors, where M and N are both positive integers. The word lines and bit lines are perpendicular to each other. The self-rectifying memristor is located at the intersection of the word lines and the bit lines. The positive end of the self-rectifying memristor is connected to the word line, and the negative end is connected to the bit line. The input is applied from the word line to the positive end of the self-rectifying memristor and is calculated with the weight stored in the self-rectifying memristor. The accumulated result of the calculation by the self-rectifying memristor in this column is read out on the bit line. The storage and computing integrated array adopts a binary calculation mode, using data that is either 0 or 1 and weights for calculation; In the integrated storage and computing array, self-rectifying memristors in adjacent rows or columns form a weight bit. If it is a one-bit weight, the computing unit includes one weight bit. If it is an n-bit weight, the computing unit includes n weight bits, where n is an integer greater than 1. The resistance state of the memristor is used to represent 0 or 1. Each bit weight is represented by the state of two memristors at the same time. The resistance states of the two self-rectifying memristors for the same weight bit are opposite.

2. The memory-computing integrated array based on self-rectifying memristors according to claim 1, characterized in that: The high resistance state of the memristor represents 0, and the low resistance state represents 1.

3. The integrated memory and computing array based on self-rectifying memristors according to claim 2, characterized in that: The memristors in odd-numbered rows are the high bits of the weight bits, and the memristors in even-numbered rows are the low bits of the weight bits. When the weight bit is 01, it represents 0, and when the weight bit is 10, it represents 1.

4. The integrated memory and computing array based on self-rectifying memristors according to claim 3, characterized in that: When the weight is updated, the two self-rectifying memristors with the same weight bit are updated to opposite resistance states at the same time.

5. The integrated memory and computing array based on self-rectifying memristors according to claim 1, characterized in that: The input is current or voltage, and the output is voltage or current.

6. The integrated memory and computing array based on self-rectifying memristors according to claim 1, characterized in that: This array is used for DNN, CNN and BNN neural networks.

7. A design method for a memory-computation integrated array based on self-rectifying memristors, characterized by: The following steps are involved: S01. Select a self-rectifying memristor and perform electrical characteristic tests on it. The test contents include the device's on / off ratio, rectification ratio, set voltage, and reset voltage. S02. Design and train a binary neural network, which is obtained by binarizing the data and weights of an existing neural network; S03. Designing a memory-computation integrated array, the memory-computation integrated array as described in any one of claims 1 to 6, mapping the device characteristics of the self-rectifying memristor to the memory-computation integrated array, selecting an array calculation method for current or voltage, selecting the number of weight bits, and designing a calculation macro; S04. Write the trained weights into the integrated storage and computing array, perform erase and write operations on the self-rectifying memristor, and test the accuracy of application task recognition. If the requirements are not met, return to S02 to redesign and train the binary neural network. If the requirements are met, test the chip parameters and put it into application.

8. The design method of the memory-computation integrated array based on self-rectifying memristors according to claim 7, characterized in that: In step S03 , the device characteristics of the self-rectifying memristor include erase voltage, maximum array expansion capability, data retention capability, device durability, read voltage used in calculation, and current or voltage values ​​of the device in high resistance state and low resistance state.

9. The design method of the memory-computation integrated array based on self-rectifying memristors according to claim 7, characterized in that: In step S02, the training data set includes an image data set, a video data set, and a text data set.

10. The design method of the memory-computation integrated array based on self-rectifying memristors according to claim 7, characterized in that: When training binary neural networks, application tasks include image recognition, video processing, and text generation.

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