Semiconductor package and method of manufacturing the same

Abstract

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a lower package including a first substrate, a first chip, and a first redistribution layer; and an upper package disposed on the lower package and including a second substrate, a second chip, and a plurality of internal connection terminals disposed on the second substrate and connected to the first redistribution layer. The first substrate comprises a concave part, the first chip is arranged in the concave part in a mode that the active surface of the first chip faces downwards, the heat conduction material fills the remaining space of the concave part, and the first redistribution layer is located on the first substrate, the heat conduction material and the first chip. The first chip includes a plurality of through silicon vias, the second chip is electrically connected to the plurality of through silicon vias via the plurality of internal connection terminals and the first redistribution layer, the first substrate further includes a signal via configured to communicate the semiconductor package with the outside, and a dummy via configured to dissipate heat of the first chip to the outside.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging, and in particular, to a semiconductor package including a package-on-package (also known as package-on-package, POP) structure and a method for manufacturing the same. Background Art

[0002] The POP structure is a common packaging structure for semiconductor packages. The current POP structure mainly consists of an upper package and a lower package, with the upper package stacked on the lower package. Figure 1 FIG. 2 shows a semiconductor package of a POP structure according to the related art. Figure 1 As shown, semiconductor package 1 includes a lower package 10 and an upper package 20. For example, lower package 10 may include an application processor package, and upper package 20 may include an LPDDR memory package. Connectors 11 may be formed around the periphery of lower package 10. For example, connectors 11 may be through molding vias (TMVs) or copper posts. Upper package 20 may include pins 21, such as solder. The arrangement of connectors 11 may be the same as the arrangement of pins 21 of upper package 20, to achieve signal connection between lower package 10 and upper package 20.

[0003] However, in the related art POP structure semiconductor package, the electrical path between the upper package 20 and the lower package 10 is long. In addition, due to the small effective connection area between the upper package 20 and the lower package 10, the number of pins 21 and connectors 11 is limited, making it difficult to improve the electrical performance of the semiconductor package. Summary of the Invention

[0004] To solve the above problems, embodiments of the present disclosure disclose a semiconductor package including a package-on-package structure and a method for manufacturing the semiconductor package, which can improve the electrical characteristics of the semiconductor package with a POP structure and / or enhance the heat dissipation of the chip.

[0005] According to one aspect of the present disclosure, a semiconductor package includes: a lower package including a first substrate, a first chip and a first redistribution layer; and an upper package disposed on the lower package and including a second substrate, a second chip and a plurality of internal connection terminals, the plurality of internal connection terminals being arranged on the second substrate and connected to the first redistribution layer, wherein the first substrate includes a recessed portion, the first chip is disposed in the recessed portion with its active surface facing downward, a thermally conductive material fills a remaining space in the recessed portion, the first redistribution layer is located on the first substrate, the thermally conductive material and the first chip, wherein the first chip includes a plurality of through-silicon vias, the second chip is electrically connected to the plurality of through-silicon vias via the plurality of internal connection terminals and the first redistribution layer, and wherein the first substrate further includes signal vias and dummy vias located around and below the recessed portion, the signal vias being configured to enable the semiconductor package to communicate with the outside, and the dummy vias being configured to dissipate heat of the first chip to the outside.

[0006] Furthermore, the first substrate of the lower package is a glass substrate, and the signal via and the dummy via are through-glass vias.

[0007] Furthermore, the recessed portion divides the first substrate into a first portion and a second portion, the first substrate has a first thickness, the first portion has a second thickness smaller than the first thickness, and the second portion surrounds the first portion and has the first thickness.

[0008] Furthermore, the dummy vias and a first portion of the signal vias are located in the first portion of the first substrate, and a second portion of the signal vias are located in the second portion of the first substrate.

[0009] Furthermore, the lower package further includes a second redistribution layer, and the first portion of signal vias passes through the first portion of the first substrate to electrically connect the first chip to the second redistribution layer.

[0010] Furthermore, the second portion of the signal vias passes through the second portion of the first substrate to electrically connect the first redistribution layer to the second redistribution layer.

[0011] Furthermore, the dummy via penetrates the first portion of the first substrate to connect the thermal conductive material to the second redistribution layer.

[0012] Further, the dummy vias are arranged between the first portion of signal vias and the second portion of signal vias, and do not overlap with the first chip in a vertical direction.

[0013] Furthermore, a height of the first portion of signal vias is smaller than a height of the second portion of signal vias and is equal to a height of the dummy vias.

[0014] Furthermore, a diameter of the first portion of signal vias is smaller than a diameter of the second portion of signal vias.

[0015] Furthermore, a diameter of the dummy via is larger than a diameter of the first portion of signal vias and smaller than a diameter of the second portion of signal vias.

[0016] Furthermore, the first chip is electrically connected to the first portion of signal vias via a plurality of bumps disposed on the active surface.

[0017] Further, an underfill material is disposed between the active surface of the first chip and the first portion of the first substrate and surrounds the plurality of bumps.

[0018] Further, the thermal conductive material contacts an outer surface of the first chip, an outer surface of the underfill material, an upper surface of the first portion of the first substrate, and an inner surface of the second portion of the first substrate.

[0019] Further, the first chip includes a passive surface opposite to the active surface, and an upper surface of the first substrate, an upper surface of the thermal conductive material, and an upper surface of the passive surface of the first chip are located at the same level.

[0020] Furthermore, the semiconductor package further includes: a plurality of external connection terminals disposed on a lower surface of the second redistribution layer.

[0021] Furthermore, the second chip is electrically connected to the second substrate via bonding wires in a manner that the active surface of the second chip faces upward.

[0022] Furthermore, the upper package further includes: a molding layer encapsulating the second chip and the bonding wires on the second substrate.

[0023] Further, the plurality of internal connection terminals are arranged between the second substrate and the first redistribution layer along a horizontal direction in a cross-sectional view.

[0024] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package includes: forming a recessed portion on a first substrate; forming signal vias and dummy vias around and below the recessed portion; arranging the first chip in the recessed portion with its active surface facing downward; filling the remaining space of the recessed portion with a thermally conductive material; forming a first redistribution layer on the first substrate, the thermally conductive material, and the first chip, thereby forming a lower package including the first substrate, the first chip, and the first redistribution layer; arranging an upper package on the lower package, the upper package including a second substrate, a second chip, and a plurality of internal connection terminals, the plurality of internal connection terminals being arranged on the second substrate and connected to the first redistribution layer, wherein the first chip includes a plurality of through-silicon vias, the second chip is electrically connected to the plurality of through-silicon vias via the plurality of internal connection terminals and the first redistribution layer, and wherein the signal vias are configured to enable the semiconductor package to communicate with the outside, and the dummy vias are configured to dissipate heat of the first chip to the outside.

[0025] Furthermore, the first substrate is a glass substrate, and the signal via and the dummy via are through-glass vias.

[0026] Furthermore, the recessed portion divides the first substrate into a first portion and a second portion, the first substrate has a first thickness, the first portion has a second thickness smaller than the first thickness, and the second portion surrounds the first portion and has the first thickness.

[0027] Further, the step of forming the signal via and the dummy via includes: forming a dummy via and a first portion of the signal vias among the signal vias passing through the first part of the first substrate, and a second portion of the signal vias among the signal vias passing through the second part of the first substrate, and filling the dummy via, the first portion of the signal via, and the second portion of the signal via with conductive material to form the dummy via, the first portion of the signal via, and the second portion of the signal via.

[0028] Further, the surface of the first substrate on which the recessed portion is formed is a first surface, and after forming the signal via and the dummy via and before setting the first chip, the method further includes: flipping the first substrate to be mounted on a first carrier, so that a second surface of the first substrate opposite to the first surface faces upward; forming a second redistribution layer on the second surface of the first substrate; removing the first carrier; and flipping the first substrate to be mounted on a second carrier, so that the first surface of the first substrate faces upward again to open the recessed portion.

[0029] Furthermore, the first chip includes a plurality of bumps arranged on the active surface, and the step of arranging the first chip further includes: electrically connecting the first chip to the first portion of signal vias via the plurality of bumps.

[0030] Furthermore, the step of providing the first chip further includes: providing an underfill material between the active surface of the first chip and the first portion of the first substrate and surrounding the plurality of bumps.

[0031] Furthermore, the first portion of signal vias passes through the first portion of the first substrate to electrically connect the first chip to the second redistribution layer.

[0032] Furthermore, the second portion of the signal vias passes through the second portion of the first substrate to electrically connect the first redistribution layer to the second redistribution layer.

[0033] Furthermore, the dummy via penetrates the first portion of the first substrate to connect the thermal conductive material to the second redistribution layer.

[0034] Further, the dummy vias are arranged between the first portion of signal vias and the second portion of signal vias, and do not overlap with the first chip in a vertical direction.

[0035] Furthermore, a height of the first portion of signal vias is smaller than a height of the second portion of signal vias and is equal to a height of the dummy vias.

[0036] Furthermore, a diameter of the first portion of signal vias is smaller than a diameter of the second portion of signal vias.

[0037] Furthermore, a diameter of the dummy via is larger than a diameter of the first portion of signal vias and smaller than a diameter of the second portion of signal vias.

[0038] Further, the thermal conductive material contacts an outer surface of the first chip, an outer surface of the underfill material, an upper surface of the first portion of the first substrate, and an inner surface of the second portion of the first substrate.

[0039] Further, the first chip includes a passive surface opposite to the active surface, and an upper surface of the first substrate, an upper surface of the thermal conductive material, and an upper surface of the passive surface of the first chip are located at the same level.

[0040] Further, the method further includes: removing the second carrier substrate; turning over the resulting structure so that the upper package is mounted downward on a third carrier and the second redistribution layer is upward; and forming a plurality of external connection terminals on the second redistribution layer.

[0041] Furthermore, the second chip is electrically connected to the second substrate via bonding wires in a manner that the active surface of the second chip faces upward.

[0042] Furthermore, the upper package further includes: a molding layer encapsulating the second chip and the bonding wires on the second substrate.

[0043] Further, the plurality of internal connection terminals are arranged between the second substrate and the first redistribution layer along a horizontal direction in a cross-sectional view. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] By describing the embodiments of the present disclosure in detail below in conjunction with the accompanying drawings, the above and other features and advantages of the present disclosure will become more apparent. In the accompanying drawings, the same reference numerals will always indicate the same elements.

[0045] Figure 1 is a schematic diagram of a semiconductor package according to the related art.

[0046] Figure 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0047] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0048] Figure 8A 、 Figure 8B as well as Figures 9 to 15 is a cross-sectional view of an intermediate stage in a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Various embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings in which some embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0050] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one element to other elements as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element previously described as "under" or "beneath" another element would then be oriented "above" the other element. Thus, the term "under" may encompass both the orientations of "above" and "under."

[0051] Figure 2 FIG is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. Figure 2 As shown, semiconductor package 10 includes a lower package 100 and an upper package 200. Lower package 100 includes a first substrate 110, a first chip 120, and a first redistribution layer 130. Upper package 200 is disposed on lower package 100 and includes a second substrate 210, a second chip 220, and a plurality of internal connection terminals 230. In an embodiment, lower package 100 may be a processor package (such as an application processor), and upper package 200 may be a memory package (such as an LPDDR memory). Semiconductor package 10 may have a package-on-package (POP) structure.

[0052] A plurality of internal connection terminals 230 are arranged on the second substrate 210 and connected to the first redistribution layer 130. In an embodiment, the plurality of internal connection terminals 230 may be solder balls or pins. In an embodiment, the plurality of internal connection terminals 230 may be arranged horizontally between the second substrate 210 and the first redistribution layer 130 in a cross-sectional view. For example, the plurality of internal connection terminals 230 may vertically overlap both the first chip 120 and the second chip 220. For example, the first chip 120 may be an application processor chip, and the second chip 220 may be an LPDDR memory chip.

[0053] The first substrate 110 includes a recessed portion R. In an embodiment, the recessed portion R divides the first substrate 110 into a first portion 110P1 and a second portion 110P2. The first substrate 110 has a first thickness T1. The first portion 110P1 has a second thickness T2 that is smaller than the first thickness T1. The second portion 110P2 surrounds or encloses the first portion 110P1 and has the first thickness T1.

[0054] The first chip 120 is disposed in the recess R with its active surface facing downward. The thermally conductive material T fills the remaining space of the recess R. In an embodiment, the thermally conductive material T may be an insulating material having good heat conduction properties.

[0055] A first redistribution layer 130 including wiring and vias is located on the first substrate 110, the thermally conductive material T, and the first chip 120. In an embodiment, the first chip 120 may include an inactive surface opposite to the active surface, and the upper surface of the first substrate 110, the upper surface of the thermally conductive material T, and the upper surface of the inactive surface of the first chip 120 may be located at the same level. In this case, the first redistribution layer 130 may cover the first substrate 110, the thermally conductive material T, and the first chip 120 and constitute the upper surface of the lower package 100.

[0056] The first chip 120 includes a plurality of through-silicon vias (TSVs). The second chip 220 is electrically connected to the plurality of through-silicon vias (TSVs) via a plurality of internal connection terminals 230 and a first redistribution layer 130 to transmit or receive signals with the first chip 120. The first substrate 110 also includes signal vias (TGVs) and dummy vias (DVs) located around and below the recessed portion (R). The signal vias (TGVs) are configured to enable communication between the semiconductor package 10 and the outside. The dummy vias (DVs) are configured to dissipate heat from the first chip 120 to the outside.

[0057] The semiconductor package 10 according to an embodiment of the present disclosure can have a reduced interconnection path between the lower package 100 and the upper package 200. Furthermore, due to the use of the first redistribution layer 130, the number of the plurality of internal connection terminals 230 can be increased compared to the POP structure of the related art, and the arrangement freedom of the plurality of internal connection terminals 230 can be more flexible, thereby improving the electrical characteristics of the entire semiconductor package 10.

[0058] In addition, the recess R can be filled with a thermally conductive material T, so that the thermally conductive material T can surround the first chip 120 to improve heat dissipation efficiency. At the same time, a dummy via DV is provided at the bottom of the recess R for heat dissipation, thereby improving heat dissipation of the lower package 100.

[0059] Below, still combined Figure 2 With reference to the illustrated embodiment, other preferred features and additional aspects of the semiconductor package 10 will be described.

[0060] In an embodiment, the first substrate 110 may be a glass substrate. In this case, the signal vias TGV and the dummy vias DV may be through-glass vias.

[0061] In an embodiment, a first portion of the signal vias TGV1 and the dummy vias DV among the signal vias TGV may be in the first portion 110P1 of the first substrate 110, and a second portion of the signal vias TGV2 among the signal vias TGV may be in the second portion 110P2 of the first substrate 110. For example, the first portion of the signal vias TGV1 may be located at the bottom of the recessed portion R, and the second portion of the signal vias TGV2 may be located around the recessed portion R. For example, the dummy vias DV may be arranged between the first portion of the signal vias TGV1 and the second portion of the signal vias TGV2 and may not overlap with the first chip 120 in the vertical direction.

[0062] In an embodiment, the height of the first portion of the signal vias TGV1 may be less than the height of the second portion of the signal vias TGV2 and equal to the height of the dummy vias DV. In this embodiment, the height of the second portion of the signal vias TGV2 may be equal to the first thickness T1 of the first substrate 110. The height of the second portion of the signal vias TGV2 and the height of the dummy vias DV may be equal to the second thickness T2 of the first portion 110P1 of the first substrate 110.

[0063] In an embodiment, the diameter of the first portion of signal vias TGV1 may be smaller than that of the second portion of signal vias TGV2 . In this embodiment, the diameter of the dummy vias DV may be larger than that of the first portion of signal vias TGV1 and smaller than that of the second portion of signal vias TGV2 .

[0064] In an embodiment, the first chip 120 may be electrically connected to the first portion of the signal vias TGV1 via a plurality of bumps B disposed on its active surface. In this embodiment, an underfill material U may also be disposed between the active surface of the first chip 120 and the first portion 110P1 of the first substrate 110 and surround the plurality of bumps B. In this case, the thermally conductive material T may contact the outer surface of the first chip 120, the outer surface of the underfill material U, the upper surface of the first portion 110P1 of the first substrate 110, and the inner surface of the second portion 110P2 of the first substrate 110.

[0065] In an embodiment, the lower package 100 may further include a second redistribution layer 140 , and the first partial signal vias TGV1 penetrate the first portion 110P1 of the first substrate 110 to electrically connect the first chip 120 to the second redistribution layer 140 .

[0066] In this embodiment, the second partial signal via TGV2 may penetrate the second portion 110P2 of the first substrate 110 to electrically connect the first redistribution layer 130 to the second redistribution layer 140 .

[0067] In this embodiment, the dummy via DV may penetrate the first portion 110P1 of the first substrate 110 to connect the thermal conductive material T to the second redistribution layer 140 .

[0068] In an embodiment, the semiconductor package 10 may further include a plurality of external connection terminals 150. The plurality of external connection terminals 150 may be disposed on the lower surface of the second redistribution layer 140. For example, the plurality of external connection terminals 150 may have a larger size and / or a larger pitch than the plurality of internal connection terminals 230.

[0069] In an embodiment, the second chip 220 may be electrically connected to the second substrate 210 via bonding wires W with the active surface facing upward.

[0070] In this embodiment, the upper package 200 may further include a mold layer 250. The mold layer 250 may encapsulate the second chip 220 and the bonding wires W on the second substrate 210. For example, the material of the mold layer 250 may be epoxy resin (EMC).

[0071] Next, we will Figure 2 Refer to it together Figures 3 to 15 A process for forming a semiconductor package according to the present disclosure is described in detail. Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 8A 、 Figure 8B as well as Figures 9 to 15 is a cross-sectional view of an intermediate stage in a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0072] Reference Figure 3 and Figure 8A , the method for manufacturing a semiconductor package includes: step S100, forming a recessed portion R on a first substrate 110. Figure 9 , step S200 : forming a signal via TGV and a dummy via DV around and below the recessed portion R.

[0073] In the examples, reference Figure 2 The recessed portion R can divide the first substrate 110 into a first portion 110P1 and a second portion 110P2. The first substrate 110 has a first thickness T1. The first portion 110P1 has a second thickness T2 that is smaller than the first thickness T1. The second portion 110P2 surrounds or encloses the first portion 110P1 and has the first thickness T1.

[0074] In an embodiment, the first substrate 110 may be a glass substrate, and the signal vias TGV and the dummy vias DV may be through-glass vias.

[0075] In the examples, reference Figure 4 、 Figure 8B and Figure 9 The step ( S200 ) of forming the signal via TGV and the dummy via DV may include forming a dummy via DH penetrating the first portion 110P1 of the first substrate 110, a first portion of the signal via TGH1 among the signal vias TGH, and a second portion of the signal via TGH2 among the signal vias TGH penetrating the second portion 110P2 of the first substrate 110, and filling the dummy via DH, the first portion of the signal via TGH1, and the second portion of the signal via TGH2 with a conductive material to form the dummy via DV, the first portion of the signal via TGV1 among the signal vias TGV, and the second portion of the signal via TGV2 among the signal vias TGV. For example, the conductive material may be a metal such as copper.

[0076] Reference Figure 3 and Figure 11 , step S300: placing the first chip 120 in the recessed portion R with its active surface facing downward.

[0077] In the examples, reference Figure 5 、 Figure 10 and Figure 11 The surface of the first substrate 110 where the recessed portion R is formed may be the first surface. After forming the signal via TGV and the dummy via DV and before providing the first chip 120, the method of manufacturing a semiconductor package may further include: S201, turning over the first substrate 110 to be mounted on the first carrier CA so that a second surface of the first substrate 110 opposite to the first surface faces upward; S202 , forming a second redistribution layer 140 on the second surface of the first substrate 110 ; S203, removing the first carrier CA; and S204 , the first substrate 110 is turned over to be mounted on the second carrier CB, so that the first surface of the first substrate 110 faces upward again to open the recessed portion R.

[0078] In the examples, reference Figure 6 and Figure 11The first chip 120 may include a plurality of bumps B disposed on the active surface. The step of disposing the first chip 120 may further include: S310, electrically connecting the first chip 120 to the first portion of the signal vias TGV1 via the plurality of bumps B; and S320, disposing an underfill material U between the active surface of the first chip 120 and the first portion 110P1 of the first substrate 110 and surrounding the plurality of bumps B.

[0079] Reference Figure 3 and Figure 12 , step S400: filling the remaining space of the recessed portion R with a thermally conductive material T.

[0080] In an embodiment, the first chip 120 may include an inactive surface opposite to the active surface, and the upper surface of the first substrate 110 , the upper surface of the thermally conductive material T, and the upper surface of the inactive surface of the first chip 120 may be located at the same level.

[0081] In an embodiment, the thermal conductive material T may contact the outer side surface of the first chip 120 , the outer side surface of the underfill material U, the upper surface of the first portion 110P1 of the first substrate 110 , and the inner side surface of the second portion 110P2 of the first substrate 110 .

[0082] Reference Figure 3 and Figure 13 Step S500: Forming a first redistribution layer 130 on the first substrate 110, the thermally conductive material T, and the first chip 120, thereby forming a lower package 100 including the first substrate 110, the first chip 120, and the first redistribution layer 130. For example, the first redistribution layer 130 may include wiring and vias. For example, the thickness of the first redistribution layer 130 may be less than the thickness of the second redistribution layer 140.

[0083] Reference Figure 3 and Figure 14 , step S600: setting the upper package 200 on the lower package 100. Return to reference Figure 2 , the upper package 200 includes a second substrate 210 , a second chip 220 , and a plurality of internal connection terminals 230 . The plurality of internal connection terminals 230 are arranged on the second substrate 210 and connected to the first redistribution layer 130 .

[0084] In an embodiment, the plurality of internal connection terminals 230 may be arranged between the second substrate 210 and the first redistribution layer 130 in a horizontal direction in a cross-sectional view.

[0085] Thus, the semiconductor package 10 according to the embodiment of the present disclosure may be manufactured.

[0086] Continue to refer to Figure 2The first chip 120 includes a plurality of through-silicon vias (TSVs), and the second chip 220 is electrically connected to the plurality of TSVs via a plurality of internal connection terminals 230 and a first redistribution layer 130. The signal vias (TGVs) are configured to allow the semiconductor package 10 to communicate with the outside. The dummy vias (DVs) are configured to dissipate heat from the first chip 120 to the outside.

[0087] In an embodiment, the first portion of the signal vias TGV1 penetrates the first portion 110P1 of the first substrate 110 to electrically connect the first chip 120 to the second redistribution layer 140 .

[0088] In this embodiment, the second partial signal via TGV2 may penetrate the second portion 110P2 of the first substrate 110 to electrically connect the first redistribution layer 130 to the second redistribution layer 140 .

[0089] In this embodiment, the dummy via DV may penetrate the first portion 110P1 of the first substrate 110 to connect the thermal conductive material T to the second redistribution layer 140 .

[0090] For example, refer to Figure 2 The dummy via DV is disposed between the first portion of the signal vias TGV1 and the second portion of the signal vias TGV2 and does not overlap with the first chip 120 in the vertical direction.

[0091] In an embodiment, the height of the first portion of the signal vias TGV1 may be less than the height of the second portion of the signal vias TGV2 and equal to the height of the dummy vias DV. In this embodiment, the height of the second portion of the signal vias TGV2 may be equal to the first thickness T1 of the first substrate 110. The height of the second portion of the signal vias TGV2 and the height of the dummy vias DV may be equal to the second thickness T2 of the first portion 110P1 of the first substrate 110.

[0092] In an embodiment, the diameter of the first portion of signal vias TGV1 may be smaller than that of the second portion of signal vias TGV2 . In this embodiment, the diameter of the dummy vias DV may be larger than that of the first portion of signal vias TGV1 and smaller than that of the second portion of signal vias TGV2 .

[0093] In the examples, reference Figure 3 、 Figure 7 and Figure 15 The method for manufacturing a semiconductor package may further include: step S700, removing the second carrier CB; step S800, flipping the resulting structure so that the upper package 200 is mounted downward on the third carrier CC and the second redistribution layer 140 is facing upward; and step S900, forming a plurality of external connection terminals 150 on the second redistribution layer 140.

[0094] In an embodiment, the second chip 220 may be electrically connected to the second substrate 210 via bonding wires W with the active surface facing upward.

[0095] In this embodiment, the upper package 200 may further include a mold layer 250. The mold layer 250 may encapsulate the second chip 220 and the bonding wires W on the second substrate 210. For example, the material of the mold layer 250 may be epoxy resin (EMC).

[0096] To summarize and review, the semiconductor package 10 according to an embodiment of the present disclosure includes a first redistribution layer 130 and a first chip 120 having through-silicon vias (TSVs). This structure allows the first chip 120 of the lower package 100 to be directly electrically connected to the upper package 200 in the vertical direction, thereby reducing the interconnection path between the lower package 100 and the upper package 200. Furthermore, due to the use of the first redistribution layer 130, the number of the plurality of internal connection terminals 230 can be increased compared to the related art POP structure, and the arrangement of the plurality of internal connection terminals 230 can be more flexible, thereby improving the electrical characteristics of the entire semiconductor package 10.

[0097] In addition, since the recess R can be filled with a thermally conductive material T, the thermally conductive material T can surround the first chip 120 to improve heat dissipation efficiency. At the same time, the bottom of the recess R is provided with a dummy via DV for heat dissipation, so the lower package 100 can have an improved heat dissipation effect.

[0098] While embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a lower package comprising a first substrate, a first chip and a first redistribution layer; as well as an upper package disposed on the lower package and comprising a second substrate, a second chip, and a plurality of internal connection terminals arranged on the second substrate and connected to the first redistribution layer, The first substrate includes a recessed portion, the first chip is disposed in the recessed portion with its active surface facing downward, a thermal conductive material fills the remaining space of the recessed portion, and the first redistribution layer is located on the first substrate, the thermal conductive material, and the first chip. wherein the first chip includes a plurality of through silicon vias, the second chip is electrically connected to the plurality of through silicon vias via the plurality of internal connection terminals and the first redistribution layer, and The first substrate further includes signal vias and dummy vias located around and below the recessed portion, the signal vias being configured to enable the semiconductor package to communicate with the outside, and the dummy vias being configured to dissipate heat of the first chip to the outside.

2. The semiconductor package according to claim 1, wherein The first substrate of the lower package is a glass substrate, and the signal via and the dummy via are through-glass vias.

3. The semiconductor package according to claim 2, wherein The recessed portion divides the first substrate into a first portion and a second portion, the first substrate having a first thickness, the first portion having a second thickness smaller than the first thickness, and the second portion surrounding the first portion and having the first thickness.

4. The semiconductor package according to claim 3, wherein A first portion of the dummy vias and the signal vias are located in the first portion of the first substrate, and a second portion of the signal vias are located in the second portion of the first substrate.

5. The semiconductor package according to claim 4, wherein The lower package further includes a second redistribution layer, and the first portion of signal vias penetrates the first portion of the first substrate to electrically connect the first chip to the second redistribution layer.

6. A method for manufacturing a semiconductor package, comprising: forming a recessed portion on the first substrate; forming a signal via hole and a dummy via hole around and below the recessed portion; placing the first chip in the recessed portion with its active surface facing downward; Filling the remaining space of the recessed portion with a thermally conductive material; forming the first redistribution layer on the first substrate, the thermal conductive material and the first chip, thereby forming a lower package including the first substrate, the first chip and the first redistribution layer; as well as An upper package is provided on the lower package, the upper package including a second substrate, a second chip, and a plurality of internal connection terminals arranged on the second substrate and connected to the first redistribution layer, wherein the first chip includes a plurality of through silicon vias, the second chip is electrically connected to the plurality of through silicon vias via the plurality of internal connection terminals and the first redistribution layer, and The signal via is configured to enable the semiconductor package to communicate with the outside, and the dummy via is configured to dissipate heat of the first chip to the outside.

7. The method according to claim 6, wherein The first substrate is a glass substrate, and the signal via and the dummy via are through-glass vias.

8. The method according to claim 7, wherein The recessed portion divides the first substrate into a first portion and a second portion, the first substrate having a first thickness, the first portion having a second thickness smaller than the first thickness, and the second portion surrounding the first portion and having the first thickness.

9. The method according to claim 8, wherein The steps of forming the signal via and the dummy via include: forming a dummy via hole and a first portion of the signal via holes penetrating the first portion of the first substrate and a second portion of the signal via holes penetrating the second portion of the first substrate, and Conductive material is filled in the dummy via, the first portion of the signal vias, and the second portion of the signal vias to form the dummy via, the first portion of the signal vias, and the second portion of the signal vias.

10. The method according to claim 6, wherein The surface of the first substrate where the recessed portion is formed is a first surface, and after forming the signal via and the dummy via and before providing the first chip, the method further includes: turning the first substrate over to be mounted on a first carrier so that a second surface of the first substrate opposite to the first surface faces upward; forming a second redistribution layer on the second surface of the first substrate; removing the first carrier; and The first substrate is turned over to be mounted on a second carrier so that the first surface of the first substrate faces upward again to open the recessed portion.

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