On-chip reconfigurable ferroelectric memory wake-up recovery system and method

Abstract

The invention relates to an on-chip reconfigurable ferroelectric memory wake-up recovery system and method, and the system comprises a ferroelectric memory array which is used for determining the current working state of a plurality of ferroelectric memory units in the ferroelectric memory array, and generating a corresponding wake-up instruction signal or a recovery instruction signal according to the current working state; and the reconfigurable wake-up / recovery circuit is used for receiving the wake-up instruction signal or the recovery instruction signal and generating a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up instruction signal or the recovery instruction signal so as to perform corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal. Therefore, the problems that the reliability of the existing hafnium oxide-based ferroelectric memory is seriously influenced by the ferroelectric fatigue effect, and the wake-up effect of the ferroelectric memory is easy to cause wrong reading and writing of data are solved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to an on-chip reconfigurable ferroelectric memory wake-up recovery system and method. Background Art

[0002] Hafnium oxide-based ferroelectric memory has the advantages of low power consumption, high speed, and good compatibility with complementary metal oxide semiconductor processes. It is one of the most promising solutions for the next generation of non-volatile memory technology.

[0003] However, the ferroelectric fatigue effect of hafnium oxide-based ferroelectric memory seriously affects its reliability. It is impossible to wake up the ferroelectric memory in the initial stage of operation, making it difficult to enter the normal operating state, which limits its practical application. In addition, the wake-up effect of ferroelectric memory may also cause erroneous reading and writing of data, which needs to be solved urgently. Summary of the Invention

[0004] The present application provides an on-chip reconfigurable ferroelectric memory wake-up recovery system and method to solve the problems that the ferroelectric fatigue effect of the existing hafnium oxide-based ferroelectric memory seriously affects its reliability, and the wake-up effect of the ferroelectric memory easily causes data reading and writing errors.

[0005] The first aspect of the present application provides an on-chip reconfigurable ferroelectric memory wake-up and recovery system, comprising: a ferroelectric memory array, for determining the current working state of multiple ferroelectric memory cells in the ferroelectric memory array, and generating a corresponding wake-up command signal or a recovery command signal according to the current working state; a reconfigurable wake-up / recovery circuit, for receiving the wake-up command signal or the recovery command signal, and generating a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up command signal or the recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

[0006] Optionally, in one embodiment of the present application, the ferroelectric memory array includes: a main data storage array, used to determine the fatigue state corresponding to each ferroelectric memory cell in the main data storage array, so as to output a corresponding recovery instruction signal according to the fatigue state; and a slave data backup array, used to back up the storage data of the ferroelectric memory cell to be restored in the main data storage array.

[0007] Optionally, in one embodiment of the present application, multiple master data storage modules and multiple slave data storage modules corresponding to the master data storage array and the slave data backup array are respectively constructed using the multiple ferroelectric memory cells, and the number of ferroelectric memory cells in each storage module of the multiple master data storage modules and the multiple slave data storage modules is the same.

[0008] Optionally, in one embodiment of the present application, when the current working state is a recovery state, the storage data of the main data storage module where the ferroelectric storage unit to be restored in the main data storage array is located is backed up to obtain corresponding backup data, and the backup data is transferred to the slave data storage module corresponding to the slave data backup array.

[0009] Optionally, in one embodiment of the present application, the reconfigurable wake-up / recovery circuit includes: an amplitude modulation circuit composed of a preset charge pump and a low-voltage difference linear regulator, which is used to perform amplitude modulation operation on the recovery instruction signal to generate a corresponding recovery instruction amplitude modulation signal, or to perform amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal with the same amplitude as the target read and write pulse of the preset main data storage array; a frequency modulation circuit composed of a preset voltage-controlled oscillator, which is used to perform frequency modulation processing on the recovery instruction amplitude modulation signal to generate a corresponding recovery pulse signal, and perform corresponding fatigue recovery operation on the main data storage module where the ferroelectric storage unit to be recovered is located according to the recovery pulse signal and the current working status of the ferroelectric storage unit to be recovered in the main data storage array, or to perform frequency modulation operation on the wake-up instruction amplitude modulation signal to obtain a wake-up pulse signal with the same frequency as the target read and write pulse of the main data storage array, and wake up the ferroelectric memory array through the wake-up pulse signal.

[0010] The second aspect of the present application provides an on-chip reconfigurable ferroelectric memory wake-up and recovery device, including the following steps: determining the current working status of multiple ferroelectric memory cells in a preset ferroelectric memory array, and generating a corresponding wake-up command signal or a recovery command signal based on the current working status; receiving the wake-up command signal or the recovery command signal, and generating a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up command signal or the recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

[0011] Optionally, in one embodiment of the present application, the receiving of the wake-up instruction signal or the recovery instruction signal, and generating a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up instruction signal or the recovery instruction signal, so as to perform a corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal, includes: performing an amplitude modulation operation on the recovery instruction signal to generate a corresponding recovery instruction amplitude modulation signal, or performing an amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal with the same target read and write pulse amplitude as the preset main data storage array; performing frequency modulation on the recovery instruction amplitude modulation signal to generate a corresponding recovery pulse signal, and performing a corresponding fatigue recovery operation on the main data storage module where the ferroelectric memory unit to be restored is located according to the recovery pulse signal and the current working status of the ferroelectric memory unit to be restored in the main data storage array, or performing a frequency modulation operation on the wake-up instruction amplitude modulation signal to obtain a wake-up pulse signal with the same target read and write pulse frequency as the main data storage array, and waking up the ferroelectric memory array through the wake-up pulse signal.

[0012] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored on the memory and runnable on the processor, wherein the processor executes the program to implement the on-chip reconfigurable ferroelectric memory wake-up recovery method as described in the above embodiment.

[0013] A fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above-mentioned on-chip reconfigurable ferroelectric memory wake-up recovery method.

[0014] A fifth aspect of the present application provides a computer program product, including a computer program, which is executed to implement the above-mentioned on-chip reconfigurable ferroelectric memory wake-up recovery method.

[0015] Therefore, the embodiments of the present application have the following beneficial effects:

[0016] The embodiments of the present application may include a ferroelectric memory array for determining the current working state of multiple ferroelectric memory cells in the ferroelectric memory array and generating a corresponding wake-up command signal or recovery command signal based on the current working state; a reconfigurable wake-up / recovery circuit for receiving the wake-up command signal or recovery command signal and generating a corresponding wake-up pulse signal or recovery pulse signal based on the wake-up command signal or recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or recovery pulse signal. The present application does not require the use of external equipment or systems and aims to provide an internal wake-up / recovery mechanism for ferroelectric memory, which is more efficient and convenient, thereby effectively ensuring the integrity and reliability of stored data. Thus, the problem of the ferroelectric fatigue effect of the existing hafnium oxide-based ferroelectric memory seriously affecting its reliability and the problem that the wake-up effect of the ferroelectric memory easily causes data reading and writing errors is solved.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is an example diagram of an on-chip reconfigurable ferroelectric memory wake-up recovery system according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a framework of an on-chip reconfigurable ferroelectric memory wake-up recovery system provided in one embodiment of the present application;

[0021] Figure 3 A diagram of an on-chip reconfigurable ferroelectric memory wake-up system provided in one embodiment of the present application;

[0022] Figure 4 A block diagram of an on-chip reconfigurable ferroelectric memory recovery system provided in one embodiment of the present application;

[0023] Figure 5 A schematic diagram of a ferroelectric memory array provided in accordance with an embodiment of the present application;

[0024] Figure 5 (a) is a schematic diagram of a ferroelectric memory array provided by one embodiment of the present application;

[0025] Figure 5 (b) is a schematic diagram of another ferroelectric memory array provided by one embodiment of the present application;

[0026] Figure 6 A schematic diagram of an amplitude modulation circuit and a frequency modulation circuit provided for one embodiment of the present application;

[0027] Figure 7 A schematic diagram of a wake-up pulse provided in one embodiment of the present application;

[0028] Figure 8 A schematic diagram of recovery pulses of different powers provided in one embodiment of the present application;

[0029] Figure 8 (a) is a schematic diagram of a low-power recovery pulse provided by an embodiment of the present application;

[0030] Figure 8 (b) is a schematic diagram of a medium-power recovery pulse provided by an embodiment of the present application;

[0031] Figure 8 (c) is a schematic diagram of a high-power recovery pulse provided by an embodiment of the present application;

[0032] Figure 9 A flowchart of a wake-up recovery method for an on-chip reconfigurable ferroelectric memory provided according to an embodiment of the present application;

[0033] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0034] Among them, 10 is an on-chip reconfigurable ferroelectric memory wake-up and recovery system; 100 is a ferroelectric memory array; 200 is a reconfigurable wake-up / recovery circuit; 1001 is a memory; 1002 is a processor; 1003 is a communication interface. DETAILED DESCRIPTION

[0035] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0036] The following describes, with reference to the accompanying drawings, an on-chip reconfigurable ferroelectric memory wake-up and recovery system and method according to an embodiment of the present application. To address the issues mentioned in the background art, the present application provides an on-chip reconfigurable ferroelectric memory wake-up and recovery method. The system includes a ferroelectric memory array for determining the current operating state of multiple ferroelectric memory cells in the ferroelectric memory array and generating a corresponding wake-up command signal or recovery command signal based on the current operating state; and a reconfigurable wake-up / recovery circuit for receiving the wake-up command signal or recovery command signal and, based on the wake-up command signal or recovery command signal, generating a corresponding wake-up pulse signal or recovery pulse signal to perform a corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or recovery pulse signal. This application, without the need for external equipment or systems, aims to provide an internal wake-up / recovery mechanism for ferroelectric memory, which is more efficient and convenient, thereby effectively ensuring the integrity and reliability of stored data. This solves the problem that the ferroelectric fatigue effect of existing hafnium oxide-based ferroelectric memories seriously affects their reliability, and the wake-up effect of ferroelectric memories easily causes data reading and writing errors.

[0037] Specifically, Figure 1 It is a block diagram of an on-chip reconfigurable ferroelectric memory wake-up recovery system according to an embodiment of the present application.

[0038] like Figure 1 As shown, the on-chip reconfigurable ferroelectric memory wake-up and recovery system 10 includes a ferroelectric memory array 100 and a reconfigurable wake-up / recovery circuit 200 .

[0039] The ferroelectric memory array 100 is used to determine the current working status of a plurality of ferroelectric memory cells in the ferroelectric memory array, and generate a corresponding wake-up instruction signal or a restore instruction signal according to the current working status.

[0040] The reconfigurable wake-up / recovery circuit 200 is used to receive a wake-up command signal or a recovery command signal, and generate a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up command signal or the recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

[0041] In the actual implementation process, Figure 2As shown, the on-chip reconfigurable ferroelectric memory wake-up / recovery system of the present application consists of two parts: a ferroelectric memory array and a reconfigurable wake-up / recovery circuit, wherein the ferroelectric memory array can output a wake-up instruction signal or a recovery instruction signal to the input end of the reconfigurable wake-up / recovery circuit according to the working state of the ferroelectric memory unit, and the reconfigurable wake-up / recovery circuit receives the wake-up instruction signal or the recovery instruction signal output by the ferroelectric memory array, and outputs a corresponding wake-up pulse signal or a recovery pulse signal to perform wake-up or fatigue recovery operations on the ferroelectric memory array.

[0042] Therefore, the on-chip reconfigurable ferroelectric memory wake-up / recovery strategy of the embodiment of the present application does not require the help of external devices or systems, and provides an internal wake-up / recovery mechanism for the ferroelectric memory, which is more efficient and convenient, thereby effectively ensuring the integrity and reliability of the data stored in the ferroelectric memory.

[0043] Optionally, in one embodiment of the present application, the ferroelectric memory array 100 includes: a primary data backup array and a secondary data storage array.

[0044] The main data storage array is used to determine the fatigue state corresponding to each ferroelectric memory cell in the main data storage array, so as to output a corresponding recovery instruction signal according to the fatigue state.

[0045] The slave data backup array is used to back up the storage data of the ferroelectric storage unit to be restored in the master data storage array.

[0046] In an embodiment of the present application, a ferroelectric memory array is composed of a main data storage array and a slave data backup array, and the output end of the ferroelectric memory array is connected to the input end of a reconfigurable wake-up / recovery circuit, and the output end of the reconfigurable wake-up / recovery circuit is connected to the input end of the ferroelectric memory array; when the ferroelectric memory array is in a wake-up state, the ferroelectric memory array outputs a wake-up instruction signal to the wake-up circuit; when the ferroelectric memory array is in a recovery state, the ferroelectric memory array outputs three different recovery instruction signals to the recovery circuit according to the different fatigue states of the ferroelectric memory cells in the main data storage array, and before fatigue recovery, the data of the storage cells to be recovered in the main data storage array needs to be transferred to the slave data backup array for data backup.

[0047] In the specific implementation process, in order to avoid the erroneous reading and writing of data caused by the wake-up effect of the ferroelectric memory, the embodiment of the present application can perform a wake-up operation on the ferroelectric memory in the initial stage of its operation so that it can enter a normal operating state. Figure 3 This is a block diagram of the on-chip reconfigurable ferroelectric memory wake-up system. In the wake-up state, the reconfigurable wake-up / recovery circuit functions as the wake-up circuit, and the ferroelectric memory array outputs a wake-up instruction signal ins_w to the wake-up circuit.

[0048] In addition, those skilled in the art should understand that when the main data storage array in the ferroelectric memory array is subjected to long-term repeated read and write cycle operations, the ferroelectric fatigue effect may cause performance degradation or data errors in the main data storage array. Therefore, it is necessary to fatigue recover the main data storage array in time before data errors occur to extend the working life of the ferroelectric memory. Figure 4 The block diagram of the on-chip reconfigurable ferroelectric memory recovery system is shown in FIG. Figure 4 As shown, in the recovery state, the reconfigurable wake-up / recovery circuit can function as a recovery circuit; the ferroelectric memory array outputs three different recovery instruction signals to the recovery circuit according to the three different fatigue states of the ferroelectric memory cells to be recovered in the main data storage array.

[0049] As an achievable method, in the embodiment of the present application, when the fatigue degree is less than 30%, the ferroelectric memory array outputs a recovery command signal ins_r_l; when the fatigue degree is greater than 30% and less than 60%, the ferroelectric memory array outputs a recovery command signal ins_r_m; when the fatigue degree is greater than 60% and less than 90%, the ferroelectric memory array outputs a recovery command signal ins_r_h; when the fatigue degree is greater than 90%, the fatigue state of the ferroelectric memory cell is considered to be unrecoverable, and the ferroelectric memory array no longer outputs a recovery command signal.

[0050] Therefore, the embodiment of the present application generates wake-up command signals and recovery command signals for different fatigue states (i.e., different working states) from the data backup array and the main data storage array in the ferroelectric memory array, thereby providing a reliable basis for the subsequent wake-up and recovery of the ferroelectric memory array.

[0051] Optionally, in one embodiment of the present application, multiple master data storage modules and multiple slave data storage modules corresponding to the master data storage array and the slave data backup array are respectively constructed using multiple ferroelectric memory cells, and the number of ferroelectric memory cells in each storage module in the multiple master data storage modules and the multiple slave data storage modules is the same.

[0052] In an embodiment of the present application, the main data storage array and the slave data backup array in the ferroelectric memory array are both composed of a plurality of ferroelectric memory cells, each ferroelectric memory cell includes a transistor and a ferroelectric capacitor or two transistors and two ferroelectric capacitors, and the ferroelectric capacitor is composed of a hafnium oxide-based ferroelectric material and a metal electrode.

[0053] also, Figure 5This is a detailed diagram of a ferroelectric memory array. It should be noted that the main data storage array in the ferroelectric memory array includes 32 modules with the same capacity (i.e., main data storage modules), and the slave data backup array includes 2 modules with the same capacity as a single module in the main data storage array (i.e., slave data storage modules). Figure 5 As shown in (a) and (b), the capacity refers to the number of storage units included.

[0054] Therefore, the on-chip reconfigurable ferroelectric memory wake-up / recovery strategy of the embodiment of the present application is applicable to ferroelectric memories of any storage capacity and can be expanded according to the actual capacity of the ferroelectric memory.

[0055] It can be understood that the determination of the number of main data storage array modules in the embodiment of the present application fully considers multiple factors such as storage capacity, data reading and writing, circuit layout and wake-up / recovery strategy. The determination of the number of data backup array modules fully considers the power consumption, area and simultaneous recovery of multiple modules of a large-scale main data storage array. The module division is reasonable, which effectively improves the reliability of the design and the working efficiency of the ferroelectric memory and has practical application value.

[0056] Optionally, in one embodiment of the present application, when the current working state is a recovery state, the storage data of the main data storage module where the ferroelectric storage unit to be restored in the main data storage array is located is backed up to obtain corresponding backup data, and the backup data is transferred to the slave data storage module corresponding to the slave data backup array.

[0057] During the actual execution process, taking the storage module a3 in the main data storage array as an example, when the current working state is the recovery state, the storage data of all storage units to be restored in the main data storage module where the ferroelectric storage unit to be restored in the main data storage array is located needs to be transferred in advance to the designated slave data storage module b1 of the slave data backup array.

[0058] After the data transfer is completed, the slave data storage module b1 that receives the storage unit data to be restored becomes the new master data storage module a3 to perform normal read and write operations. The master data storage module a3 after fatigue recovery becomes the new slave data storage module b1 to back up data for other storage modules in the main data storage array that have generated ferroelectric fatigue.

[0059] Therefore, the embodiments of the present application perform data backup through the main data storage array and the slave data backup array, thereby effectively avoiding data loss during the fatigue recovery process, while ensuring that normal read and write operations can be performed during the fatigue recovery process.

[0060] Optionally, in one embodiment of the present application, the reconfigurable wake-up / recovery circuit 200 includes: an amplitude modulation circuit and a frequency modulation circuit.

[0061] Among them, the amplitude modulation circuit composed of a preset charge pump and a low-voltage difference linear regulator is used to perform amplitude modulation operation on the recovery instruction signal to generate a corresponding recovery instruction amplitude modulation signal, or to perform amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal with the same target read and write pulse amplitude as the preset main data storage array.

[0062] A frequency modulation circuit composed of a preset voltage-controlled oscillator is used to frequency-modulate the recovery instruction amplitude modulation signal to generate a corresponding recovery pulse signal, and perform corresponding fatigue recovery operations on the main data storage module where the ferroelectric storage unit to be restored is located according to the recovery pulse signal and the current working status of the ferroelectric storage unit to be restored in the main data storage array, or to frequency-modulate the wake-up instruction amplitude modulation signal to obtain a wake-up pulse signal with the same target read and write pulse frequency as the main data storage array, and wake up the ferroelectric memory array through the wake-up pulse signal.

[0063] It should be noted that the reconfigurable wake-up / recovery circuit in the embodiment of the present application is composed of an amplitude modulation circuit and a frequency modulation circuit. The amplitude modulation circuit is composed of a charge pump and a low-dropout linear regulator to adjust the amplitude of the wake-up / recovery pulse signal. Figure 6 As shown in the figure, the frequency modulation circuit consists of a voltage-controlled oscillator, which is used to adjust the frequency of the wake-up / restore pulse signal. Therefore, for the four different wake-up / restore command signals ins_w, ins_r_l, ins_r_m, and ins_r_h output by the ferroelectric memory array, the reconfigurable wake-up / restore circuit can provide four corresponding wake-up / restore pulse signals pul_w, pul_r_l, pul_r_m, and pul_r_h with different amplitudes and frequencies through amplitude modulation and frequency modulation circuits. This can awaken the ferroelectric memory array or restore it to different powers under different fatigue states, improving the effectiveness of the wake-up or fatigue recovery operations.

[0064] Specifically, under the instruction of the wake-up instruction signal ins_w output by the ferroelectric memory array, the amplitude modulation circuit and the frequency modulation circuit in the wake-up circuit output the wake-up pulse signal pul_w to the ferroelectric memory array, which is the same as the normal read and write pulse amplitude and frequency (i.e., the target read and write pulse amplitude and the target read and write pulse frequency) of the main data storage array in the ferroelectric memory array, thereby waking up the ferroelectric memory array, including the main data storage array and the slave data backup array. After the ferroelectric memory array is awakened, normal read and write cycle operations can be performed on the main data storage array, such as Figure 7 shown.

[0065] Secondly, the amplitude modulation circuit and frequency modulation circuit in the recovery circuit output three recovery pulse signals with different amplitudes and frequencies to the ferroelectric memory array under the instruction of three different recovery command signals, and perform fatigue recovery of the main data storage array in the ferroelectric memory array under different fatigue states and different powers. Figure 8 Schematic diagram of recovery pulses with different powers; when the fatigue degree is less than 30%, a low-power recovery pulse is used for fatigue recovery, such as Figure 8 As shown in (a); the recovery circuit outputs a small-amplitude, low-frequency pulse signal pul_r_l; when the fatigue degree is greater than 30% and less than 60%, a medium-power recovery pulse is used for fatigue recovery, such as Figure 8 As shown in (b); the recovery circuit outputs a medium-amplitude medium-frequency pulse signal pul_r_m. When the fatigue degree is greater than 60% and less than 90%, a high-power recovery pulse is used for fatigue recovery. The recovery circuit outputs a large-amplitude high-frequency pulse signal pul_r_h, as shown in Figure 8 As shown in (c) in .

[0066] It should be noted that, in the recovery state, when the recovery circuit outputs a recovery pulse signal to perform fatigue recovery on the ferroelectric memory array, a module in the main data storage array where the memory cell generating ferroelectric fatigue is located is entirely recovered.

[0067] Therefore, the embodiment of the present application can provide wake-up / recovery pulse signals with different amplitudes and frequencies according to the amplitude modulation circuit and the frequency modulation circuit through the reconfigurable wake-up / recovery circuit, thereby improving the wake-up or fatigue recovery operation effect.

[0068] According to an embodiment of the present application, an on-chip reconfigurable ferroelectric memory wake-up and recovery device includes a ferroelectric memory array 100, which is used to determine the current operating state of multiple ferroelectric memory cells in the ferroelectric memory array and generate a corresponding wake-up command signal or recovery command signal based on the current operating state; and a reconfigurable wake-up / recovery circuit 200, which is used to receive the wake-up command signal or recovery command signal and, based on the wake-up command signal or recovery command signal, generate a corresponding wake-up pulse signal or recovery pulse signal to perform a corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or recovery pulse signal. This application does not require the use of external equipment or systems and aims to provide an internal wake-up / recovery mechanism for ferroelectric memory, which is more efficient and convenient, thereby effectively ensuring the integrity and reliability of stored data.

[0069] Next, an on-chip reconfigurable ferroelectric memory wake-up recovery method proposed in accordance with an embodiment of the present application will be described with reference to the accompanying drawings.

[0070] Figure 9 This is a flowchart of a wake-up and recovery method for an on-chip reconfigurable ferroelectric memory provided in an embodiment of the present application.

[0071] like Figure 9 As shown, the on-chip reconfigurable ferroelectric memory wake-up recovery method includes the following steps:

[0072] In step S901 , the current working states of a plurality of ferroelectric memory cells in a preset ferroelectric memory array are determined, and corresponding awakening instruction signals or restoring instruction signals are generated according to the current working states.

[0073] In step S902, a wake-up command signal or a recovery command signal is received, and based on the wake-up command signal or the recovery command signal, a corresponding wake-up pulse signal or a recovery pulse signal is generated to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

[0074] Optionally, in one embodiment of the present application, a wake-up instruction signal or a recovery instruction signal is received, and based on the wake-up instruction signal or the recovery instruction signal, a corresponding wake-up pulse signal or a recovery pulse signal is generated to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal, including: performing amplitude modulation operation on the recovery instruction signal to generate a corresponding recovery instruction amplitude modulation signal, or performing amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal with the same target read and write pulse amplitude as the preset main data storage array; performing frequency modulation on the recovery instruction amplitude modulation signal to generate a corresponding recovery pulse signal, and performing corresponding fatigue recovery operations on the main data storage module where the ferroelectric memory unit to be restored is located according to the recovery pulse signal and the current working status of the ferroelectric memory unit to be restored in the main data storage array, or performing frequency modulation operation on the wake-up instruction amplitude modulation signal to obtain a wake-up pulse signal with the same target read and write pulse frequency as the main data storage array, and waking up the ferroelectric memory array through the wake-up pulse signal.

[0075] It should be noted that the above explanation of the embodiment of the on-chip reconfigurable ferroelectric memory wake-up recovery system is also applicable to the on-chip reconfigurable ferroelectric memory wake-up recovery method of this embodiment, and will not be repeated here.

[0076] According to the on-chip reconfigurable ferroelectric memory wake-up and recovery method proposed in an embodiment of the present application, the current operating state of multiple ferroelectric memory cells in a preset ferroelectric memory array is determined, and a corresponding wake-up command signal or recovery command signal is generated based on the current operating state. The wake-up command signal or recovery command signal is received, and based on the wake-up command signal or recovery command signal, a corresponding wake-up pulse signal or recovery pulse signal is generated to perform a corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or recovery pulse signal. This application does not require the use of external equipment or systems and aims to provide an internal wake-up / recovery mechanism for ferroelectric memory, which is more efficient and convenient, thereby effectively ensuring the integrity and reliability of stored data.

[0077] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0078] A memory 1001 , a processor 1002 , and a computer program stored in the memory 1001 and executable on the processor 1002 .

[0079] When the processor 1002 executes the program, the on-chip reconfigurable ferroelectric memory wake-up recovery method provided in the above embodiment is implemented.

[0080] Furthermore, the electronic device further includes:

[0081] The communication interface 1003 is used for communication between the memory 1001 and the processor 1002 .

[0082] The memory 1001 is used to store computer programs that can be run on the processor 1002 .

[0083] The memory 1001 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0084] If the memory 1001, the processor 1002, and the communication interface 1003 are implemented independently, the communication interface 1003, the memory 1001, and the processor 1002 can be connected to each other via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0085] Optionally, in a specific implementation, if the memory 1001, the processor 1002 and the communication interface 1003 are integrated on a chip, the memory 1001, the processor 1002 and the communication interface 1003 can communicate with each other through an internal interface.

[0086] The processor 1002 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0087] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned on-chip reconfigurable ferroelectric memory wake-up recovery method.

[0088] An embodiment of the present application further provides a computer program product, including a computer program, which, when executed, is used to implement the above-mentioned on-chip reconfigurable ferroelectric memory wake-up recovery method.

[0089] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0091] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing a custom logical function or process step, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed in a different order than shown or discussed, including performing functions in a substantially simultaneous manner or in a reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0092] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or N wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing it in other suitable ways as necessary, and then storing it in a computer memory.

[0093] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0095] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0096] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. An on-chip reconfigurable ferroelectric memory wake-up recovery system, characterized in that: include: A ferroelectric memory array, configured to determine a current working state of a plurality of ferroelectric memory cells in the ferroelectric memory array, and generate a corresponding wake-up instruction signal or a restore instruction signal according to the current working state; A reconfigurable wake-up / recovery circuit is used to receive the wake-up command signal or the recovery command signal, and generate a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up command signal or the recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

2. The system according to claim 1, wherein: The ferroelectric memory array comprises: A main data storage array, configured to determine a fatigue state corresponding to each ferroelectric memory cell in the main data storage array, and output a corresponding recovery instruction signal according to the fatigue state; The slave data backup array is used to back up the storage data of the ferroelectric memory cells to be restored in the master data storage array.

3. The system according to claim 2, characterized in that The multiple ferroelectric memory cells are used to respectively construct multiple master data storage modules and multiple slave data storage modules corresponding to the master data storage array and the slave data backup array, and the number of ferroelectric memory cells in each storage module of the multiple master data storage modules and the multiple slave data storage modules is the same.

4. The system according to claim 3, characterized in that When the current working state is the recovery state, the storage data of the main data storage module where the ferroelectric storage unit to be restored in the main data storage array is located is backed up to obtain corresponding backup data, and the backup data is transferred to the slave data storage module corresponding to the slave data backup array.

5. The system according to claim 1, wherein: The reconfigurable wake-up / recovery circuit includes: an amplitude modulation circuit composed of a preset charge pump and a low-dropout linear regulator, configured to perform an amplitude modulation operation on the restore instruction signal to generate a corresponding restore instruction amplitude modulation signal, or to perform an amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal having the same amplitude as a preset target read / write pulse of the main data storage array; A frequency modulation circuit composed of a preset voltage-controlled oscillator is used to frequency-modulate the recovery instruction amplitude modulation signal to generate a corresponding recovery pulse signal, and perform corresponding fatigue recovery operations on the main data storage module where the ferroelectric storage unit to be restored is located according to the recovery pulse signal and the current working status of the ferroelectric storage unit to be restored in the main data storage array, or perform frequency modulation operations on the wake-up instruction amplitude modulation signal to obtain a wake-up pulse signal with the same target read and write pulse frequency as the main data storage array, and wake up the ferroelectric memory array through the wake-up pulse signal.

6. A wake-up recovery method for an on-chip reconfigurable ferroelectric memory, characterized in that: The following steps are involved: Determining the current working state of a plurality of ferroelectric memory cells in a preset ferroelectric memory array, and generating a corresponding wake-up instruction signal or a restore instruction signal according to the current working state; Receive the wake-up command signal or the recovery command signal, and generate a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up command signal or the recovery command signal, so as to perform corresponding wake-up or fatigue recovery operations on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal.

7. The method according to claim 6, characterized in that The receiving the wake-up instruction signal or the recovery instruction signal, and generating a corresponding wake-up pulse signal or a recovery pulse signal based on the wake-up instruction signal or the recovery instruction signal, so as to perform a corresponding wake-up or fatigue recovery operation on the ferroelectric memory array according to the wake-up pulse signal or the recovery pulse signal, includes: Performing an amplitude modulation operation on the recovery instruction signal to generate a corresponding recovery instruction amplitude modulation signal, or performing an amplitude modulation operation on the wake-up instruction signal to generate a wake-up instruction amplitude modulation signal having the same amplitude as a target read / write pulse of a preset main data storage array; The recovery instruction amplitude modulation signal is frequency modulated to generate a corresponding recovery pulse signal, and a corresponding fatigue recovery operation is performed on the main data storage module where the ferroelectric memory unit to be restored is located according to the recovery pulse signal and the current working status of the ferroelectric memory unit to be restored in the main data storage array. Alternatively, the wake-up instruction amplitude modulation signal is frequency modulated to obtain a wake-up pulse signal with the same target read and write pulse frequency as the main data storage array, and the ferroelectric memory array is awakened by the wake-up pulse signal.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the on-chip reconfigurable ferroelectric memory wake-up recovery method according to any one of claims 6 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the on-chip reconfigurable ferroelectric memory wake-up recovery method according to any one of claims 6 to 7.

10. A computer program product comprising a computer program, characterized in that The computer program is executed to implement the on-chip reconfigurable ferroelectric memory wake-up recovery method according to any one of claims 6 to 7.

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