Differential calculation circuit, memory device including same, and operation method of memory device

Abstract

The invention discloses a difference calculation circuit, a memory device including the same, and an operation method of the memory device. The memory device may include a format conversion circuit configured to generate a plurality of differential weights based on a plurality of weights provided from an external device; a memory cell array configured to store a first input element provided from an external device and the plurality of differential weights; a quantization circuit configured to generate a plurality of scaling coefficients based on the plurality of differential weights; and an input element scaling circuit configured to provide a plurality of output elements to an external device based on the plurality of scaling coefficients, the plurality of output elements corresponding to a product of the first input element and each of the plurality of weights.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0039288 filed on March 21, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various example embodiments relate to a semiconductor memory device, and more particularly, to a differential calculation circuit that performs a multiplication calculation and / or a memory device including the same. Background Art

[0003] With recent advances in artificial intelligence (AI) technology, the amount of computing required to operate AI models is rapidly increasing. However, the amount of computing power typically available on a device (such as a smartphone, personal computer, or similar) may not be sufficient to properly power an AI model. Therefore, various methods are being researched for operating AI models with less computational effort.

[0004] Typically, the operating speed of memory devices and processors is faster than the communication speed between the processor and memory devices. In this case, bottlenecks may occur in the operation of the memory devices and the computation of the processor due to the communication speed between the processor and the memory devices. Specifically, if an artificial intelligence model is operated by a processor and a memory device, the operation speed of the artificial intelligence model may be degraded by the bottleneck. Therefore, various technologies are being researched to resolve or improve the bottleneck caused by communication speed. For example, recently, research has been conducted on processing-in-memory (PIM) technology, in which a memory device performs some computational operations. Summary of the Invention

[0005] Various exemplary embodiments may solve or improve the above-mentioned technical problems. More specifically, various exemplary embodiments may provide a differential calculation circuit that performs calculation operations in a more simplified form, and / or a memory device including the differential calculation circuit.

[0006] According to some example embodiments, a memory device includes: a format conversion circuit configured to generate a plurality of differential weights based on a plurality of weights provided from an external device; a memory cell array configured to store a first input element provided from the external device and to store the plurality of differential weights; a quantization circuit configured to generate a plurality of scaling coefficients based on the plurality of differential weights; and an input element scaling circuit configured to provide a plurality of output elements to the external device based on the plurality of scaling coefficients, the plurality of output elements corresponding to a product of the first input element and each of the plurality of weights.

[0007] Alternatively or additionally, a differential calculation circuit according to various example embodiments, the differential calculation circuit being included in an internal processor of a memory device, includes: a quantization circuit configured to generate 0th to nth scaling factors based on 0th to nth differential weights, where n is an integer greater than or equal to 1; and an input element scaling circuit configured to generate 0th to nth output elements based on the 0th to nth scaling factors and an input element. The input element scaling circuit includes: a power scaling circuit configured to generate 0th to nth differentially scaled input elements by scaling the input elements based on the 0th to nth scaling factors; and an accumulation circuit configured to sequentially generate 0th to nth output elements by sequentially accumulating the 0th to nth differentially scaled input elements.

[0008] Optionally or additionally, an operating method of a memory device according to various example embodiments includes: storing a 0th differential weight and a first differential weight, the 0th differential weight and the first differential weight being generated based on the 0th weight and the first weight provided from an external device; receiving a first input element from the external device; receiving a weight multiplication command for the 0th differential weight, the first weight, and the first input element from the external device; in response to the weight multiplication command, generating a 0th output element and a first output element based on the 0th differentially scaled input element and the first differentially scaled input element, the 0th differentially scaled input element and the first differentially scaled input element corresponding to the product of the first input element and the 0th differential weight and the product of the first input element and the first differential weight, respectively, the 0th output element and the first output element corresponding to the product of the first input element and the 0th weight and the product of the first input element and the first weight, respectively; and outputting the 0th output element and the first output element to the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system according to various example embodiments.

[0010] Figure 2 is shown in more detail Figure 1 A block diagram of a memory device.

[0011] Figure 3 It shows Figure 2 Block diagram of the internal processor configuration.

[0012] Figure 4 is shown in more detail Figure 3 A diagram of the operation of the format conversion circuit.

[0013] Figure 5 is shown in more detail Figure 3A diagram showing the configuration and operation of a differential calculation circuit.

[0014] Figure 6 is a more detailed illustration of various exemplary embodiments. Figure 5 A diagram of the operation of the quantization circuit.

[0015] Figure 7 is a more detailed illustration of various exemplary embodiments. Figure 5 A diagram of the operation of the quantization circuit.

[0016] Figure 8 is a more detailed illustration of various exemplary embodiments. Figure 5 A diagram of the operation of the quantization circuit.

[0017] Figure 9 The embodiment according to the present invention is shown in more detail. Figure 5 A diagram of the operation of the quantization circuit.

[0018] Figure 10 is shown in more detail Figure 5 A diagram of the configuration and operation of the input element scaling circuit.

[0019] Figure 11 is shown in more detail Figure 10 Schematic diagram of the operation of the power scaling circuit.

[0020] Figure 12 is a flowchart illustrating an operating method of a memory device according to various example embodiments.

[0021] Figure 13 is shown in more detail Figure 12 Flowchart of operation S120.

[0022] Figure 14 is a flowchart illustrating an operating method of a memory device according to various example embodiments.

[0023] Figure 15 is shown in more detail Figure 14 Flowchart of operation S230.

[0024] Figure 16 is a diagram illustrating various exemplary embodiments Figure 2 A diagram of the configuration and operation of the control logic circuit. DETAILED DESCRIPTION

[0025] Hereinafter, various example embodiments will be described clearly and in detail to the extent that a person of ordinary skill in the technical field of the present disclosure can easily perform the present disclosure. Details (such as detailed configuration and detailed structure) are provided only to facilitate a comprehensive understanding of the example embodiments. Therefore, without departing from the technical spirit and scope of the present disclosure, a person of ordinary skill in the art can perform modifications of the example embodiments described herein. In addition, for the sake of clarity and brevity, descriptions of well-known functions and structures may be omitted. The configurations in the drawings or specific embodiments of the present disclosure may be connected to elements other than those shown in the drawings or described in the specific embodiments. The terms used herein are defined in consideration of the functions of the example embodiments and are not limited to specific functions. The definition of the terms can be determined based on the details described in the specific embodiments.

[0026] Elements described with reference to terms used in the detailed description (such as, driver, block, etc.) can be implemented in the form of software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. For example, hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, active components, or a combination thereof.

[0027] Figure 1 is a block diagram illustrating a memory system according to various example embodiments. Figure 1 , the memory system MS may include a host device 10 and a memory device 100. The memory device 100 may include an internal processor 111.

[0028] In one embodiment, the host device 10 may be or may include one or more of various types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0029] For a more concise description, it is assumed below that the memory device 100 is or includes a dynamic random access memory (DRAM) device, and that the host device 10 and the memory device 100 communicate with each other based on a low-power double data rate (LPDDR) interface. However, the scope of the inventive concept is not limited thereto. For example, alternatively or additionally, the host device 10 and the memory device 100 may communicate with each other based on a double data rate (DDR) interface.

[0030] The host device 10 may store data in the memory device 100 and / or may read data from the memory device 100. For example, the host device 10 may control the operation of the memory device 100 by sending a command CMD to the memory device 100.

[0031] The memory device 100 may perform various computing operations in response to the control of the host device 10. For example, the internal processor 111 may perform various computing operations based on the command CMD provided from the host device 10. Hereinafter, the operation of the memory device 100 based on the internal processor 111 will be exemplarily described.

[0032] The host device 10 may write a plurality of weights W into the memory device 100, each weight W being in the same format or in a differential format. For example, the host device 10 may send a plurality of weights W and a differential weight write command CMD_DWW to the memory device 100. In this case, the memory device 100 may convert the plurality of weights W into a differential format by using the internal processor 111. Thereafter, the memory device 100 may store the plurality of weights W converted into the differential format. Figures 3 to 5 The detailed method by which the internal processor 111 converts the plurality of weights W into a differential format is described in more detail.

[0033] The host device 10 may write the input element IE into the memory device 100. For example, the host device 10 may send an input element write command to the memory device 100. In this case, the memory device 100 may store the input element IE. In some embodiments, the memory device of the present disclosure may be applied to artificial intelligence (AI). In this case, the input element IE may include multimedia data or data associated with multimedia data (for example, the multimedia data may include at least one of voice data, image data, video data, and text data).

[0034] The host device 10 may request the memory device 100 to obtain a result obtained by multiplying the input element IE by each of the plurality of weights W. For example, the host device 10 may provide the memory device 100 with a weight multiplication command CMD_WM. In this case, based on the plurality of weights W converted into a differential format, the memory device 100 may calculate, via the internal processor 111, a plurality of output elements OE corresponding to the result obtained by multiplying the input element IE by each of the plurality of weights W. Thereafter, the memory device 100 may provide the calculated plurality of output elements OE to the host device 10.

[0035] In various example embodiments, if the internal processor 111 calculates a plurality of output elements OE based on a plurality of weights W in a differential format, the amount of calculation of the internal processor 111 may be reduced compared to a case where the internal processor 111 calculates the plurality of output elements OE by directly multiplying the input element IE by each of the plurality of weights W. For example, according to some example embodiments, the internal processor 111 may calculate a plurality of output elements OE corresponding to “a result obtained by multiplying the input element IE by each of the plurality of weights W” with a reduced or minimized amount of calculation. Figures 5 to 11 The detailed method by which the internal processor 111 calculates the plurality of output elements OE is described in more detail.

[0036] In various example embodiments, the case where the memory device 100 (eg, the internal processor 111 ) directly calculates the multiple output elements OE may reduce the amount of calculations processed by the host device 10 compared to the case where the host device 10 calculates the multiple output elements OE.

[0037] In various example embodiments, if the memory device 100 directly calculates the plurality of output elements OE, the host device 10 may immediately or more immediately receive the plurality of output elements OE from the memory device 100 without having to read the plurality of weights W and input elements IE. Therefore, according to some example embodiments, data exchange between the host device 10 and the memory device 100 may be reduced or minimized, so that a bottleneck phenomenon in the operation of the host device 10 and the memory device 100 caused by communication between the host device 10 and the memory device 100 may be reduced or minimized.

[0038] Because bottlenecks are reduced or minimized, data represented by multiple output elements (OEs) can be used as input or more useful during the execution of an application that utilizes an artificial intelligence (AI) model (e.g., an AI application that includes one or more of large language model (LLM) computations and / or diffusion-based computations). By reducing the bottleneck of providing multiple output elements (OEs) for such an application, the AI ​​application can run faster and / or with reduced power consumption.

[0039] In various example embodiments, the memory system MS may be included in one or more of various types of electronic devices (such as one or more of a smartphone, laptop computer, personal computer, tablet PC, etc.), and / or included in a system including one or more of the aforementioned electronic devices. In this case, the memory system MS may be used to operate an on-device artificial intelligence model driven by the electronic device. However, example embodiments are not limited thereto.

[0040] In various example embodiments, the host device 10 may provide the command CMD to the memory device 100 based on a plurality of command / address pins. However, the scope of the present disclosure is not limited to a specific manner in which the host device 10 provides the command CMD to the memory device 100.

[0041] Figure 2 is shown in more detail Figure 1 Block diagram of a memory device. Figure 2 , the memory device 100 may include a control logic circuit 110, a row decoder 120, a memory cell array 130, and an input / output (I / O) circuit 140. Each of the control logic circuit 110, the row decoder 120, the memory cell array 130, and the input / output circuit 140 may communicate with the others of the control logic circuit 110, the row decoder 120, the memory cell array 130, and the input / output circuit 140 as shown and / or in other manners thereof (such as, in a unidirectional manner and / or a bidirectional manner and / or a broadcast manner), although example embodiments are not limited thereto.

[0042] The control logic circuit 110 may receive a command CMD and may control the overall operation of the memory device 100 based on the command CMD. For example, the control logic circuit 110 may control the operation of the row decoder 120 and / or the input / output circuit 140.

[0043] The row decoder 120 may control the plurality of word lines WL in response to the control of the control logic circuit 110. For example, the row decoder 120 may activate some of the plurality of word lines WL in response to the control of the control logic circuit 110.

[0044] The memory cell array 130 may include a plurality of memory cells arranged in a matrix (eg, in row and column directions) and connected to a plurality of word lines WL extending in the row direction and a plurality of bit lines BL extending in the column direction.

[0045] The input / output circuit 140 may receive data from the host device 10 or may transmit data to the host device 10. For example, the input / output circuit 140 may receive a plurality of weights W and input elements IE from the host device 10 and may provide a plurality of output elements OE to the host device 10.

[0046] The input / output circuit 140 may be connected to the memory cell array 130 through a plurality of bit lines BL. The input / output circuit 140 may control the plurality of bit lines BL to read data stored in the memory cell array 130 or store data in the memory cell array 130.

[0047] When a write command for an input element IE is provided to the control logic circuit 110 , the control logic circuit 110 may control the row decoder 120 and the input / output circuit 140 to store the input element IE in the memory cell array 130 .

[0048] The control logic circuit 110 may include an internal processor 111. The internal processor 111 may perform various computing operations.

[0049] When the differential weight write command CMD_DWW is provided to the control logic circuit 110, the internal processor 111 may convert the plurality of weights W provided from the host device 10 into a differential format. Thereafter, the control logic circuit 110 may control the row decoder 120 and the input / output circuit 140 to store the plurality of weights W converted into the differential format (hereinafter referred to as a plurality of differential weights DW).

[0050] In various example embodiments, if the differential weight write command CMD_DWW is provided to the control logic circuit 110, the control logic circuit 110 may store a plurality of differential weights DW in the memory cell array 130. For example, the control logic circuit 110 may store a plurality of differential weights DW (instead of a plurality of weights W) in the memory cell array 130 in response to the differential weight write command CMD_DWW. However, example embodiments are not limited thereto, and the control logic circuit 110 may store both a plurality of weights W and a plurality of differential weights DW in the memory cell array 130 in response to the differential weight write command CMD_DWW.

[0051] When the weight multiplication command CMD_WM is provided to the control logic circuit 110, the control logic circuit 110 may control the row decoder 120 and the input / output circuit 140 to provide the input element IE and the plurality of differential weights DW stored in the memory cell array 130 to the internal processor 111. In this case, the internal processor 111 may calculate the plurality of output elements OE based on the input element IE and the plurality of differential weights DW. Thereafter, the control logic circuit 110 may provide the plurality of output elements OE to the host device 10 through the input / output circuit 140. Figures 5 to 11 The detailed method by which the internal processor 111 calculates the plurality of output elements OE is described in more detail.

[0052] Figure 3 It shows Figure 2 A block diagram of the internal processor configuration. Figures 1 to 3 , the internal processor 111 may include a format conversion circuit FCC and a differential calculation circuit DCC.

[0053] The format conversion circuit FCC may convert the plurality of weights W into a differential format. For example, the format conversion circuit FCC may generate a plurality of differential weights DW based on the plurality of weights W. Figure 4 The operation of the format conversion circuit FCC is described in more detail.

[0054] The differential calculation circuit DCC can generate a plurality of output elements OE based on a plurality of differential weights DW and an input element IE. In this case, the plurality of output elements OE may correspond to the product of the plurality of differential weights DW and the input element IE, respectively. Figures 5 to 11 The configuration and operation of the differential calculation circuit DCC are described in more detail.

[0055] The format conversion circuit FCC may communicate with the differential calculation circuit DCC in one or more of a unidirectional manner, a bidirectional manner, or a broadcast manner, and may send and / or receive data (such as serial data and / or parallel data in an analog format and / or a digital format), although example embodiments are not limited thereto.

[0056] Figure 4 is shown in more detail Figure 3 FIGURE 1 shows the operation of the format conversion circuit. Figures 1 to 4 , the format conversion circuit FCC may convert the plurality of weights W into a differential format. That is, the format conversion circuit FCC may generate a plurality of differential weights DW based on the plurality of weights W. For a more concise description, various exemplary embodiments in which the format conversion circuit FCC generates the 0th differential weights DW0 to the nth differential weights DWn based on the 0th weight W0 to the nth weight Wn will be representatively described below.

[0057] The format conversion circuit FCC may receive 0th weight W0 to nth weight Wn.

[0058] The format conversion circuit FCC may generate a 0th differential weight DW0 corresponding to the 0th weight W0 based on the 0th weight W0. For example, the 0th differential weight DW0 may be the same as the 0th weight W0.

[0059] The format conversion circuit FCC can generate first to nth differential weights DW1 to DWn based on the difference between each of the first to nth weights W1 to Wn and the weight preceding each of the first to nth weights. In other words, the format conversion circuit FCC can generate a kth differential weight DWk (where "k" is an integer equal to or greater than 1 and equal to or less than n) based on the difference between the kth weight Wk and the (k-1)th weight Wk-1. For example, the format conversion circuit FCC can generate a first differential weight DW1 based on the difference between the first weight W1 and the 0th weight W0, and can generate a second differential weight DW2 based on the difference between the second weight W2 and the first weight W1. In a similar manner, the format conversion circuit FCC can also generate third to nth differential weights DW3 to DWn.

[0060] In various example embodiments, the 0th weight W0 may be referred to as an initial weight. The initial weight may be a frontmost weight among a plurality of weights W provided to the memory device 100.

[0061] In various example embodiments, each of the 0th to nth weights W0 to Wn may have a floating-point data type. For example, each of the 0th to nth weights W0 to Wn may include a sign portion, an exponent portion, and a mantissa portion.

[0062] In various example embodiments, if each of the 0th weight W0 to the nth weight Wn has an FP32 data type, the code length of the exponent part of each of the 0th weight W0 to the nth weight Wn can be 8 bits, and the code length of the mantissa part of each of the 0th weight W0 to the nth weight Wn can be 23 bits.

[0063] In various example embodiments, if each of the 0th weight W0 to the nth weight Wn has an FP16 data type, the code length of the exponent part of each of the 0th weight W0 to the nth weight Wn can be 5 bits, and the code length of the mantissa part of each of the 0th weight W0 to the nth weight Wn can be 10 bits.

[0064] In various example embodiments, each of the 0th to nth differential weights DW0 to DWn may have a floating point data type. That is, each of the 0th to nth differential weights DW0 to DWn may have the same data type as each of the 0th to nth weights W0 to Wn.

[0065] In various example embodiments, the 0th differential weight DW0 may be referred to as an initial differential weight. The initial differential weight may be the same as the initial weight.

[0066] In various example embodiments, the control logic circuit 110 may store the 0th to nth differential weights DW0 to DWn calculated by the format conversion circuit FCC in the memory cell array 130 .

[0067] In various example embodiments, if a read request for the 0th to nth weights W0 to Wn is received from the host device 10, the control logic circuit 110 may calculate the 0th to nth weights W0 to Wn based on the 0th to nth differential weights DW0 to DWn via the internal processor 111. For example, the control logic circuit 110 may calculate the first weight W1 by summing the 0th weight W0 and the first differential weight DW1, and may calculate the second weight W2 by summing the first weight W1 and the second differential weight DW2. In this manner, the control logic circuit 110 may sequentially calculate the 0th to nth weights W0 to Wn based on the 0th to nth differential weights DW0 to DWn, and provide the calculated weights to the host device 10. However, example embodiments are not limited thereto.

[0068] Figure 5 is shown in more detail Figure 3 Schematic diagram of the configuration and operation of the differential calculation circuit. Figures 1 to 5 In some example embodiments, the differential calculation circuit DCC may include a quantization circuit DCCa and an input element scaling circuit DCCb.

[0069] The quantization circuit DCCa may receive a plurality of differential weights DW. For example, the quantization circuit DCCa may receive 0th to nth differential weights DW0 to DWn stored in the memory cell array 130.

[0070] The quantization circuit DCCa can generate a plurality of scaling coefficients SC based on a plurality of differential weights DW. For example, the quantization circuit DCCa can generate the 0th scaling coefficient SC0 to the nth scaling coefficient SCn by quantizing the 0th differential weight DW0 to the nth differential weight DWn respectively. Figures 6 to 9 A more detailed operation of the quantization circuit DCCa is described in more detail.

[0071] In various exemplary embodiments, the 0th to nth scaling coefficients SC0 to SCn may have integer data types. In this case, the code length of each of the 0th to nth scaling coefficients SC0 to SCn may be smaller than the code length of each of the 0th to nth differential weights DW0 to DWn.

[0072] In various example embodiments, a scaling coefficient generated based on the initial differential weight (eg, a 0th scaling coefficient SC0) may be referred to as an initial scaling coefficient.

[0073] In some example embodiments, the quantization circuit DCCa may not quantize the initial differential weights among the plurality of differential weights DW. For example, the quantization circuit DCCa may generate the first to nth scaling coefficients SC1 to SCn by quantizing the first to nth differential weights DW1 to DWn, respectively, and may not quantize the 0th differential weight DW0. In this case, the initial differential weight may be equal to the initial scaling coefficient. Figure 9 Various example embodiments in which the quantization circuit DCCa does not quantize the initial differential weights are described in more detail.

[0074] The input element scaling circuit DCCb may receive the input element IE. For example, the input element scaling circuit DCCb may receive the input element IE stored in the memory cell array 130.

[0075] The input element scaling circuit DCCb may receive a plurality of scaling coefficients SC. For example, the input element scaling circuit DCCb may receive 0th scaling coefficient SC0 to nth scaling coefficient SCn from the quantization circuit DCCa.

[0076] The input element scaling circuit DCCb may generate a plurality of output elements OE based on the input element IE and a plurality of scaling coefficients SC. For example, the input element scaling circuit DCCb may generate the 0th output element OE0 to the nth output element OEn based on the input element IE and the 0th scaling coefficient SC0 to the nth scaling coefficient SCn. In this case, the magnitudes (or amplitudes (such as absolute values)) of the 0th output element OE0 to the nth output element OEn may respectively correspond to “values ​​obtained by multiplying the 0th weight W0 to the nth weight Wn by the input element IE”. This will be referred to below. Figure 10 The configuration and operation of the input element scaling circuit DCCb are described in more detail.

[0077] In various example embodiments, the differential calculation circuit DCC may further include a buffer circuit (not shown) configured to temporarily store the plurality of output elements OE and commonly provide the plurality of output elements OE to the memory cell array 130. However, example embodiments are not limited thereto.

[0078] Figure 6 is a more detailed illustration of various exemplary embodiments. Figure 5 Schematic diagram of the operation of the quantization circuit. Figures 1 to 6 The quantization circuit DCCa may generate a plurality of scaling coefficients SC by quantizing a plurality of differential weights DW into a power of 2. For a more concise description, various exemplary embodiments in which the quantization circuit DCCa generates a 0th scaling coefficient SC0 to an nth scaling coefficient SCn based on a 0th differential weight DW0 to an nth differential weight DWn will be representatively described below.

[0079] The quantization circuit DCCa may receive the 0th to nth differential weights DW0 to DWn. The quantization circuit DCCa may convert the data type of each of the 0th to nth differential weights DW0 to DWn into an integer data type to identify the magnitude (or size, or absolute value) of each of the 0th to nth differential weights DW0 to DWn.

[0080] The quantization circuit DCCa may generate the 0th to nth scaling coefficients SC0 to SCn based on the magnitude of each of the 0th to nth differential weights DW0 to DWn. For example, the quantization circuit DCCa may generate the 0th to nth scaling coefficients SC0 to SCn by quantizing the magnitudes of the 0th to nth differential weights DW0 to DWn, respectively. For example, the quantization circuit DCCa may generate the 0th to nth scaling coefficients SC0 to SCn by quantizing the magnitudes of the 0th to nth differential weights DW0 to DWn, respectively. The magnitude of each of the 0th to nth differential weights DW0 to DWn is quantized in the form of (where N is an integer).

[0081] In some examples, the quantization circuit DCCa may approximate each of the 0th to nth differential weights DW0 to DWn in the form of an integer power of 2, with a magnitude similar to that of each of the 0th to nth differential weights DW0 to DWn. In this case, the quantization circuit DCCa may determine an exponent of each of the 0th to nth differential weights DW0 to DWn approximated in the form of an integer power of 2 (i.e., N) as each of the 0th to nth scaling coefficients SC0 to SCn, respectively.

[0082] For a more detailed example, the quantization circuit DCCa can approximate the magnitude of the 0th differential weight DW0 as In this case, the quantization circuit DCCa may determine the 0th scaling coefficient SC0 as Similarly, the quantization circuit DCCa can approximate the amplitude of the first differential weight DW1 as In this case, the quantization circuit DCCa may determine the first scaling coefficient SC1 as In this way, the quantization circuit DCCa can determine the 0th to nth scaling coefficients SC0 to SCn.

[0083] In some cases, reference Figure 6 , the quantization circuit DCCa may generate the 0th to nth scaling coefficients SC0 to SCn by quantizing all the 0th to nth differential weights DW0 to DWn. In this case, the data types of the 0th to nth scaling coefficients SC0 to SCn may be the same as each other. However, example embodiments are not limited thereto.

[0084] In various example embodiments, the quantization circuit DCCa may approximate the magnitude of each of the 0th to nth differential weights DW0 to DWn in the form of integer powers of 2 based on various types of approximate calculation algorithms (such as rounding up, rounding down, rounding to the nearest power of 2, etc.). Figure 7 and Figure 8 A method in which the quantization circuit DCCa determines the 0th to nth scaling coefficients SC0 to SCn based on various types of approximate calculation algorithms is described in more detail.

[0085] Figure 7 is a more detailed illustration of various exemplary embodiments. Figure 5 A diagram of the operation of the quantization circuit. Figure 7 The horizontal axis of may represent the index of the differential weight DW and the index of the scaling coefficient SC, and Figure 7 The vertical axis of may represent the magnitude of the differential weight DW and the magnitude of the scaling factor SC. Figures 1 to 7 , representatively describes an operation in which the quantization circuit DCCa converts the 0th differential weight DW0 to the nth differential weight DWn into the 0th scaling coefficient SC0 to the nth scaling coefficient SCn, respectively, based on the “algorithm of rounding to the nearest power of 2”.

[0086] The quantization circuit DCCa may identify an integer power of 2 having a magnitude most similar to the magnitude of each of the 0th differential weight DW0 to the nth differential weight DWn. For example, the quantization circuit DCCa may identify an integer power of 2 having a magnitude most similar to the 0th differential weight DW0 as In this case, the quantization circuit DCCa may determine the 0th scaling coefficient SC0 corresponding to the 0th differential weight DW0 as "p+2", where "p+2" is Similarly, the quantization circuit DCCa may identify the integer power of 2 having the most similar magnitude to the first differential weight DW1 as ; The integer power of 2 that can be identified to have the most similar magnitude to the second differential weight DW2 is ; and the integer power of 2 that can be identified to have the most similar magnitude to the nth differential weight DWn is In this case, the quantization circuit DCCa may determine the first scaling coefficient SC1 as “p−2”, may determine the second scaling coefficient SC2 as “p”, and may determine the nth scaling coefficient SCn as “p−1”.

[0087] Figure 8 is a more detailed illustration of various exemplary embodiments. Figure 5 A diagram of the operation of the quantization circuit. Figure 8 The horizontal axis of may represent the index of the differential weight DW and the index of the scaling coefficient SC, and Figure 8 The vertical axis of may represent the magnitude of the differential weight DW and the magnitude of the scaling factor SC. Figures 1 to 6 and Figure 8 , representatively describes an operation in which the quantization circuit DCCa converts the 0th differential weight DW0 to the nth differential weight DWn into the 0th scaling coefficient SC0 to the nth scaling coefficient SCn, respectively, based on the “round-down approximate calculation algorithm”.

[0088] The quantization circuit DCCa can identify the largest integer power of 2 among the integer powers of 2 smaller than each of the 0th differential weight DW0 to the nth differential weight DWn. For example, the quantization circuit DCCa can identify the largest integer power of 2 smaller than the 0th differential weight DW0 is In this case, the quantization circuit DCCa may determine the 0th scaling coefficient SC0 corresponding to the 0th differential weight DW0 as "p+1", where "p+1" is Similarly, the quantization circuit DCCa can recognize that the largest integer power of 2 smaller than the first differential weight DW1 is The largest integer power of 2 that can be identified to be smaller than the second differential weight DW2 is ; and the largest integer power of 2 that can be identified to be smaller than the nth differential weight DWn is In this case, the quantization circuit DCCa may determine the first scaling coefficient SC1 as “p-2”, may determine the second scaling coefficient SC2 as “p-1”, and may determine the nth scaling coefficient SCn as “p-1”.

[0089] Figure 9 is a more detailed illustration of various exemplary embodiments. Figure 5 Schematic diagram of the operation of the quantization circuit. Figures 1 to 5 and Figure 9 The quantization circuit DCCa can generate a plurality of scaling coefficients SC by quantizing the remaining differential weights except the initial differential weight among the plurality of differential weights DW. For a more concise description, various exemplary embodiments in which the quantization circuit DCCa generates the 0th scaling coefficient SC0 to the nth scaling coefficient SCn based on the 0th differential weight DW0 to the nth differential weight DWn will be representatively described below.

[0090] The quantization circuit DCCa may not quantize the 0th differential weight DW0. In this case, the 0th scaling coefficient SC0 may be equal to the 0th differential weight DW0.

[0091] The quantization circuit DCCa can generate the first to nth scaling coefficients SC1 to SCn by quantizing the first to nth differential weights DW1 to DWn. Figures 6 to 8 The methods described are similar, so their detailed descriptions are omitted.

[0092] In some examples, the quantization circuit DCCa may not quantize only the initial differential weights from the 0th differential weight DW0 to the nth differential weight DWn. In this case, the 0th scaling coefficient SC0 may have a data type different from the data types of the first scaling coefficients SC1 to the nth scaling coefficients SCn. For example, the 0th scaling coefficient SC0 may have a floating-point data type, and each of the first scaling coefficients SC1 to the nth scaling coefficients SCn may have an integer data type. In this case, since the 0th differential weight DW0 is not quantized, the error in the output element OE caused by the quantization of the 0th differential weight DW0 can be reduced or minimized.

[0093] Figure 10 is shown in more detail Figure 5 A diagram showing the configuration and operation of the input element scaling circuit. Figures 1 to 10 , the input element scaling circuit DCCb may include a power scaling circuit DCCb_1 , an accumulation circuit DCCb_2 and an output register DCCb_3 .

[0094] The power scaling circuit DCCb_1 may receive an input element IE and a plurality of scaling coefficients SC. For example, the power scaling circuit DCCb_1 may receive an input element IE and may sequentially receive a 0th to an nth scaling coefficient SC0 to SCn.

[0095] The power scaling circuit DCCb_1 can sequentially generate the 0th differential scaled input element DSIE0 to the nth differential scaled input element DSIEn by multiplying the input element IE by each of the powers of 2 for the 0th scaling coefficient SC0 to the nth scaling coefficient SCn (i.e., with each of the 0th scaling coefficient SC0 to the nth scaling coefficient SCn as a power of 2 for the exponent portion). For example, the power scaling circuit DCCb_1 can generate the 0th differential scaled input element DSIE0 by multiplying the input element IE by the power of 2 for the 0th scaling coefficient SC0; and can generate the first differential scaled input element DSIE1 by multiplying the input element IE by the power of 2 for the first scaling coefficient SC1. In this way, the power scaling circuit DCCb_1 can generate and sequentially output the 0th differential scaled input element DSIE0 to the nth differential scaled input element DSIEn. Referring to Figure 11 The operation of the power scaling circuit DCCb_1 is described in more detail.

[0096] In various exemplary embodiments, as described above with reference to Figure 9As described above, if the quantization circuit DCCa_1 is implemented so as not to quantize the 0th scaling coefficient SC0, the data type of the 0th scaling coefficient SC0 may be a floating-point data type. In this case, the power scaling circuit DCCb_1 may generate the 0th differentially scaled input element DSIE0 by performing a floating-point multiplication of the input element IE and the 0th scaling coefficient SC0, rather than multiplying the input element IE by a power of 2 for the 0th scaling coefficient SC0. However, example embodiments are not limited thereto.

[0097] Accumulator circuit DCCb_2 may sequentially receive a plurality of differentially scaled input elements DSIE. Accumulator circuit DCCb_2 may sequentially provide a plurality of output elements OE to output register DCCb_3 based on the order in which the plurality of differentially scaled input elements DSIE were provided. Output register DCCb_3 may sequentially provide the plurality of output elements OE to input / output circuit 140 and accumulator circuit DCCb_2.

[0098] For a more detailed example, the accumulation circuit DCCb_2 may generate a 0th output element OE0 based on the 0th differentially scaled input element DSIE0. The 0th output element OE0 may be the same as the 0th differentially scaled input element DSIE0. The accumulation circuit DCCb_2 may provide the 0th output element OE0 to the output register DCCb_3. The output register DCCb_3 may provide the 0th output element OE0 to the input / output circuit 140 and may feed the 0th output element OE0 back to the accumulation circuit DCCb_2.

[0099] Thereafter, the accumulation circuit DCCb_2 may generate a first output element OE1 by accumulating the 0th output element OE0 provided from the output register DCCb_3 and the first differentially scaled input element DSIE1. The accumulation circuit DCCb_2 may provide the first output element OE1 to the output register DCCb_3. The output register DCCb_3 may provide the first output element OE1 to the input / output circuit 140 and may feed the first output element OE1 back to the accumulation circuit DCCb_2.

[0100] In this manner, the accumulation circuit DCCb_2 can generate a k-th output element OEk by accumulating the (k-1)-th output element OEk-1 provided from the output register DCCb_3 and the k-th differentially scaled input element DSIEk, where "k" is an integer equal to or greater than 1 and equal to or less than n. In this case, the accumulation circuit DCCb_2 can provide the k-th output element OEk to the output register DCCb_3, and the output register DCCb_3 can provide the k-th output element OEk to the host device 10 through the input / output circuit 140.

[0101] In other words, the accumulation circuit DCCb_2 can generate a plurality of output elements OE by sequentially accumulating a plurality of differentially scaled input elements DSIE. In this case, the 0th output element OE0 may be the same as the 0th differentially scaled input element DSIE0; and the kth output element OEk may correspond to the sum of the 0th differentially scaled input element DSIE0 to the kth differentially scaled input element DSIEk.

[0102] On the other hand, the powers of two for the 0th to nth scaling coefficients SC0 to SCn (i.e., the powers of two with each of the 0th to nth scaling coefficients SC0 to SCn as the exponent portion) may be approximate calculated values ​​of the 0th to nth differential weights DW0 to DWn, respectively. In this case, the 0th to kth differentially scaled input elements DSIE0 to DSIEk may be approximate calculated values ​​of the products of the 0th to nth differential weights DW0 to DWn and the input element IE, respectively. That is, the 0th differentially scaled input element DSIE0 may be an approximate calculated value of the product of the input element IE and the 0th differential weight DW0; and the kth differentially scaled input element DSIEk may be an approximate calculated value of the product of the input element IE and the kth differential weight DWk.

[0103] Therefore, the kth output element OEk corresponding to the "sum of the 0th differentially scaled input element DSIE0 to the kth differentially scaled input element DSIEk" can be an approximate calculated value of the value obtained by multiplying the input element IE by the "sum of the 0th differential weight DW0 to the kth differential weight DWk." In this case, the "sum of the 0th differential weight DW0 to the kth differential weight DWk" can correspond to the kth weight Wk, so that the kth output element OEk can be the product of the kth weight Wk and the input element IE. In other words, the 0th output element OE0 to the nth output element OEn can be approximate values ​​of the values ​​XW0 to XWn obtained by multiplying the input element IE by the 0th weight W0 to the nth weight Wn, respectively. In this way, the differential calculation circuit DCC can calculate multiple output elements OE corresponding to the "product of the input element IE and the plurality of weights W."

[0104] As a result, according to some example embodiments, the differential calculation circuit DCC may perform the product of the input element IE and each of the plurality of weights W with a smaller amount of calculation. For example, according to some example embodiments, even if the differential calculation circuit DCC does not perform floating-point multiplication on the plurality of weights W and the input element IE, the differential calculation circuit DCC may calculate the plurality of output elements OE corresponding to “the product of the plurality of weights W and the input element IE”.

[0105] Figure 11 is shown in more detail Figure 10 Schematic diagram of the operation of the power scaling circuit. Figures 1 to 8 、 Figure 10 and Figure 11 The power scaling circuit DCCb_1 can sequentially generate a 0th differentially scaled input element DSIE0 to an nth differentially scaled input element DSIEn by multiplying the input element IE by each of the powers of two for the 0th scaling coefficient SC0 to the nth scaling coefficient SCn. For a more concise description, the operation of the power scaling circuit DCCb_1 for generating the 0th differentially scaled input element DSIE0 will be representatively described below. However, example embodiments are not limited thereto, and in a similar manner, the power scaling circuit DCCb_1 can also generate a first differentially scaled input element DSIE1 to an nth differentially scaled input element DSIEn.

[0106] The input element IE may have a floating point data type. For example, the input element IE may include a sign part SPa, an exponent part EXPPa, and a mantissa part MTSPa.

[0107] The power scaling circuit DCCb_1 may generate a 0th differentially scaled input element DSIE0 by changing the exponent portion EXPPa based on the 0th scaling coefficient SC0. For example, the power scaling circuit DCCb_1 may generate a 0th differentially scaled input element DSIE0 corresponding to a result of multiplying the input element IE by a power of 2 with respect to the 0th scaling coefficient SC0 by increasing the exponent portion EXPPa by the 0th scaling coefficient SC0.

[0108] The 0th differentially scaled input element DSIE0 may have a floating-point data type. For example, the 0th differentially scaled input element DSIE0 may include a sign portion SPb, an exponent portion EXPPb, and a mantissa portion MTSPb. In this case, the sign portion SPb may be the same as the sign portion SPa, and the mantissa portion MTSPb may be the same as the mantissa portion MTSPa. The exponent portion EXPPb may be larger than the exponent portion EXPPa by the 0th scaling factor SC0.

[0109] For example, according to some example embodiments, the power scaling circuit DCCb_1 may generate a plurality of differentially scaled input elements DSIE by simply changing the exponent portion EXPPa of the input element IE. In this case, since the input element IE is scaled by increasing the exponent portion EXPPa of the input element IE without performing floating-point multiplication, the differential calculation circuit DCC may be implemented using a smaller number of transistors. Therefore, according to some example embodiments, the circuit area, power consumption, and computational complexity of the differential calculation circuit DCC may be reduced or minimized.

[0110] Figure 12 is a flowchart illustrating an operating method of a memory device according to various example embodiments of the present disclosure. Figures 1 to 12In operation S110 , the memory device 100 may receive a differential weight write command CMD_DWW for a plurality of weights W from the host device 10 .

[0111] In operation S120 , the memory device 100 may generate a plurality of differential weights DW by converting a plurality of weights W into a differential format. For example, the internal processor 111 may generate 0th to nth differential weights DW0 to DWn based on 0th to nth weights W0 to Wn.

[0112] In operation S130, the memory device 100 may write a plurality of differential weights DW into the memory cell array 130. For example, the control logic circuit 110 may control the row decoder 120 and the input / output circuit 140 to store 0th to nth differential weights DW0 to DWn in the memory cell array 130.

[0113] For a more concise description, Figure 12 , operation S130 is representatively described as being performed after operation S120, but example embodiments are not limited thereto. For example, the memory device 100 may be implemented to repeatedly perform operations of generating a differential weight DW and storing the differential weight DW in the memory cell array 130.

[0114] Figure 13 is shown in more detail Figure 12 Flowchart of operation S120. Figures 1 to 13 , operation S120 may include the following operations S121 to S125.

[0115] In operation S121 , a variable i may be set to 0. The variable i is only used to describe the repetitive operation of the format conversion circuit FCC, but example embodiments are not limited thereto.

[0116] In operation S122, the format conversion circuit FCC may generate an i-th differential weight DWi corresponding to the i-th weight Wi. That is, the format conversion circuit FCC may generate a 0th differential weight DW0 corresponding to the 0th weight W0. In this case, the 0th differential weight DW0 may be equal to the 0th weight W0.

[0117] In operation S123, the format conversion circuit FCC may increase the variable i by "1".

[0118] In operation S124, the format conversion circuit FCC may generate an i-th differential weight DWi based on a difference between the (i-1)th weight Wi-1 and the i-th weight Wi. For example, the format conversion circuit FCC may generate the i-th differential weight DWi based on a value obtained by subtracting the (i-1)th weight Wi-1 from the i-th weight Wi.

[0119] In operation S125, the format conversion circuit FCC may determine whether the variable i is "n." For example, the format conversion circuit FCC may determine whether differential weights DW have been generated for all weights W. If the variable i is determined to be "n," operation S120 may be terminated, and if the variable i is determined not to be "n," operation S123 may be repeated. In this manner, the format conversion circuit FCC may sequentially generate the 0th differential weight DW0 to the nth differential weight DWn.

[0120] In various example embodiments, if the memory device 100 is implemented to repeatedly perform generating one differential weight DW and storing one differential weight DW in the memory cell array 130, the control logic circuit 110 may be implemented to store the generated differential weight DW in the memory cell array 130 after performing operations S122 and S124. However, example embodiments are not limited thereto.

[0121] Figure 14 is a flowchart illustrating an operating method of a memory device according to various example embodiments of the present disclosure. Figures 1 to 14 In operation S210, the memory device 100 may receive an input element IE from the host device 10. In this case, the memory device 100 may store the input element IE in the memory cell array 130.

[0122] For a more concise description, hereinafter, it is assumed that the above operations S110 to S130 have been performed before operation S220 is performed. In this case, before operation S220 is performed, the input element IE and the plurality of differential weights DW may be stored in the memory cell array 130.

[0123] In operation S220 , the memory device 100 may receive a weight multiplication command CMD_WM for the input element IE and the plurality of differential weights DW from the host device 10 .

[0124] In operation S230, the memory device 100 may generate a plurality of output elements OE corresponding to the product of the input element IE and the plurality of differential weights DW. For example, the internal processor 111 may generate the 0th output element OE0 to the nth output element OEn based on the input element IE and the 0th differential weight DW0 to the nth differential weight DWn. Figure 15 Operation S230 is described in more detail.

[0125] In operation S240, the memory device 100 may output a plurality of output elements OE to the host device 10. For example, the memory device 100 may output 0th to nth output elements OE0 to OEn to the host device 10.

[0126] For a more concise description, Figure 14 , operation S240 is representatively described as being performed after operation S230, but example embodiments are not limited thereto. For example, the memory device 100 may be implemented to repeatedly perform the operation of "generating one output element OE and outputting one output element OE to the host device 10."

[0127] Figure 15 is shown in more detail Figure 14 Flowchart of operation S230. Figures 1 to 15 , operation S230 may include the following operations S231 to S234.

[0128] In operation S231 , the variable i may be set to 0. The variable i is only used to describe the repetitive operation of the differential calculation circuit DCC, but example embodiments are not limited thereto.

[0129] In operation S232, the differential calculation circuit DCC may generate an i-th output element OEi by accumulating i-th differentially scaled input elements DSIEi, where the i-th differentially scaled input element DSIEi is generated by multiplying the input element IE by a power of two for an i-th scaling coefficient SCi (i.e., a power of two with the i-th scaling coefficient SCi as an exponent portion), where the i-th scaling coefficient SCi is generated based on an i-th differential weight DWi. For example, the quantization circuit DCCa may generate the i-th scaling coefficient SCi based on the i-th differential weight DWi; and the input element scaling circuit DCCb may generate the i-th output element OEi by accumulating the i-th differentially scaled input element DSIEi generated based on the i-th scaling coefficient SCi and the input element IE.

[0130] For a more detailed example, the power scaling circuit DCCb_1 may generate an i-th differentially scaled input element DSIEi by multiplying the input element IE by the power of 2 for the i-th scaling coefficient SCi. The accumulation circuit DCCb_2 may generate an i-th output element OEi by accumulating the 0th differentially scaled input element DSIE0 to the i-th differentially scaled input element DSIEi.

[0131] In operation S233, the differential calculation circuit DCC may determine whether the variable i is "n." For example, the differential calculation circuit DCC may determine whether the output elements OE corresponding to all weights W have been generated. If the variable i is determined to be "n," operation S230 may be terminated. If the variable i is determined not to be "n," operation S234 may be performed.

[0132] In operation S234 , the differential calculation circuit DCC may increase the variable i by “1.” Thereafter, the above-described operation S232 may be repeatedly performed. In this manner, the differential calculation circuit DCC may sequentially generate the 0th to nth output elements OE0 to OEn.

[0133] Figure 16 is a diagram illustrating various exemplary embodiments Figure 2 The configuration and operation of the control logic circuit are shown in FIG. Figures 1 to 16 , the control logic circuit 110 may include an internal processor 111 and a storage format management circuit 112. Figure 2 A detailed description of the configuration and operation of the internal processor 111 will be omitted.

[0134] The storage format management circuit 112 may include a storage format table SFT. The storage format management circuit 112 may manage input / output operations of the memory device 100 based on the storage format table SFT.

[0135] The storage format management circuit 112 may manage the format of data stored in the memory cell array 130 based on the storage format table SFT. For example, the storage format table SFT may indicate one or more of the address, data attribute, storage format, and differential index of the memory cell array 130.

[0136] For a more detailed example, the storage format table SFT may indicate that the weight W is stored in the original format at address "0x000A" of the memory cell array 130; may indicate that the input element IE is stored in the original format (or form) at address "0x000B" of the memory cell array 130; and may indicate that multiple weights W are stored in a differential form (or format) at addresses "0x000C to 0x000E" of the memory cell array 130. In some examples, the storage format table SFT may indicate that the data stored at addresses "0x000C to 0x000E" are differential weights DW.

[0137] The storage format management circuit 112 may perform a read operation in response to a read command from the host device 10 based on the storage format table SFT.

[0138] If a read command for data stored in the original format is issued from the host device 10, the storage format management circuit 112 may control the memory device 100 to perform a normal (e.g., regular) read operation on the data stored in the original format. For a more detailed example, if a read command for address "0x000A" is issued from the host device 10, the storage format management circuit 112 may control the memory device 100 to output the data stored at address "0x000A" to the host device 10.

[0139] On the other hand, if a read command for data stored in a differential format is issued from the host device 10, the storage format management circuit 112 may convert the data stored in the differential format into the original format and then provide the converted data to the host device 10. For a more detailed example, if a read command for address "0x000E" is issued from the host device 10, the storage format management circuit 112 may identify the data stored at address "0x000E" as the second differential weight DW2 based on the differential index value "2." In this case, the storage format management circuit 112 may control the internal processor 111 to calculate the second differential weight W2 by summing the data stored at addresses corresponding to differential indexes 0 and 1 (i.e., 0x000C and 0x000D) (i.e., the 0th differential weight DW0 and the first differential weight DW1) with the second differential weight DW2. Thereafter, the storage format management circuit 112 may control the memory device 100 to output the calculated second differential weight W2 to the host device 10.

[0140] Any of the elements and / or functional blocks disclosed above may include processing circuitry (e.g., hardware including logic circuitry, a hardware / software combination (e.g., a processor executing software), or any combination thereof), or may be implemented in processing circuitry (e.g., hardware including logic circuitry, a hardware / software combination (e.g., a processor executing software), or any combination thereof). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. The processing circuitry may include electrical components (e.g., at least one of a transistor, a resistor, a capacitor, and the like). The processing circuitry may include electronic components (e.g., logic gates including at least one of an AND gate, an OR gate, a NAND gate, a NOR gate, and the like).

[0141] What has been described above is a specific embodiment for implementing the present disclosure. Examples may include not only the above-described example embodiments, but also example embodiments in which the design can be simply changed and / or example embodiments that can be easily modified. In addition, example embodiments may also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined by the claims described and the claims and equivalents of the present disclosure. In addition, example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

Claims

1. A memory device comprising: a format conversion circuit configured to generate a plurality of differential weights based on a plurality of weights provided from an external device; a memory cell array configured to store a first input element provided from an external device and to store the plurality of differential weights; a quantization circuit configured to generate a plurality of scaling coefficients based on the plurality of differential weights; as well as An input element scaling circuit is configured to provide a plurality of output elements to an external device based on the plurality of scaling coefficients, the plurality of output elements corresponding to a product of the first input element and each of the plurality of weights.

2. The memory device of claim 1, wherein: The format conversion circuit is configured to generate a first differential weight based on a difference between a first weight and a second weight included in the plurality of weights, the first differential weight being included in the plurality of differential weights.

3. The memory device of claim 1, wherein: The powers of 2 with the multiple scaling factors as exponent parts respectively correspond to the magnitudes of the multiple differential weights respectively.

4. The memory device of claim 1, wherein: Each of the first input element, the plurality of weights, and the plurality of differential weights has a floating point data type, and Each of the plurality of scaling factors has an integer data type.

5. The memory device of claim 4, wherein: The input element scaling circuit includes: a power scaling circuit configured to generate a plurality of differentially scaled input elements based on the plurality of scaling factors, the plurality of differentially scaled input elements corresponding to products of the first input element and each of the plurality of differential weights; and An accumulation circuit is configured to generate the plurality of output elements by sequentially accumulating the plurality of differentially scaled input elements.

6. The memory device of claim 5, wherein: The input element scaling circuit also includes: The output register is configured to sequentially receive the plurality of output elements and sequentially provide the plurality of output elements to an external device and an accumulation circuit.

7. The memory device of claim 5, wherein: The power scaling circuit is configured to generate the plurality of differentially scaled input elements by varying an exponential portion of a first input element based on the plurality of scaling factors.

8. The memory device of claim 1 , further comprising: The storage format management circuit is configured to manage a storage format table, wherein the storage format table indicates storage formats of the plurality of differential weights.

9. A differential calculation circuit, the differential calculation circuit being included in an internal processor of a memory device, the differential calculation circuit comprising: a quantization circuit configured to generate 0th to nth scaling coefficients based on 0th to nth differential weights, where n is an integer greater than or equal to 1; and an input element scaling circuit configured to generate 0th to nth output elements based on 0th to nth scaling factors and an input element, The input element scaling circuit includes: a power scaling circuit configured to generate a 0th differential scaled input element to an nth differential scaled input element by scaling the input element based on a 0th scaling factor to an nth scaling factor, and The accumulation circuit is configured to sequentially generate a 0th output element to an nth output element by sequentially accumulating a 0th differentially scaled input element to an nth differentially scaled input element.

10. The differential calculation circuit according to claim 9, wherein: The powers of 2 having the first to nth scaling factors as exponent parts respectively correspond to the amplitudes of the first to nth differential weights, respectively.

11. The differential calculation circuit according to claim 10, wherein: The 0th scaling factor and the 0th differential weight are identical to each other.

12. The differential calculation circuit according to claim 11, wherein: The data type of each of the first to nth scaling factors is the first data type, and The data type of the 0th scaling factor is a second data type different from the first data type.

13. The differential calculation circuit according to claim 10, wherein: The quantization circuit is configured as: Approximately calculating the magnitude of each of the 0th differential weight to the nth differential weight in the form of a power of 2; as well as Based on the exponential parts of the 0th to nth differential weights approximately calculated in the form of powers of 2, the 0th to nth scaling coefficients are generated, respectively.

14. The differential calculation circuit according to claim 10, wherein: The power scaling circuit is configured as: A kth differentially scaled input element is generated by changing an exponential portion of the input element by a kth scaling factor, where k is an integer greater than or equal to 1 and less than or equal to n.

15. The differential calculation circuit according to claim 9, wherein: The kth output element among the 0th to nth output elements corresponds to the sum of the 0th to kth differentially scaled input elements.

16. The differential calculation circuit according to claim 14, wherein: The input element scaling circuit also includes: The output register is configured to sequentially receive the 0th to nth output elements and sequentially provide the 0th to nth output elements to an external device and an accumulation circuit.

17. The differential calculation circuit according to claim 16, wherein: The summing circuit is configured as: The k-th output element is generated by accumulating the k-1-th differentially scaled input element provided from the power scaling circuit and the k-1-th output element provided from the output register.

18. A method for operating a memory device, comprising: storing a 0th differential weight and a first differential weight, the 0th differential weight and the first differential weight being generated based on the 0th weight and the first weight provided from an external device; receiving a first input element from an external device; receiving a weight multiplication command for a 0th weight, a first weight, and a first input element from an external device; In response to the weight multiplication command, generating a 0th output element and a first output element based on a 0th differentially scaled input element and a first differentially scaled input element, the 0th differentially scaled input element and the first differentially scaled input element corresponding to a product of the first input element and a 0th differential weight and a product of the first input element and the first differential weight, respectively, and the 0th output element and the first output element corresponding to a product of the first input element and the 0th weight and a product of the first input element and the first weight, respectively; as well as The 0th output element and the first output element are output to an external device.

19. The operating method according to claim 18, wherein: The step of storing the 0th differential weight and the first differential weight includes: generating a 0th differential weight based on the 0th weight; and A first differential weight is generated based on a difference between the first weight and the 0th weight.

20. The operating method according to claim 18, wherein: The steps of generating the 0th output element and the first output element include: generating a 0th scaling factor based on the 0th differential weight; Generate a 0th differentially scaled input element corresponding to a 0th output element based on a 0th scaling factor and a first input element; generating a first scaling factor based on the first differential weight; generating a first differentially scaled input element based on the first scaling factor and the first input element; and The first output element is generated by accumulating the 0th output element and the first differentially scaled input element.

Images