Equalization method and equalization circuit for signal insertion loss

Abstract

The invention discloses a signal insertion loss equalization method and equalization circuit. The method comprises the following steps: respectively carrying out first-stage equalization processing and second-stage equalization processing on an original input signal through a continuous time linear equalizer based on a first equalization parameter and a second equalization parameter to generate an equalized output signal; updating a second equalization parameter according to a preset linear equalization algorithm based on the equalized output signal, and performing decision feedback equalization processing on the equalized output signal through a decision feedback equalizer to obtain a feedback tap coefficient of the decision feedback equalizer; weighting the feedback tap coefficient according to a preset weight to generate a weighted coefficient; and comparing the weighted coefficient with a preset noise threshold, and updating the first equalization parameter according to a preset first strategy or a preset second strategy. According to the invention, the problem of over-equalization caused by taking the second-stage equalization value as the first-stage equalization value in the equalization architecture of the joint equalization signal of the decision feedback equalizer and the continuous time linear equalizer is solved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a signal insertion loss equalization method and equalization circuit. Background Art

[0002] In serial communication systems, signal quality deteriorates during signal transmission from the transmitter to the receiver due to channel losses, such as high-frequency attenuation and crosstalk, which seriously impacts communication reliability. Therefore, a combined architecture of a continuous-time linear equalizer (CTLE) and a decision-feedback equalizer (DFE) is required at the receiver to mitigate signal distortion. Specifically, the DFE compensates for inter-symbol interference (ISI) by adaptively adjusting tap coefficients, while the CTLE compensates for high-frequency attenuation and low-frequency loss.

[0003] In traditional CTLE and DFE joint equalization architectures, the DFE's adaptive nature overrides the CTLE's first-stage equalization point, preventing the CTLE's first-stage equalization algorithm from dynamically updating the CTLE's first-stage equalization value based on the equalization algorithm. Therefore, the CTLE's second-stage equalization value is typically used as the CTLE's first-stage equalization value. However, this design has significant drawbacks in scenarios with low signal insertion loss. The CTLE's second-stage equalization value is often too large, which in turn causes the CTLE's first-stage equalization value to be too large. Ultimately, this leads to severe over-equalization of signals with low insertion loss, increasing the subsequent DFE compensation burden and ultimately affecting the signal's eye diagram height and bit error rate. Summary of the Invention

[0004] In view of the above problems, the present application provides a signal insertion loss equalization method and equalization circuit to solve the above technical problems.

[0005] In a first aspect, the present application provides a signal insertion loss equalization method, which is applied to an equalization architecture in which a decision feedback equalizer and a continuous time linear equalizer jointly equalize signals. The signal insertion loss equalization method includes:

[0006] Based on the first equalization parameter and the second equalization parameter, the original input signal is subjected to a first-stage equalization process and a second-stage equalization process respectively by a continuous-time linear equalizer to generate an equalized output signal;

[0007] Based on the equalized output signal, updating the second equalization parameter according to a preset linear equalization algorithm, and performing decision feedback equalization processing on the equalized output signal through a decision feedback equalizer to obtain feedback tap coefficients of the decision feedback equalizer;

[0008] Performing weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients;

[0009] Compare the weighted coefficient with the preset noise threshold,

[0010] If the weighted coefficient is greater than the noise threshold, updating the first equalization parameter according to a preset first strategy;

[0011] If the weighted coefficient is less than the noise threshold, updating the first equalization parameter according to a preset second strategy;

[0012] The first strategy includes: Y=X+1, and Y≤Z; the second strategy includes: Y=X; Y is the updated first balancing parameter, X is the first balancing parameter before the update, and Z is the preset upper limit threshold of the first balancing parameter;

[0013] Wherein, in the step of performing first-stage equalization processing and second-stage equalization processing on the original input signal based on the first equalization parameter and the second equalization parameter by a continuous time linear equalizer to generate an equalized output signal,

[0014] The first equalization parameter and the second equalization parameter are dynamically updated, and in an initialization phase, the first equalization parameter is configured as a preset first equalization value, and the second equalization parameter is configured as a preset second equalization value.

[0015] In a second aspect, the present application provides a signal insertion loss equalization circuit, comprising:

[0016] A continuous-time linear equalization module, configured to perform a first-stage equalization process and a second-stage equalization process on the original input signal based on the first equalization parameter and the second equalization parameter, respectively, to generate an equalized output signal;

[0017] a second-stage equalization parameter processing module, configured to update the second equalization parameters according to a preset linear equalization algorithm based on the equalized output signal;

[0018] A decision feedback equalization module, configured to perform decision feedback equalization processing on the equalized output signal and obtain feedback tap coefficients of the decision feedback equalization module;

[0019] The first-stage equalization parameter processing module is used to perform weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients, and compare the weighted coefficients with a preset noise threshold.

[0020] If the weighted coefficient is greater than the noise threshold, updating the first equalization parameter according to a preset first strategy;

[0021] If the weighted coefficient is less than the noise threshold, updating the first equalization parameter according to a preset second strategy;

[0022] The first strategy includes: Y=X+1, and Y≤Z; the second strategy includes: Y=X; Y is the updated first balancing parameter, X is the first balancing parameter before the update, and Z is the preset upper limit threshold of the first balancing parameter;

[0023] In the first-level equalization parameter processing module, the first equalization parameter is configured as a preset first equalization value during the initialization phase; in the second-level equalization parameter processing module, the second equalization parameter is configured as a preset second equalization value during the initialization phase.

[0024] The present application provides a signal insertion loss equalization method and equalization circuit. The signal insertion loss equalization method is based on a first equalization parameter and a second equalization parameter. The original input signal is subjected to first-stage equalization and second-stage equalization by a continuous-time linear equalizer to generate an equalized output signal. Based on the equalized output signal, the second equalization parameter is updated according to a preset linear equalization algorithm, and the equalized output signal is subjected to decision feedback equalization by a decision feedback equalizer to obtain feedback tap coefficients of the decision feedback equalizer. The feedback tap coefficients are weighted according to preset weights to generate weighted coefficients. The weighted coefficients are compared with a preset noise threshold, and the first equalization parameter is updated according to a preset first strategy (Y=X+1, and Y≤Z) or a second strategy (Y=X) based on the comparison result. The signal insertion loss equalization method provided by the present application solves the over-equalization problem caused by using the second-stage equalization value as the first-stage equalization value in an equalization architecture in which a decision feedback equalizer and a continuous-time linear equalizer jointly equalize a signal. Therefore, the signal insertion loss equalization method provided in this application can be applied not only to scenarios with large signal insertion loss but also to scenarios with small signal insertion loss, significantly improving the adaptability and equalization accuracy of the equalization structure to different insertion loss scenarios.

[0025] Among them, the small insertion loss and large insertion loss described in this application are relative divisions of channel insertion loss in high-speed serial communication systems. This division is dynamically adapted based on the system's equalization capabilities and communication rate requirements, rather than a fixed physical threshold. For example, some manufacturers define an insertion loss less than 8 decibels as a small insertion loss, and an insertion loss greater than 12 decibels as a large insertion loss. Insertion losses between 8 decibels and 12 decibels can be considered small insertion losses or large insertion losses. However, it should be clear that the above thresholds are only empirical values ​​set by some manufacturers based on the equalization capabilities of their equalizers, rather than industry-wide unified standards. As parameters such as hardware capabilities, data transmission rates, and device materials increase / decrease, the definitions of small insertion losses and large insertion losses may also change accordingly.

[0026] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A flow chart of a signal insertion loss equalization method provided in an embodiment of the present application is shown.

[0029] Figure 2 Another flow chart of the signal insertion loss equalization method provided in an embodiment of the present application is shown.

[0030] Figure 3 Another flow chart of the signal insertion loss equalization method provided in an embodiment of the present application is shown.

[0031] Figure 4 Another flow chart of the signal insertion loss equalization method provided in an embodiment of the present application is shown.

[0032] Figure 5 A schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown.

[0033] Figure 6 A schematic diagram of a continuous-time linear equalization module provided in an embodiment of the present application is shown.

[0034] Figure 7 A schematic diagram of a first-stage equalization parameter processing module provided in an embodiment of the present application is shown.

[0035] Figure 8Another schematic diagram of the first-stage equalization parameter processing module provided in an embodiment of the present application is shown.

[0036] Figure 9 Another schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown.

[0037] Figure 10 Another schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0039] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0040] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0041] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0042] The embodiment of the present application provides a signal insertion loss equalization method, which is applied to an equalization architecture in which a decision feedback equalizer and a continuous time linear equalizer jointly equalize signals. Figure 1 A flow chart of a signal insertion loss equalization method provided in an embodiment of the present application is shown. Figure 1 As shown, the equalization method for the signal insertion loss includes:

[0043] Based on the first equalization parameter and the second equalization parameter, the original input signal is subjected to the first-level equalization processing and the second-level equalization processing respectively by the continuous-time linear equalizer to generate an equalized output signal. Optionally, the first-level equalization processing is used to compensate for the high-frequency attenuation of the original input signal due to dielectric loss, and the second-level equalization processing is used to compensate for the low-frequency loss of the original input signal due to the current skin effect. The equalized output signal is the signal after the original input signal is compensated for the high-frequency attenuation and the low-frequency loss. The first equalization parameter and the second equalization parameter correspond to the gain coefficient of the first-level equalization processing and the gain coefficient of the second-level equalization processing of the continuous-time linear equalizer, respectively, thereby controlling the compensation strength of the continuous-time linear equalizer. It can be understood that in the embodiment of the present application, the original input signal is the signal that needs to be equalized, and its source is not limited here. For example, the original input signal can be a signal directly output by the transmitter of the serial communication system, or it can be a signal after the receiver processes the signal output by the transmitter. In addition, the embodiment of the present application is an improvement to the adaptive update of the first equalization parameter of the continuous-time linear equalizer, and the specific process of the continuous-time linear equalizer performing equalization processing on the signal belongs to the known technology in the field. Therefore, the specific implementation method of the continuous-time linear equalizer to implement equalization processing is not described here. Finally, the embodiment of the present application only involves the first equalization parameter and the second-level equalization parameter. Therefore, the third-level equalization, fourth-level equalization and more-level equalization processing that may exist in the continuous-time linear equalizer do not belong to the improvement points of the present application, nor do they constitute a limitation on the scope of protection of the present application, and will not be repeated here.

[0044] Based on the equalized output signal, a second equalization parameter is updated according to a preset linear equalization algorithm, and decision feedback equalization processing is performed on the equalized output signal via a decision feedback equalizer to obtain feedback tap coefficients for the decision feedback equalizer. Optionally, the equalized output signal is used as an input parameter for the linear equalization algorithm, causing the linear equalization algorithm to output new second equalization parameters based on the input parameters, thereby updating the second equalization parameters. Similarly, the equalized output signal is used as an input signal for the decision feedback equalizer, causing the decision feedback equalizer to perform decision feedback equalization processing on it, thereby obtaining feedback tap coefficients that are adaptively adjusted by the decision feedback equalizer based on the input signal. It is understood that calculating equalization values ​​for a continuous-time linear equalizer using a linear equalization algorithm is a known technique in the art and does not constitute an improvement of the present application. Therefore, the specific implementation process of the linear equalization algorithm and the corresponding circuit for implementing the linear equalization algorithm are not described here. Furthermore, the decision feedback equalizer is also a known technique in the art and can perform nonlinear compensation for intersymbol interference based on the received signal and dynamically adjust the feedback tap coefficients using an adaptive algorithm to improve signal quality. However, this does not constitute an improvement of the present application, so the specific implementation of the decision feedback equalization processing is not described here. Finally, the embodiment of the present application only needs to obtain the feedback tap coefficient of the decision feedback equalizer for the subsequent update of the first equalization parameter, and does not depend on the final output signal of the decision feedback equalizer. Therefore, the final output signal of the decision feedback equalizer is not described here.

[0045] The feedback tap coefficients are weighted according to preset weights to generate weighted coefficients. Optionally, the weights of the feedback tap coefficients are empirical values. Specifically, the weights of the feedback tap coefficients are set based on actual channel characteristics, data rate, bit error rate, and other performance requirements, and are ultimately obtained through training statistical analysis to improve the accuracy of the weighted coefficients in adjusting the first equalization parameter.

[0046] The weighted coefficient is compared with a preset noise threshold. If the weighted coefficient is greater than the noise threshold, the first equalization parameter is updated according to a preset first strategy; if the weighted coefficient is less than the noise threshold, the first equalization parameter is updated according to a preset second strategy. The first strategy includes: Y = X + 1, and Y ≤ Z; the second strategy includes: Y = X, where Y is the updated first equalization parameter, X is the first equalization parameter before the update, and Z is the preset upper limit threshold of the first equalization parameter. Optionally, the noise threshold is also an empirical value, usually set based on 30% to 50% of the maximum noise amplitude that can be equalized by the first feedback tap of the decision feedback equalizer. For example, when the maximum noise amplitude that can be equalized by the first feedback tap of the decision feedback equalizer is 20mV, the noise threshold value range is usually set between 6mV and 10mV to prevent misjudgment and over-adjustment of the first equalization parameter due to excessive noise.

[0047] In an embodiment of the present application, based on the first equalization parameter and the second equalization parameter, the original input signal is subjected to first-level equalization processing and second-level equalization processing respectively by a continuous-time linear equalizer, and in the step of generating the equalized output signal, the first equalization parameter and the second equalization parameter are dynamically updated, and in the initialization phase, the first equalization parameter is configured to a preset first equalization value, and the second equalization parameter is configured to a preset second equalization value. Specifically, after the new first equalization parameter and the second equalization parameter are generated in the subsequent step, based on the first equalization parameter and the second equalization parameter, the original input signal is subjected to first-level equalization processing and second-level equalization processing respectively by a continuous-time linear equalizer, and in the step of generating the equalized output signal, the current first equalization parameter and the second equalization parameter will be replaced with the newly generated first equalization parameter and the second equalization parameter, thereby achieving continuous adaptation to the channel state and dynamic optimization of the equalization performance. When the signal insertion loss equalization method is in the initialization stage (i.e., during the initial operation), a first equalization value and a second equalization value are preset as the first equalization parameter and the second equalization parameter of the initialization stage, and the signal insertion loss equalization method is continuously run to obtain the final stable first equalization parameter and the second equalization parameter, wherein the preset first equalization value and the second equalization value are empirical values, which are usually obtained based on statistical analysis of typical channel environments and historical operation data, so as to achieve rapid convergence to a reasonable equilibrium state at the initial startup.

[0048] It is understood that the signal insertion loss equalization method provided in the embodiments of the present application is applied to an equalization architecture that combines a decision feedback equalizer and a continuous-time linear equalizer to equalize a signal. This equalization architecture is used to address the channel transmission loss problem that occurs when a signal is transmitted from a transmitter to a receiver in a serial communication system. That is, this equalization architecture is typically deployed at the receiver end of a serial communication system. Furthermore, when the serial communication system is a high-speed serial communication system, the original input signal described in the embodiments of the present application is a high-speed differential signal.

[0049] The signal insertion loss equalization method provided in the embodiment of the present application dynamically adjusts the first-level equalization gain of the continuous-time linear equalizer according to a preset strategy by weighting the feedback tap coefficient of the decision feedback equalizer and comparing it with the noise threshold, thereby solving the over-equalization problem caused by using the second-level equalization value as the first-level equalization value in the equalization architecture in which the decision feedback equalizer and the continuous-time linear equalizer jointly equalize the signal. Therefore, the signal insertion loss equalization method provided in the present application can be applied to scenarios with large signal insertion loss as well as scenarios with small signal insertion loss, significantly improving the adaptability and equalization accuracy of the equalization structure to different insertion loss scenarios. Specifically, in the embodiment of the present application, the first equalization parameter is set to be updated according to the preset first strategy or second strategy, and the second strategy makes the first equalization parameter have a maximum value. In the scenario of small insertion loss, the feedback tap coefficient is also small. Therefore, as long as the upper limit threshold of the first equalization parameter is controlled, the first equalization parameter obtained based on the feedback tap coefficient can be maintained at a small value, thereby providing a small gain for the continuous-time linear equalizer. In scenarios with high insertion loss, the interference value of the input signal after equalization is large, and the feedback tap coefficient after the decision feedback equalizer is also large. Therefore, the first equalization parameter obtained based on the feedback tap coefficient can still maintain a large value, thereby improving the equalization effect of the continuous-time linear equalizer and further reducing the equalization pressure of the DFE. Therefore, this method can effectively cope with scenarios with both high and low insertion loss.

[0050] In some embodiments, Figure 2 Another flow chart of the signal insertion loss equalization method provided in an embodiment of the present application is shown, Figure 2 As shown, in the embodiment of the present application, the step of obtaining the feedback tap coefficient of the decision feedback equalizer includes:

[0051] The feedback tap coefficients corresponding to the decision symbols of the decision feedback equalizer are obtained in ascending order of the time delay of each decision symbol until a preset number of feedback tap coefficients are obtained. Optionally, the decision feedback equalizer determines the current symbol by determining the output signal after equalization, and then uses the previous symbols obtained by determination as decision symbols, and selects them in order from small to large according to their time delay relative to the current symbol, multiplying them with the corresponding feedback tap coefficients and summing them, thereby generating an estimate of the noise component caused by backward inter-symbol interference in the current symbol, and finally subtracting the estimate from the current signal to achieve effective suppression of backward inter-symbol interference. Specifically, the decision symbol is a symbol determined earlier than the current symbol in the decision feedback equalizer; the time delay represents the number of symbol periods between the corresponding decision symbol and the current symbol; and the feedback tap coefficient represents the relative strength of the interference caused by the corresponding decision symbol to the current symbol. In the embodiment of the present application, N feedback tap coefficients of the decision feedback equalizer are taken, where N is a positive integer not exceeding the total number of taps of the decision feedback equalizer. Usually, the feedback tap coefficients corresponding to several decision symbols with the smallest time delay are selected as the input parameters for the subsequent weighted calculation. For example, when the decision feedback equalizer has 8 taps, the feedback coefficients of the first 2 to 3 taps are usually selected as the input parameters for the weighted calculation, because the decision symbols corresponding to these early taps have the greatest impact on the inter-symbol interference caused by the current symbol. Therefore, the tap feedback coefficients of the subsequent taps can usually be ignored. However, it should be clear that the embodiment of the present application can also select the feedback tap coefficients of all taps as the input parameters for the subsequent weighted calculation.

[0052] In some embodiments, as Figure 1 and Figure 2 As shown, the feedback tap coefficients are weighted according to preset weights, and in the step of generating weighted coefficients, the weights of the feedback tap coefficients meet the preset third strategy, which includes: the sum of the weights of the feedback tap coefficients is 1, and the smaller the time delay of the decision symbol, the greater the weight of the feedback tap coefficient corresponding to the decision symbol. Optionally, the sum of the weights of the feedback tap coefficients is constrained to 1 to achieve weight normalization. In addition, the smaller the time delay of the decision symbol, the greater the inter-symbol interference caused by the decision symbol. Therefore, the weight of the feedback tap coefficient corresponding to the decision symbol is set to be larger, thereby enhancing the ability to suppress near-end interference. It can be understood that the embodiment of the present application does not make any requirements on the specific weight setting of each feedback tap coefficient, as long as the weight setting of each feedback tap coefficient meets the above-mentioned third strategy.

[0053] In some embodiments, Figure 3 Another flow chart of the signal insertion loss equalization method provided in the embodiment of the present application is shown. Figure 3As shown, after the step of performing decision feedback equalization on the equalized output signal by the decision feedback equalizer and obtaining the feedback tap coefficient of the decision feedback equalizer, the feedback tap coefficient is weighted according to a preset weight, and before the step of generating the weighted coefficient, the method further includes:

[0054] Determine whether the feedback tap coefficient satisfies the preset fourth strategy. If the feedback tap coefficient satisfies the preset fourth strategy, then sequentially execute the following steps: weight the feedback tap coefficient according to the preset weight to generate the weighted coefficient. If the feedback tap coefficient does not satisfy the preset fourth strategy, then return to the execution step: perform decision feedback equalization on the equalized output signal through the decision feedback equalizer to obtain the feedback tap coefficient of the decision feedback equalizer. The fourth strategy includes: the update flag corresponding to the feedback tap coefficient update has been updated, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range for a preset number of consecutive times. Optionally, the fourth strategy for determining whether the feedback tap coefficient satisfies the preset condition is intended to evaluate the stability of the feedback tap coefficient. Therefore, it is necessary to sequentially detect the update flag corresponding to the feedback tap coefficient update, the error of the current feedback tap coefficient, and the error of the feedback tap coefficient obtained for a preset number of consecutive times before weighting the feedback tap coefficient. The specific value of the preset number of times is not limited here. For example, the feedback tap coefficient may be obtained for 5 consecutive times, or it may be obtained for 10 consecutive times, 20 consecutive times, or even more or less times. It is understandable that the signal insertion loss equalization method provided in the embodiment of the present application is always running, so the feedback tap coefficient will be continuously output. Therefore, the error of the feedback tap coefficient obtained for a preset number of consecutive times can be detected here.

[0055] In some embodiments, the embodiments of the present application use a state machine device to determine whether the feedback tap coefficient meets the preset fourth strategy. Specifically, the state machine device is configured to be an initial state, a first state, a second state and a third state. The first state, the second state and the third state respectively correspond to three events: whether the update flag corresponding to the update of the feedback tap coefficient is updated, whether the error between the updated feedback tap coefficient and the feedback tap coefficient before the update meets the preset error range, and whether the error between the updated feedback tap coefficient and the feedback tap coefficient before the update meets the preset error range for a preset number of consecutive times. The state machine device starts from the initial state and executes the events corresponding to the first state, the second state and the third state in sequence. When any of the events does not meet the corresponding conditions, the state device will return to the initial state, and will subsequently continue to execute the events corresponding to the first state, the second state and the third state in sequence until each event meets the corresponding conditions.

[0056] In some embodiments, Figure 4 Another flow chart of the signal insertion loss equalization method provided in the embodiment of the present application is shown. Figure 4 As shown, the steps of updating the second equalization parameter according to a preset linear equalization algorithm based on the equalized output signal, and obtaining the feedback tap coefficient of the decision feedback equalizer through the decision feedback equalizer based on the equalized output signal also include:

[0057] The digital signal corresponding to the feedback tap coefficient is converted into an analog signal, and a subtraction operation is performed on the equalized output signal and the analog signal to generate an equalized intersymbol interference reduction signal.

[0058] Based on the equalized intersymbol interference reduced signal, the second equalization parameter is updated according to a linear equalization algorithm.

[0059] A decision feedback equalizer is used to perform decision feedback equalization processing on the equalized inter-symbol interference reduced signal, and a feedback tap coefficient of the decision feedback equalizer is obtained to update the feedback tap coefficient.

[0060] The feedback tap coefficient in the initialization phase is a preset feedback value.

[0061] Optionally, in an embodiment of the present application, after obtaining the feedback tap coefficients of the decision feedback equalizer through the decision feedback equalizer, in addition to weighting the feedback tap coefficients according to preset weights, the feedback tap coefficients are also digital-to-analog converted and superimposed with the equalized output signal. Specifically, a subtraction operation is performed between the two to generate an equalized inter-symbol interference reduction signal, thereby eliminating part of the inter-symbol interference of the equalized output signal to improve the signal quality of the equalized output signal. The second equalization parameter and the feedback tap coefficients are then updated based on the equalized inter-symbol interference reduction signal to achieve an update of the first equalization parameter. The first and second equalization parameters obtained based on the equalized inter-symbol interference reduction signal will also be superior to the first and second equalization parameters obtained based on the equalized output signal. In the initial stage, the feedback tap coefficients can be set to a preset feedback value, thereby performing a digital-to-analog conversion on the preset feedback value and performing a subtraction operation with the initially received equalized output signal. The preset feedback value can be set to any value including zero. Among them, the digital-to-analog conversion of the feedback tap coefficient can be achieved through a digital-to-analog conversion circuit, and the subtraction operation of the equalized output signal and the feedback tap coefficient can be achieved through an adder circuit. Regardless of the digital-to-analog conversion circuit or the adder circuit, its specific circuit structure is a known technical means in the field, and the embodiments of the present application are not improvements to these two parts of the structure, so the detailed structure of these two parts of the circuit will not be repeated here.

[0062] The implementation method of the step of updating the second equalization parameter according to the linear equalization algorithm based on the equalized inter-symbol interference reduced signal and the implementation method of the step of performing decision feedback equalization on the equalized inter-symbol interference reduced signal through a decision feedback equalizer to obtain the feedback tap coefficient of the decision feedback equalizer to update the feedback tap coefficient are the same as the implementation method of the step of updating the second equalization parameter according to the preset linear equalization algorithm based on the equalized output signal and performing decision feedback equalization on the equalized output signal through a decision feedback equalizer to obtain the feedback tap coefficient of the decision feedback equalizer as described above. The difference is that the equalized output signal in the previous article is replaced by the equalized inter-symbol interference reduced signal here. In view of the same implementation method of the two, this step will not be repeated here.

[0063] Based on the signal insertion loss equalization method provided in the above embodiment, the embodiment of the present application further provides a signal insertion loss equalization circuit. Figure 5 A schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown, Figure 5 As shown, the signal insertion loss equalization circuit includes:

[0064] The continuous-time linear equalization module is used to perform first-stage equalization processing and second-stage equalization processing on the original input signal based on the first equalization parameter and the second equalization parameter respectively, to generate an equalized output signal.

[0065] The second-level equalization parameter processing module is used to update the second equalization parameter according to the preset linear equalization algorithm based on the equalized output signal. It can be understood that running the linear equalization algorithm to calculate the equalization value of the continuous-time linear equalizer through the corresponding circuit structure is a known technology in the art, and its circuit structure does not belong to the improvement point of the present application. Therefore, the embodiment of the present application does not describe the specific implementation process of the linear equalization algorithm and the corresponding circuit for implementing the linear equalization algorithm. For example, a conventional second-level equalization parameter processing module includes a voting unit (Vote), a subtraction unit (Subtraction), a shift unit (Shift) and a filter unit (Filter). The voting unit is used to receive the equalized output signal in digital form and count the number of symbols of the continuous-time linear equalization parameter (the embodiment of the present application is only applied to the second-level equalization parameter, so it only refers to the second-level equalization parameter here) that needs to be adjusted in the equalized output signal. The number of symbols is divided into two categories, namely Increase and Decrease, which respectively indicate that the continuous-time linear equalization gain needs to be enhanced and the continuous-time linear equalization gain needs to be weakened. The subtraction unit is used to calculate the difference between Increase and Decrease, so as to determine the adjustment direction of the continuous-time linear equalization gain. If the difference is positive, it means that the continuous-time linear equalization gain is to be increased, and if the difference is negative, it means that the continuous-time linear equalization gain is to be weakened. The shift unit is used to shift the difference result. Specifically, when the difference is small, the difference result is amplified to enhance the adjustment strength, and when the difference is large, the difference result is reduced to avoid overshoot. The difference result amplified or reduced by the shift unit is the second equalization parameter updated by the second-level equalization parameter processing module. The filtering unit is used to smooth and filter the difference result output by the shift unit to enhance its stability. The second-level equalization parameter processing module finally outputs the difference result output by the filtering unit to the continuous-time linear equalization module, so that the continuous-time linear equalization module generates an equalized output signal according to the updated second equalization parameter.

[0066] A decision feedback equalization module is configured to perform decision feedback equalization on the equalized output signal to obtain feedback tap coefficients of the decision feedback equalizer. Optionally, the decision feedback equalization module is a decision feedback equalizer, which is electrically connected to the first-stage equalization parameter processing module to transmit the feedback tap coefficients of the decision feedback equalizer to the first-stage equalization parameter processing module.

[0067] The first-level equalization parameter processing module is configured to weight the feedback tap coefficients according to preset weights to generate weighted coefficients. The module then compares the weighted coefficients with a preset noise threshold. If the weighted coefficients are greater than the noise threshold, the first equalization parameters are updated according to a preset first strategy. If the weighted coefficients are less than the noise threshold, the first equalization parameters are updated according to a preset second strategy. The first strategy includes: Y = X + 1, and Y ≤ Z; the second strategy includes: Y = X, where Y is the updated first equalization parameter, X is the first equalization parameter before the update, and Z is the preset upper limit threshold of the first equalization parameter. Optionally, the first-level equalization parameter processing module is connected to the continuous-time linear equalization module so that the continuous-time linear equalization module generates an equalized output signal based on the updated first equalization parameters.

[0068] In the first-level equalization parameter processing module, the first equalization parameter is configured as a preset first equalization value in the initialization stage; in the second-level equalization parameter processing module, the second equalization parameter is configured as a preset second equalization value in the initialization stage.

[0069] For other details about how the modules in the signal insertion loss equalization circuit implement the above technical solution, please refer to the description of the signal insertion loss equalization method provided in the above invention embodiment, which will not be repeated here.

[0070] In some embodiments, the signal insertion loss equalization circuit provided in the embodiments of the present application is used to implement the signal insertion loss equalization method provided in the above embodiments. It is applied to an equalization architecture that jointly equalizes signals using a decision feedback equalizer and a continuous-time linear equalizer. When this equalization architecture is used to address the channel transmission loss problem caused by signal transmission from the transmitter to the receiver in a serial communication system, the equalization architecture is typically provided at the receiver of the serial communication system, that is, the signal insertion loss equalization circuit provided in the embodiments of the present application is also provided at the receiver of the serial communication system with the equalization architecture. In addition, when the serial communication system is a high-speed serial communication system, the original input signal described in the embodiments of the present application is a high-speed differential signal.

[0071] In some embodiments, Figure 6 FIG. 4 shows a schematic diagram of a continuous time linear equalization module provided in an embodiment of the present application, as shown in FIG. Figure 6 As shown, the continuous time linear equalization module includes:

[0072] A continuous-time linear equalizer is used to perform first-level equalization processing and second-level equalization processing on an original input signal based on a first equalization parameter and a second equalization parameter, respectively, to generate an analog-shaped equalized output signal. It can be understood that the embodiment of the present application is an improvement on the adaptive update of the first equalization parameter of the continuous-time linear equalizer, and the specific circuit structure of the continuous-time linear equalizer and the specific process of equalization processing of the signal belong to the known technology in the field. Therefore, the specific circuit structure of the continuous-time linear equalizer and the specific implementation method of the equalization processing are not described here. In addition, the embodiment of the present application only involves the first equalization parameter and the second equalization parameter, and the third-level equalization, fourth-level equalization and more-level equalization processing that may exist in the continuous-time linear equalizer do not belong to the improvement points of the present application, nor do they constitute a limitation on the scope of protection of the present application, and are not described in detail here.

[0073] The first filtering unit is configured to filter the analog equalized output signal. Optionally, the first filtering unit may be configured as a low-pass filter or other circuit structure having a filtering function. The specific structure of the first filtering unit is not limited herein, as long as it can achieve the filtering function described above.

[0074] The sampling unit is configured to convert the filtered, analog, equalized output signal into a digital, equalized output signal. Optionally, the sampling unit can be configured as a sampler or other circuit structure with a sampling function. The specific structure of the sampling unit is not limited herein, as long as it can achieve the aforementioned sampling function.

[0075] The demultiplexer unit is used to output the digital equalized output signal to the first equalization parameter processing module and the second-stage equalization parameter processing module respectively.

[0076] In some embodiments, these four functional units can also be integrated into a circuit device and defined as a continuous-time linear equalizer. Obviously, this method does not deviate from the technical concept of this application and should still be regarded as within the scope of protection of this application.

[0077] In some embodiments, in the decision feedback equalization module, obtaining the feedback tap coefficient of the decision feedback equalization module includes:

[0078] The feedback tap coefficients corresponding to the decision symbols of the decision feedback equalization module are obtained in ascending order of the time delay of each decision symbol, until a preset number of feedback tap coefficients are obtained. It can be understood that the circuit structure and implementation method of the decision feedback equalizer are both known technical means in the field, which can perform nonlinear compensation for its inter-symbol interference based on the received signal, and dynamically adjust the feedback tap coefficients through an adaptive algorithm to improve the signal quality. Its circuit structure and implementation method do not belong to the improvement points of the present application, so the circuit structure and specific implementation method of the decision feedback to generate the feedback tap coefficients are not described here. Moreover, the embodiment of the present application only needs to obtain the feedback tap coefficients of the decision feedback equalizer for the subsequent update of the first equalization parameter, and does not depend on the final output signal of the decision feedback equalizer, so the final output signal of the decision feedback equalizer is not described here.

[0079] For other details about how the decision feedback equalization module in the above-mentioned signal insertion loss equalization circuit obtains the feedback tap coefficient of the decision feedback equalization module, please refer to the description of the signal insertion loss equalization method provided in the above-mentioned embodiment of the invention, which will not be repeated here.

[0080] In some embodiments, Figure 7 FIG2 shows a schematic diagram of a first-level equalization parameter processing module provided in an embodiment of the present application. Figure 8 Another schematic diagram of the first-stage equalization parameter processing module provided in an embodiment of the present application is shown. Figure 7 and Figure 8 As shown, the first-level equalization parameter processing module includes:

[0081] A state machine unit is used to determine whether the feedback tap coefficient satisfies a preset fourth strategy, where the fourth strategy includes: an update flag corresponding to the feedback tap coefficient update has been updated, and an error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within a preset error range, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range for a preset number of consecutive times. Optionally, the state machine unit is configured to be an initial state, a first state, a second state and a third state. The first state, the second state and the third state respectively correspond to three events: whether the update flag corresponding to the update of the feedback tap coefficient is updated, whether the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is in line with a preset error range, and whether the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is in line with a preset error range for a preset number of consecutive times. The state machine unit starts from the initial state and executes the events corresponding to the first state, the second state and the third state in sequence after receiving the feedback tap coefficient. When any of the events does not meet the corresponding conditions, the state will return to the initial state to wait for receiving the new feedback tap coefficient, and subsequently for the new feedback tap coefficient, the state machine unit will still execute the events corresponding to the first state, the second state and the third state in sequence until each event meets the corresponding conditions.

[0082] A weighting unit is used to perform weighted processing on the feedback tap coefficient according to a preset weight to generate a weighted coefficient, wherein the weight of the feedback tap coefficient satisfies a preset third strategy, and the third strategy includes: the sum of the weights of the feedback tap coefficients is 1, and the smaller the time delay of the decision symbol, the greater the weight of the feedback tap coefficient corresponding to the decision symbol. It can be understood that the circuit for implementing weighted processing of digital signals (feedback tap coefficients) is also a known technology in the field. For example, designers can implement weighted processing through weighting methods such as addition operations, weighted capacitor networks, and weighted resistor networks, and the circuit structure of the weighting unit does not belong to the improvement points of the embodiment of the present application. In view of this, the embodiment of the present application does not limit the circuit structure of the weighting unit.

[0083] A comparison unit is used to compare the weighted coefficient with a preset noise threshold. Optionally, the comparison unit is connected to a state machine unit. When the feedback tap coefficient satisfies the preset fourth strategy, the state machine unit outputs an enable signal to enable the comparison unit. At this time, the comparison unit works to compare the weighted coefficient with the preset noise threshold. It can be understood that the circuit structure of the comparison unit is also a known technical means in the art. For example, it can be directly implemented by a comparator or by designers self-assembling the comparison unit through an operational amplifier. The circuit structure of the comparison unit does not belong to the improvement point of the embodiment of the present application. In view of this, the embodiment of the present application does not limit the circuit structure of the comparison unit.

[0084] The second filtering unit is configured to filter the comparison result output by the comparison unit, thereby enhancing the stability of the output signal. It is understood that the second filtering unit can be configured as a filter or other circuit structure having a filtering function. The specific structure of the second filtering unit is not limited herein, as long as it can achieve the filtering function described above.

[0085] The data holding unit is configured to update the first equalization parameter based on the filtered comparison result output by the second filtering unit, wherein if the weighted coefficient is greater than the noise threshold, the first equalization parameter is updated according to the first strategy; if the weighted coefficient is less than the noise threshold, the first equalization parameter is updated according to the second strategy. It is understood that the circuit capable of implementing the functions of the above-mentioned data holding unit is also a known technology in the art. Obviously, the data holding unit is a conventional holding circuit, and designers can implement this function through combinational logic, hardware description language of programmable logic devices, etc. For example, the improvement of the embodiment of the present application does not lie in the circuit structure. In view of this, the embodiment of the present application does not limit the circuit structure of the data holding unit.

[0086] For other details about the weighting unit, comparison unit, and data holding unit in the above-mentioned signal insertion loss equalization circuit, please refer to the description of the signal insertion loss equalization method provided in the above-mentioned embodiment of the invention, which will not be repeated here.

[0087] In some embodiments, as Figure 7 As shown, in the signal insertion loss equalization circuit provided by the embodiment of the present application, the weighting unit and the state machine unit are parallel structures. When the weighting unit enables the comparison unit to make the comparison unit effective, because the weighting unit and the state machine unit synchronously receive the feedback tap coefficient output by the decision feedback module, when the feedback tap coefficient received by the state machine unit satisfies the fourth strategy, the feedback tap coefficient received by the weighting unit will also satisfy the fourth strategy, that is, at this time, the weighted coefficient received by the comparison unit is obviously also weighted by the feedback tap coefficient that satisfies the fourth strategy.

[0088] In some embodiments, as Figure 8 As shown, in the signal insertion loss equalization circuit provided in the embodiment of the present application, the weighting unit is controlled and enabled by the state machine unit. When the feedback tap coefficient output by the decision feedback device received by the state machine unit at the current moment satisfies the fourth strategy, the weighting unit is enabled to generate a weighted coefficient based on the feedback tap coefficient output by the decision feedback device at the current moment.

[0089] In some embodiments, Figure 9 Another schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown. Figure 10 Another schematic diagram of a signal insertion loss equalization circuit provided in an embodiment of the present application is shown. Figure 9and Figure 10 As shown, the signal insertion loss equalization circuit also includes:

[0090] The digital-to-analog conversion module is used to convert the digital signal corresponding to the feedback tap coefficient into an analog signal.

[0091] The adder module is used to perform a subtraction operation on the analog equalized output signal and the analog signal corresponding to the above-mentioned feedback tap coefficient to generate an equalized inter-symbol interference reduction signal, and output the equalized inter-symbol interference reduction signal to the second-stage equalization parameter processing module and the decision feedback equalization module respectively through the sampling unit and the demultiplexer unit.

[0092] The second-stage equalization parameter processing module is further configured to update the second equalization parameter according to a linear equalization algorithm based on the equalized inter-symbol interference reduction signal.

[0093] The decision feedback equalization module is further used to perform decision feedback equalization processing on the equalized inter-symbol interference reduced signal, and obtain feedback tap coefficients of the decision feedback equalizer to update the feedback tap coefficients.

[0094] In some embodiments, as Figure 9 As shown, the adder module is connected to the first filtering unit to perform a subtraction operation on the filtered analog output signal of the equalized output and the analog signal corresponding to the feedback tap coefficient to generate an equalized inter-symbol interference reduction signal, and output the equalized inter-symbol interference reduction signal to the second-stage equalization parameter processing module and the decision feedback equalization module respectively through the sampling unit and the demultiplexer unit.

[0095] In some embodiments, as Figure 10 As shown, the adder module is connected to the continuous-time linear equalizer to perform a subtraction operation on the equalized output signal in the analog form before filtering and the analog signal corresponding to the feedback tap coefficient to generate an equalized inter-symbol interference reduction signal, and output the equalized inter-symbol interference reduction signal to the second-stage equalization parameter processing module and the decision feedback equalization module respectively through the first filtering unit, the sampling unit and the demultiplexer unit.

[0096] It can be understood that the circuit structure of implementing the digital-to-analog conversion module and the adder module is a known technical means in the art. For example, it can be implemented by a digital-to-analog converter and an adder, and its circuit structure does not belong to the improvement point of the present application. In view of this, the embodiment of the present application does not limit the circuit structure of the digital-to-analog conversion module and the adder module.

[0097] For other details about the digital-to-analog conversion module and the adder module in the above-mentioned signal insertion loss equalization circuit, please refer to the description of the signal insertion loss equalization method provided in the above-mentioned embodiment of the invention, which will not be repeated here.

[0098] The signal insertion loss equalization circuit provided in the embodiment of the present application dynamically adjusts the first-stage equalization gain of the continuous-time linear equalizer according to a preset strategy by weighting the feedback tap coefficient of the decision feedback equalization module and comparing it with the noise threshold, thereby solving the over-equalization problem caused by using the second-stage equalization value as the first-stage equalization value in the equalization architecture in which the decision feedback equalizer and the continuous-time linear equalizer jointly equalize the signal. Therefore, the signal insertion loss equalization circuit provided in the present application can be applied to scenarios with large signal insertion loss as well as scenarios with small signal insertion loss, significantly improving the adaptability and equalization accuracy of the equalization structure to different insertion loss scenarios. Specifically, in the embodiment of the present application, the first equalization parameter is set to be updated according to the preset first strategy or second strategy, and the second strategy makes the first equalization parameter have a maximum value. In the scenario of small insertion loss, the feedback tap coefficient is also small. Therefore, as long as the upper limit threshold of the first equalization parameter is controlled, the first equalization parameter obtained based on the feedback tap coefficient can be maintained at a small value, thereby providing a small gain for the continuous-time linear equalization module. In scenarios with high insertion loss, the interference value of the input signal after equalization is large, and the feedback tap coefficient after the decision feedback equalization module is also large. Therefore, the first equalization parameter obtained based on the feedback tap coefficient can still maintain a large value, thereby improving the equalization effect of the continuous-time linear equalizer and further reducing the equalization pressure of the DFE. Therefore, this method can effectively cope with scenarios with both high and low insertion loss.

[0099] It can be understood that, in specific implementations, the various modules / units contained in the various devices and products described in the above embodiments may be software modules / units, hardware modules / units, or partly software modules / units and partly hardware modules / units.

[0100] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The unit can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0101] The above content is a further detailed description of the present application in conjunction with specific implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered as the scope of protection of the present application.

Claims

1. A method for equalizing signal insertion loss, characterized in that: An equalization architecture for jointly equalizing a signal using a decision feedback equalizer and a continuous time linear equalizer, wherein the equalization method for the signal insertion loss includes: Based on the first equalization parameter and the second equalization parameter, the original input signal is subjected to a first-stage equalization process and a second-stage equalization process respectively by a continuous-time linear equalizer to generate an equalized output signal; Based on the equalized output signal, updating the second equalization parameter according to a preset linear equalization algorithm, and performing decision feedback equalization processing on the equalized output signal through a decision feedback equalizer to obtain feedback tap coefficients of the decision feedback equalizer; Performing weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients; Compare the weighted coefficient with the preset noise threshold, If the weighted coefficient is greater than the noise threshold, updating the first equalization parameter according to a preset first strategy; If the weighted coefficient is less than the noise threshold, updating the first equalization parameter according to a preset second strategy; The first strategy includes: Y=X+1, and Y≤Z; the second strategy includes: Y=X; Y is the updated first balancing parameter, X is the first balancing parameter before the update, and Z is the preset upper limit threshold of the first balancing parameter; Wherein, in the step of performing first-stage equalization processing and second-stage equalization processing on the original input signal based on the first equalization parameter and the second equalization parameter by a continuous time linear equalizer to generate an equalized output signal, The first equalization parameter and the second equalization parameter are dynamically updated, and in an initialization phase, the first equalization parameter is configured as a preset first equalization value, and the second equalization parameter is configured as a preset second equalization value.

2. The signal insertion loss equalization method according to claim 1, wherein: The step of obtaining the feedback tap coefficient of the decision feedback equalizer comprises: The feedback tap coefficients corresponding to the decision symbols of the decision feedback equalizer are obtained in ascending order of the time delay of the decision symbols until a preset number of feedback tap coefficients are obtained.

3. The signal insertion loss equalization method according to claim 2, wherein: In the step of weighting the feedback tap coefficients according to preset weights to generate weighted coefficients, The weight of the feedback tap coefficient satisfies a preset third strategy, and the third strategy includes: The sum of the weights of the feedback tap coefficients is 1, and the smaller the time delay of the decision symbol is, the greater the weight of the feedback tap coefficient corresponding to the decision symbol is.

4. The signal insertion loss equalization method according to claim 1, wherein: After the step of performing decision feedback equalization processing on the equalized output signal by a decision feedback equalizer to obtain feedback tap coefficients of the decision feedback equalizer, and before the step of performing weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients, the method further includes: Determine whether the feedback tap coefficient satisfies a preset fourth strategy, If the feedback tap coefficient satisfies the preset fourth strategy, the steps are sequentially executed: weighting the feedback tap coefficient according to the preset weight to generate a weighted coefficient; If the feedback tap coefficient does not satisfy the preset fourth strategy, returning to the execution step: performing decision feedback equalization processing on the equalized output signal through a decision feedback equalizer to obtain the feedback tap coefficient of the decision feedback equalizer; The fourth strategy includes: The update flag corresponding to the feedback tap coefficient update has been updated, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range for a preset number of consecutive times.

5. The signal insertion loss equalization method according to claim 1, wherein: The step of updating the second equalization parameter according to a preset linear equalization algorithm based on the equalized output signal, and obtaining the feedback tap coefficient of the decision feedback equalizer through a decision feedback equalizer based on the equalized output signal further includes: Converting the digital signal corresponding to the feedback tap coefficient into an analog signal, performing a subtraction operation on the equalized output signal and the analog signal to generate an equalized intersymbol interference reduced signal; Based on the equalized intersymbol interference reduced signal, updating the second equalization parameter according to the linear equalization algorithm; performing decision feedback equalization processing on the equalized inter-symbol interference reduced signal through the decision feedback equalizer, obtaining feedback tap coefficients of the decision feedback equalizer to update the feedback tap coefficients; Wherein, the feedback tap coefficient in the initialization stage is a preset feedback value.

6. A signal insertion loss equalization circuit, characterized in that: include: A continuous-time linear equalization module, configured to perform a first-stage equalization process and a second-stage equalization process on the original input signal based on the first equalization parameter and the second equalization parameter, respectively, to generate an equalized output signal; a second-stage equalization parameter processing module, configured to update the second equalization parameters according to a preset linear equalization algorithm based on the equalized output signal; A decision feedback equalization module, configured to perform decision feedback equalization processing on the equalized output signal and obtain feedback tap coefficients of the decision feedback equalization module; The first-stage equalization parameter processing module is used to perform weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients, and compare the weighted coefficients with a preset noise threshold. If the weighted coefficient is greater than the noise threshold, updating the first equalization parameter according to a preset first strategy; If the weighted coefficient is less than the noise threshold, updating the first equalization parameter according to a preset second strategy; The first strategy includes: Y=X+1, and Y≤Z; the second strategy includes: Y=X; Y is the updated first balancing parameter, X is the first balancing parameter before the update, and Z is the preset upper limit threshold of the first balancing parameter; In the first-level equalization parameter processing module, the first equalization parameter is configured as a preset first equalization value during the initialization phase; in the second-level equalization parameter processing module, the second equalization parameter is configured as a preset second equalization value during the initialization phase.

7. The signal insertion loss equalization circuit according to claim 6, wherein: The continuous time linear equalization module includes: A continuous-time linear equalizer is configured to perform a first-stage equalization process and a second-stage equalization process on an original input signal based on a first equalization parameter and a second equalization parameter, respectively, to generate an equalized output signal in an analog form; a first filtering unit, configured to filter the equalized output signal of the analog form; a sampling unit, configured to convert the filtered analog balanced output signal into a digital balanced output signal; The demultiplexer unit is configured to output the equalized output signal in digital form to the first-stage equalization parameter processing module and the second-stage equalization parameter processing module respectively.

8. The signal insertion loss equalization circuit according to claim 6, wherein: In the decision feedback equalization module, obtaining the feedback tap coefficient of the decision feedback equalization module includes: The feedback tap coefficients corresponding to the decision symbols of the decision feedback equalization module are obtained in ascending order of the time delay of the decision symbols until a preset number of feedback tap coefficients are obtained.

9. The signal insertion loss equalization circuit according to claim 6, wherein: The first-level equalization parameter processing module includes: a state machine unit, configured to determine whether the feedback tap coefficient satisfies a preset fourth strategy, the fourth strategy comprising: an update flag corresponding to the feedback tap coefficient update has been updated, an error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within a preset error range, and the error between the updated feedback tap coefficient and the feedback tap coefficient before the update is within the preset error range for a consecutive preset number of times; a weighting unit, configured to perform weighted processing on the feedback tap coefficients according to preset weights to generate weighted coefficients, wherein the weights of the feedback tap coefficients satisfy a preset third strategy, the third strategy including: the sum of the weights of the feedback tap coefficients is 1, and the smaller the time delay of the decision symbol, the greater the weight of the feedback tap coefficient corresponding to the decision symbol; a comparing unit, configured to compare the weighted coefficient with a preset noise threshold; a second filtering unit, configured to perform filtering processing on the comparison result output by the comparison unit; a data holding unit, configured to update the first equalization parameter based on the filtered comparison result output by the second filtering unit, wherein if the weighted coefficient is greater than the noise threshold, the first equalization parameter is updated according to the first strategy; and if the weighted coefficient is less than the noise threshold, the first equalization parameter is updated according to the second strategy.

10. The signal insertion loss equalization circuit according to claim 7, wherein: Also includes: A digital-to-analog conversion module, configured to convert the digital signal corresponding to the feedback tap coefficient into an analog signal; an adder module, configured to perform a subtraction operation on the equalized output signal in analog form and the analog signal to generate an equalized inter-symbol interference reduction signal, and output the equalized inter-symbol interference reduction signal to the second-stage equalization parameter processing module and the decision feedback equalization module respectively through the sampling unit and the demultiplexer unit; The second-stage equalization parameter processing module is further configured to update the second equalization parameter according to the linear equalization algorithm based on the equalized inter-symbol interference reduced signal; The decision feedback equalization module is further configured to perform decision feedback equalization processing on the equalized inter-symbol interference reduced signal, and obtain feedback tap coefficients of the decision feedback equalizer to update the feedback tap coefficients; Wherein, the feedback tap coefficient in the initialization stage is a preset feedback value.

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