Loop bandwidth control for fractional crossover frequency synthesizer

Abstract

In an example, a system includes a phase locked loop (100) including a charge pump (104) coupled to a phase frequency detector (102), a low pass filter (106) coupled to the charge pump (104), and a VCO (108) coupled to the low pass filter (106), where the charge pump (104) is configured to provide a charge pump current (126) to the low pass filter (106). The system also includes a current source (114) configured to provide a bias current (130) to the charge pump (104). The system includes a first bias compensation circuit (116) configured to increase the bias current (130) in response to a control voltage (128) provided to the VCO (108) being within a first range. The system also includes a second bias compensation circuit (116) configured to reduce the bias current (130) in response to the control voltage (128) provided to the VCO (108) being within a second range.

Description

Background Art

[0001] A phase-locked loop (PLL) is a system that compares the frequency of a local oscillator to the frequency of a received input signal and uses a feedback loop to lock the local oscillator's frequency to the received input signal's frequency. The local oscillator's output frequency can be a multiple of the input frequency. A PLL may include a phase-frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). Frequency synthesizers in frequency-modulated continuous wave (FMCW) radar systems (such as those used in automotive and industrial applications) can use a PLL to transmit a signal with a frequency that ramps up over time (called a chirp signal). Summary of the Invention

[0002] According to at least one example of the described content, a system includes a phase-locked loop (PLL) comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a voltage-controlled oscillator (VCO) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter. The system also includes a current source configured to provide a bias current to the charge pump. The system includes a first bias compensation circuit configured to increase the bias current in response to a control voltage provided to the VCO being within a first range. The system also includes a second bias compensation circuit configured to decrease the bias current in response to a control voltage provided to the VCO being within a second range.

[0003] According to at least one example of the described content, a method includes providing a bias current to a charge pump in a phase-locked loop (PLL) using a current source. The method also includes providing a control voltage to a VCO in the PLL, wherein the control voltage is provided in response to a charge pump current from the charge pump. The method includes increasing the bias current provided to the charge pump using a first bias compensation circuit in response to the control voltage being within a first range. The method also includes decreasing the bias current provided to the charge pump using a second bias compensation circuit in response to the control voltage being within a second range.

[0004] According to at least one example of the described content, a system includes a phase-locked loop (PLL) comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a voltage-controlled oscillator (VCO) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter, the low-pass filter is configured to provide a control voltage to the VCO, and the gain of the VCO varies with the control voltage. The system also includes a current source configured to provide a bias current to the charge pump, wherein the charge pump current varies with the bias current. The system includes a voltage threshold generator configured to provide a first voltage range and a second voltage range. The system also includes a first bias compensation circuit configured to increase the bias current in response to the control voltage provided to the VCO being within the first voltage range. The system also includes a second bias compensation circuit configured to decrease the bias current in response to the control voltage provided to the VCO being within the second voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a PLL according to various examples.

[0006] Figure 2 is a graph of VCO gain and VCO control voltage according to various examples.

[0007] Figure 3 is a block diagram of a PLL according to various examples.

[0008] Figure 4 is a block diagram of a circuit for varying charge pump current according to various examples.

[0009] Figure 5 is a block diagram of a circuit for varying charge pump current according to various examples.

[0010] Figure 6 is a block diagram of an FMCW radar system including an FMCW radar system-on-chip (SOC) according to various examples.

[0011] Figure 7 is a flow chart of a method for adjusting a charge pump current in a PLL according to various examples.

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (functionally and / or structural) features. DETAILED DESCRIPTION

[0013] The PLL receives at its input an input reference signal F with a relatively stable frequency IN , and produces an output signal at the output whose frequency is a multiple of the reference signal, called F OUTThe PLL also uses the input signal to lock the phase of the output signal. The PLL may contain a PFD followed by a charge pump. The PFD receives a reference signal F at its two inputs. IN and feedback signal F FBK , and determines whether one of the two inputs has a slower frequency or a lagging phase. The PFD provides one or more phase error output signals (e.g., an up signal and a down signal). The charge pump receives the phase error output signals from the output of the PFD and converts these signals into currents that push or pull in the loop filter. The charge pump generates the control voltage V for the VCO CTRL , which controls the frequency of the VCO. A loop filter can be located between the charge pump and the VCO.

[0014] For automotive and industrial radar systems, a PLL can be used to generate a radar frequency signal for transmission that has a consistent amplitude and a frequency that varies (e.g., increases) generally linearly over time from a lower frequency limit to an upper frequency limit. The chirp signal generated by the PLL can have a wide bandwidth. Therefore, it is beneficial for the VCO to have a wide continuous tuning range to generate a chirp signal with a wide bandwidth. The VCO may include a varactor, which is a voltage-controlled capacitor, that is used to control the frequency of the radar frequency output signal. By varying the control voltage V CTRL To change the capacitance of the varactor, this produces a frequency change in the chirp signal. CTRL The relationship between VCO gain and frequency is called VCO gain (e.g., K VCO ) and is expressed in Hertz / V (Hz / V). K VCO Can follow V CTRL If K VCO With V CTRL The loop bandwidth can also change with the change of V CTRL If the loop bandwidth is not consistent across the chirp, phase noise variations may occur, with some frequencies being noisier than others. In addition, the loop bandwidth may have to be constrained to a worst-case scenario (e.g., highest K VCO ), which may allow excessive reference clock noise.

[0015] In this example, the charge pump current I CP Can be used with V CTRL changes to compensate for the V CTRL The change of K VCO As described below, the loop bandwidth is related to K VCO and the charge pump current I CP The two are proportional. Therefore, if K VCO For the first range of V CTRL If the value is low, you can increase I CPAssuming the first range of V CTRL The value provides consistent bandwidth. If K VCO For the second range of V CTRL If the value is high, you can reduce I CP The second range of V CTRL The value provides consistent bandwidth. CP can be used to generate chirp across the V CTRL The entire range of values ​​is related to K VCO The change in V CTRL The circuit system increases or decreases the bias current supplied to the charge pump to change the value of I CP In one example, one or more current-steering digital-to-analog converters (DACs) are used to change the I CP The current steering DAC can have a variety of configurations. In this example, the current steering DAC has a binary input and produces an analog output in the form of a current based on the voltage value provided at the binary input. The current steering DAC can be tuned or fine-tuned to provide the appropriate current to compensate for the K of a given VCO. VCO Using the examples presented in this paper, the full bandwidth of the chirp can be generated by a single VCO, which reduces the area and power consumption of the radar system.

[0016] Figure 1 is a block diagram of a PLL circuit 100 according to various examples herein. In one example, PLL 100 is a fractional-frequency PLL. A fractional-frequency PLL can generate output frequencies that are not limited to integer multiples of an input frequency. The fractional-frequency PLL includes additional circuitry that enables it to accurately interpolate between integer multiples of a reference frequency. PLL 100 includes a PFD 102, a charge pump (CP) 104, a low-pass filter (LPF) 106, and a VCO 108. PLL 100 also includes a frequency divider 110, a Σ-Δ modulator 112, and a bias current source 114. A DAC 116 is coupled to bias current source 114.

[0017] The PFD 102 includes a received reference signal F IN The first input 118 receives the feedback signal F FBK The PFD 102 is based on the reference signal F IN With the feedback signal F FBK The difference between the PFD 102 and the charge pump 104 provides an up or down signal (e.g., UP signal 122 or DN signal 124) to the charge pump 104. If the PFD 102 sends an UP signal to the charge pump 104, the charge pump 104 delivers a pull-up current to the LPF 106. The charge pump current is shown as I CP 126. Pull-up current increases voltage V CTRL128, which is provided by LPF 106 to VCO 108. If PFD 102 sends a DN signal to charge pump 104, charge pump 104 pulls down the current from LPF 106, which reduces V CTRL 128. The base current provided by the charge pump 104 and the I provided by the bias current source 114 BIAS 130 is proportional. Increase or decrease I BIAS 130 will result in I CP 126 increase or decrease. With I CP 126 changes, providing V to VCO 108 CTRL 128 changes. VCO 108 receives V CTRL 128 signals and generate F OUT Signal 132, where F OUT The frequency is based on V CTRL 128. In PLL 100, frequency divider 110 provides feedback, and Σ-Δ modulator 112 allows for feedback that is not integer-based. Frequency divider 110 can provide integer values, and Σ-Δ modulator 112 allows for values ​​between integers by rapidly sending alternating integer values. In one example, a chirp profile provides a chirped frequency range.

[0018] Because the PLL 100 is used to generate a signal F that varies with time in a carefully controlled manner OUT 132, so it is beneficial for the PLL 100 to have a consistent, linear, and predictable response to various control signals. As mentioned above, V CTRL 128 and F OUT 132 may not be linear, and in some embodiments, by adjusting the influence of V CTRL 128 control (for example, I CP 126) to apply compensation.

[0019] In one example, K is determined for PLL 100 through testing. VCO With V CTRL 128. Ideally, K VCO is flat and does not change with V CTRL 128. However, testing can show that, if Figure 2 As shown, K VCO For V CTRL 128 is high for some ranges, and for V CTRL The other ranges of 128 are low. Figure 1 DAC 116 is configured to be based on V CTRL 128 value to increase or decrease I BIAS130. The DAC 116 can push or pull current into or out of the bias current source 114 to change the I BIAS 130, thus the V CTRL 128 application adjustment. With V CTRL 128 changes, K VCO will change, and change I via DAC 116 BIAS 130 to offset K VCO The change across V CTRL The range of 128 values ​​produces a consistent bandwidth. Each DAC 116 is an example of an offset compensation circuit, and other embodiments may include other types of offset compensation circuits to respond to V CTRL 128 to control the bias current I BIAS 130. Below is about Figure 2-6 Provide additional description of this process.

[0020] Figure 2 is based on the K of each instance VCO With V CTRL 128. In the graph 200, the x-axis represents V in volts. CTRL 128. The y-axis represents K in Hz / V VCO Graph 200 has two curves 202 and 204. Curve 202 represents a first example VCO, labeled VCO1, which may be typical of a 77 GHz automotive radar system. Curve 204 represents a second example VCO, labeled VCO2, which may be typical of a 60 GHz automotive or industrial radar system. In one example, VCO1 has a 1.25 GHz bandwidth and VCO2 has a 2.33 GHz bandwidth, and these bandwidths can be multiplied to provide higher frequencies using circuitry not shown herein.

[0021] As shown in graph 200, K VCO With V CTRL 128. For example, at 0.4V V CTRL At 128, VCO2's K VCO (curve 204) is approximately 1.2 x 10 9 Hz / V. At 0.9V V CTRL At 128, VCO2's K VCO is approximately 3.2x10 9 Hz / V. Finally, at 1.3V V CTRL At 128, VCO2's K VCO is approximately 2.1x 10 9Hz / V. Curve 202 for VCO1 shows a similar pattern. The third-order waveforms shown for curves 202 and 204 indicate that an example VCO with a wide tuning range may have a K that varies in a nonlinear manner. VCO The examples in this article provide a method for changing the charge pump current I CP 126 to offset the K shown in the graph 200 VCO Systems and methods for reducing the nonlinearity of a curve and producing a uniform loop bandwidth.

[0022] Figure 3 is a block diagram of a PLL 100 according to various examples herein. Figure 1 The components of PLL 100 and its operation are described. Figure 3 is a phase domain block diagram showing the phase transfer function of PLL 100. In this example, LPF 106 includes resistor R Z 302 and capacitor C 304. The phases of the signal are Figure 3 is marked. For example, Φ IN (s) 306 is the input reference signal F IN The phase, Φ FBK (s) 308 is the feedback signal F FBK The phase of Φ E (s)310 is the phase error signal, Φ OUT (s)312 is F OUT The phase of signal 132. The phase transfer function of PLL 100 is shown in equation (1):

[0023]

[0024] In equation (1), Φ E (s) is the phase error signal, M is the feedback division ratio of the frequency divider 110, I CP is the charge pump current I CP 126, K VCO is the VCO gain in Hz / V. In equation (1), R Z is the zero resistor of LPF 106, and C is the capacitor 304. The bandwidth (BW) of this example PLL 100 can be estimated by equation (2):

[0025] BW~(I CP *K VCO *R Z ) / (2*π*M) (2)

[0026] Therefore, the bandwidth is related to the charge pump current I CP 126.K VCO and R ZAs shown in equation (2), if K VCO If the change is large, the bandwidth will also change. Figure 2 shows that for some VCOs, K VCO With V CTRL 128. Therefore, as V CTRL 128 changes to produce chirp, the loop bandwidth will also vary. As described above, if the loop bandwidth is not consistent across chirps, phase noise variations may result. In addition, the loop bandwidth may have to be constrained to the worst case scenario (e.g., the highest K VCO ), which reduces the bandwidth of the chirp signal.

[0027] Equation (2) shows that the bandwidth increases with K VCO However, the bandwidth also varies with I CP 126 changes. The other values ​​in equation (2) are constant. Therefore, in order to cross V CTRL A value of 128 produces a consistent bandwidth, I CP 126 can be connected with V CTRL K caused by the change of 128 VCO As an example, if K VCO For a given V CTRL 128 is low, then I CP 126 can be raised. If K VCO For a given V CTRL 128 is high, then I CP 126 can be reduced by VCO With V CTRL 128 changes to adjust I CP 126, a more consistent bandwidth can be achieved with the PLL 100. In the example herein, the current steering DAC 116 is configured to CTRL 128 value to increase or decrease I BIAS 130. The DAC 116 can push or pull current into or out of the bias current source 114 to change the I BIAS The value of 130. CP 126 with I BIAS 130 changes, so this process makes I CP 126 With V CTRL 128 changes and compensates for the cross-V CTRL 128 range of K VCO changes.

[0028] Figure 4 It is used to make I according to each example of this article CP126 changes. The circuit 400 includes one or more DACs 116 that push or pull current into or out of the bias current source 114 to change I BIAS The value of 130 makes I CP 126 changes. DAC 116 is configured to CTRL As described above, each DAC 116 is an example of an offset compensation circuit, and other embodiments may include other types of offset compensation circuits to respond to V CTRL 128 to control the bias current I BIAS 130.

[0029] Circuit 400 includes bias current source 114, charge pump 104, DACs 116A, 116B, and 116C (collectively, DACs 116), and a threshold generator 402. In other examples, any number of DACs 116 may be present. In this example, three DACs are useful. Threshold generator 402 may include a memory configured to store a voltage threshold for each DAC 116 that governs when the corresponding DAC 116 is active and the threshold for V CTRL 128. In some examples, threshold generator 402 can be a voltage threshold generator circuit and include any suitable circuitry for generating a threshold voltage, such as a resistor network. In another example, threshold generator 402 can be circuitry configured to provide a voltage threshold. Threshold generator 402 generates V for DAC 116A. THRESH1 404A, V for DAC116B THRESH2 404B and V for DAC 116C THRESH3 404C. Each DAC 116 also receives V CTRL 128, so DAC116 can convert V CTRL 128 is compared to the voltage threshold of the DAC and is turned on or off based on the comparison. Turning the DAC 116 on or off pushes or pulls current into or out of the bias current source 114 to adjust I CP 126.

[0030] The bias current source 114 generates I CP 126. In this example, this baseline current is I CONST 406. Based on V by DAC 116 CTRL The value of the current provided is the adjusted current I ADJUST 408. In the examples herein, I ADJUST 408 can be positive or negative. CONST 406 and IADJUST 408 combined to form I BIAS 130, which is provided to the charge pump 104. The charge pump 104 is based on I BIAS The value of 130 provides I to LPF 106. CP 126. If I BIAS 130 increases, then I CP 126 increase. If I BIAS 130 decreases, then I CP 126 decreased.

[0031] As shown in equation (2) above, the loop bandwidth is related to I CP 126 and K VCO If K VCO If it is low, you can increase I CP 126 to balance the loop bandwidth. If K VCO If it is high, you can reduce I CP 126 to balance the loop bandwidth. VCO With V CTRL 128 changes, so V CTRL The value of 128 can be used to determine whether to increase or decrease I CP 126. DAC 116 each receives V CTRL 128 and V CTRL 128 and V received from threshold generator 402 THRESH The values ​​are compared. Each DAC 116 will then be turned on or off in response to the comparison. In this example, DAC 116A and DAC 116C are boost DACs. If the boost DACs are turned on, they will provide power to the I ADJUST 408 provides positive current. In this example, DAC 116B is an attenuation DAC. If the attenuation DAC is turned on, they are ADJUST 408 pulls current. Therefore, by CTRL The value of 128 selectively turns DAC 116 on or off, which can change the I ADJUST 408 Change I BIAS 130, which in turn changes the I CP 126 K for changes VCO Make adjustments.

[0032] In one example, the K of PLL 100 VCO The curve is Figure 2 Curve 204 in FIG. Figure 2 As shown, if V CTRL 128 is low (e.g., less than 600mV), then K VCO Therefore, if no compensation is performed, for VCTRL 128, the loop bandwidth will be lower. In this example, if V CTRL 128 is less than 600mV, DAC 116A is turned on. THRESH1 404A is set at approximately 600mV. DAC 116A sets V CTRL 128 and V THRESH1 404A is compared. If V CTRL 128 is lower, then coupled to V CTRL The transistor in the 128-input DAC 116A turns on and increases the current I1 410A provided by the DAC 116A, thereby increasing the current I ADJUST 408. The DAC 116 can use current mirrors and other internal circuitry to push or pull current, as described herein. In this example, if V CTRL 128 is below 600mV, DACs 116B and 116C are shut down. Therefore, if V CTRL 128 is below 600 mV, the current I2 410B from DAC 116B and the current I3 410C from DAC 116C are approximately zero. CTRL 128 When I is lower than 600mV ADJUST The increase of 408 will increase I CP 126, which compensates for this V CTRL 128 range low K VCO (like Figure 2 shown).

[0033] With V CTRL 128 rises above 600mV, DAC 116A shuts down and stops supplying current I1 410A. If V CTRL 128 is between 600mV and 1100mV, DAC 116B is turned on. DAC 116B can be configured to CTRL 128 is turned on within any suitable voltage range. If V CTRL 128 is between the voltage range of 600 to 1100 mV in this example, then DAC 116B is turned on. DAC 116B is an attenuation DAC and is switched from I BIAS 130 pulls current. Current I2 410B is the current that is drawn from the charge pump 104, and therefore when the DAC 116B is on, I ADJUST 408 is negative during this phase. If DAC 116B sources or sinks current, then V CTRL If 128 is within the above range, I CP 126 down. Figure 2As shown, if V CTRL 128 is between approximately 600 and 1100 mV, then K VCO is high, so I CP 126 should be reduced to compensate within this voltage range. If K VCO is high, then an attenuation DAC such as DAC 116B reduces I CP 126, and therefore across this V CTRL The 128 range provides more consistent bandwidth.

[0034] In this example, as V CTRL 128 rises above 1100 mV, DAC 116B turns off and current I2 410B drops to zero. DAC 116C is configured to CTRL 128 turns on when it reaches approximately 1100mV. For V CTRL 128, DAC 116C to I ADJUST 408 provides current I3 410C. DAC 116C is a boost DAC and provides positive current I3 410C. CTRL 128 In this voltage range, I ADJUST 408 increases, thus making I CP 126 increases. Because K VCO For higher V CTRL 128 is a lower value (such as Figure 2 So for this voltage range, I CP 126 compensates for the lower K VCO , and across V CTRL The full voltage range of 128 provides a flatter bandwidth.

[0035] Reference again Figure 2 , such as curve 204 and other examples K VCO The curve indicates that at low V CTRL Lower K at 128 VCO , in the medium range V CTRL Higher K at 128 VCO , as well as at high V CTRL Lower K at 128 VCO DAC 116 operates at low V CTRL 128 additional I CP 126. In the medium range V CTRL 128 places reduce I CP 126, as well as at high V CTRL 128 places added I again CP 126 to compensate for this change in KVCO As shown in equation (2), the loop bandwidth is proportional to I CP 126 and K VCO The product of is proportional to. VCO When it is low, I CP 126 and in K VCO When it is high, reduce I CP 126, cross V CTRL The 128 range achieves a more consistent bandwidth.

[0036] In other examples, a different number of DACs 116 may be useful. Figure 2 The third-order K shown VCO Curves 202 and 204 (or similar curves) can be used Figure 4 The three DACs 116 shown are compensation, two boost DACs 116 and one attenuation DAC 116. In other examples, K VCO The curve may have different shapes, and different configurations of DAC 116 may be useful. Other examples may use only one or two DACs 116 to provide compensation. VCO In another example of the curve, more than three DACs 116 may be useful. The DACs 116 may also be configured for any range of V CTRL 128 values. In some examples, the attenuation DAC 116 can be used for low or high V CTRL 128 values, while the boost DAC 116 can be used for mid-range V CTRL 128 values. DAC 116 and threshold V THRESH Any suitable configuration of 404 may be useful in other instances.

[0037] Turning the DAC 116 on or off CTRL The value of 128 is an example, and other voltage values ​​may be used in other examples. Also, in some examples, the ranges for turning on the DAC 116 may overlap. For example, for V CTRL A small window of 128, based on V THRESH1 404A and V THRESH2 404B, both DAC 116A and DAC 116B can be turned on. With V CTRL 128 to increase or decrease, one of the DACs 116A or 116B can be as determined by V THRESH The value is determined and the device is turned off.

[0038] The bias current source 114 may include any suitable circuitry to provide the current I CONST 406, the current and I ADJUST408 combination to produce I BIAS 130. Threshold generator 402 may include any suitable circuitry to provide a voltage threshold V to DAC 116. THRESH 404, which determines when the DAC 116 is turned on or off. In one example, the threshold generator 402 includes a resistor network with multiple taps, and a specific tap is selected for each DAC 116 to provide the appropriate V THRESH 404.

[0039] In an example, K is determined through testing for a given PLL 100. VCO Curve (such as Figure 2 Then, one can implement, for example Figure 4 The circuit system described in (eg, DAC 116 and threshold generator 402) is configured to generate a threshold value based on a given V CTRL 128 Provide what you need CP 126. The circuitry can be fine-tuned or tuned to provide appropriate voltage thresholds for turning DAC 116 on and off, and for providing appropriate amounts of current (e.g., currents 410A, 410B, and 410C) from DAC 116. In other examples, any suitable circuitry may be useful. The use of bias current source 114, DAC 116, and threshold generator 402 is one example of implementing the system described herein.

[0040] Figure 5 It is used to change I according to various examples in this article CP 126. The circuit 500 includes the above Figure 1 Components of the PLL 100 described in FIG. 5. Circuit 500 also includes a number (denoted by “A”) of attenuation DACs 116 and a number (denoted by “B”) of boost DACs 116. In the examples herein, A and B can be any number. Circuit 500 shows how the DACs 116 are configured to respond to V CTRL The value of 128 is used to increase or decrease the current I BIAS 130.

[0041] In the circuit 500, B boost DACs 116 are shown, numbered from <0> arrive <b-1>Each boost DAC 116 includes a representative current source 502 and a voltage comparator 504. DAC 116 <b-1>The current source 502 generates a current I BOOST,B-1 , which in one example is current 410 (as described above with respect to Figure 4 Based on the voltage comparator 504, the current I BOOST,B-1 Provide to I ADJUST 408. The voltage comparator 504 receives V at a first input. CTRL 128 and receives V at the second input BOOST,B-1 In this example, V BOOST,B-1 As mentioned above Figure 4 The threshold voltage V THRESH 404. Based on the control voltage V CTRL 128 and V BOOST,B-1 Comparison between DAC 116 <b-1>If the DAC 116 <b1>When it is turned on, the current I BOOST,B-1 Provided to I ADJUST 408, and with I BIAS 130 combinations to increase I CP 126. If DAC 116 <b-1>If the boost DAC 116 is off, it does not provide current. In the examples herein, any number of boost DACs 116 may exist, and V BOOST (For example, V THRESH ) can be configured to CTRL 128 value, the boost DAC 116 is turned on to compensate for the change in K VCO .

[0042] Similarly, "A" attenuation DACs 116 are shown, numbered from <0> arrive <a-1>Each attenuation DAC 116 includes a representative current source 508 and a voltage comparator 506. DAC 116 <a-1>The current source 508 generates a current I ATTEN,A-1 , which in one example is current 410 (as described above with respect to Figure 4 Based on the voltage comparator 506 from I ADJUST 408 pull current I ATTEN,A-1 The voltage comparator 506 receives V CTRL 128 and receives V at the second input ATTEN,A-1 In this example, V ATTEN,A-1 As mentioned above Figure 4 The threshold voltage V THRESH 404. Based on V CTRL 128 and V ATTEN,A-1 Comparison between DAC 116 <a-1>If the DAC 116 <a-1>When it is turned on, the current I ATTEN,A-1 From I ADJUST 408 pulls and reduces I BIAS 130 to reduce I CP 126. If DAC 116 <a-1>If the attenuation DAC 116 is off, it does not draw current. In the examples herein, there may be any number of attenuation DACs 116, and V ATTEN The value (for example, V THRESH ) can be configured to CTRL 128 turns on the attenuation DAC 116 to compensate for the changing K VCO .

[0043] Figure 5 The PLL shown in FIG1 operates similarly to the PLL 100 described above. The charge pump 104 provides I to the LPF 106. CP 126. LPF 106 provides V to VCO 108 CTRL 128, and VCO 108 is based on V CTRL A value of 128 provides an output signal F OUT 132. In order to cross V CTRL The range of 128 values ​​provides a stable bandwidth, as described herein, using DAC 116 to make I CP 126 changes to compensate for the change in K VCO .

[0044] Figure 6 6 is a block diagram of an FMCW radar system including an FMCW radar SOC according to various examples herein. The radar system includes a processing unit 650 and an FMCW radar SOC 600. In some examples, the processing unit 650 is integrated into the FMCW radar SOC 600. The radar SOC 600 may include multiple transmit channels 604 for transmitting FMCW signals and multiple receive channels 602 for receiving reflected transmitted signals. Furthermore, the number of receive channels may be greater than the number of transmit channels. For example, the radar SOC 600 may have two transmit channels and four receive channels. The transmit channels include suitable transmitters and antennas, while the receive channels include suitable receivers and antennas. Furthermore, each of the receive channels 602 is identical and includes mixers 606, 608 for mixing the transmitted signal with the received signal to generate a beat signal (alternatively referred to as a dechirped signal, an intermediate frequency (IF) signal, or the original radar signal), baseband bandpass filters 610, 612 for filtering the beat signal, variable gain amplifiers (VGAs) 614, 616 for amplifying the filtered beat signal, and analog-to-digital converters (ADCs) 618, 620 for converting the analog beat signal into a digital beat signal.

[0045] The receive channel 602 is coupled to a digital front end (DFE) 622, which performs decimation filtering on the digital beat signal to reduce the sampling rate and return the signal to baseband. The DFE 622 may also perform other operations on the digital beat signal, such as direct current (DC) offset removal. The DFE 622 is coupled to a high-speed interface component 624 to pass the output of the DFE 622 to the processing unit 650.

[0046] Processing unit 650 can execute all or part of the method for operating a radar system on the received digital beat signal. Processing unit 650 can include any suitable processor or combination of processors 651. For example, processing unit 650 can be a digital signal processor, a microcontroller unit (MCU), an FFT engine, a DSP+MCU processor, a field programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In some examples, processing unit 650 and / or memory component 652 are integrated into FMCW radar SOC 600.

[0047] Memory component 652 provides a storage area, such as a non-transitory computer-readable medium, which can be used, for example, to store software instructions, such as any software instructions for implementing the operations described herein, for execution by processing unit 650. Memory component 652 can include any suitable combination of read-only memory (ROM) and / or random access memory (RAM) (e.g., static RAM).

[0048] Control component 626 includes functionality to control the operation of radar SOC 600. Control component 626 may include, for example, an MCU that executes software to control the operation of radar SOC 600 between a detection mode and an operational mode.

[0049] A serial peripheral interface (SPI) 628 provides an interface for communicating with the processing unit 650. For example, the processing unit 650 may use the SPI 628 to send control information to the radar SOC 600, such as the timing and frequency of chirps, the enabling of transmit antennas and the timing between transmit antennas, output power levels, triggering of monitoring functions, etc.

[0050] Programmable timing engine 642 includes functionality to receive chirp parameter values ​​for a sequence of chirps in a radar frame from control component 626 and generate chirp control signals that control the transmission and reception of chirps in the frame based on the parameter values, including timing between chirps generated by different transmit antennas in a classification mode and timing between chirps generated by the same transmit antenna in a detection mode.

[0051] Radio frequency synthesizer (RFSYNTH) 630 includes functionality to generate an FMCW signal for transmission based on a chirp control signal from timing engine 642. In some examples, RFSYNTH 630 includes a PLL with a VCO. In one example, the PLL is PLL 100 as described herein.

[0052] Clock multiplier 640 increases the frequency of the transmission signal from RFSYNTH 630 to the frequency of mixers 606 and 608. Cleanup PLL 634 is used to increase the frequency of the signal of an external low-frequency reference clock (not shown) to the frequency of RFSYNTH 630 and filter out reference clock phase noise from the clock signal.

[0053] Figure 7 is used to adjust the charge pump current in the PLL to compensate for the variation of K according to various examples in this article. VCO The steps of method 700 may be performed in any suitable order. Figure 1 、 3 , 4, 5, and / or 6 can perform the method 700. In some examples, any suitable hardware, software, or digital logic can perform the method 700.

[0054] Method 700 begins at 710 where a current source provides a bias current to a charge pump in a phase locked loop circuit. In this example, bias current source 114 provides a bias current I as described above. BIAS 130. Bias current I BIAS 130 can affect the charge pump current I provided by the charge pump CP 126 and can be used to compensate for nonlinear behavior elsewhere in the phase-locked loop circuit.

[0055] Method 700 continues at 720 where LPF 106 provides a control voltage V to VCO 108 in the PLL. CTRL 128. In response to the charge pump current I CP 126 provides control voltage V CTRL 128. As described above, the PFD 102 is used to CP 126 changes, and uses the bias current I BIAS 130 to adjust the I CP To make V CTRL 128 changes. V CTRL 128 controls the output signal F provided by VCO 108 OUT 132.

[0056] Method 700 continues at 730 where, in response to the control voltage V CTRL In the first range, the bias current I provided to the charge pump 104 is increased by the first bias compensation circuit. BIAS 130. In this example, the first bias compensation circuit can be a boost DAC. As described above, in K VCO When the value is low, the bias current I BIAS 130 helps provide a more constant loop bandwidth.

[0057] Method 700 continues at 740 where, in response to the control voltage V CTRL 128 In the second range, the bias current I provided to the charge pump 104 is reduced by using the second bias compensation circuit. BIAS 130. In this example, the second bias compensation circuit can be an attenuation DAC. As described above, in K VCO When the value is high, the bias current I BIAS 130 helps provide a more constant loop bandwidth. In other examples, more than two DACs or offset compensation circuits can be used to compensate for the cross-control voltage V CTRL 128 changes in K VCO .

[0058] In this example, the charge pump current I CP 126 can be used with V CTRL 128 varies to compensate for the V CTRL K caused by the change of 128 VCO The loop bandwidth of the PLL is related to K VCO and the charge pump current I CP 126The two are proportional. Therefore, if K VCO For the first range of V CTRL 128 is low, you can increase I CP 126 is the first range of V CTRL A value of 128 provides consistent bandwidth. If K VCO For the second range of V CTRL 128 value is high, you can reduce I CP 126 is the second range of V CTRL 128 values ​​provide consistent bandwidth. In one example, one or more current steering DACs 116 are used to make I CP 126 changes. The current steering DAC 116 can be configured to provide the appropriate current to compensate for the K of a given VCO. VCO Using the examples presented in this paper, the full bandwidth of the chirp can be generated by a single VCO, which reduces the area and power consumption of the radar system.

[0059] As used herein, the term "coupled" may encompass any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0060] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may occur via firmware and / or software programming of the device, via the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0061] Circuits or devices described herein as including certain components may actually be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0062] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to functionality available before the component replacement.

[0063] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter. The described examples may be modified, and other examples are possible, within the scope of the claims.

Claims

1. A system comprising: a phase-locked loop comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a voltage-controlled oscillator (VCO) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter; a current source configured to provide a bias current to the charge pump; a first bias compensation circuit configured to increase the bias current in response to a control voltage provided to the VCO being within a first range; as well as A second bias compensation circuit is configured to reduce the bias current in response to the control voltage provided to the VCO being within a second range.

2. The system of claim 1 , further comprising: A third bias compensation circuit is configured to increase the bias current in response to the control voltage provided to the VCO being within a third range.

3. The system of claim 1, wherein the first bias compensation circuit is a current-steering digital-to-analog converter (DAC).

4. The system of claim 1 , further comprising: A voltage threshold generator circuit is configured to provide the first range and the second range.

5. The system of claim 1, wherein the phase-locked loop circuit is configured to generate a chirp signal, wherein the chirp signal varies in frequency in response to the control voltage. The system of claim 1 , wherein a gain of the VCO varies with the control voltage. 7 . The system of claim 6 , wherein the first bias compensation circuit increases the bias current to compensate for the gain of the VCO.

8. The system of claim 6, wherein the second bias compensation circuit reduces the bias current to compensate for the gain of the VCO.

9. The system of claim 1, wherein increasing the bias current increases the charge pump current and decreasing the bias current decreases the charge pump current.

10. The system of claim 1, wherein increasing the bias current increases a bandwidth of the phase-locked loop and decreasing the bias current decreases the bandwidth of the phase-locked loop.

11. A method comprising: A current source is used to provide bias current to a charge pump in a phase-locked loop; providing a control voltage to a voltage controlled oscillator (VCO) in the phase locked loop, wherein the control voltage is provided in response to a charge pump current from the charge pump; In response to the control voltage being within a first range, increasing the bias current provided to the charge pump using a first bias compensation circuit; as well as In response to the control voltage being within a second range, the bias current provided to the charge pump is reduced using a second bias compensation circuit.

12. The method according to claim 11, further comprising: In response to the control voltage being within a third range, the bias current provided to the charge pump is increased using a third bias compensation circuit.

13. The method of claim 11, wherein the first bias compensation circuit is a current-steering digital-to-analog converter (DAC).

14. The method according to claim 11, further comprising: A chirp signal is generated using the phase locked loop, wherein the chirp signal varies in frequency in response to the control voltage.

15. The method of claim 11, wherein increasing the bias current increases a bandwidth of the phase-locked loop.

16. The method of claim 11, wherein reducing the bias current reduces a bandwidth of the phase-locked loop.

17. A system comprising: a phase-locked loop comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a voltage-controlled oscillator (VCO) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter, the low-pass filter is configured to provide a control voltage to the VCO, and a gain of the VCO varies with the control voltage; a current source configured to provide a bias current to the charge pump, wherein the charge pump current varies with the bias current; a voltage threshold generator configured to provide a first voltage range and a second voltage range; A first bias compensation circuit is configured to provide a bias compensation circuit in response to the control voltage provided to the VCO. increasing the bias current within a first voltage range; as well as A second bias compensation circuit is configured to provide a bias compensation circuit in response to the control voltage provided to the VCO. The bias current is reduced within the second voltage range.

18. The system of claim 17, wherein increasing the bias current increases a bandwidth of the phase-locked loop.

19. The system of claim 17, wherein reducing the bias current reduces a bandwidth of the phase-locked loop.

20. The system of claim 17, further comprising: A third bias compensation circuit is configured to increase the bias current in response to the control voltage provided to the VCO being within a third voltage range.

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