Dynamic on-resistance testing device for GaN device

Abstract

The invention belongs to the technical field of power semiconductor device testing, and particularly relates to a GaN device dynamic on-resistance testing device which comprises a testing main circuit and an auxiliary testing clamping circuit. Three test reserved interfaces are arranged in the test main circuit, when the test reserved interface 1 is connected with the test reserved interface 3, the test main circuit is in a hard switch working mode, and when the test reserved interface 2 is connected with the test reserved interface 3, the test main circuit is in a soft switch working mode; the auxiliary test clamping circuit is connected in parallel with two ends of a to-be-tested switch tube DUT in the test main circuit; the auxiliary test clamping circuit is connected in parallel to the two ends of the to-be-tested GaN device, so that the voltage swing of the to-be-tested GaN device in the switching state switching process is reduced, drain-source voltage clamping in the whole test process is achieved, meanwhile, the conduction voltage drop of the to-be-tested GaN device can be accurately represented, and the measurement accuracy of the oscilloscope is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor device testing, and in particular relates to a GaN device dynamic on-resistance testing device. Background Art

[0002] Gallium nitride (GaN), as the main representative of the third generation of power semiconductors, has significant advantages in terms of structure and performance parameters. Compared with silicon (Si) MOSFET, it has advantages such as larger bandgap, higher thermal conductivity, stronger breakdown field strength and faster electron saturation drift velocity, making it more suitable for high frequency, high voltage, high temperature and high power applications. However, in actual applications, due to the unique physical structure of GaN devices, surface trap capture induced by the gate and drain will cause the GaN device to have a dynamic resistance degradation effect (current collapse effect). That is, after the GaN device is subjected to a high drain-source voltage bias in the off state, when it switches to the on state, the on-resistance shows a temporary increase trend. Since GaN devices usually operate at high switching frequencies, the dynamic resistance of the GaN device cannot be restored to the ideal value in time during the on time, which will lead to an increase in the additional power loss of the device, and then reduce the overall efficiency of the system, limiting the further application and development of GaN devices.

[0003] In practical applications, when GaN devices are subjected to various stress conditions, some charges may be trapped in specific areas of the GaN device structure. Under different switching conditions, the on-resistance will show a certain regular dynamic change trend. Factors affecting the dynamic on-resistance of GaN devices mainly include off-state voltage stress, off-state voltage stress duration, load current, switching conditions, switching frequency, and duty cycle. The existence of dynamic on-resistance not only makes it difficult to accurately predict and calculate the conduction loss of GaN devices, but also brings a series of reliability issues and challenges. Therefore, research on dynamic resistance testing technology for GaN devices has become an industry focus.

[0004] At present, the dynamic on-resistance test of GaN devices can be tested by using test equipment such as curve tracers, and the dynamic on-resistance is tested by controlling the gate-source and drain-source voltages, but the test frequency is limited and is mainly for bare chip testing. For packaged devices, the more common method is to build a test platform to implement its dynamic on-resistance test. GaN devices withstand a high off-state voltage when turned off, and the drain-source voltage is usually only a few hundred mV to a few V when turned on. When performing dynamic on-resistance testing, it is necessary to accurately measure the change in its on-state voltage. Usually, a high-precision oscilloscope can be used to measure the drain-source voltage, but because there is a large difference in the drain-source voltage of GaN devices in the off and on states, the oscilloscope needs a large measurement range to capture the on-state voltage. Otherwise, the amplifier inside the oscilloscope will be distorted, resulting in the inability to capture the complete waveform and the inability to accurately measure the on-state voltage. Summary of the Invention

[0005] To solve the above problems, the present invention provides a GaN device dynamic on-resistance testing device, which can evaluate the dynamic on-resistance of GaN devices under different stress conditions, and then accurately predict and calculate the conduction loss of GaN devices. At the same time, it can provide a research basis for the application optimization method of the dynamic on-resistance phenomenon of GaN devices, thereby improving the reliability of GaN devices in practical applications.

[0006] The device specifically includes a test main circuit and an auxiliary test clamping circuit; the test main circuit is provided with three test reserved interfaces. When the test reserved interface 1 is connected to the test reserved interface 3, the test main circuit is in a hard switching working mode; when the test reserved interface 2 is connected to the test reserved interface 3, the test main circuit is in a soft switching working mode; the auxiliary test clamping circuit is connected in parallel to both ends of the switch tube DUT to be tested in the test main circuit.

[0007] Beneficial effects of the present invention:

[0008] The present invention reduces the voltage swing of the GaN device under test when switching between switch states by connecting an auxiliary test clamp circuit in parallel at both ends of the GaN device under test. While achieving drain-source voltage clamping during the entire test process, it can accurately characterize the on-state voltage drop of the GaN device under test, thereby improving the accuracy of oscilloscope measurements. The main test circuit in the present invention can be switched between hard switching test conditions and soft switching test conditions. Different test modes can be selected for the GaN device under test by converting the port connection method in the main test circuit according to the actual application scenario. The present invention can achieve zero voltage and zero current switching of the auxiliary test clamp circuit switching device, with faster response time and shorter delay time. At the same time, it can effectively reduce switching losses. The test circuit can operate under conditions of higher turn-off voltage and larger on-state current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 1 is a schematic structural diagram of a GaN device dynamic on-resistance test device according to some embodiments of the present invention;

[0010] Figure 2 is a circuit diagram of a main test circuit in a hard switching operating mode according to some embodiments of the present invention;

[0011] Figure 3 is a circuit diagram of a main test circuit in a soft switching operating mode as shown in some embodiments of the present invention;

[0012] Figure 4 1. The waveforms of various signals in the hard switching working mode shown in some embodiments of the present invention;

[0013] Figure 5These are various signal waveforms in the soft switching working mode shown in some embodiments of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0015] Some embodiments of the present invention provide a GaN device dynamic on-resistance test device, including a test main circuit and an auxiliary test clamping circuit; the test main circuit is provided with three test reserved interfaces, when the test reserved interface 1 is connected to the test reserved interface 3, the test main circuit is in a hard switching working mode, when the test reserved interface 2 is connected to the test reserved interface 3, the test main circuit is in a soft switching working mode; the auxiliary test clamping circuit is connected in parallel to both ends of the switch tube DUT to be tested in the test main circuit.

[0016] Figure 1 It is a structural schematic diagram of a GaN device dynamic on-resistance testing device shown in some embodiments of the present invention.

[0017] In some embodiments, as Figure 1 As shown, the test main circuit includes a DC power supply Vin, a voltage stabilizing capacitor Cin, an output capacitor Co, a load resistor Ro, an inductor L, an upper bridge test switch S1, a test switch DUT, a first switch driver module, and a second switch driver module, wherein:

[0018] Connect the test reserved interface 1 to the positive terminal of the DC power supply Vin; connect the two ends of the voltage stabilizing capacitor Cin to the positive and negative terminals of the DC power supply Vin respectively;

[0019] Test reserved interface 2 is connected to one end of the output capacitor Co, and the other end of the output capacitor Co is connected to the negative terminal of the DC power supply Vin; one end of the load resistor Ro is connected to one end of the output capacitor Co, and the other end of the load resistor Ro is connected to the negative terminal of the DC power supply Vin;

[0020] The test reserved interface 3 is connected to one end of the inductor L; the other end of the inductor L is connected to the source of the upper bridge test switch S1 and the drain of the switch tube DUT to be tested; the gate of the upper bridge test switch S1 is connected to the first switch tube driver module, and the first switch tube driver module is connected to the gate drive signal V GS1 The drain of the upper bridge test switch S1 is connected to the positive terminal of the DC power supply Vin; the gate of the switch tube DUT to be tested is connected to the second switch tube driver module, and the second switch tube driver module is connected to the gate drive signal V GS2;The source of the switch tube under test DUT is connected to the negative end of the DC power supply Vin.

[0021] Figure 2 4 is a circuit diagram showing a main test circuit in a hard switching operation mode according to some embodiments of the present invention. Figure 3 4 is a circuit diagram showing a main test circuit in a soft switching mode according to some embodiments of the present invention.

[0022] like Figure 2 As shown in the figure, when the test main circuit is in hard switching mode, the inductor L is connected to the positive terminal of the DC power supply Vin. Since the load resistor Ro and the output capacitor Co have no effect, they are directly ignored in the test main circuit. Figure 3 As shown in FIG, when the test main circuit is in the soft switching working mode, the inductor L is connected to the load resistor Ro and the output capacitor Co.

[0023] In the soft switching mode, the gate drive signal V corresponding to the upper bridge test switch S1 is controlled. GS1 Duty cycle, can be used to test the voltage at the test end (i.e. the voltage V across the diode D2) probe ) is controlled by controlling the gate drive signal V GS1 , gate drive signal V GS2 The GaN device to be tested (ie, the switch tube to be tested DUT in the embodiment of the present invention) can be obtained under the set off-state voltage stress V DS-off and the drain current I DS Dynamic on-resistance parameters under drain-source voltage V DS Refers to the voltage between the drain and source of the switch tube DUT under test, the drain current I DS Refers to the drain current of the switch tube DUT under test, that is, the current flowing through the switch tube DUT under test when the switch tube DUT under test is turned on. DS-off It refers to the voltage stress between the drain and source of the switch tube under test (DUT) when it is turned off.

[0024] In some embodiments, in order to improve the measurement accuracy of the on-state voltage of the GaN device under test, an auxiliary test clamp circuit is connected in parallel to the switch tube DUT under test. The auxiliary test clamp circuit clamps the drain-source voltage of the GaN device under test to a smaller range when it is turned off, thereby reducing the voltage swing of the device when switching between the on and off states, thereby improving the measurement accuracy. Figure 1 As shown, the auxiliary test clamp circuit includes a test switch tube S2, a resistor R1, a diode D1, a diode D2 and a third switch tube driving module, wherein:

[0025] The gate of the accompanying test switch S2 is connected to the third switch drive module, and the third switch drive module is connected to the gate drive signal V GS3The drain of the accompanying test switch tube S2 is connected to the drain of the switch tube under test DUT, the source of the accompanying test switch tube S2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the source of the switch tube under test DUT; the two ends of the diode D1 are connected in parallel to the two ends of the resistor R1; the two ends of the diode D2 are connected in anti-parallel to the two ends of the diode D1, and the two ends of the diode D1 are respectively connected to the test port 4 and the test port 5.

[0026] In some embodiments, when the test main circuit is in hard switching mode, the circuit principle is as follows: Figure 2 As shown. Based on this analysis, the leakage current I DS Related to the inductor current: In the hard switching mode, when the switch tube DUT is turned off, the drain current I DS is 0, the inductor current i L In the freewheeling state; during the on-time of the switch tube DUT under test, the inductor current i L Rising, at this time the inductor current i L and drain current I DS At t'0, a driving pulse (i.e., gate driving signal V GS2 ), the switch tube DUT is turned on, the inductor L is charged, and the current i L Linear rise, continues until t'3 ​​moment, according to the inductor current rising slope , it can be seen that , so the inductor current i L The size is affected by the time t'0 and t'3. The test variable drain current I can be controlled by changing the duration from t'0 to t'3. DS From t'3 to t'5, the high-side companion test switch S1 is turned on, the DUT is turned off, and the inductor current continues to flow. During this phase, the duration of the off-state voltage stress of the test variable (i.e., the dynamic state of the DUT) can be adjusted by varying the time between t'3 and t'5. The critical stage for determining the dynamic on-resistance of the DUT is from t'6 to t'7. The DUT and companion test switch S2 are turned on, and the on-state voltage waveform of the DUT is measured from t'6 to t'7.

[0027] Figure 4 1 and 2 are waveforms of various signals in a hard switching operation mode according to some embodiments of the present invention.

[0028] For example, Figure 4 As shown in FIG. 1 , when the test main circuit is in hard switching mode, the state adjustment process of the upper bridge test switch S1, the test switch DUT, and the test switch S2 includes:

[0029] At t'0, the switch tube under test DUT is turned on, the upper bridge test switch tube S1 is turned off, and the test switch tube S2 is turned off. At this time, the resistance of the test switch tube S2 is much higher than the series resistor R1. The test voltage V probe (i.e. the voltage between test port 4 and test port 5) is close to 0V.

[0030] At time t'1, the upper bridge test switch S1 is turned off, the test switch DUT and the test switch S2 are both in the on state, and the test switch S2 is turned on with zero voltage and zero current. At this time, the resistance of the test switch S2 is much smaller than the series resistor R1, and the test voltage V probe is the voltage drop of the switch tube DUT under test.

[0031] At time t'2, the upper bridge test switch S1 is turned off, the test switch DUT remains on, and the test switch S2 is switched to the off state, and the test switch S2 is turned off with zero current and zero voltage.

[0032] At time t'3, the switch tube DUT under test is switched to the off state, the parasitic capacitance of the switch tube DUT under test is quickly charged through the test main circuit, and the parasitic capacitance of the accompanying switch tube S2 is quickly charged through the test main circuit and diode D2, and the voltage divider of the accompanying switch tube S2 rises.

[0033] At time t'4, the parasitic capacitance of the test switch S2 is fully charged. At this time, the resistance of the test switch S2 is much higher than that of R1. The test voltage V probe Close to 0V.

[0034] This continues until t'5, completing one round of adjustment. The next round of adjustment begins at t'5, and the adjustment process is the same as above:

[0035] At time t'5, the switch tube under test DUT is turned on, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off;

[0036] At time t'6, the upper bridge test switch S1 is turned off, the test switch S2 is turned on, and the test switch DUT is turned on; the test switch S2 is turned on with zero voltage and zero current.

[0037] At time t'7, the upper bridge test switch S1 is turned off, the test switch DUT is turned on, the test switch S2 is turned off, and the test switch S2 achieves zero current and zero voltage shutdown;

[0038] At time t'8, the switch tube under test DUT is turned off, the accompanying switch tube S2 is turned off, and the upper bridge accompanying switch tube S1 is turned on.

[0039] The gate drive signal V of the test switch S2 in the auxiliary test clamp circuit GS3The gate drive signal V GS2 middle.

[0040] The test is divided into stages based on the above adjustment process, including:

[0041] From t'0 to t'3, the inductor L is charged and the current of the inductor L increases linearly;

[0042] From time t'3 to time t'5, the current of the inductor L continues to flow. If the duration from time t'3 to time t'5 is short, at time t'5 when the switch tube DUT under test is turned on for the second time, the on-state current of the switch tube DUT under test is approximately equal to the preset drain current.

[0043] From t'6 to t'7, the test voltage Vprobe at the oscilloscope probe end is the voltage drop V of the switch tube under test DUT. DS-on ;Measure the drain current I during this period DS , calculate the dynamic on-resistance Rdson =V DS-on / I DS ;

[0044] At time t'8, the switch tube DUT under test is turned off again, and the upper bridge test switch tube S1 is turned on. The drain current continues to flow through the upper bridge test switch tube S1 and gradually decays to zero, and the test ends.

[0045] In some embodiments, when the test main circuit is in the soft switching mode, the circuit principle is as follows: Figure 3 As shown. Based on this analysis, the principle of the test main circuit is similar to the synchronous rectification BUCK circuit. The gate drive signal of the upper bridge test switch S1 and the test switch DUT are in opposite phases. When the upper bridge test switch S1 is in the on state in each cycle, the test switch DUT is in the off state. The current charges the inductor L through the upper bridge test switch S1. The inductor current i L Gradually rising, its slope , V Ro Represents the load resistance R O The voltage across the two ends, the current i L The inductor current flows through the inductor L to the output capacitor Co and the load resistor Ro, charging the output capacitor Co. The on-time of the high-side test switch S1 is related to the set gate drive pulse duty cycle. When the high-side test switch S1 is in the off state, the test switch DUT is in the on state, and the inductor current continues to flow through the test switch DUT.

[0046] Figure 5 1 and 2 are waveforms of various signals in a soft switching operation mode according to some embodiments of the present invention.

[0047] For example, Figure 5As shown in FIG. 1 , when the test main circuit is in hard switching mode, the state adjustment process of the upper bridge test switch S1, the test switch DUT, and the test switch S2 includes:

[0048] At time t0, the upper bridge test switch S1 is turned on, the test switch DUT is turned off, and the test switch S2 is turned off;

[0049] At time t1, the upper bridge test switch S1 is turned off, the switch under test DUT is turned off, and the test switch S2 is turned off;

[0050] Among them, during the period from t0 to t1, a narrow pulse drive signal of about 100ns is applied to the gate of the upper bridge test switch S1 to make it turn on first, the inductor L is charged, and the inductor current increases, and its rising slope di L / dt=(Vin-V Ro ) / L.

[0051] The dead time from t1 to t2 is the time during which the loop current discharges the parasitic capacitance of the DUT, causing the DUT's drain-source voltage to drop. When the DUT's drain-source voltage drops to 0, the GaN device under test conducts in the reverse direction.

[0052] At time t2, the accompanying test switch S1 is turned off, and the accompanying test switch S2 is turned off; a driving signal is applied to the gate of the switch tube under test DUT, and the switch tube under test DUT is soft-switched on, and the inductor L is reversely charged;

[0053] At time t3, the switch tube under test DUT is turned on, the accompanying switch tube S2 is turned on, and the upper bridge accompanying switch tube S1 is turned off;

[0054] At time t4, the switch tube under test DUT is turned on, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off;

[0055] At time t5, the switch tube under test DUT is turned off, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off;

[0056] The time from t5 to t6 is the dead time;

[0057] At time t6, the accompanying test switch S2 is turned off, and the switch under test DUT is turned off; the upper bridge accompanying test switch S1 is turned on;

[0058] At time t7, the switch tube under test DUT is turned off, the accompanying switch tube S1 is turned off, and the accompanying switch tube S2 is turned off;

[0059] The time from t7 to t8 is the dead time.

[0060] At time t8, the accompanying test switch tube S1 is turned off, and the accompanying test switch tube S2 is turned off; a driving signal is applied to the gate of the switch tube under test DUT, and the switch tube under test DUT is soft-switched on again, and the inductor L is reversely charged, and the cycle repeats.

[0061] Similar to the hard switching mode, the gate drive signal V GS3 The gate drive signal V GS2 middle.

[0062] The test is divided into stages based on the above adjustment process, including:

[0063] From t3 to t4, the switch tube under test DUT and the accompanying switch tube S2 are both in the on state. At this stage, the oscilloscope probe end V probe is the voltage drop V of the switch under test DUT DS-on , measure the drain current I during this period DS , compare the tested on-state voltage value with the drain current value to obtain the final dynamic on-resistance value Rdson, that is, Rdson=V DS-on / I DS .

[0064] In the present invention, unless otherwise clearly stipulated and limited, the terms "installation", "setting", "connection", "fixation", "rotation" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0065] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A GaN device dynamic on-resistance test device, characterized in that: It includes a test main circuit and an auxiliary test clamping circuit; the test main circuit is provided with three test reserved interfaces. When the test reserved interface 1 is connected to the test reserved interface 3, the test main circuit is in a hard switching working mode; when the test reserved interface 2 is connected to the test reserved interface 3, the test main circuit is in a soft switching working mode; the auxiliary test clamping circuit is connected in parallel to both ends of the switch tube DUT to be tested in the test main circuit.

2. A GaN device dynamic on-resistance test device according to claim 1, characterized in that: The main test circuit includes a DC power supply Vin, a voltage stabilizing capacitor Cin, an output capacitor Co, a load resistor Ro, an inductor L, an upper bridge test switch S1, a switch under test DUT, a first switch driver module, and a second switch driver module, wherein: Connect the test reserved interface 1 to the positive terminal of the DC power supply Vin; connect the two ends of the voltage stabilizing capacitor Cin to the positive and negative terminals of the DC power supply Vin respectively; Test reserved interface 2 is connected to one end of the output capacitor Co, and the other end of the output capacitor Co is connected to the negative terminal of the DC power supply Vin; one end of the load resistor Ro is connected to one end of the output capacitor Co, and the other end of the load resistor Ro is connected to the negative terminal of the DC power supply Vin; The test reserved interface 3 is connected to one end of the inductor L; the other end of the inductor L is connected to the source of the upper bridge test switch S1 and the drain of the switch tube DUT to be tested; the gate of the upper bridge test switch S1 is connected to the first switch tube driver module, and the first switch tube driver module is connected to the gate drive signal V GS1 The drain of the upper bridge test switch S1 is connected to the positive terminal of the DC power supply Vin; the gate of the switch tube DUT to be tested is connected to the second switch tube driver module, and the second switch tube driver module is connected to the gate drive signal V GS2 ;The source of the switch tube under test DUT is connected to the negative end of the DC power supply Vin.

3. A GaN device dynamic on-resistance test device according to claim 2, characterized in that: An auxiliary test clamp circuit is connected in parallel to the switch tube under test DUT. The auxiliary test clamp circuit includes a test switch tube S2, a resistor R1, a diode D1, a diode D2 and a third switch tube driver module, wherein: The gate of the accompanying test switch S2 is connected to the third switch drive module, and the third switch drive module is connected to the gate drive signal V GS3 The drain of the accompanying test switch tube S2 is connected to the drain of the switch tube under test DUT, the source of the accompanying test switch tube S2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the source of the switch tube under test DUT; the two ends of the diode D1 are connected in parallel to the two ends of the resistor R1; the two ends of the diode D2 are connected in anti-parallel to the two ends of the diode D1, and the two ends of the diode D1 are respectively connected to the test port 4 and the test port 5.

4. A GaN device dynamic on-resistance test device according to claim 3, characterized in that: Test port 4 and test port 5 are used to connect oscilloscope voltage probes.

5. The GaN device dynamic on-resistance test device according to claim 3, characterized in that: When the main test circuit is in hard switching mode, the state adjustment process of the upper bridge test switch S1, the test switch DUT, and the test switch S2 includes: At t'0, the switch tube under test DUT is turned on, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off; At time t'1, the upper bridge test switch S1 is turned off, the test switch S2 is turned on, and the test switch DUT is turned on; at this time, the test switch S2 is turned on with zero voltage and zero current; At time t'2, the upper bridge test switch S1 is turned off, the DUT is turned on, and the test switch S2 is turned off. At this time, the test switch S2 is turned off with zero current and zero voltage. At time t'3, the switch tube under test DUT is turned off, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned on; At time t'5, the switch tube under test DUT is turned on, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off; At time t'6, the upper bridge test switch S1 is turned off, the test switch S2 is turned on, and the test switch DUT is turned on; at this time, the test switch S2 is turned on with zero voltage and zero current; At time t'7, the upper bridge test switch S1 is turned off, the test switch DUT is turned on, and the test switch S2 is turned off. At this time, the test switch S2 achieves zero current and zero voltage shutdown. At time t'8, the switch tube under test DUT is turned off, the accompanying switch tube S2 is turned off, and the upper bridge accompanying switch tube S1 is turned on.

6. A GaN device dynamic on-resistance test device according to claim 5, characterized in that: When the main circuit is in hard switching mode, the test process includes: From t'0 to t'3, the inductor L is charged and the current of the inductor L increases linearly; From time t'3 to time t'5, the current of the inductor L continues to flow. If the duration from time t'3 to time t'5 is short, at time t'5 when the switch tube DUT under test is turned on for the second time, the on-state current of the switch tube DUT under test is approximately equal to the preset drain current. From t'6 to t'7, the test voltage Vprobe at the oscilloscope probe end is the voltage drop V of the switch tube under test DUT. DS-on ;Measure the drain current I during this period DS , calculate the dynamic on-resistance Rdson =V DS-on / I DS ; At time t'8, the switch tube DUT under test is turned off again, and the upper bridge test switch tube S1 is turned on. The drain current continues to flow through the upper bridge test switch tube S1 and gradually decays to zero, and the test ends.

7. A GaN device dynamic on-resistance test device according to claim 3, characterized in that: When the main test circuit is in the soft switching mode, the state adjustment process of the upper bridge test switch S1, the test switch DUT, and the test switch S2 includes: At time t0, the upper bridge test switch S1 is turned on, the test switch DUT is turned off, and the test switch S2 is turned off; At time t1, the upper bridge test switch S1 is turned off, the switch under test DUT is turned off, and the test switch S2 is turned off; The time from t1 to t2 is the dead time; At time t2, the switch tube DUT under test is turned on, the accompanying switch tube S1 is turned off, and the accompanying switch tube S2 is turned off; At time t3, the switch tube under test DUT is turned on, the accompanying switch tube S2 is turned on, and the upper bridge accompanying switch tube S1 is turned off; At time t4, the switch tube under test DUT is turned on, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off; At time t5, the switch tube under test DUT is turned off, the accompanying test switch tube S2 is turned off, and the upper bridge accompanying test switch tube S1 is turned off; The time from t5 to t6 is the dead time; At time t6, the accompanying test switch S2 is turned off, and the switch under test DUT is turned off; the upper bridge accompanying test switch S1 is turned on; At time t7, the switch tube under test DUT is turned off, the accompanying switch tube S1 is turned off, and the accompanying switch tube S2 is turned off; The time from t7 to t8 is the dead time.

8. The GaN device dynamic on-resistance test device according to claim 7, characterized in that: When the main circuit is in the soft switching mode, from t3 to t4, the voltage V probe is the voltage drop V of the switch under test DUT DS-on ;Measure the drain current I during this period DS , calculate the dynamic on-resistance Rdson =V DS-on / I DS .

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