Digital back-end full-process script design method

Abstract

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of digital integrated circuit design, and in particular to a method for digital back-end full-process script design. Background Art

[0002] With the continuous evolution of chip manufacturing technology, the complexity of chip design continues to increase, especially at advanced process nodes, the integration and functional density of chips have increased dramatically, bringing huge challenges to digital back-end design.

[0003] Currently, the mainstream digital back-end design process in the industry generally includes synthesis, place and route, physical verification, and SIGNOFF. During the synthesis phase, the behavioral-level design needs to be converted into a gate-level netlist and logic optimized and mapped. During the place and route phase, standard cells need to be placed and routed based on physical constraints and routing resources. During the physical verification phase, the place and route results need to be checked for DRC / LVS / ANT rules. During the SIGNOFF phase, STA / Power / IR analysis is required to ensure chip functionality, performance, and reliability.

[0004] However, different designs use different process library files and constraint files, resulting in poor compatibility and consistency of synthesis results, requiring repeated manual processing and debugging, which is inefficient. Summary of the Invention

[0005] In response to the problem of low efficiency of the chip digital back-end design process in the existing technology, this application provides a method for full-process script design of the digital back-end. Through script-driven approach, each link of the digital back-end design is processed in a process-oriented manner, and a general standard unit process library file is generated through RTL design, process library and constraint conditions. At the same time, a unified interface is established for tasks such as layout and routing, physical verification, power consumption analysis and IR analysis, etc., thereby improving design efficiency.

[0006] The purpose of this application is achieved through the following technical solutions.

[0007] The present application provides a method for full-process script design of a digital back-end, comprising: receiving an RTL behavioral-level netlist, a process library file, and a constraint file as input, and generating a library configuration file value_lib.tcl; using the library configuration file value_lib.tcl, generating a gate-level netlist and a corresponding synthesis report; performing logic synthesis using the make syn command based on the behavioral-level netlist to generate a gate-level netlist, and generating layout and routing data; performing antenna checking using the make ant command based on the layout and routing data, performing design rule checking using the make drc command, and performing comparison checking between the generated layout and the schematic diagram using the make lvs command; and outputting a GDSII layout file using the make out command based on the layout and routing data.

[0008] The RTL behavioral netlist (Register Transfer Level Design File) is a high-level description method for digital circuit design, using hardware description languages ​​(such as Verilog and VHDL) to describe the circuit's structure and behavior. The RTL behavioral netlist defines the registers, combinational logic, sequential logic, and the data flow between them in a register transfer level (RTL) abstraction. An RTL behavioral netlist typically contains module definitions, port declarations, register definitions, combinational logic expressions, sequential logic statements, and other content. It describes the circuit's functionality and timing relationships and serves as the starting point for logic synthesis.

[0009] Technology Library File: A file that describes the characteristics and parameters of library cells such as standard cells, I / O cells, and memories at a specific process node. The technology library file contains information such as the library cell's logical function, input and output ports, timing parameters (such as delay and load), physical parameters (such as area and power consumption), as well as design rules and parasitic models related to layout and routing. The technology library file is provided by the chip manufacturer (foundry) and reflects the technical characteristics and limitations of a specific process node. Logic synthesis, layout and routing, and other links all rely on the technology library file to map the RTL design to actual physical devices and interconnections.

[0010] Constraint File: It is a text file that specifies the design intent and requirements, and is used to guide the optimization and implementation of logic synthesis, layout and routing, and other links. The constraint file contains various types of constraints such as timing constraints (TimingConstraint), physical constraints (Physical Constraint), and power constraints (Power Constraint). Timing constraints define the circuit's clock frequency, setup time (Setup Time), hold time (Hold Time) and other timing requirements; physical constraints define the chip's size, pin location, layout area and other physical limitations; power constraints define the chip's power budget, power domain division and other power requirements. Constraint files are written in formats such as SDC (Synopsys DesignConstraint) and TCL (Tool Command Language), and are continuously refined and updated as the design process progresses.

[0011] A gate-level netlist is a circuit description file generated after logic synthesis, describing the circuit's gate-level structure and connections. In the form of a netlist, the gate-level netlist maps abstract structures such as registers and combinational logic in the RTL design to actual standard cells (such as NAND gates, NOR gates, and flip-flops) in the process library and the interconnections between them. The gate-level netlist contains information such as the instantiation, port connections, and hierarchy of each standard cell, reflecting the circuit's logical function and structure. The gate-level netlist serves as input for subsequent steps such as place and route, static timing analysis, and formal verification, and is an important basis for evaluating the quality of logic synthesis.

[0012] Furthermore, it also includes: performing power consumption analysis based on layout and routing data; and performing IR analysis based on parasitic parameters.

[0013] Furthermore, the RTL behavioral netlist, process library file, and constraint file are received as input to generate a library configuration file value_lib.tcl, including: receiving the RTL behavioral netlist, process library file, and constraint file as input; wherein the RTL behavioral netlist uses Verilog or VHDL language to describe the logical function and structure of the chip; the process library file is used to define the physical and electrical characteristics of the standard cell; the constraint file is used to define the timing constraints and physical constraints of the design; using the RTL behavioral netlist, process library file, and constraint file, a logic synthesis tool is used to synthesize and generate a behavioral netlist file value.v; wherein the logic synthesis tool reads the RTL behavioral netlist, combines the process library file and constraint file, and converts the behavioral-level logic description into a gate-level circuit description to achieve the conversion from behavioral level to gate level; and based on the flow configuration file value.tcl, a library configuration file value_lib.tcl is generated through flow. The library configuration file contains the cell information, logical function, and timing constraint information of the process library.

[0014] The Logic Synthesis Tool converts the RTL behavioral netlist into a behavioral netlist file (value.v). The Logic Synthesis Tool accepts the RTL behavioral netlist, process library file, and constraint file as input. Through a series of optimization and mapping algorithms, it converts the behavioral logic description into a gate-level circuit description. Specifically, the Logic Synthesis Tool first performs syntax checking and elaboration on the RTL design, generating internal data structures and hierarchical relationships. Next, the Logic Synthesis Tool performs high-level synthesis, converting abstract structures such as registers, combinational logic, and state machines in the RTL into basic logic units such as AND gates, OR gates, and flip-flops. Next, the Logic Synthesis Tool combines the standard cell information provided by the process library file to map, optimize, and restructure the generated logic circuit to meet the timing and area requirements defined in the constraint file. Finally, the Logic Synthesis Tool generates the behavioral netlist file (value.v), which describes the circuit's gate-level structure and connectivity. Common logic synthesis tools include Synopsys Design Compiler, Cadence RTL Compiler, Mentor Precision, etc. These tools provide a rich set of commands and scripting interfaces, support multiple HDL languages ​​and constraint formats, and can achieve automatic synthesis and optimization from RTL to gate level.

[0015] The Library File Format Conversion Tool (LIFT) generates the library configuration file (value_lib.tcl) based on the configuration in the Flow configuration file (value.tcl). The LIFT accepts the behavioral netlist file (value.v) as input, extracts the standard cell information, and generates the library configuration file (value_lib.tcl) in a specific library format (such as the Synopsys Liberty format). Specifically, the LIFT first reads the behavioral netlist file (value.v), parsing the module definitions, instantiation statements, and port connection information. The LIFT then iterates over each standard cell instance, extracting its logical function, input / output ports, timing parameters, and other properties. The LIFT then organizes the extracted standard cell information into a .lib file, conforming to the Liberty format syntax and structure. This file contains the library header information, cell definitions, pin definitions, and timing definitions. Finally, the LIFT generates the library configuration file (value_lib.tcl) as input for subsequent steps.

[0016] Common library file formats include Synopsys Liberty, Cadence LEF / DEF, and Verilog. Different EDA tools and design flows may use different library file formats, necessitating the use of corresponding library file format conversion tools for conversion and adaptation. Some EDA tools provide built-in library file format conversion capabilities, while others require the use of third-party conversion tools, such as Synopsys Library Compiler and Cadence Abstract Generator.

[0017] Specifically, the goal of isochronous optimization is to balance the delays of different paths in a circuit so that the delays of all paths are close to the clock period, thereby reducing clock skew and improving circuit speed and reliability. Isochronous optimization primarily utilizes two techniques: logic reconfiguration and buffer insertion. Logic reconfiguration involves adjusting and reorganizing the circuit's logic structure to balance path delays. Specifically, logic reconfiguration is achieved through the following methods: Identifying critical paths: Static timing analysis (STA) is used to identify the critical paths with the longest delays in the circuit. The delays of these paths determine the circuit's maximum speed. Optimizing critical paths: Optimizing logic cells along critical paths. For example, complex logic cells can be split into multiple simpler ones to reduce the delay of individual logic cells; or the number of logic levels along critical paths can be adjusted to reduce the number of logic levels and shorten path delays. Balancing non-critical paths: Appropriately balance the delays of non-critical paths to keep them close to the critical path, avoiding over-optimization of non-critical paths and the resulting unnecessary area and power consumption.

[0018] Buffer insertion involves inserting buffers into long-delay interconnects to reduce interconnect delay. Specifically, buffer insertion is achieved through the following methods: Calculating the optimal buffer size and location: Based on the interconnect length, load, and delay requirements, the optimal buffer size and insertion location are calculated to minimize interconnect delay. Buffer insertion: Buffers are inserted at selected locations. Buffers can be inverters or non-inverters, featuring strong drive force and low delay. Buffer sizing: Based on actual delay and load conditions, the inserted buffer size is adjusted to further optimize delay and area. Through logic reconfiguration and buffer insertion, isochronous optimization can effectively balance the delays of different paths in the circuit, reduce clock skew, and improve circuit speed and reliability. However, isochronous optimization also introduces additional area and power consumption overhead, necessitating a trade-off between performance and cost.

[0019] Logic optimization simplifies logic circuits through Boolean simplification, constant propagation, and dead code elimination. The goal of logic optimization is to simplify the logic structure of a circuit, reducing the number and complexity of logic cells, thereby reducing circuit area and power consumption. Logic optimization primarily employs three techniques: Boolean simplification, constant propagation, and dead code elimination. Boolean simplification involves expressing complex logic functions using simpler logical expressions, thereby reducing the number of logic cells. Specifically, Boolean simplification is achieved through the following methods: Logic expression simplification: Utilizing Boolean algebra's equivalence transformations and theorems such as the absorption and distributive laws, complex logic expressions are simplified into simpler forms, such as minterms and maxterms. Karnaugh graph simplification: Utilizing Karnaugh graphs (K-Maps) to intuitively represent logic functions, simplifying them into simpler logical expressions by merging adjacent grids. Quine-McCluskey simplification: Utilizing the Quine-McCluskey algorithm, using the concept of prime implicants, Boolean functions are systematically simplified to their simplest form.

[0020] Constant propagation refers to the propagation of known constant inputs within a logic circuit, simplifying the logic cells determined by these constant inputs. Specifically, constant propagation is achieved through the following methods: Constant input identification: By analyzing the input signal, constant inputs that are always 0 or 1 are identified. Constant input propagation: Based on the function of the logic cell, the constant input is propagated to the next-level logic cell until further propagation is impossible. Logic cell simplification: For logic cells determined by constant inputs, they are simplified to simpler forms based on their logical functions, such as constant 0, constant 1, or single-input buffers. Dead code elimination refers to the removal of unused logic cells in a logic circuit, reducing circuit area and power consumption. Specifically, dead code elimination is achieved through the following methods: Dead code identification: By analyzing the circuit topology and connectivity, unused logic cells, such as floating output ports and undriven input ports, are identified. Dead code removal: Identified dead code is removed from the circuit and the corresponding connectivity is adjusted to ensure circuit correctness. Iterative Optimization: Dead code elimination may generate new dead code, so it must be performed iteratively until no dead code is left. Through Boolean simplification, constant propagation, and dead code elimination, logic optimization can effectively simplify logic circuits, reducing the number and complexity of logic cells, and lowering circuit area and power consumption. However, logic optimization can also introduce new timing issues, such as delay mismatch and glitches. This requires integration with timing optimization to achieve a comprehensive trade-off and optimization.

[0021] Furthermore, based on the behavioral-level netlist, make syn performs logic synthesis to generate a gate-level netlist and generate layout and routing data, including: generating an MMMC file through the make mmmc command to define constraint information under different working modes and process angles; generating an initialization file through the make init command to initialize the environmental parameters of the chip design; generating a floorplan based on the physical design constraints through the makefp command to determine the physical size and position of the chip; wherein the physical design constraints include chip area, chip IO pin position and pre-layout macro cell position; performing standard cell layout and macro cell layout based on layout constraints through the make place command; wherein the standard cell includes NAND gates, NOR gates and triggers; the macro cell includes memory and PLL; performing clock tree synthesis based on clock constraints through the make cts command to generate a clock tree allocation plan and a buffer insertion plan to balance the delay of the clock tree; performing routing based on routing resources and routing constraints through the make route command to connect standard cells and macro cells; performing parasitic parameter extraction and static timing analysis on the routed design according to the optimization goals through the make postopt command.

[0022] Specifically, modern EDA (Electronic Design Automation) tools, such as Synopsys ICC, Cadence Innovus, and Mentor Nitro, provide a rich set of command interfaces for executing various design tasks and processes. These command interfaces are typically provided in the form of TCL (Tool Command Language) scripts. Designers can automate the design process by calling these commands from the tool's command line interface or script files. The make mmmc command is used to generate MMMC (Multi-Mode Multi-Corner) files. This command typically corresponds to commands such as set_multi_mode_constraint or write_mmmc_script in EDA tools, which define constraint information for different operating modes and process perspectives. The make init command is used to initialize chip design environment parameters. This command typically corresponds to commands such as init_design or source_initialize in EDA tools, which are used to load design files, set process libraries, and constraint files. The make fp command is used to generate a floorplan. This command typically corresponds to commands such as floorplan or create_floorplan in EDA tools, which determine the chip's physical dimensions, I / O pin locations, and macrocell locations.

[0023] Furthermore, based on the layout and routing data, antenna checking is performed through the make ant command, design rule checking is performed through the make drc command, and comparison checking of the generated layout and schematic diagram is performed through the make lvs command, including: based on the layout and routing data, using the make ant command to perform antenna effect checking using the antenna checking tool; wherein, the antenna checking tool calculates the antenna ratio of each signal network by analyzing the metal wiring length, metal wiring area and connected transistor gate area in the layout and routing data, compares the calculation with the threshold, obtains the violating network whose antenna ratio exceeds the threshold, and generates an antenna checking report; based on the layout and routing data, using the make drc command to perform design rule checking using the design rule checking tool; wherein, the design rule checking tool checks whether the layout and routing meet the minimum line width, minimum spacing, inter-layer wiring, wiring blockage and boundary extension by comparing the layout and routing data with the process design rules, and generates a design rule checking report. Based on the layout and routing data, use the make lvs command to check the consistency of the layout and schematic diagram using the Layout vs. Schematic checking tool. The Layout vs. Schematic checking tool extracts the device connection netlist from the layout and routing data and compares it with the generated gate-level netlist to check whether the device type, device quantity, and device connection topology are consistent between the two, and then generates a Layout vs. Schematic inspection report.

[0024] Furthermore, the antenna checking tool includes at least one of PegasusARC, IC ValidatorARC, CalibreAntennaChecker, TotemAntenna Checker and QuartzARC; the design rule checking tool includes at least one of Pegasus DRC, IC Validator DRC, Calibre DRC, Totem DRC, Quartz DRC and SKIPPER DRC.

[0025] Furthermore, power consumption analysis is performed based on the layout and routing data, including: extracting parasitic parameters of the routing including parasitic resistance and parasitic capacitance based on a parasitic parameter extraction tool through a makestarrc_step or make starrc command based on the layout and routing data; wherein the parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance values ​​of each routing segment based on the geometric parameters and process parameters of the routing.

[0026] Specifically, `make starrc_step:` is a command used to generate configuration files and control files for parasitic parameter extraction, preparing for subsequent parasitic parameter extraction. This command generates the input files required by the STARRC tool, such as the .STARRC_STEP_MAP file and the .starrc_step.tcl file, based on the design's hierarchy, netlist structure, and process information. These files define the extraction settings, boundary conditions, and output format. `make starrc:` is a command used to perform the actual parasitic parameter extraction. This command invokes the STARRC tool to analyze the layout and routing data based on the configuration files and control files generated by `make starrc_step`, extracting the parasitic resistance and capacitance values ​​for each routing segment. The STARRC tool considers routing geometry parameters (such as length, width, and spacing) and process parameters (such as the resistivity of metal layers and the dielectric constant of dielectric layers), calculates distributed RC values, and generates parasitic parameter files, such as .spef and .sbpf, for subsequent timing and power analysis. The difference between make starrc_step and make starrc is that the former is responsible for generating the configuration and control of the extraction, while the latter is responsible for performing the actual extraction.

[0027] Using the PrimeTime static timing analysis tool, standard static timing analysis is performed based on parasitic parameters using the make pt_step command. Multi-mode, multi-angle static timing analysis is also performed using the make pt_dmsa command. Timing analysis reports are generated. Standard static timing analysis calculates data path delay, setup time, and hold time timing metrics under typical process corners and operating modes. Multi-mode, multi-angle static timing analysis calculates data path timing margins and violation count timing metrics under multiple process corners and operating modes. Specifically, standard static timing analysis (makept_step) is performed under typical process corners and operating modes. Typical process corners refer to the selection of representative process parameter combinations, such as typical transistor speed and typical interconnect resistance, reflecting the performance of devices and interconnects under normal process conditions. Typical operating modes refer to the selection of representative operating conditions, such as typical supply voltage and typical temperature, reflecting the circuit's behavior under normal use. From a typical process perspective and in a typical operating mode, static timing analysis tools (such as PrimeTime) calculate the timing indicators of the data path, such as path delay, setup time, hold time, etc., and generate a timing report to evaluate whether the circuit's timing performance meets the design requirements.

[0028] Multi-mode, multi-angle static timing analysis (make pt_dmsa): This analysis is performed under multiple process corners and multiple operating modes. Multiple process corners consider extreme variations in process parameters, such as the fastest and slowest corners, reflecting the performance fluctuations of devices and interconnects under different process conditions. Multiple operating modes consider extreme variations in operating conditions, such as maximum and minimum supply voltages, and maximum and minimum temperatures, reflecting the differences in circuit behavior under different usage environments. Under multiple process corners and operating modes, the static timing analysis tool calculates metrics such as timing slack and violation counts for each data path. Timing slack represents the difference between the actual timing of a data path and the required timing. A positive value indicates that the timing requirement is met, while a negative value indicates a timing violation. The violation count indicates the number of paths that violate the timing requirement. Multi-mode and multi-angle analysis can comprehensively evaluate the timing performance of the circuit under various extreme conditions, identify critical paths that are sensitive to process and environmental changes, and provide guidance for subsequent timing optimization.

[0029] Static power analysis (make ptpx): Based on static timing analysis, the PrimeTimePX (PTPX) tool estimates circuit power consumption based on information in the timing analysis report, such as circuit switching activity, signal transitions, and capacitive loading. The PTPX tool considers various power sources, such as switching power, internal power, and leakage power, and generates a detailed power analysis report (powerreport). This report provides power consumption statistics and distribution, such as total power, average power, maximum power, and the power contribution of each module. This power analysis report can help designers evaluate the circuit's power performance, identify high-power modules and paths, and guide power optimization.

[0030] Timing ECO (Engineering Change Order) optimization is performed based on multi-mode and multi-angle static timing analysis, with the goal of correcting timing violations and improving the timing performance of the circuit. ECO optimization tools (such as PrimeTime ECO) automatically or interactively insert buffers in the gate-level netlist, adjust drive strength, etc., to repair timing violation paths: Specific optimization strategies include: Buffer insertion: Insert buffers on timing-critical paths to reduce interconnect delays and increase signal transmission speed. Drive strength adjustment: Increase or decrease the drive strength of the cell, match the load capacity, and optimize the rise and fall times of the signal. Gate type replacement: Replace cells on the timing-critical path with higher-performance gate types, such as replacing ordinary cells with low-threshold voltage (low-Vt) cells. Clock tree optimization: Adjust the structure and parameters of the clock tree, balance the delay of the clock path, and reduce clock skew.

[0031] Based on the timing analysis report, use the PrimeTime static power analysis tool with the make ptpx command to perform static power analysis and generate a power report. Based on the timing analysis report, use the make eco command with the ECO optimization tool to debug and optimize the multi-mode and multi-angle static timing analysis results and correct timing violations. The ECO optimization tool automatically or interactively inserts buffers in the netlist, adjusts drive strength, and repairs timing violation paths until the timing under multi-mode and multi-angle conditions meets the requirements, generating the final gate-level netlist.

[0032] Furthermore, IR analysis is performed based on the parasitic parameters, including: generating a view file through an IR analysis tool based on the parasitic parameters; wherein the view file contains the power network topology, parasitic parameters and pin information of the chip; when the chip is in static state, static IR analysis is performed through the make static_ir command; wherein, the static IR analysis evaluates the static IR performance of the power network by calculating the DC voltage drop and average current density distribution of the power network; when the chip is in a dynamic working state, dynamic IR analysis is performed through the make dynamic_ir command; wherein, the dynamic IR analysis obtains the flip information of the chip by reading the VCD waveform file or the SAIF flip activity file, and calculates the AC voltage drop and transient current density distribution of the power network in combination with the flip information to evaluate the dynamic IR performance of the power network; and an IR analysis report is generated based on the results of the static IR analysis and the dynamic IR analysis.

[0033] Specifically, R stands for Voltage Drop and Electro Migration. Among them, I represents electric current and R represents resistance. IR analysis tools (such as Voltus, RedHawk, etc.) will generate a view file (view file) based on the parasitic parameter file (such as SPEF, SBPF, etc.) as the input of IR analysis. The view file usually contains the following information: Power network topology: describes the hierarchy, connection relationship and physical properties of the power network in the chip, such as the size, spacing, material, etc. of the power grid, power ring, power line, etc. Parasitic parameters: including the parasitic resistance and parasitic capacitance values ​​of each wiring segment in the power network. These parameters determine the voltage drop and current distribution characteristics of the power network. Pin information: including the location, type, load and other properties of the chip's power pins, ground pins, signal pins, etc. This information affects the power supply and load distribution.

[0034] Static IR analysis (make static_ir): Static IR analysis is performed when the chip is in a static state, assuming the circuit is in a steady state with no signal flips and no dynamic current. The purpose of static IR analysis is to evaluate the DC characteristics of the power network, namely the spatial distribution of voltage drop (IR drop) and current density (current density). The make static_ir command initiates static IR analysis, which calls the IR analysis tool, reads the view file, and performs the following calculations: DC voltage drop: Based on Ohm's law (V=IR), the voltage drop at each node in the power network is calculated, that is, the difference between the power supply voltage and the actual voltage. A larger voltage drop indicates a greater impedance of the power network and poorer power quality. Average current density: Based on Kirchhoff's current law (KCL), the average current density of each wiring segment in the power network is calculated, that is, the ratio of current intensity to wiring cross-sectional area. A larger current density indicates a heavier wiring load, resulting in higher heat generation and reliability risks.

[0035] Dynamic IR Analysis (make dynamic_ir): Dynamic IR analysis is performed when the chip is in dynamic operation, taking into account the effects of signal toggle and dynamic current. The purpose of dynamic IR analysis is to evaluate the AC characteristics of the power network, namely, the temporal variation of voltage drop and current density. Extracting toggle information is a key step in dynamic IR analysis, providing the necessary input for calculating AC voltage drop and transient current density. Toggle information reflects the dynamic behavior of each signal in the circuit, namely, the changes in signal value. The IR analysis tool extracts toggle information by reading VCD (Value Change Dump) waveform files or SAIF (Switching Activity Interchange Format) switching activity files. The specific steps for extracting toggle information are as follows: File format parsing: The IR analysis tool first identifies the input file format (such as VCD or SAIF) and invokes the corresponding file parser to read the file contents into memory and convert them into internal data structures. Signal mapping: Based on the signal definitions and design hierarchy in the file, the IR analysis tool constructs a signal mapping table, mapping signal names in the file to actual nodes and nets in the circuit. Extract flip information: The IR analysis tool will traverse each time point or each signal in the file, extract the corresponding flip count, flip time, flip rate and other information, and store it in the internal data structure. Calculate flip statistics: The IR analysis tool will count and calculate the extracted flip information to obtain indicators such as the total flip count, average flip rate, and maximum flip frequency of each signal for subsequent dynamic IR analysis. Associate to the power network: The IR analysis tool will associate the extracted flip information with the corresponding nodes and networks of the power network as input for calculating the AC voltage drop and transient current density. By extracting flip information, the IR analysis tool can obtain the dynamic behavior characteristics of the circuit and convert it into dynamic excitation of the power network, thereby realizing the calculation of AC voltage drop and transient current density, and evaluating the dynamic IR performance of the power network.

[0036] Static IR analysis is used to evaluate the DC characteristics of the power network, such as the initial layout of power traces, the location of power pins, and the structure of the power grid. It is usually performed in the early stages of the design to provide guidance for subsequent optimization. Dynamic IR analysis is used to evaluate the AC characteristics of the power network, such as the width of power traces, the number and location of power decoupling capacitors, and the effectiveness of clock gating and power-down techniques. It is usually performed in the later stages of the design to provide final verification of power integrity.

[0037] Compared with the existing technology, the advantages of this application are:

[0038] By introducing the generation of standard cell process libraries, the RTL design, process library files, and constraint files are preprocessed to generate the flow library configuration file value_lib.tcl, resolving compatibility issues between different designs using process libraries. This standardized process library processing significantly reduces duplication in subsequent synthesis, layout, and routing steps, improving design efficiency.

[0039] A two-stage synthesis strategy is used: a preliminary gate-level netlist is synthesized based on the flow library configuration file value_lib.tcl. This preliminary gate-level netlist is then subjected to isochronous and logic optimization to generate an optimized gate-level netlist. This phased optimization synthesis approach further improves the timing characteristics of the design, reduces timing violations, and eases timing closure while ensuring optimal design area.

[0040] Using an incremental physical design approach, we decompose the layout and routing tasks into sub-steps, including floorplan, placement, CTS, routing, and eco. We use the make command to automate the execution and interface connection of each step. This modular, incremental physical design process fully leverages existing layout and routing results, focuses on local optimization, accelerates layout and routing convergence, and shortens the physical design cycle.

[0041] The platform integrates multiple physical verification tools and inspection methods to perform comprehensive quality checks on layout and routing results, including antenna effect checks, design rule checks, and layout-to-schematic comparisons. This comprehensive, multi-tool physical verification platform automatically identifies layout and routing defects and provides timely feedback to designers for corrections, ensuring design manufacturability from the outset and avoiding tapeout risks caused by physical defects.

[0042] Static and dynamic power analysis are introduced to comprehensively evaluate the chip's power consumption characteristics. Static power analysis extracts parasitic parameters and combines them with standard static timing analysis to calculate the chip's average power consumption and the power distribution of critical paths. Dynamic power analysis reads VCD waveforms or SAIF flip files and combines them with parasitic parameters to calculate the chip's transient and peak power consumption. Power analysis results can guide chip power optimization, such as inserting power gating in high-power areas and optimizing the clock tree to meet power budgets.

[0043] Static IR analysis and dynamic IR analysis are introduced to comprehensively evaluate the chip's power integrity. Static IR analysis solves the DC equations of the power network, calculates the chip's voltage drop and current density distribution, and identifies static IR violations. Dynamic IR analysis uses signal toggle information to solve the dynamic equations of the power network, calculate the chip's transient voltage drop and transient current density, and identify dynamic IR violations. IR analysis results can guide chip power optimization, such as adjusting power supply planning, increasing power line width, and inserting decoupling capacitors to meet IR constraints.

[0044] By organically integrating all aspects of digital back-end design, a Tcl script-based design platform has been formed. Designers only need to provide input files (such as RTL design, process library, and SDC constraints) according to specifications to start the full design process with a single click, significantly reducing the designer's workload and skill requirements. Furthermore, design managers can embed design constraints into the entire process through customized Tcl scripts, enabling automated checking of design specifications and reducing human error. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present application will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same numbers represent the same structures, wherein:

[0046] Figure 1 This is an exemplary flow chart of a method for designing a digital backend full-process script according to some embodiments of the present application;

[0047] Figure 2 is an exemplary flow chart for generating layout and routing data according to some embodiments of the present application;

[0048] Figure 3 is an exemplary flow chart of performing antenna inspection according to some embodiments of the present application;

[0049] Figure 4 is an exemplary flow chart of performing power consumption analysis according to some embodiments of the present application;

[0050] Figure 5 is an exemplary flow chart for performing IR analysis according to some embodiments of the present application. DETAILED DESCRIPTION

[0051] The method and system provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0052] Figure 1This is an exemplary flow chart of a method for full-process script design of a digital backend, according to some embodiments of the present application. This application provides a method for full-process script design of a digital backend, aiming to improve the efficiency of chip digital backend design. By introducing standardized interfaces, a modular architecture, and automated processes, this method achieves full-process optimization from RTL-level design to GDSII layout. The method includes: receiving an RTL behavioral-level netlist, process library files, and constraint files as input, and a flow library configuration file (value_lib.tcl); using the flow library configuration file (value_lib.tcl) to generate a gate-level netlist and a corresponding synthesis report; performing logic synthesis using the "make syn" command based on the behavioral-level netlist to generate a gate-level netlist and layout and routing data; performing antenna checks using the "make ant" command, design rule checks using the "make drc" command, and comparing the generated layout with the schematic diagram using the "make lvs" command based on the layout and routing data; outputting a GDSII layout file using the "make out" command based on the layout and routing data; performing power consumption analysis based on the layout and routing data; and performing IR analysis based on parasitic parameters.

[0053] The Flow library configuration file, value_lib.tcl, receives as input an RTL behavioral netlist, process library files, and constraint files. The RTL behavioral netlist uses Verilog or VHDL to describe the chip's logical functions and structure, such as module partitioning, interface definition, and state machine description. The process library file is used to define the physical characteristics (such as size and pin layout) and electrical characteristics (such as delay and drive strength) of standard cells. The constraint file is used to define the timing constraints (such as clock frequency, setup and hold time) and physical constraints (such as area, power consumption, and pin layout) of the chip design. Using the RTL behavioral netlist, process library files, and constraint files, logic synthesis is performed using a logic synthesis tool (such as Design Compiler) to generate the behavioral netlist file, value.v. Specifically, the logic synthesis tool first reads the RTL behavioral-level netlist and converts the high-level hardware description language into a register transfer-level (RTL) data flow description; then, combined with the standard cell information provided by the process library file and the constraints provided by the constraint file, the behavioral-level data flow description is mapped to the gate-level netlist, realizing automatic conversion and optimization from the behavioral level to the gate level.

[0054] The flow library configuration file, value_lib.tcl, is generated using the make gen function in flow using the flow configuration file, value.tcl. Specifically, the library file format conversion tool first reads the behavioral netlist file, value.v, and extracts the logical function (e.g., NAND gate, NOR gate), input / output ports (e.g., signal line direction and bit width), and timing parameters (e.g., delay and fan-out) of each standard cell. It then converts the data into the text syntax and data structure defined in the Synopsys Liberty format (.lib). The Liberty format is a common library file format in the industry, recognized and used by mainstream EDA tools. The standard cell library file, value_lib.tcl, contains three key pieces of information: cell information (cell) of the process library defines the physical dimensions, pin layout, and manufacturing hierarchy of each standard cell; logical function information (pin) defines the input / output ports, truth table, and logical expression of each standard cell; and timing constraint information (timing) defines the delay, fan-out, and setup / hold time of each standard cell.

[0055] The library configuration file value_lib.tcl is used to generate a gate-level netlist and the corresponding synthesis report. This includes generating a synthesis constraint file sdc file based on the flow library configuration file value_lib.tcl, combined with timing constraints and physical constraints. Among them, the timing constraint defines the chip's clock frequency (such as 100MHz), setup time (such as 0.2ns) and hold time (such as 0.1ns) to guide logic synthesis and optimization; the physical constraint defines the chip's area (such as 10mm 2 ), power consumption (such as 500mW), and pin location (such as IORing layout) are used to control the physical characteristics of the synthesis results. The synthesis constraint file stores constraint information in the Synopsys Design Constraints (SDC) format.

[0056] Using a synthesis tool (such as Design Compiler), perform logic synthesis on the behavioral netlist using the make syn command based on the synthesis constraint file (sdc) to generate a gate-level netlist with the optimal area and a synthesis report. Specifically, the synthesis tool first reads the behavioral netlist file (value.v), combines the gate-level components (such as NAND gates and flip-flops) with the constraints provided by the synthesis constraint file (such as timing and area), and then uses a logic mapping algorithm to map the gate-level netlist to the standard cells defined in the standard cell process library. Optimizations such as equivalent replacement and redundant logic removal are then performed to generate a gate-level netlist with the smallest area. The synthesis report summarizes metrics such as cell area, power consumption, and critical path timing for the synthesized circuit.

[0057] Perform timing optimization and logic optimization on the gate-level netlist to generate a further optimized gate-level netlist. Timing optimization adjusts the combinational logic on critical paths through logic reconstruction and buffer insertion, balancing path delays and reducing clock skew, thereby improving circuit timing performance. Logic optimization simplifies the combinational logic through Boolean minimization, constant propagation, and dead code elimination, removing redundant logic gates and reducing circuit area and power consumption.

[0058] Figure 2This is an exemplary flow chart for generating layout and routing data according to some embodiments of the present application. Layout and routing are performed based on the gate-level netlist Makeout to generate layout and routing data, including: generating a Multi-Mode Multi-Corner (MMMC) file using the make_mmmc command to define constraint information under different operating modes (e.g., normal mode, test mode) and process angles (e.g., typical, worst-case). The MMMC file contains library file links, process parameter settings, and constraint condition settings under different conditions, providing a complete constraint model for subsequent layout and routing. An initialization file is generated using the make_init command to initialize chip design environment parameters, such as the design library path, technology file path, and layout hierarchy definition. The initialization file ensures that layout and routing tools (e.g., ICC II) can correctly read the design data and technology files. A floorplan is generated using the make_fp command based on physical design constraints to determine the chip's physical die size and module location. Physical design constraints include chip area (e.g., 10mm x 10mm), chip IO pin locations (e.g., arranged around the perimeter), and pre-layout macrocell locations (e.g., SRAM placed in the center). An interactive graphical user interface (GUI) allows intuitive floorplan adjustments. The make_place command performs standard cell placement and macrocell placement based on placement constraints. Standard cells include basic logic gates such as NAND gates, NOR gates, and flip-flops; macrocells include complex functional modules such as SRAM and phase-locked loops (PLLs). Placement constraints define rules such as spacing, alignment, and orientation between cells. The layout engine generates a floorplan by solving a constraint-based optimization problem. The make_cts command performs clock tree synthesis based on clock constraints, generating the clock tree topology and buffer insertion plan. Clock tree synthesis uses a recursive partitioning algorithm to construct a balanced clock tree and insert buffers at nodes and leaves to minimize clock skew. The make_route command performs routing to connect standard cells and macrocells based on routing resources and routing constraints. Routing resources define the physical properties of the metal layer, such as line width, spacing, resistance and capacitance; routing constraints define line length matching, antenna rules, current density, etc.The routing engine solves a constraint-based maze algorithm to determine routing topology and linewidth allocation. Using the make_postopt command, the post-routed design undergoes parasitic extraction and static timing analysis based on optimization objectives. Parasitic extraction considers the resistance and capacitance effects of routing and back-annotates them into the gate-level netlist. Static timing analysis, using MMMC files as input, calculates the circuit's timing slack under different process conditions, identifies violating paths, and guides layout and routing optimization.

[0059] Figure 3 This is an exemplary flowchart for performing antenna inspection according to some embodiments of the present application. The antenna effect inspection is performed using the antenna inspection tool (Antenna Checker) through the make_ant command. The input data for the antenna effect inspection is the design data after layout and routing, including layout files (such as GDS, OASIS, etc.) and parasitic parameter files (such as SPEF, DSPF, etc.). The layout file contains the physical structure information of the chip, such as the geometry, position and hierarchical relationship of the metal wiring; the parasitic parameter file contains the electrical characteristic information of the metal wiring, such as resistance, capacitance and inductance. Designers need to generate layout and routing data that conforms to process rules and design constraints through the layout and routing process of the EDA tool.

[0060] Antenna checking tools are usually provided as plug-ins for EDA tools or as standalone software. Designers need to configure the parameters and options of the antenna checking tool according to specific process requirements and design rules. The main configuration items include: Process rules: define geometric parameters such as the minimum width, minimum spacing, and maximum length of different metal layers, as well as antenna ratio thresholds in different scenarios. Design rules: define the layout constraints and connection rules of the chip's functional units, power networks, clock networks, etc. Check rules: define the specific algorithms and standards for antenna effect checking, such as the calculation formula for the antenna ratio and the judgment conditions for violating networks.

[0061] Designers launch the Antenna Check tool to analyze layout and routing data by executing the make_ant command in the EDA tool's command line interface or a script file. The Antenna Check tool automatically reads the layout file and parasitic parameter file and calculates the antenna ratio of each signal net based on the configured process rules, design rules, and checking rules. The specific calculation process includes: Extracting Metal Routing: Based on the geometric information in the layout file, the metal routing for each signal net is extracted and its length and area are calculated. Extracting Transistors: Based on the device information in the layout file, the transistors connected to each signal net are extracted and their gate areas are calculated. Calculating Antenna Ratio: Based on the antenna ratio calculation formula, the antenna ratio of each signal net is calculated and compared with the threshold specified by the process. Common antenna ratio calculation formulas include: Metal 1 Antenna Ratio = Metal 1 Area / Gate Area; Metal 2 Antenna Ratio = (Metal 1 Area + Metal 2 Area) / Gate Area; Metal 3 Antenna Ratio = (Metal 1 Area + Metal 2 Area + Metal 3 Area) / Gate Area; ... Generate violation report: For signal networks whose antenna ratio exceeds the threshold, the Antenna Check Tool generates a violation report that identifies the name, location, antenna ratio, and severity of the violating network.

[0062] Designers can review the antenna check report to understand the antenna effect risks in their designs. The report is typically presented in text, table, or graphical format and includes the following: Net Violation Summary: This report summarizes the number, type, and distribution of violating nets in the design. Net Violation Detail: This report lists each violating net's name, location, connected devices, antenna ratio, and severity. Net Violation Visualization: Violating nets are identified with different colors or icons in the layout editor, making it easier for designers to locate and analyze them. For violating nets discovered during the antenna check, designers need to optimize the layout and routing to eliminate or mitigate the antenna effect. Common optimization methods include: Inserting protection diodes: Inserting protection diodes on violating nets provides a discharge path to ground, preventing damage to the transistor gate oxide. Adjusting metal routing: By changing the width, length, and level of metal routing, the metal routing area can be reduced, thereby reducing the antenna ratio. Adjusting device layout: By changing the position, orientation, and size of transistors, the gate area can be increased, thereby reducing the antenna ratio. Split long signal networks: For long signal networks that span multiple metal layers, insert buffers or bridge resistors in the middle layer to split the long signal network into multiple short signal networks to reduce the antenna ratio.

[0063] Use the make_drc command to perform design rule checking using the Design Rule Checker (DRC). The input data for design rule checking is the design data after placement and routing, typically including layout files (such as GDS or OASIS). Layout files contain information about the chip's physical structure, such as the geometry, location, and hierarchical relationships of different routing layers. Designers need to generate layout data that reflects the final physical design through the EDA tool's placement and routing process. Process design rules define the geometric parameters and physical constraints of different routing layers, such as minimum line width, minimum spacing, inter-layer routing rules, routing blocking rules, and boundary extension rules. Process design rules are provided in specific file formats (such as Tech Files and Calibre DRC Rule Files) and must be obtained from the process vendor or PDK (Process Design Kit). Checking rules define the specific algorithms and criteria for design rule checking, such as rule priority, check areas and layers, and violation marking. Checking rules can be customized and optimized based on design characteristics and requirements. Checking options define the execution method and output format of the design rule check, such as parallel processing, memory usage, and output file format.

[0064] Data preprocessing: Perform preprocessing operations such as format conversion, data compression, and layer extraction on the layout data to improve inspection efficiency and accuracy. Rule matching: Use a rule-based pattern matching algorithm to compare the layout data with the process design rules, quickly scan the entire chip layout, and find graphics and locations that violate the design rules. Commonly used pattern matching algorithms include scan line algorithms, region decomposition algorithms, and vectorization algorithms. Violation marking: For graphics that violate the design rules, the design rule checking tool will generate violation markers (error markers) to identify the type, location, and severity of the violation. Violation markers are usually presented in the layout editor in the form of different colors or icons to facilitate positioning and analysis by designers. Result output: The design rule checking tool will generate a design rule check report (DRC Report) that summarizes the inspection results and statistical information. The report is usually output in the form of text, tables, or graphics, and contains the number, type, distribution, and detailed information of the violations.

[0065] By reviewing the design rule check report and violation markers, you can understand design rule issues in your design. A design rule check report typically includes the following: Violation summary information: This provides statistics on the number, type, and distribution of violations in the design, such as the total number of DRC violations and the number of violations by rule type. Violation details: This lists each violation's location, hierarchy, rule type, severity, and related graphics. Violation visualization: Violations are identified in the layout editor with different colors or icons, making it easier for designers to locate and analyze them. Common repair methods include: Manual repair: Based on violation markers and design rule reports, designers manually adjust the geometry in the layout, such as moving, resizing, deleting, or adding graphics. Automatic repair: Using the automatic repair features provided by EDA tools, such as DRC Auto-Fix and layout optimization, the layout is automatically adjusted to eliminate violations. Automatic repair is often based on predefined repair rules and heuristic algorithms, which can quickly fix simple violations and reduce the workload of manual repair. Design Rule Waivers (DRC Waivers): For special design situations, such as analog circuits and custom circuits, designers can apply for design rule waivers, allowing violations of certain design rules in specific areas or under specific conditions. Design rule waivers require review and approval, and receive special treatment during design rule checks.

[0066] Use the Layout vs. Schematic (LVS) checking tool via the make_lvs command to perform a consistency check between the layout and the schematic. The input data for the LVS check includes layout and routing data and gate-level netlists. Layout and routing data is typically provided as layout files in formats such as GDS and OASIS, and contains information about the physical structure of the chip, such as device layout, wiring geometry, and hierarchical relationships. Gate-level netlists are typically provided in SPICE or Verilog format, describing the logical functions of the circuit and device connections, and are schematic representations of the circuit design. Gate-level netlists can be generated through logic synthesis or manual programming.

[0067] LVS checking tools are typically provided as plug-ins for EDA tools or standalone software. Designers need to configure the LVS checking tool's parameters and options based on specific process requirements and design constraints. Key configuration items include: Process files: These define the physical parameters and extraction rules for different device types, such as the geometric parameters and parasitic parameter extraction methods for devices like MOSFETs, resistors, and capacitors. These files are typically provided in formats like Tech Files and Calibre LVS Rule Files and must be obtained from the process vendor or the PDK (Process Design Kit). Mapping files: These define the mapping between layout devices and gate-level devices, such as the mapping between MOSFET geometric parameters in the layout and MOSFET electrical parameters in the gate-level netlist. Mapping files are typically provided in formats like mapping files or layer map files and must be configured based on the device types and naming conventions of the design. Comparison options: These define the LVS comparison methods and tolerances, such as the comparison tolerances for device parameters, the netlist normalization method, and the blackbox processing method.

[0068] By executing the make_lvs command in the EDA tool's command line interface or script file, the LVS checking tool is launched to compare the layout and routing data with the gate-level netlist. The LVS checking tool automatically reads the layout file, gate-level netlist, and configuration file, and performs a consistency check on the two based on the configured process file, mapping file, and comparison options. The specific checking process includes: Layout extraction: Based on the layout file and process file, the device, network, and connection information in the layout are extracted to generate a layout netlist. The layout extraction process identifies the device geometry in the layout and calculates the device's electrical parameters, such as the W / L ratio of MOS tubes and the resistance value of resistors, based on the extraction rules in the process file. Netlist preprocessing: Preprocess the layout extraction netlist and gate-level netlist, such as removing redundant devices and nets, merging equivalent devices and nets, and renaming matching devices and nets, to facilitate subsequent comparison. Topology Comparison: Using algorithms such as normalization and isomorphic matching, the topological structures of the layout-extracted netlist and the gate-level netlist are compared for consistency. This involves checking whether the device types, number of devices, and connectivity relationships match. This topology comparison considers device orientation, symmetry, and equivalence, as well as the hierarchical and modular organization of the netlist. Parameter Comparison: For topologically matched devices, the electrical parameters are further compared to ensure they are within the specified tolerances. This involves checking whether the device parameters extracted from the layout match those in the gate-level netlist. This parameter comparison considers factors such as device process corners, environmental conditions, and test conditions. Result Output: The LVS checking tool generates an LVS report summarizing the comparison results and statistical information. The report is typically output in text, table, or graphical format and includes a summary of the comparison results, a list of mismatched devices and nets, and a visualization of the layout and schematic.

[0069] Analyze LVS Check Results: Comparison Results Summary: Counts the number of matching and mismatching devices, nets, and connections between the layout and schematic, providing an overall assessment of the consistency check. Mismatched Devices and Nets List: Lists the devices and nets found to be inconsistent during topology or parameter comparison, and provides specific reasons for the mismatch, such as different device types, device parameters out of tolerance, or missing connections. Layout and Schematic Visualization: Mismatched devices and nets are identified with different colors or icons in the layout and schematic editors, making it easier for designers to locate problems.

[0070] Fix LVS mismatch: For mismatches discovered by LVS checks, designers need to analyze the causes and repair the layout or schematics to ensure consistency between the two. Common mismatch causes and repair methods include: Layout errors: The placement of devices and wiring connections in the layout are inconsistent with the schematics, and the layout file needs to be modified, such as adjusting the device position, modifying the wiring direction, etc. Schematic errors: The devices and networks in the schematics are inconsistent with the design intent, and the gate-level netlist needs to be modified, such as adding missing devices, deleting redundant connections, etc. Inconsistent naming: The names of devices and networks in the layout and schematics are inconsistent, and the naming rules or mapping files need to be modified to unify the naming conventions of the two. Parameter matching: The device parameters extracted from the layout are inconsistent with the device parameters in the schematics, and the device's geometric parameters or extraction rules need to be adjusted, such as adjusting the W / L ratio of the MOS tube, modifying the layout of the resistor, etc.

[0071] Based on the layout data, the make_out command is used to output a GDSII layout file, completing the digital back-end design. This process involves the following steps: After ensuring that the layout data meets design rules, antenna rules, and LVS consistency requirements through physical verification, the make_out command is used to call the layout exporter to convert the layout data into a GDSII-formatted layout file. The layout exporter first reads the layout database (such as the DEF / LEF format) and extracts the geometry, connectivity, and hierarchy information. The geometry defines geometric elements such as polygons, paths, and text in the layout; the connectivity defines topological elements such as nets, pins, and vias; and the hierarchy defines logical elements such as cells, arrays, and blocks. The layout exporter then encodes the extracted geometry, connectivity, and hierarchy information into binary records in the GDSII stream format. The GDSII stream format consists of a Header Record, Library Record, Structure Record, Element Record, and Tail Record, using a Tag-Length-Value encoding scheme. Each record begins with a specific tag, followed by the data length and the actual data value. The layout export tool maps the contents of the layout and routing database to corresponding GDSII records and arranges the records in a standardized order. During the encoding process, the layout export tool uses the mapping table provided by the Process Design Kit to convert abstract information such as layer names and wiring rules in the layout and routing database into specific information such as layer numbers and data types in the GDSII file. Different processes may use different GDSII layer numbering and naming conventions. The layout export tool also supports custom GDSII encoding options such as resolution, units, and compression to meet diverse customer requirements. Finally, the layout export tool writes the encoded GDSII records to a file, generating a complete GDSII layout file. GDSII layout files are stored in ASCII or binary format and usually have the extension .gds or .gdsii.GDSII layout files are a common layout exchange format in the industry and can be directly passed to chip manufacturers (such as TSMC and GlobalFoundries) for the production of photomasks and wafers. GDSII layout files can also be imported into other EDA tools for subsequent layout verification and manufacturability analysis. The make_out command converts the layout and routing database into a GDSII layout file through the layout output tool, achieving the final deliverable of the digital back-end design. GDSII layout files are an important interface between digital back-end design and chip manufacturing, and their quality directly affects the yield and reliability of the chip.

[0072] In addition, this method also integrates power consumption analysis and IR analysis functions as important supplements to digital back-end design:

[0073] Figure 4 This is an exemplary flow chart for performing power consumption analysis according to some embodiments of the present application. Power consumption analysis is performed based on layout and wiring data. According to the layout and wiring data, a parasitic extraction tool (Parasitic Extraction Tool), such as Star-RCXT, Calibre xRC, etc., is called through the make_starrc_step or make_starrc command to extract the parasitic parameters of the wiring, including parasitic resistance and parasitic capacitance. The parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance values ​​of each section of wiring based on the geometric parameters (such as line width, line length) and process parameters (such as metal resistivity, dielectric constant) of the wiring, and generates a parasitic parameter model file (such as SPEF, DSPF format). The parasitic parameters reflect the electrical characteristics of the wiring and are important inputs for timing analysis and power consumption analysis.

[0074] Use the PrimeTime Static Timing Analysis Tool to perform standard static timing analysis (Standard STA) based on the gate-level netlist and parasitic parameters using the make_pt_step command. Perform multi-mode, multi-corner static timing analysis (Multi-Mode, Multi-Corner STA) using the make_pt_dmsa command and generate a timing analysis report. Standard static timing analysis calculates data path delay, setup time, hold time, and other timing metrics under typical process corners and typical operating modes to evaluate circuit performance. Multi-mode, multi-corner static timing analysis calculates timing metrics such as timing slack and violation count for statistical paths under multiple process corners (e.g., worst-case and best-case) and operating modes (e.g., high-voltage and low-voltage) to evaluate circuit robustness.

[0075] Based on the timing analysis report, use the PrimeTime Static Power Analysis Tool (make_ptpx) to perform static power analysis and generate a power analysis report. Static power analysis calculates the circuit's dynamic power, static power, peak power, and other power consumption metrics based on the gate-level netlist, parasitic parameters, and switching activity information, and analyzes the temporal and spatial distribution of power consumption. The power analysis report provides guidance for low-power chip design.

[0076] Based on the timing analysis report, the ECO optimization tool (Engineering Change Order Tool) uses the make_eco command to debug and optimize the multi-mode, multi-angle static timing analysis results and correct timing violations. The ECO optimization tool automatically or interactively inserts buffers, adjusts driving strength, and adjusts load capacitance in the gate-level netlist, fixing timing violation paths until the multi-mode, multi-angle timing metrics meet the design constraints, generating the final gate-level netlist. The ECO optimization process typically requires multiple iterations until timing convergence is achieved. Power analysis, based on layout and routing data, evaluates circuit performance, power consumption, and robustness through steps such as parasitic parameter extraction, static timing analysis, and static power analysis. Timing closure is achieved through ECO optimization. Power analysis runs throughout the entire digital back-end design process, tightly integrated with layout and routing and physical verification to form a closed-loop feedback loop and continuous optimization. The make command automatically invokes the corresponding EDA tool, executes each analysis step, and generates a standardized analysis report. Power consumption analysis is crucial to chip quality and cost. Designers must comprehensively weigh multiple objectives, such as area, timing, and power consumption, and continuously adjust and optimize the design to ultimately achieve the optimal design solution.

[0077] Figure 5 This is an exemplary flow chart for performing IR analysis according to some embodiments of the present application. According to parasitic parameters, IR analysis (IRAnalysis) is performed, including the following steps: According to the parasitic parameters, the step of generating a view file by the IR analysis tool: First, the IR analysis tool reads the parasitic parameter file, such as SPEF (Standard Parasitic Exchange Format) or DSPF (Detailed Standard Parasitic Format) format. The parasitic parameter file is generated by the parasitic parameter extraction tool and contains parasitic parameter information such as resistance, capacitance, and inductance of the chip wiring. The IR analysis tool parses the parasitic parameter file and extracts the resistance value (resistance) and inductance value (inductance) therein for subsequent IR analysis.

[0078] The IR analysis tool then reads the chip's layout and routing data, such as in DEF (Design Exchange Format) or LEF / DEF (Library Exchange Format / Design Exchange Format) formats. This layout and routing data describes the chip's physical design, including geometric information such as the power network's routing topology and pin locations. The IR analysis tool analyzes the layout and routing data, identifying the power network's structure, such as power rings, power planes, and power straps, and extracting pin information, such as pin coordinates, layers, and clearance attributes. The IR analysis tool then matches and correlates the parasitic parameters with the layout and routing data to generate a power network model for the chip. Using a geometric matching algorithm, the IR analysis tool maps the resistance and inductance values ​​in the parasitic parameter file to the corresponding line segments in the layout and routing data, resulting in a power network topology with parasitic parameters. The power network model is represented as a graph, with nodes representing pins, edges representing routing, and weights representing parasitic parameters.

[0079] Finally, the IR analysis tool converts the power network model into a view file in a specific format, such as Milkyway or OpenAccess. The view file is stored in ASCII or binary format and adheres to the standard interface specifications of EDA tools. The view file contains complete information about the chip's power network, including topology, parasitic parameters, and pin properties. It can be read and processed by other EDA tools, such as place-and-route tools and timing analysis tools. View file generation must be consistent with layout and routing to ensure that the power network model matches the actual routing.

[0080] IR analysis tools typically provide flexible configuration options and scripting interfaces, allowing users to customize view file generation parameters, such as precision, units, and filters, to meet diverse design and tool requirements. Users can modify configuration files or write scripts to control the view file generation process, such as selecting specific layers, setting threshold conditions, and merging duplicate elements, thereby optimizing view file quality and efficiency.

[0081] When the chip is in a static state, the steps for performing static IR analysis using the make_static_ir command are as follows: First, invoke the IR analysis tool using the make_static_ir command and load the previously generated view file. The view file contains the chip power network topology, parasitic parameters, and pin information, serving as the foundational data for static IR analysis. The IR analysis tool reads the view file and constructs a matrix equation for the power network, where the rows and columns of the matrix correspond to the nodes of the power network, and the elements of the matrix correspond to the resistance values ​​between the nodes. The IR analysis tool then sets the boundary and load conditions for the static IR analysis. The boundary conditions specify the voltage values ​​of the power supply and ground nodes of the power network, such as VDD = 1.0V and VSS = 0V. The load conditions specify the current consumption distribution of the power network, specifically the static current value for each pin. The static current value can be obtained through design specifications, power estimation, and other methods, reflecting the static power consumption characteristics of the chip.

[0082] Next, the IR analysis tool solves the DC voltage drop and average current density distribution of the power network. Based on the modified nodal analysis (MNA) algorithm, the IR analysis tool calculates the voltage and current values ​​of each node in the power network. The DC voltage drop refers to the voltage difference between the power node and the load node, reflecting the IR voltage drop of the power network. The average current density refers to the average current intensity per unit area, reflecting the current distribution of the power network. The IR analysis tool iteratively solves the matrix equation to obtain converged voltage and current values ​​and saves the results in memory or a file. The IR analysis tool then post-processes and analyzes the DC voltage drop and average current density. The IR analysis tool extracts key IR performance indicators such as maximum IR drop, minimum voltage level, and maximum current density, compares them with design constraints, and identifies IR violations that exceed the threshold. The IR analysis tool also generates intuitive visualization results, such as voltage drop heatmap and current density vectormap, to help designers intuitively understand the IR distribution.

[0083] Finally, the IR analysis tool generates a static IR analysis report, summarizing IR performance metrics and violation information, and providing optimization suggestions and remediation guidance. The static IR analysis report is presented in tables and charts, allowing designers to quickly identify and resolve IR issues. Common optimization techniques include increasing the metal width of the power network, adding power vias, and adjusting pin locations to reduce resistance and balance current density. Based on the static IR analysis report, designers can iteratively optimize the power network until IR performance requirements are met.

[0084] When the chip is in dynamic operation, the steps for dynamic IR analysis using the make_dynamic_ir command are as follows: First, call the IR analysis tool using the make_dynamic_ir command and load the previously generated view file and flip activity file. The view file provides static information about the power network, while the flip activity file provides dynamic flip information about the pins. The flip activity file can be in VCD (Value Change Dump) format or SAIF (Switching Activity Interchange Format) format, recording the flip count and flip time of each pin at different time points. The IR analysis tool reads the view file and flip activity file to extract the power network topology, parasitic parameters, and flip activity data.

[0085] The IR analysis tool then preprocesses and maps the flip activity. The IR analysis tool parses and filters the flip activity file, extracting pin flip information related to the power network. The IR analysis tool maps the flip activity data to the corresponding pins of the power network, generating a dynamic current waveform for each pin. The dynamic current waveform reflects the instantaneous current consumption of the pin at different time points, taking into account the effects of the number of flips and flip time. The IR analysis tool also performs time alignment and interpolation to ensure that the dynamic current waveform matches the time step of the power network.

[0086] Next, the IR analysis tool sets the boundary conditions and simulation parameters for dynamic IR analysis. Similar to static IR analysis, dynamic IR analysis also requires specifying the voltage values ​​of the power and ground nodes of the power network. Furthermore, dynamic IR analysis requires setting parameters such as the simulation time range, time step, and convergence criteria to control the accuracy and efficiency of the simulation. The IR analysis tool also supports multi-threading and distributed simulation to accelerate dynamic IR analysis of large-scale power networks.

[0087] The IR analysis tool then performs dynamic IR simulation to calculate the AC voltage drop and transient current density distribution of the power network. Based on the power network's matrix equations and dynamic current waveforms, the IR analysis tool employs transient simulation algorithms, such as the implicit Euler method and the trapezoidal method, to solve for node voltages and branch currents in the power network at different time points. AC voltage drop refers to the dynamic voltage difference between the power node and the load node, reflecting the transient IR drop of the power network. Transient current density refers to the dynamic current intensity per unit area, reflecting the dynamic current distribution of the power network. The IR analysis tool iteratively solves the matrix equations to obtain converged voltage and current waveforms and saves the results in memory or a file.

[0088] Next, the IR analysis tool post-processes and analyzes the dynamic IR simulation results. The IR analysis tool extracts key dynamic IR performance metrics, such as peak IR drop, minimum voltage amplitude, maximum transient current density, and average dynamic power, and compares them with design constraints, identifying dynamic IR violations that exceed thresholds. The IR analysis tool also generates dynamic IR visualizations, such as voltage waveform plots and current density animations, to help designers intuitively understand dynamic IR behavior.

[0089] Finally, the IR analysis tool generates a dynamic IR analysis report summarizing dynamic IR performance metrics, violation information, and optimization recommendations. The dynamic IR analysis report is presented in various formats, including tables, waveforms, and animations, allowing designers to comprehensively evaluate the dynamic IR characteristics of the power network. Common optimization techniques include adjusting the power network topology, adding decoupling capacitors, and balancing the distribution of flip-flop activity to suppress transient noise and minimize dynamic IR voltage drop. Based on the dynamic IR analysis report, designers can iteratively optimize the dynamic behavior of the power network and chip until dynamic IR performance requirements are met.

[0090] Based on the results of static and dynamic IR analysis, the IR analysis tool generates an IR analysis report (IR Analysis Report). The IR analysis report presents the IR performance indicators of the power network in text and chart form, such as maximum IR voltage drop, maximum current density, minimum voltage amplitude, etc., and identifies the location and severity of IR violations. The IR analysis report also provides intuitive visualization results such as voltage drop heatmaps and current density vectormaps to help designers quickly locate and fix IR problems.

[0091] Based on parasitic parameters and flip information, IR analysis uses static and dynamic IR analysis to evaluate the IR performance of a chip's power network, including key metrics such as DC voltage drop, AC voltage drop, and current density distribution, and generates an IR analysis report. IR analysis is closely related to power analysis, and together they ensure the chip's low power consumption and reliability. The make command automatically calls the IR analysis tool, executes the IR analysis process, and generates standardized analysis results. IR analysis is crucial to the design and optimization of power networks. It requires comprehensive consideration of multiple factors, including the chip's functionality, layout, and process, to balance IR performance and cost, ultimately achieving a stable and reliable power supply. IR analysis runs throughout the entire digital back-end design process, tightly integrated with layout and routing, power analysis, and other steps to form a closed-loop feedback loop and continuous optimization.

Claims

1. A method for designing a digital backend full-process script, characterized in that: include: Receive RTL behavioral level netlist, process library file and constraint file as input and generate library configuration file value_lib.tcl; Use the library configuration file value_lib.tcl to generate a gate-level netlist, perform logic synthesis through make syn, and generate the corresponding synthesis report; Based on the behavioral-level netlist, make syn performs logic synthesis to generate a gate-level netlist and generate layout and routing data; Based on the layout and routing data, use the make ant command to check the antenna, use the make drc command to check the design rules, and use the make lvs command to compare the generated layout with the schematic diagram. According to the layout and routing data, output the GDSII layout file through the make out command; Perform power consumption analysis based on layout and routing data; Perform IR analysis based on parasitic parameters.

2. The method for designing a digital backend full-process script according to claim 1, characterized in that: Generate the library configuration file value_lib.tcl, including: Receive RTL behavioral netlist, process library file and constraint file as input; the RTL behavioral netlist uses Verilog or VHDL language to describe the logical function and structure of the chip; the process library file is used to define the physical and electrical characteristics of the standard unit; the constraint file is used to define the timing constraints and physical constraints of the design; The RTL behavioral netlist, process library file, and constraint file are synthesized using a logic synthesis tool to generate a behavioral netlist file, value.v. The logic synthesis tool reads the RTL behavioral netlist, combines it with the process library file and constraint file, and converts the behavioral-level logic description into a gate-level circuit description, thus achieving the conversion from behavioral level to gate level. The flow configuration file value.tcl is used to generate the library configuration file value_lib.tcl through the library file format conversion tool. The library file format conversion tool reads the flow configuration file value.tcl and generates the flow library configuration file value_lib.tcl according to the format split view. The standard cell library file value_lib.tcl contains the cell information, logic function information and timing constraint information of the process library.

3. The method for designing a digital backend full-process script according to claim 2, characterized in that: Generate gate-level netlist Make syn and corresponding synthesis report, including: Generate the synthesis constraint file makesyn based on the flow library configuration file value_lib.tcl, combined with timing constraints and physical constraints. Timing constraints define the clock frequency, setup time, and hold time; physical constraints define the chip area, power consumption, and pin locations. Using a synthesis tool, perform logic synthesis on the generated behavioral netlist file value.v according to the synthesis constraint file to generate a gate-level netlist and a synthesis report syn report. The synthesis tool reads the behavioral netlist file value.v and the synthesis constraint file make syn, and performs logic synthesis to map the behavioral netlist into an area-optimized gate-level netlist based on the standard cell library. The synthesis report syn report includes area, power consumption, and timing. Perform isochronous optimization and logic optimization on the gate-level netlist to generate a gate-level netlist. Isochronous optimization balances path delays and reduces clock skew through logic reconstruction and buffer insertion. Logic optimization simplifies logic circuits through Boolean simplification, constant propagation, and dead code elimination.

4. The method for designing a digital backend full-process script according to claim 3, characterized in that: Generates placement and routing data, including: Generate the MMMC file through the make mmmc command to define the constraint information under different working modes and process angles; Generate an initialization file through the make init command to initialize the environment parameters of the chip design; Generate a floorplan based on the physical design constraints using the make fp command to determine the physical size and location of the chip. The physical design constraints include chip area, chip IO pin locations, and pre-layout macro cell locations. Use the make place command to perform standard cell layout and macro cell layout based on layout constraints. Standard cells include NAND gates, NOR gates, and flip-flops; macro cells include memories and PLLs. Perform clock tree synthesis based on clock constraints using the make cts command to generate clock tree allocation and buffer insertion plans to balance clock tree delays. Use the make route command to perform routing based on routing resources and routing constraints to connect standard cells and macro cells; Use the make postopt command to perform parasitic parameter extraction and static timing analysis on the post-routing design based on the optimization goals.

5. The method for designing a digital backend full-process script according to claim 4, characterized in that: Based on the layout and routing data, use the make ant command to check the antenna, use the make drc command to check the design rules, and use the make lvs command to compare the generated layout with the schematic diagram, including: Based on the layout and routing data, use the make ant command to check the antenna effect using the antenna check tool. The antenna check tool analyzes the metal wiring length, metal wiring area, and connected transistor gate area in the layout and routing data, calculates the antenna ratio of each signal network, compares it with the threshold, obtains the violating networks whose antenna ratio exceeds the threshold, and generates an antenna check report.

6. The method for designing a digital backend full-process script according to claim 5, characterized in that: Based on the layout and routing data, the design rule checking tool is used to perform design rule checking through the make drc command. The design rule checking tool compares the layout and routing data with the process design rules to check whether the layout and routing meet the minimum line width, minimum spacing, inter-layer routing, routing blockage and boundary extension, and generates a design rule checking report.

7. The method for designing a digital backend full-process script according to claim 6, characterized in that: Based on the layout and routing data, use the make lvs command to check the consistency of the layout and schematic diagram using the Layout vs. Schematic checking tool. The Layout vs. Schematic checking tool extracts the device connection netlist from the layout and routing data and compares it with the generated gate-level netlist to check whether the device type, device quantity, and device connection topology are consistent between the two, and then generates a Layout vs. Schematic inspection report.

8. The method for designing a digital backend full-process script according to any one of claims 5 to 7, characterized in that: The antenna inspection tool includes at least one of PegasusARC, IC ValidatorARC, CalibreAntenna Checker, TotemAntenna Checker, and QuartzARC; The design rule checking tool includes at least one of Pegasus DRC, IC Validator DRC, Calibre DRC, Totem DRC, Quartz DRC, and SKIPPER DRC.

9. The method for designing a digital backend full-process script according to claim 8, characterized in that: Perform power consumption analysis based on layout and routing data, including: Based on the layout and routing data, the parasitic parameters of the routing, including parasitic resistance and parasitic capacitance, are extracted using a parasitic parameter extraction tool through the make starrc_step or make starrc command. The parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance values ​​of each routing segment based on the geometric parameters and process parameters of the routing. Use the PrimeTime static timing analysis tool to perform standard static timing analysis based on parasitic parameters using the make pt_step command, and multi-mode and multi-angle static timing analysis using the make pt_dmsa command, and generate a timing analysis report. Standard static timing analysis calculates the data path's delay, setup time, and hold time timing indicators under typical process angles and typical operating modes; multi-mode and multi-angle static timing analysis calculates the data path's timing margin and violation count timing indicators under multiple process angles and multiple operating modes. Based on the timing analysis report, use the PrimeTime static power analysis tool to perform static power analysis and generate a power report using the make ptpx command. Based on the timing analysis report, use the ECO optimization tool through the make eco command to debug and optimize the multi-mode and multi-angle static timing analysis results and correct timing violations. The ECO optimization tool automatically or interactively inserts buffers in the netlist, adjusts drive strengths, and repairs timing violation paths until the timing under multiple modes and multiple angles meets the requirements, generating the final gate-level netlist.

10. The method for designing a digital backend full-process script according to claim 9, characterized in that: Perform IR analysis based on parasitic parameters, including: Generate a view file using the IR analysis tool based on the parasitic parameters. The view file contains the chip's power network topology, parasitic parameters, and pin information. When the chip is in a static state, run the make static_ir command to perform static IR analysis. This analysis evaluates the static IR performance of the power supply network by calculating the DC voltage drop and average current density distribution of the power supply network. When the chip is in a dynamic working state, dynamic IR analysis is performed using the make dynamic_ir command. Dynamic IR analysis obtains the chip's flip information by reading VCD waveform files or SAIF flip activity files. Combined with the flip information, the AC voltage drop and transient current density distribution of the power network are calculated to evaluate the dynamic IR performance of the power network. Generate an IR analysis report based on the results of static IR analysis and dynamic IR analysis.

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