Semiconductor manufacturing apparatus, inspection apparatus, and semiconductor device manufacturing method

Abstract

The invention provides a technology capable of improving detection sensitivity of defects. The semiconductor manufacturing apparatus includes: (a) an image capturing device that captures an image of a bare chip; (b) an illumination device for oblique light illumination having a rectangular light-emitting surface, the illumination device being provided such that the long side of the light-emitting surface faces one side of the bare chip, and being provided so as to irradiate illumination light obliquely at a first predetermined angle with respect to the optical axis of the imaging device; and (c) a control unit configured so as to be able to adjust a direction in which the illumination light is irradiated with respect to the one side of the bare chip in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor manufacturing apparatus, for example, a die mounter that can be applied to perform surface inspection of a bare chip. Background Art

[0002] The manufacturing process of semiconductor devices includes the process of separating bare chips from a semiconductor wafer (hereinafter simply referred to as a wafer) (dicing process) and the die attach process of mounting the separated bare chips on a substrate. During the die attach process or prior processes such as dicing, defects such as cracks may occur in the bare chips.

[0003] When inspecting defects in an image captured by an optical system including a camera, the optical system's illumination configuration sometimes utilizes a dark field method that darkens the background and brightens the desired object (for example, Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-13841 Summary of the Invention

[0007] Depending on the pattern formed on the bare chip, the detection sensitivity of defects may be low.

[0008] The present disclosure aims to provide a technique capable of improving the detection sensitivity of defects. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] The representative outline of the present disclosure is briefly described below.

[0010] That is, the semiconductor manufacturing device comprises: (a) a photographing device for photographing a bare chip; (b) an illumination device, which is an oblique light illumination device having a rectangular light-emitting surface, wherein the illumination device is arranged so that the long side of the light-emitting surface is opposite to one side of the bare chip, and is arranged to irradiate illumination light at an inclined first predetermined angle relative to the optical axis of the photographing device; and (c) a control unit, which is configured to be able to irradiate the illumination light in a direction relative to the one side of the bare chip when viewed from above.

[0011] Effects of the Invention

[0012] According to the present disclosure, it is possible to improve the detection sensitivity of defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic plan view showing a configuration example of a die mounter in the embodiment.

[0014] Figure 2 It means from Figure 1 A diagram showing the schematic structure when viewed in the direction of arrow A.

[0015] Figure 3 It shows Figure 1 A schematic cross-sectional view of the main parts of the wafer supply unit is shown.

[0016] Figure 4 It shows Figure 1 A block diagram showing the schematic configuration of a control system for a die mounter.

[0017] Figure 5 It shows that the Figure 1 A flow chart showing a method for manufacturing a semiconductor device using a die mounter.

[0018] Figure 6 1 is a diagram showing a configuration example of a dark field inspection system in a comparative example.

[0019] Figure 7 It shows Figure 6 A diagram showing an example of an image captured in a dark field inspection system.

[0020] Figure 8 Is used to illustrate Figure 6 Diagram showing problem points in the dark field inspection system.

[0021] Figure 9 It is a diagram explaining the change in defect detection sensitivity depending on the lighting direction.

[0022] Figure 10 This is a diagram showing a first example of rotating the lighting device in the horizontal direction.

[0023] Figure 11 This is a diagram showing a second example of rotating the lighting device in the horizontal direction.

[0024] Figure 12 This is a diagram showing a third example of rotating the bare chip in the horizontal direction.

[0025] Figure 13 This is a diagram illustrating another example of changing the direction of illumination from the illumination device relative to the bare chip.

[0026] The description of the accompanying drawings is as follows:

[0027] 1Chip mounter (semiconductor manufacturing equipment)

[0028] 14 Wafer recognition camera (shooting device)

[0029] 15 lighting fixtures

[0030] 80 Control Department DETAILED DESCRIPTION

[0031] The following describes the embodiments and variations using the accompanying drawings. However, in the following description, identical components may be denoted by the same reference numerals, and repeated descriptions may be omitted. It should be noted that, to clarify the description, the widths, thicknesses, and shapes of various components in the drawings may be schematically illustrated, compared to their actual form. Furthermore, the dimensional relationships and ratios of the various components in the multiple drawings are not necessarily consistent.

[0032] use Figures 1 to 3 The configuration of a die mounter as one embodiment of a semiconductor manufacturing apparatus will be described. Figure 1 It is a schematic plan view showing a configuration example of a die mounter in the embodiment. Figure 2 It means from Figure 1 A diagram showing the schematic structure when viewed in the direction of arrow A. Figure 3 It shows Figure 1 A schematic cross-sectional view of the main parts of the wafer supply unit is shown.

[0033] The die bonder 1 generally comprises a wafer supply unit 10, a pickup unit 20, an intermediate stage 30, a placement unit 40, a conveyor unit 50, a substrate supply unit 60, a substrate unloading unit 70, and a control unit (control device) 80. The Y2-Y1 direction (Y direction) represents the front-to-back direction of the die bonder 1, the X2-X1 direction (X direction) represents the left-to-right direction, and the Z1-Z2 direction (Z direction) represents the up-down direction. The wafer supply unit 10 is located at the front of the die bonder 1, and the placement unit 40 is located at the rear. The X, Y, and Z directions are orthogonal to each other.

[0034] The wafer supply unit 10 includes a wafer cassette elevator 11 , a wafer holding table 12 , a peeling unit 13 , and a wafer recognition camera 14 .

[0035] The cassette elevator 11 moves a wafer cassette (not shown) that holds multiple wafer rings WR up and down to a wafer transfer height. A wafer alignment chute (not shown) aligns the wafer rings WR supplied from the cassette elevator 11. A wafer unloader (not shown) removes wafer rings WR from the cassette and supplies them to the wafer holding table 12, or removes them from the wafer holding table 12 and stores them in the cassette.

[0036] The wafer holding table 12 includes an expansion ring 121 that holds the wafer ring WR, and a support ring 122 that holds the wafer ring WR and horizontally positions the dicing tape DT. The peeling unit 13 is disposed inside the support ring 122 .

[0037] A wafer W is bonded (attached) to the dicing tape DT. This wafer W is divided into a plurality of bare chips D. The wafer W is, for example, a semiconductor wafer or a glass wafer, and the bare chips D are semiconductor chips or glass chips. A thin film adhesive material DF, called a die attach film (DAF), may be bonded between the wafer W and the dicing tape DT. The adhesive material DF is cured by heating.

[0038] The wafer holding table 12 is moved in the X1-X2 and Y1-Y2 directions by a drive unit (not shown), moving the picked-up bare chip D to the position of the peeling unit 13. Furthermore, the wafer holding table 12 is rotated by a drive unit (not shown) within the XY plane by a drive unit (not shown). The peeling unit 13 is moved in the vertical direction by a drive unit (not shown). The peeling unit 13 peels the bare chip D from the dicing tape DT.

[0039] The wafer recognition camera 14 as an imaging device recognizes the pickup position of the bare chip D picked up from the wafer W or performs surface inspection of the bare chip D.

[0040] The pickup unit 20 includes a pickup head 21 and a Y-drive unit 23. The pickup head 21 is equipped with a collet chuck 22 at its front end, which suction-holds the peeled bare chip D. The pickup head 21 picks up the bare chip D from the wafer supply unit 10 and places it on the intermediate stage 31. The Y-drive unit 23 moves the pickup head 21 in the Y1-Y2 direction. The pickup unit 20 also includes various drive units (not shown) that raise and lower, rotate, and move the pickup head 21 in the X direction.

[0041] The intermediate stage 30 includes an intermediate stage 31 on which a bare chip D is placed, and a stage recognition camera 34 for identifying the bare chip D on the intermediate stage 31. The intermediate stage 31 has suction holes for attracting the placed bare chip D. Furthermore, the intermediate stage 31 may be provided with a rotation mechanism for adjusting the inclination of the placed bare chip D relative to the horizontal. The placed bare chip D is temporarily held on the intermediate stage 31. The intermediate stage 31 serves as both a placement stage for placing the bare chip D and a pickup stage for picking up the bare chip D.

[0042] The mounting section 40 includes a mounting head 41, a Y drive section 43, a substrate recognition camera 44, and a mounting table 46. The mounting head 41 is provided with a collet 42 that adsorbs and holds the bare chip D at the front end. The Y drive section 43 moves the mounting head 41 in the Y1-Y2 direction. The substrate recognition camera 44 captures the position recognition mark (not shown) of the substrate S to identify the mounting position. Here, the substrate S includes, for example, a wiring substrate, a lead frame, a glass substrate, etc. A plurality of product areas (hereinafter referred to as package areas P) that eventually become one package are formed on the substrate S. Position recognition marks are provided for each package area P. The mounting table 46 rises when the bare chip D is placed on the substrate S and supports the substrate S from below. The mounting table 46 has a suction port (not shown) for vacuum adsorption of the substrate S, which can fix the substrate S. The mounting table 46 has a heating section (not shown) for heating the substrate S.

[0043] With this configuration, the placement head 41 corrects the pickup position or posture based on the image data from the stage recognition camera 34 and picks up the bare chip D from the intermediate stage 31. The placement head 41 then places the bare chip D on the package area P of the substrate S, or places the bare chip on top of a bare chip already placed on the package area P of the substrate S, based on the image data from the substrate recognition camera 44.

[0044] The transport unit 50 includes a transport claw 51 that grips and transports a substrate S, and a transport path 52 along which the substrate S moves. A ball screw (not shown) provided along the transport path 52 drives a nut (not shown) on the transport claw 51 of the transport path 52, thereby moving the substrate S in the X direction. With this configuration, the substrate S moves from the substrate supply unit 60 along the transport path 52 to the placement position. After placement, the substrate S moves to the substrate removal unit 70, where it is delivered.

[0045] The substrate supply unit 60 takes out the substrate S stored and carried in by the conveying jig from the conveying jig and supplies it to the conveying unit 50. The substrate unloading unit 70 stores the substrate S conveyed by the conveying unit 50 on the conveying jig.

[0046] Next, use Figure 4 The control unit 80 will be described. Figure 4 It shows Figure 1 A block diagram showing the schematic configuration of a control system for a die mounter.

[0047] The control system 8 includes a control unit (control device) 80, a drive unit 86, a signal unit 87, an optical system 88, and the like. The control unit 80 generally includes a control / calculation unit 81 comprised of a CPU (Central Processing Unit), a storage device 82, an input / output device 83, a bus 84, and a power supply 85. The storage device 82 includes a main storage device 82a and an auxiliary storage device 82b. The main storage device 82a is comprised of a RAM (Random Access Memory) that stores processing programs, etc. The auxiliary storage device 82b is comprised of an HDD (Hard Disk Drive) or SSD (Solid State Drive) that stores control data and image data required for control.

[0048] The input / output device 83 includes a monitor 83a for displaying device status and information, a touch panel 83b for inputting operator instructions, a mouse 83c for operating the monitor 83a, and an image acquisition device 83d for acquiring image data from the optical system 88. The input / output device 83 also includes a motor control unit 83e and an I / O signal control unit 83f. The motor control unit 83e controls the XY stage (not shown) of the wafer supply unit 10, the ZY drive axes of the placement head stage, and the drive unit of the peeling unit 13. The I / O signal control unit 83f acquires or controls signals from a signal unit 87, which includes switches or knobs for controlling the brightness of various sensors and lighting devices. The optical system 88 includes the wafer recognition camera 14, the stage recognition camera 34, and the substrate recognition camera 44. The control / calculation unit 81 acquires necessary data and performs calculations via the bus 84 to control the pickup head 21 and other components and transmit information to the monitor 83a and other components.

[0049] use Figure 5 A part of the manufacturing process of a semiconductor device (a method of manufacturing a semiconductor device) using the die mounter 1 will be described. Figure 5 It shows that the Figure 1 Flowchart of a method for manufacturing a semiconductor device using a die mounter 1 is shown. In the following description, the operation of each component constituting the die mounter 1 is controlled by the control unit 80.

[0050] (Wafer loading process: process S1)

[0051] A wafer cassette containing wafer rings WR is loaded onto the cassette elevator 11. The loaded wafer rings WR are supplied (loaded) onto the wafer holding table 12. It should be noted that the wafers W are inspected in advance for each bare die using an inspection device such as a prober, and wafer mapping data indicating whether the bare die is good or bad is generated. This wafer mapping data is stored in the storage device of the control unit 80.

[0052] (Substrate loading process: process S2)

[0053] The transport jig storing the substrate S is supplied to the substrate supply unit 60 . The substrate S is unloaded from the transport jig by the substrate supply unit 60 . Then, the substrate S is supplied (carried in) to the mounting unit 40 via the transport unit 50 .

[0054] (Picking process: process S3)

[0055] After step S1, the wafer holding table 12 is moved in a manner that enables the desired bare chip D to be picked up from the dicing tape DT. The bare chip D is photographed by the wafer recognition camera 14, and the positioning and surface inspection of the bare chip D are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offset amount (X, Y, θ directions) of the bare chip D on the wafer holding table 12 relative to the bare chip position reference point of the chip mounter is calculated and positioned. It should be noted that, as the initial setting of the device, the specified position of the wafer holding table 12 is maintained as the bare chip position reference point in advance. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0056] The positioned bare chip D is peeled from the dicing tape DT by the peeling unit 13 and the pickup head 21 . The bare chip D peeled from the dicing tape DT is sucked and held by the collet 22 provided on the pickup head 21 , and is transported and placed on the intermediate stage 31 .

[0057] The stage recognition camera 34 captures the bare chip D on the intermediate stage 31. Based on the captured image data, the bare chip D is positioned and inspected on the surface. Image processing is performed on the image data to calculate the offset (in the X, Y, and θ directions) of the bare chip D on the intermediate stage 31 relative to the die placement machine's bare chip position reference point, and then position the bare chip. It should be noted that the intermediate stage 31 is initially set to a predetermined position as the bare chip position reference point. Image processing is performed on the image data to inspect the surface of the bare chip D.

[0058] The pickup head 21 that has conveyed the bare chip D to the intermediate stage 31 returns to the wafer supply unit 10. The next bare chip D is peeled from the dicing tape DT in the above-described order, and thereafter, the bare chips D are peeled one by one from the dicing tape DT in the same order.

[0059] (Placement process: process S4)

[0060] The conveyor unit 50 conveys the substrate S to the mounting table 46. The substrate S placed on the mounting table 46 is photographed by the substrate recognition camera 44, and the positioning and surface inspection of the substrate S are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offset amount (X, Y, and θ directions) of the substrate S relative to the substrate position reference point of the chip mounter 1 is calculated. It should be noted that as an initial setting of the device, the predetermined position of the mounting unit 40 is maintained as the substrate position reference point. By performing image processing on the image data, the surface inspection of the substrate S is performed.

[0061] The placement head 41's suction position is corrected based on the amount of misalignment of the bare chip D on the intermediate stage 31 calculated in step S3, and the collet 42 is used to suction the bare chip D. The placement head 41, which has suctioned the bare chip D from the intermediate stage 31, is then placed on a predetermined portion of the substrate S supported by the placement stage 46. The predetermined portion of the substrate S is the package area P of the substrate S, or an area where bare chips D are placed in addition to already placed bare chips D, or a placement area for stacked bare chips D. The bare chip D placed on the substrate S is imaged by the substrate recognition camera 44, and the image data obtained from the image capture is used to check whether the bare chip D is placed in the desired position.

[0062] The placement head 41 that has placed the bare chip D on the substrate S returns to the intermediate stage 31. Following the above sequence, the next bare chip D is picked up from the intermediate stage 31 and placed on the substrate S. This sequence is repeated to place bare chips D on all the packaging areas P of the substrate S.

[0063] (Substrate Unloading Step: Step S5)

[0064] The substrate S with the bare chip D mounted thereon is transported from the mounting section 40 to the substrate unloading section 70 by the transport section 50. In the substrate unloading section 70, the substrate S is taken out and stored on a transport jig, and then unloaded. The transport jig storing the substrate S is unloaded from the die mounter 1.

[0065] As described above, the bare chip D is mounted on the substrate S and unloaded from the die mounter 1. Thereafter, for example, the transport jig holding the substrate S with the mounted bare chip D is transported in a wire bonding process, where the electrodes of the bare chip D are electrically connected to the electrodes of the substrate S via Au wires or the like. Subsequently, the substrate S is transported in an injection molding process, where the bare chip D and the Au wires are sealed with an injection resin (not shown), completing the semiconductor package.

[0066] Surface inspection for defects (damage such as scratches) can be performed at least at one of the wafer supply unit 10, the intermediate stage unit 30, and the mounting unit 40, which are the places where the bare chip position identification is performed, but it is more preferable to perform it at all locations. If the wafer supply unit 10 is used to perform surface inspection for defects, the defects can be detected as early as possible. If the intermediate stage unit 30 is used to perform surface inspection for defects, defects that are not detected by the wafer supply unit 10 or defects that occur after the picking process (defects that do not appear before the chip mounting process) can be detected before mounting. In addition, if the mounting unit 40 is used to perform surface inspection for defects, defects that are not detected by the wafer supply unit 10 and the intermediate stage unit 30 (defects that do not appear before the chip mounting process) or defects that occur after the chip mounting process can be detected before the next bare chip is stacked or before the substrate is discharged.

[0067] Hereinafter, the surface inspection for defects will be described using the wafer supply unit 10 as an example, but the intermediate stage unit 30 and the placement unit 40 can also be inspected using the same configuration.

[0068] use Figures 6 to 8 A dark field inspection system using a dark field method is described. Figure 6 It is a diagram showing a configuration example of a dark field inspection system. Figure 6 The upper side is a top view, and the lower side is a main view. Figure 7 It shows Figure 6 A diagram showing images captured in a dark-field inspection system. Figure 8 It is a diagram illustrating the width of diffused light and the width of incident light.

[0069] like Figure 6 As shown, the wafer recognition camera 14 is arranged above the surface of the bare chip D of the inspection object. The wafer recognition camera 14 is composed of a camera body 141 and a lens 142. The field of view CV of the wafer recognition camera 14 includes the bare chip D of the inspection object and part or all of the adjacent peripheral bare chips Dp. The lighting device 15 is an oblique light illumination such as an oblique light bar, which irradiates the illumination light IL near the outer side of the bare chip D of the inspection object at a prescribed angle (first prescribed angle) relative to the optical axis OA. Here, the illumination light IL is irradiated toward the peripheral bare chip Dp adjacent to the X2 side of the bare chip D. The light-emitting surface of the lighting device 15 extends in the Y direction. The lighting device 15 has a rectangular light-emitting surface consisting of a long side and a short side. The irradiation direction of the illumination light IL in the horizontal direction is the X1 direction. It should be noted that the bare chip D has a square or rectangular shape when viewed from above.

[0070] The surface of the bare chip D has a very strong specular reflection characteristic. Therefore, most of the light is specularly reflected, and a portion of the diffusely reflected light is also included, and will not be incident on the lens 142. Figure 7 As shown in FIG, the surface of the bare chip D is photographed very darkly. In contrast, the defect K on the surface of the bare chip D has a full reflection characteristic. Figure 8 As shown, in diffuse reflection, the reflection angle of the reflected light on the subject surface SP has a width. Here, diffuse reflection considers only the width of the principal ray (light reflected in the regular direction by the surface of the bare chip D from the incident light INL). In this specification, the diffusion width angle θd of the reflected light is referred to as the diffuse light width or the reflected light NA.

[0071] The diffusely reflected light from the defect K also has directivity along the reflection angle of the specularly reflected light, and the reflected light NA of the diffusely reflected light from the defect K is increased. Therefore, the diffusely reflected light enters the lens 142 and is captured as bright. This enables dark field inspection of the defect K with the surface of the bare chip D as the background.

[0072] To further clarify the lighting for surface inspection in this embodiment, use Figure 9 Explain the problems with lighting used for defect detection. Figure 9 It is a diagram explaining the change in defect detection sensitivity depending on the lighting direction.

[0073] Figure 9 The illumination device 15 in A is located on the X2 side of the bare chip D. The illumination surface of the illumination device 15 extends in the Y direction (first direction). The illumination light IL is incident in the X1 direction (second direction) in the horizontal direction. The side SD1 of the bare chip D facing the illumination device 15 (first side) extends in the Y direction (first direction).

[0074] The bare chip D may be composed of a memory cell region MR and a logic circuit region CR. The surface of the memory cell region MR has many specular reflection components. The logic circuit region CR is a region where circuit patterns, wiring, and pads are present. In the logic circuit region CR, as with the defect K, the reflected light has many diffuse reflection components. In addition, due to slight unevenness on the surface of the logic circuit region CR, specular reflection occurs in a direction different from the horizontal direction of the bare chip surface. As a result, the reflected light is focused by the lens 142, as shown in FIG. Figure 9 As shown in A, the logic circuit region CR is captured very brightly. Therefore, it is difficult to distinguish between the logic circuit region CR as the background and the defect K, and the inspection sensitivity is reduced.

[0075] In other words, when illuminated with oblique light, while the amount of reflected light from the memory cell region MR is small, the amount of reflected light from the logic circuit region CR is large, resulting in a brighter image. The logic circuit region CR has similar reflection characteristics to the defect K, resulting in a high brightness ratio (contrast) between the background and the defect K in the memory cell region MR. However, the brightness ratio between the background and the defect K in the logic circuit region CR decreases, reducing inspection sensitivity. Consequently, while the defect K in the memory cell region MR is visible, the defect K in the logic circuit region CR is less easily visible.

[0076] Next, use Figure 9 The lighting for surface inspection in this embodiment will be described. Figure 9 B shows that the incident angle of the illumination light IL in the horizontal direction is slightly inclined from the X1 direction toward the Y2 direction. Figure 9 The incident angle of the illumination light IL in the horizontal direction shown in C is greatly inclined from the X1 direction toward the Y2 direction.

[0077] The reflection characteristics of the light reflected from the logic circuit region CR and the light reflected from the defect K vary significantly depending on the horizontal angle of incidence of the incident illumination light IL. This is because the light incident perpendicular to the side surface of the convex portion is strongly reflected toward the lens 142 directly above, influenced by the fine three-dimensional structure of the surface of the logic circuit region CR and the fine three-dimensional structure of the defect K. Since the fine structure of the defect K and the logic circuit region CR is very similar, the reflected light exhibits similar properties. However, the wall surface of the three-dimensional structure of the defect K is not uniform compared to that of the logic circuit region CR. Therefore, the reflection characteristics of the defect K and the logic circuit region CR differ slightly in the spread of the reflected light, with the reflected light from the defect K exhibiting a slightly larger diffusion angle.

[0078] Here, the pattern wiring of the logic circuit region CR is substantially parallel or perpendicular to the direction along the side of the bare chip (the X direction or the Y direction). Therefore, by simply slightly rotating the horizontal incident direction of the illumination light IL, the amount of light reflected in the logic circuit region CR toward the lens 142 can be reduced.

[0079] The defect K is generated by applying pressure from the bottom of the bare chip D, for example, in a manner that matches the stacking structure of the bare chip D or the direction of silicon crystal growth. The defect K is easily formed in a direction close to the edge of the bare chip D (X direction or Y direction). Therefore, the reflection characteristics of the defect K have properties similar to those of the logic circuit area CR. However, the defect K is not a managed groove, so the reflection angle width of the reflected light is slightly wider than that of the logic circuit area CR and is uneven. Therefore, with respect to the horizontal rotation of the incident direction of the illumination light IL, the incident angle width of the reflection of the defect K is wider than that of the logic circuit area CR, and the reflection of light in the direction of the lens 142 will remain at very small angles.

[0080] In other words, the NA of the reflected light from the defect K is slightly larger than the NA of the reflected light from the logic circuit region CR. Since the NA of the reflected light from the logic circuit region CR is small, Figure 9 As shown in B, when the incident angle of the illumination light IL is slightly misaligned, there is no incident light to the lens 142, and the image of the logic circuit area CR becomes darker. Since the reflected light NA is different, the incident angle at which it starts to darken is slightly larger than that of the logic circuit area CR. This difference is used to separate the reflected light of the defect K and the reflected light of the logic circuit area CR, and the defect K and the logic circuit area CR are separated and distinguished. Here, the illumination light IL can also be diffuse light, but in this case, the illumination light IL with a small incident light width (preferably less than 15° and very narrow) is used. Here, in this specification, as Figure 8 As shown in FIG. 8B , the angle width θw of the light incident from the light source light emitting surface LS to the subject surface SP is referred to as the incident light width or the incident light NA.

[0081] like Figure 9 As shown in Figure C, if the angular misalignment of the illumination light IL increases further, the images of the defect K on the surface of the memory cell region MR and the defect K on the surface of the logic circuit region CR become darker. This makes it difficult to distinguish the defect K from the logic circuit region CR as the background, and the inspection sensitivity decreases.

[0082] The irradiation direction of the illumination light IL from the illumination device 15 in the vertical direction is inclined at a predetermined angle (first predetermined angle) relative to the optical axis of the wafer recognition camera 14. The first predetermined angle can be a high angle of 5 degrees to 45 degrees, or a low angle of 45 degrees to 95 degrees, but the low angle is preferred.

[0083] The irradiation direction of the illumination light IL from the illumination device 15 in the horizontal direction is inclined at a predetermined angle (second predetermined angle) relative to the direction (X direction) in which the side (second side) SD2 of the bare chip D extends. The second predetermined angle is preferably, for example, not less than 1 degree and not more than 20 degrees. Figure 9 In the state shown in B, defects are detected by binarizing the image captured by the wafer recognition camera 14.

[0084] In order to obtain the second predetermined angle according to the properties of various bare chips, a rotation mechanism may be provided in a lighting device or the like to teach and determine the angle at which the reflected light in the logic circuit region disappears.

[0085] use Figures 10 to 12 The following describes a rotation mechanism for changing the horizontal irradiation direction of the illumination light IL. Figure 10 This is a diagram showing a first example of rotating the lighting device in the horizontal direction. Figure 11This is a diagram showing a second example of rotating the lighting device in the horizontal direction. Figure 12 This is a diagram of a third example in which the bare chip is rotated in the horizontal direction.

[0086] exist Figures 10 to 12 , an example of two illumination devices 15_1 and 15_2 is shown. Illumination device 15_1 is located on the X2 side of the bare chip D, and illumination device 15_2 is located on the Y1 side of the bare chip D. This allows detection of defects extending not only in the Y direction but also in the X direction. It should be noted that illumination devices can also be located on both the X1 and Y2 sides of the bare chip D.

[0087] like Figure 10 As shown, the lighting devices 15_1 and 15_2 include a rotation mechanism that rotates in the horizontal direction with the center of the lighting devices 15_1 and 15_2 in the horizontal direction as the rotation center.

[0088] like Figure 11 As shown, the lighting devices 15_1 and 15_2 include a rotation mechanism that rotates in the horizontal direction with the center of the bare chip D as the rotation center.

[0089] like Figure 12 As shown, the lighting devices 15_1 and 15_2 are fixed and have a rotation mechanism that rotates the bare chip D horizontally with the center of the bare chip D as the rotation center. A drive unit such as the rotation mechanism of the wafer holding table 12 can be used. For surface inspection of defects on the intermediate stage 30, the rotation mechanism of the intermediate stage 31 can be used.

[0090] Modifications

[0091] The following are representative variations of several embodiments. In the following descriptions of the variations, the same reference numerals as in the above-described embodiment are used for parts having the same configuration and functions as those described using the above-described embodiment. The description of these parts may be appropriately incorporated into the description of the above-described embodiment to the extent that they are not technically inconsistent. Furthermore, a portion of the above-described embodiment, as well as all or a portion of the multiple variations, may be appropriately combined and applied to the extent that they are not technically inconsistent.

[0092] In the embodiment, an example of rotating the lighting device 15 or the bare chip D and changing the irradiation direction is described, but when the illumination is diffuse light illumination, it can also be a linear movement of the lighting device 15 or the bare chip D or a change in the lighting position of the lighting device 15.

[0093] For this, use Figure 13 Provide explanation. Figure 13This is a diagram illustrating another example of changing the direction of illumination from the illumination device relative to the bare chip. Figure 13 A is a diagram illustrating an example of moving a bare chip relative to a lighting device. Figure 13 FIG. B is a diagram illustrating an example of changing the lighting position of the lighting device. Figure 13 The illustrated lighting device 15 is disposed on the X2 side of the bare chip D, and the illumination surface of the lighting device 15 extends in the Y direction.

[0094] like Figure 13 As shown in Figure A, the lighting device 15 is moved in the Y direction (Y1 direction) so that the incident light width does not include the positive side. For example, even if the logic circuit region CR exists in the area of ​​the bare chip D (the area RA encircled by the quadrilateral) located on the Y2 side relative to the vertical line (dashed line) at the end of the lighting device 15 on the Y2 side, defects can still be detected. By moving the lighting device 15 and thus the area RA, defects can be detected in the logic circuit region CR of the entire bare chip D. Alternatively, the lighting device 15 can be fixed and the bare chip D can be moved in the Y direction (Y2 direction).

[0095] In addition, if Figure 13 As shown in B, the illumination of a portion of the lighting device 15 is turned off, and the width of the incident light is set to not include the front side. For example, the length of the illuminated surface of the lighting device 15 in the Y direction is increased to be longer than the Y direction of the bare chip D, and the illuminated area 15a is set on the end side of the Y1 direction and the end side of the Y2 direction. Even if the logic circuit area CR exists in the area of ​​the bare chip D (the area RA circled by the rectangle) that is located on the light-off side relative to the vertical line (dashed line) on the boundary between the illuminated area 15a and the light-off area 15b, defects can still be detected. By moving the boundary between the illuminated area 15a and the light-off area 15b of the lighting device 15, thereby moving the area RA, defects can be detected in the logic circuit area CR of the entire bare chip D.

[0096] It should be noted that the number of lighting areas 15a may be increased so that the light-emitting surface of the lighting device 15 emits light in a stripe pattern. If the stripe pattern is alternately lit, the number of images can be reduced, thereby increasing the inspection speed.

[0097] As mentioned above, the invention proposed by the inventors of the present disclosure has been specifically described based on the embodiment and the modified examples. However, the present disclosure is not limited to the above-mentioned embodiment and the modified examples, and various modifications are possible.

[0098] For example, in the embodiment, the bare chip position recognition is followed by the bare chip appearance inspection and recognition. However, the bare chip position recognition may be followed by the bare chip appearance inspection and recognition.

[0099] In addition, in the embodiment, DAF is attached to the back surface of the wafer, but DAF may not be required.

[0100] In addition, in the embodiment, there is a pickup head and a placement head, but two or more can be provided. In addition, in the embodiment, there is an intermediate stage, but it is also possible not to have an intermediate stage. In this case, the pickup head and the placement head can be used concurrently.

[0101] In the embodiment, the bare chip is placed with its front surface facing up. However, after picking up the bare chip, it can also be placed with its back surface facing up. In this case, the intermediate stage is not required. This device is called a flip-chip bonder.

[0102] In addition, in the embodiment, an example of a chip mounter (semiconductor manufacturing device) that places a bare chip on a substrate is described, but it can also be applied to an inspection device that inspects the surface of a wafer (bare chip) before it is loaded into the chip mounter or an inspection device that inspects the surface of a bare chip placed on a substrate that is unloaded from the chip mounter.

Claims

1. A semiconductor manufacturing device, characterized in that: have: a photographing device for photographing a bare chip, wherein the bare chip has a first side extending in a first direction and a second side along a second direction intersecting the first direction in a plan view; an illumination device for oblique lighting having a rectangular light-emitting surface formed of long and short sides, the illumination device being arranged such that the long side of the light-emitting surface is opposed to the first side, and being arranged to irradiate illumination light obliquely at a first predetermined angle with respect to the optical axis of the imaging device; and The control unit is configured to be able to adjust a direction in which illumination light is irradiated with respect to the first side of the bare chip in a plan view.

2. The semiconductor manufacturing apparatus according to claim 1, wherein The lighting device is configured to irradiate illumination light at an angle of a second predetermined angle with respect to the second direction in a plan view.

3. The semiconductor manufacturing apparatus according to claim 2, wherein: The lighting device has a rotating mechanism, The control unit is configured to adjust the second predetermined angle via the rotation mechanism.

4. The semiconductor manufacturing apparatus according to claim 2, wherein: It also has a wafer holding table with a rotating mechanism. The control unit is configured to adjust the second predetermined angle via the rotation mechanism.

5. The semiconductor manufacturing apparatus according to claim 2, wherein: It also has an intermediate table with a rotating mechanism. The control unit is configured to adjust the second predetermined angle via the rotation mechanism.

6. The semiconductor manufacturing apparatus according to claim 1, wherein The lighting device is configured to be movable relative to the bare chip in the first direction.

7. The semiconductor manufacturing apparatus according to claim 1, wherein The lighting device is configured to be able to change a lighting area.

8. The semiconductor manufacturing apparatus according to any one of claims 1 to 7, wherein: The bare chip has a memory cell area and a logic circuit area. The control unit is configured to change the horizontal irradiation direction of the illumination light from the lighting device and photograph the plurality of bare chips through the photographing device, and obtain the vanishing angle of the reflected light in the logic circuit area based on the change in the brightness of the logic circuit area in the photographed image.

9. An inspection device, characterized in that: have: a photographing device for photographing a bare chip, wherein the bare chip has a first side extending in a first direction and a second side along a second direction intersecting the first direction in a plan view; an illumination device for oblique lighting having a rectangular light-emitting surface formed of long and short sides, the illumination device being arranged such that the long side of the light-emitting surface is opposed to the first side, and being arranged to irradiate illumination light obliquely at a first predetermined angle with respect to the optical axis of the imaging device; and The control unit is configured to be able to adjust a direction in which illumination light is irradiated with respect to the first side of the bare chip in a plan view.

10. A method for manufacturing a semiconductor device, characterized in that: include: A process of loading a wafer ring into a semiconductor manufacturing apparatus, the semiconductor manufacturing apparatus comprising an imaging device, an illumination device, and a control unit, the imaging device imaging a bare chip, the bare chip having a first side extending in a first direction and a second side along a second direction intersecting the first direction when viewed from above, the illumination device being an oblique lighting device having a rectangular light-emitting surface composed of long and short sides, the illumination device being arranged so that the long side of the light-emitting surface is opposite to the first side and being arranged to irradiate illumination light at an inclined first predetermined angle relative to an optical axis of the imaging device, the control unit being configured to be able to adjust the direction of illumination light irradiated relative to the first side of the bare chip when viewed from above; and A step of inspecting defects of the bare chips attached to the dicing tape held by the wafer ring.

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