Class D amplifier and operation method thereof

Abstract

The application provides a class D amplifier and a method of operating the same, the class D amplifier including an output driver stage configured to output an output signal at an output node. The class D amplifier also includes a current sense circuit coupled to the output node of the output driver stage, and the current sense circuit may include: a peak detector coupled to the output node of the output driver stage, the peak detector configured to retrieve a peak of the output signal; and a current sensor coupled to the peak detector and configured to receive the peak of the output signal and generate a sensing current based on the peak of the output signal.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits in audio systems. More particularly, the present invention relates to a Class-D amplifier utilizing charge accumulation for peak current measurement and an operating method thereof. Background Art

[0002] A Class D amplifier (also known as a switching amplifier) ​​is an electronic amplifier in which the transistors act as a binary switch, which is either fully on or fully off during operation. Class D amplifiers use rail-to-rail output switching, where, ideally, the output transistors of these Class D amplifiers almost always carry zero current or zero voltage. As a result, these Class D amplifiers have very little power dissipation and provide high efficiency over a wide range of power levels. The advantageous high efficiency of these Class D amplifiers has driven their use in a variety of audio applications, from cellular phones to flat-screen televisions and home theater receivers. Class D audio power amplifiers have higher efficiency than Class AB audio power amplifiers. Because of their higher efficiency, Class D amplifiers require smaller power supplies and do not require heat sinks, significantly reducing overall system cost, size, and weight. Summary of the Invention

[0003] A general aspect includes a Class D amplifier. The Class D amplifier also includes an output driver stage configured to output an output signal at an output node. The Class D amplifier also includes a current sensing circuit coupled to the output node of the output driver stage. The current sensing circuit may include: a peak detector coupled to the output node of the output driver stage, the peak detector configured to detect a peak value of the output signal; and a current sensor coupled to the peak detector and configured to receive the peak value of the output signal and generate a sensed current based on the peak value of the output signal.

[0004] Another general aspect includes a method for operating a Class D amplifier. The method includes outputting an output signal at an output node of an output driver stage. The method also includes detecting a peak value of the output signal by a peak detector. The method also includes generating a sense current by a current sensor based on the peak value of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

[0006] Figure 1AFIG. 1 is a simplified schematic diagram of a Class D amplifier, which is a conventional Class D amplifier with a feedback loop.

[0007] Figure 1B for Figure 1A FIG. 1 is a waveform diagram of the modulation of the signal in the class-D amplifier 100 .

[0008] Figure 2A An example of an existing configuration for current sensing in a Class D amplifier.

[0009] Figure 2B is a graphical illustration of a waveform of the voltage drop across the first sense resistor.

[0010] Figure 2C is a graphical illustration of the output signal of the low pass filter amplifier corresponding to the voltage drop across the first sense resistor.

[0011] Figure 2D FIG. 1 is an illustration of another conventional configuration for current sensing in a Class D amplifier.

[0012] Figure 3A is a block diagram of a current sensing circuit for a Class-D amplifier according to some embodiments.

[0013] Figure 3B is a diagram of an example of a sensing circuit for a Class-D amplifier according to some embodiments.

[0014] Figure 4A is a diagram of an exemplary conversion circuit according to some embodiments.

[0015] Figure 4B is a diagram of another exemplary conversion circuit according to some embodiments.

[0016] Figure 5 is a flow chart of an illustrative method for operating a Class-D amplifier according to some embodiments.

[0017] Explanation of symbols

[0018] 100: Class D amplifier

[0019] 101: First comparator

[0020] 102: Second comparator

[0021] 103: Oscillator

[0022] 106: First PWM signal

[0023] 107: Second PWM signal

[0024] 110: Load

[0025] 191: Output transistor

[0026] 192: Output transistor

[0027] 193: Output transistor

[0028] 194: Output transistor

[0029] 290: Output driver stage

[0030] 291: p-type output transistor

[0031] 292: n-type output transistor

[0032] 293: p-type output transistor

[0033] 294: n-type output transistor

[0034] 295: Sensing transistor

[0035] 300: Current sensing circuit

[0036] 310: Peak Detector

[0037] 312: First operational amplifier

[0038] 314: First n-type transistor

[0039] 316: First capacitor

[0040] 318: Second n-type transistor

[0041] 320: Second capacitor

[0042] 322: The third n-type transistor

[0043] 350: Current sensor

[0044] 352: Another operational amplifier

[0045] 354: First p-type transistor

[0046] 356: Second p-type transistor

[0047] 358: The third p-type transistor

[0048] 360: Current Mirror

[0049] 390: Output driver stage

[0050] 392: n-type output transistor

[0051] 395: Sensing transistor

[0052] 410: Exemplary conversion circuit

[0053] 412: Resistor

[0054] 414: Analog-to-Digital Converter (ADC)

[0055] 450: Another exemplary conversion circuit

[0056] 452: Capacitor

[0057] 454: Comparator

[0058] 456: Counter

[0059] 462: Ramp signal waveform

[0060] 464: PWM waveform

[0061] 500: Method

[0062] 502: Steps

[0063] 504: Steps

[0064] 506: Steps

[0065] A: Output node

[0066] B: Node

[0067] C: Node

[0068] CK: clock signal

[0069] CKB: clock signal

[0070] D: Node

[0071] E: Node

[0072] INM: Second audio input signal

[0073] INP: First audio input signal

[0074] I_out: output current

[0075] Ipeak: peak current

[0076] Isense: sensing current

[0077] I_out_peak: peak value

[0078] L1: Inductor

[0079] OUTM: First output signal

[0080] OUTP: Second output signal

[0081] R1: Resistor

[0082] R S :resistance

[0083] R S1 : First sensing resistor

[0084] R S2 : Second sensing resistor

[0085] T OUTM : First output terminal

[0086] T OUTP : Second output terminal

[0087] V: voltage drop

[0088] V DD : Higher power rails

[0089] V DS : Voltage drop

[0090] V GS : Gate to source voltage

[0091] Vout: output signal after sampling

[0092] Vpeak: Peak value

[0093] VREF: triangle wave signal

[0094] Vref: reference voltage

[0095] Vs: voltage drop

[0096] V SS : Lower power rail DETAILED DESCRIPTION

[0097] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. In addition, the disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations described.

[0098] Additionally, source / drain ("S / D") regions may be referred to individually or collectively as sources or drains, depending on the context. For example, a device may include a first source / drain region and a second source / drain region, among other components. The first source / drain region may be a source region, while the second source / drain region may be a drain region, or vice versa. Persons of ordinary skill will recognize many variations, modifications, and alternatives.

[0099] Some embodiments of the present disclosure have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Some of the features described below may be replaced or eliminated, and additional features may be added for different embodiments. Although some embodiments are described with respect to operations performed in a particular order, these operations may be performed in another logical order.

[0100] A Class D audio power amplifier converts an audio input signal into high-frequency pulses that switch the output transistors according to the audio input signal. Some Class D amplifiers use a pulse-width modulator (PWM) to generate a series of modulated pulses whose width varies according to the amplitude of the audio input signal. These pulses of varying width switch the output transistors at a fixed frequency. Other Class D amplifiers may rely on other types of pulse modulators. The following description will primarily refer to pulse-width modulators, but those of ordinary skill in the art will recognize that Class D amplifiers can be configured with other types of modulators.

[0101] Figure 1A FIG. 1 is a simplified schematic diagram of a conventional class D amplifier 100. Figure 1A As shown in FIG, Class D amplifier 100 is a differential amplifier. A pair of differential audio input signals INP and INM (i.e., a first audio input signal INP and a second audio input signal INM) are input to a first comparator 101 and a second comparator 102, respectively. Each of the differential audio input signals INP and INM is compared with a triangular wave signal (i.e., a signal having a triangular waveform) VREF generated by an oscillator 103 to generate a first PWM signal 106 and a second PWM signal 107, respectively. Because the first and second audio input signals INP and INM are differential signals and the same triangular wave signal VREF serves as a reference signal, the first and second PWM signals 107 are also differential signals. For example, if the first PWM signal has a 60% duty cycle, the second PWM signal has a 40% duty cycle; if the first PWM signal has a 70% duty cycle, the second PWM signal has a 30% duty cycle.

[0102] The first PWM signal 106 is coupled to the gates of the output transistors 191 and 192 that are electrically connected together. Therefore, the first PWM signal 106 controls the on / off switching of the output transistors 191 and 192. The second PWM signal 107 is coupled to the gates of the output transistors 193 and 194 that are electrically connected together. Therefore, the second PWM signal 107 controls the on / off switching of the output transistors 193 and 194. Therefore, the first output signal OUTM and the second output signal OUTP of the class D amplifier 100 are also differential output signals. Figure 1AAs shown in FIG. 1 , the first output signal OUTM and the second output signal OUTP are applied to both ends of a (speaker) load 110. Figure 1A In the figure, the inductor L1 and the resistor R1 are represented.

[0103] Figure 1B for Figure 1A The waveform diagram of the modulation of the signal in the Class D amplifier 100 is shown. Figure 1B As shown in FIG, the first audio input signal INP and the second audio input signal INM are compared with the triangle wave signal VREF, which is combined with the above Figure 1A The output signals of the first comparator 101 and the second comparator 102 are pulse signals at a fixed frequency (i.e., a fixed cycle), and the pulse widths of the pulse signals are proportional to the corresponding audio input signals. Therefore, the first output signal OUTM and the second output signal OUTP are two PWM signals, such as Figure 1B As shown in .

[0104] Figure 2A An example of a current sensing configuration for a Class D amplifier. Figure 1A In the example shown in FIG. 1 , the output driver stage 290 includes Figure 2A Specifically, the source of the p-type output transistor 291 is connected to a higher power rail (e.g., V DD ), the drain of the p-type output transistor 291 is at the first output terminal T OUTM The drain of the n-type output transistor 292 is connected to the drain of the n-type output transistor 292, and the source of the n-type output transistor 292 is connected to the lower power rail (eg, V SS The source of the p-type output transistor 293 is connected to a higher power rail (e.g., V DD ), the drain of the p-type output transistor 293 is at the second output terminal T OUTP The drain of the n-type output transistor 294 is connected to the drain of the p-type output transistor 293, and the source of the p-type output transistor 293 is connected to a lower power rail (eg, V SS or grounded). A speaker load 110 including an inductor L1 and a resistor R1 is connected to the first output terminal T OUTM With the second output terminal T OUTP between.

[0105] The first sensing resistor R S1 Connect to a lower power rail (for example, V SS or ground) and the source of the n-type output transistor 292. The second sensing resistor R S2 Connect to a lower power rail (for example, V SSor ground) and the source of the n-type output transistor 294. The first sensing resistor R S1 and the second sensing resistor R S2 As a current sensor, it converts the voltage drop (Vs) across it into a current value. The output current (I_out) can be calculated as I_out = Vs / R S1 calculate.

[0106] Figure 2B is across the first sensing resistor R S1 Graph showing the waveform of the voltage drop (Vs). Figure 2C corresponds to the first sensing resistor R S1 The voltage drop (Vs) of the output signal of the low-pass filter amplifier is shown in the figure. Figure 2B As shown in FIG, across the first sensing resistor R S1 The waveform of the voltage drop (Vs) is similar to Figure 1B The PWM signal shown in , except that the envelope of the waveform is a sine wave. The voltage drop (Vs) is input to a low-pass filter amplifier. The low-pass filter amplifier usually has a relatively large gain and a resistor-capacitor (RC) circuit that occupies a relatively large chip area. The low-pass filter amplifier can filter out the high-frequency components of the signal, thereby smoothing the signal and providing some gain. The output signal of the low-pass filter amplifier is fed to an analog-to-digital converter (ADC), which converts the analog signal into a digital signal by sampling the analog signal. As Figure 2C As shown in FIG, the sampled output signal (Vout) corresponds to the voltage across the first sensing resistor R S1 The waveform of the voltage drop (Vs). Figure 2C The peak value (Vpeak) of the output signal (Vout) after sampling is obtained. Therefore, the peak current (Ipeak) can be calculated according to Ipeak=Vpeak / (g*R S ), where g is the gain of the low-pass filter amplifier, and R S is the first sensing resistor R S1 resistance.

[0107] However, this existing configuration has some disadvantages. The RC circuit and ADC occupy a considerable chip area. Removing the RC circuit and ADC will significantly reduce the chip area used for current sensing, thereby saving costs.

[0108] Figure 2D This is an example of another existing configuration for current sensing in a Class D amplifier. Figure 1A In the example shown in FIG. 1 , the output driver stage 290 includes Figure 2ASpecifically, the source of the p-type output transistor 291 is connected to a higher power rail (e.g., V DD ), the drain of the p-type output transistor 291 is at the first output terminal T OUTM The drain of the n-type output transistor 292 is connected to the drain of the n-type output transistor 292, and the source of the n-type output transistor 292 is connected to the lower power rail (eg, V SS The source of the p-type output transistor 293 is connected to a higher power rail (e.g., V DD ), the drain of the p-type output transistor 293 is at the second output terminal T OUTP The drain of the n-type output transistor 294 is connected to the drain of the p-type output transistor 293, and the source of the p-type output transistor 293 is connected to a lower power rail (eg, V SS or grounded). A speaker load 110 including an inductor L1 and a resistor R1 is connected to the first output terminal T OUTM With the second output terminal T OUTP between.

[0109] Different from the first sensing resistor R S1 For current sensing Figure 2A In the configuration shown in FIG, the sensing transistor 295 is used instead Figure 2D . Sense transistor 295 is connected in another branch parallel to the branch consisting of p-type output transistor 291 and n-type output transistor 292. The gate of sense transistor 295 is connected to the gate of n-type output transistor 292. The source of sense transistor 295 is connected to the lower power rail (e.g., V SS or ground). Therefore, the source of the sensing transistor 295 and the source of the n-type output transistor 292 are connected to the same voltage level. Therefore, the gate-to-source voltage (V GS ) is equal to the gate-to-source voltage of the n-type output transistor 292.

[0110] When the transistor operates in the linear region, the drain current through the transistor is calculated according to the following equation:

[0111]

[0112] Among them I D is the drain current, μ n is the effective charge carrier mobility, C OX is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, V DS is the voltage drop across the drain and source, and V thAs suggested by the above equations, if the sensing transistor 295 and the n-type output transistor 292 are fabricated at the same process corner, some of these parameters (μ n 、C OX 、V th ) are the same. As stated above, the gate-to-source voltage (V GS ) is equal to the gate-to-source voltage of the n-type output transistor 292. Therefore, if the voltage drop across the drain and source (V DS ) are the same, the drain current of the sense transistor 295 is proportional to the drain current of the n-type output transistor 292, depending on the respective W / L ratios. In other words, the current ratio between the two transistors can be controlled by controlling the W / L ratio of the n-type output transistor 292 and the W / L ratio of the sense transistor 295. Figure 2D In the example shown in FIG, the W / L ratio of the n-type output transistor 292 is M times the W / L ratio of the sense transistor 295. Therefore, assuming that the voltage drop across the drain and source (V DS ), the drain current of the sense transistor 295 is 1 / M of the drain current of the n-type output transistor 292. It should be understood that M can be selected from various available values ​​(e.g., 10, 100, 1000, 10000, etc.) as appropriate.

[0113] However, the voltage drop across the drain and source (V DS ) is not always the same. Therefore, the sense current (ie, the drain current of the sense transistor 295) is not exactly 1 / M of the drain current of the n-type output transistor 292, thus introducing errors in the current sensing process.

[0114] In order to solve the Figures 2A to 2D These deficiencies are described and novel current sensing configurations and circuits are provided. Figure 3A is a block diagram of a current sensing circuit for a Class-D amplifier according to some embodiments. Figure 3B is a diagram of an example of a sensing circuit for a Class-D amplifier according to some embodiments.

[0115] like Figure 3A As shown in FIG. 1 , the current sensing circuit 300 is coupled to a class D amplifier (eg, Figure 1A The output driver stage 390 (eg, Figure 2A The current sensing circuit 300 includes a peak detector 310 and a current sensor 350, as well as other components. The peak detector 310 is coupled to the output driver stage 390 and is configured to capture and lock the peak value of the first output signal OUTM (e.g., Figure 2A The V shown in S ). Figure 3B One embodiment of the peak detector 310 is shown in FIG. However, it should be understood that Figure 3B The example shown in FIG. 3 is illustrative and non-limiting, and other implementations may be employed. The current sensor 350 is coupled to the peak detector 310. The current sensor 350 is configured to receive the peak value of the output voltage captured by the peak detector 310 and generate a sense current based on the peak value of the output voltage. Figure 3B One embodiment of the current sensor 350 is shown in FIG. However, it should be understood that Figure 3B This example shown in is illustrative and not limiting, and other implementations may be used.

[0116] exist Figure 3B In the example shown in FIG. 1 , the peak detector 310 includes an operational amplifier (also referred to as a “first operational amplifier”) 312, a first n-type transistor 314, a second n-type transistor 318, a third n-type transistor 322, a first capacitor 316, and a second capacitor 320, among other components. The positive input terminal of the operational amplifier 312, which is the input node of the peak detector 310, is coupled to the first output terminal T OUTM , and the negative input terminal of the operational amplifier 312 is coupled to the output node A of the peak detector 310. The drain of the first n-type transistor 314 is coupled to a higher power rail (eg, V DD ), a source of the first n-type transistor 314 is coupled to the output node A, and a gate of the first n-type transistor 314 is coupled to the output terminal of the operational amplifier 312.

[0117] The first capacitor 316 is coupled between the output node A and the lower power rail (eg, V SS or ground). The drain of the second n-type transistor 318 is coupled to the output node A, the source of the second n-type transistor 318 is coupled to the node B, and the gate of the second n-type transistor 318 is coupled to the clock signal (at Figure 3B The second capacitor 320 is coupled between node B and the lower power rail (eg, V SS The drain of the third n-type transistor 322 is coupled to the node B, and the source of the third n-type transistor 322 is coupled to the lower power rail (eg, V SS or ground), and the gate of the third n-type transistor 322 is coupled to the clock signal (at Figure 3B The complementary clock signal (marked as "CK" in Figure 3B marked as “CKB” in the figure).

[0118] When the first output signal OUTM increases, the voltage level at the first input terminal of the operational amplifier 312 increases. Therefore, the voltage level at the output terminal of the operational amplifier 312 increases accordingly. Since the output terminal of the operational amplifier 312 is coupled to the gate of the first n-type transistor 314, the first n-type transistor 314 is turned on. The voltage level at the output node A is accordingly pulled up to a higher power rail (e.g., V DD )(minus the voltage drop across the source and drain of the first n-type transistor 314).

[0119] When the first output signal OUTM decreases, the voltage level at the first input terminal of the operational amplifier 312 decreases. Therefore, the voltage level at the output terminal of the operational amplifier 312 decreases accordingly. Since the output terminal of the operational amplifier 312 is coupled to the gate of the first n-type transistor 314, the first n-type transistor 314 is turned off. However, due to the presence of the first capacitor 316, there is no pull-down path to reduce the voltage level at the output node A. In other words, the voltage level at the output node A can only change in one direction (i.e., increase rather than decrease). When the first output signal decreases, the voltage level at the output node A remains unchanged. Therefore, the first output terminal T is captured and locked at the output node A of the peak detector 310. OUTM The peak value of the first output signal OUTM at .

[0120] However, the peak voltage of OUTM exhibits variability, with different peaks corresponding to different sine waves. In order to effectively capture subsequent peaks, a compact discharge path must be implemented, which is traditionally achieved by utilizing larger resistors. However, the disadvantages associated with using larger resistors, namely increased space requirements and increased costs, have prompted the exploration of alternative solutions. The present invention achieves this by employing switched capacitors (to be described below). Figure 3B The second capacitor 320 in FIG. 1 introduces a novel approach as a more space-efficient and cost-effective alternative to existing resistors, thereby promoting optimal discharge and enhanced peak capture.

[0121] The second capacitor 320, the second n-type transistor 318, and the third n-type transistor 322 are described below. The capacitance of the second capacitor 320 is less than the capacitance of the first capacitor 316. In one embodiment, the capacitance of the second capacitor 320 is 0.1%, 1%, 5%, or 10% of the capacitance of the first capacitor 316. Figure 3B When the complementary clock signal (marked as "CK") is at a logic high level, the second n-type transistor 318 is turned on. Figure 3BThe first capacitor 316 is connected to the second capacitor 320 in parallel with the first capacitor 316, and a portion of the charge stored in the first capacitor 316 is transferred to the second capacitor 320. From another perspective, the total capacitance increases due to the parallel connection, and the voltage level at the output node A decreases while the total amount of charge remains unchanged.

[0122] When the clock signal ( Figure 3B When the complementary clock signal (marked as "CK") is at a logic low level, the second n-type transistor 318 is turned off. Figure 3B The second capacitor 320 is no longer connected in parallel with the first capacitor 316, and both sides of the second capacitor 320 are connected to the lower power rail (e.g., V SS or grounded). Therefore, since the voltage drop becomes zero, the charges migrated to the second capacitor 320 are discharged.

[0123] exist Figure 3B In the example shown in FIG, the current sensor 350 includes another operational amplifier (also referred to as a "second operational amplifier") 352, a sensing transistor 395, a first p-type transistor 354, a second p-type transistor 356, and a third p-type transistor 358, among other components. The negative terminal of the operational amplifier 352 is coupled to the output node A of the peak detector 310, and the positive terminal of the operational amplifier 352 is coupled to the node C. The output terminal of the operational amplifier 352 is coupled to the gate of the first p-type transistor 354. The drain of the sensing transistor 395 is coupled to the node C, and the source of the sensing transistor 395 is coupled to the lower power rail (e.g., V SS The gate of the sense transistor 395 is connected to the gate of the n-type output transistor 392.

[0124] Since the positive and negative inputs of the operational amplifier 352 are virtually short-circuited, the voltage level of the positive input (and therefore, the voltage level at the node C) is the same as the voltage level at the output node A of the peak detector 310. In other words, the voltage level at the output node A of the peak detector 310 is replicated at the node C. Therefore, the V DS With the V of the n-type output transistor 392 DS The peak value is the same as above. Figure 2D As described, the drain current of the sense transistor 395 is proportional to the drain current of the n-type output transistor 392 because the V DS Clamped to the V of the n-type output transistor 392 DS The peak value. Figure 3BIn the example shown in FIG, the W / L ratio of the n-type output transistor 392 is M times the W / L ratio of the sense transistor 395. Therefore, the drain current of the sense transistor 395 is 1 / M of the drain current of the n-type output transistor 392.

[0125] The source of the first p-type transistor 354 is coupled to the drain and gate of the second p-type transistor 356. The drain of the first p-type transistor 354 is coupled to the node C. The voltage level at the output terminal is at a low level, and the first p-type transistor 354 is turned on, thereby coupling the sensing transistor 395 to the current mirror 360 formed by the second p-type transistor 356 and the third p-type transistor 358. The source of the second p-type transistor 356 and the source of the third p-type transistor 358 are coupled to a higher power rail (e.g., V DD ). The drain of the second p-type transistor 356 is coupled to the gates of the second p-type transistor 356 and the third p-type transistor 358. Figure 3B , the drain current of the third p-type transistor 358 is 1 / N of the drain current of the second p-type transistor 356. Therefore, the sense current (Isense) can be calculated according to Isense=I_out_peak / (M*N), where I_out_peak is the peak value of the output current I_out flowing through the n-type output transistor 392. In one example, M is equal to 10. In another example, M is equal to 100. In yet another example, M is equal to 1000. In yet another example, M is equal to 10000. In one example, N is equal to 10. In another example, N is equal to 100. In yet another example, N is equal to 1000. It should be understood that these examples are not intended to be limiting and other values ​​may be employed in other embodiments.

[0126] In some embodiments, the sense current (Isense) may be further converted into a digital signal for additional processing such as digital signal processing (DSP). Figure 4A is a diagram of an exemplary conversion circuit 410 according to some embodiments. Figure 4B is a diagram of another exemplary conversion circuit 450 according to some embodiments.

[0127] exist Figure 4A In the example shown in FIG, the conversion circuit 410 includes a resistor 412 and an analog-to-digital converter (ADC) 414, among other components. The sense current (Isense) is generated by a resistor connected to a higher power rail (e.g., V DD ) and node D. Resistor 412 is connected between node D and the lower power rail (eg, V SSor ground). The voltage level at node D is calculated according to Vsense = Isense * R, where R is the resistance of resistor 412. The voltage level at node D is input to ADC 414, which converts it into a digital value. However, ADC 414 occupies a relatively large chip area and is generally associated with a relatively high cost.

[0128] exist Figure 4B In the example shown in FIG, the conversion circuit 450 includes a capacitor 452, a comparator 454, and a counter 456, among other components. The sense current (Isense) is generated by a voltage connected to a higher power rail (e.g., V DD ) and node E. Capacitor 452 is connected between node E and the lower power rail (eg, V SS The negative input of the comparator 454 is coupled to the node E, and the reference voltage is supplied to the positive input of the comparator 454. The output of the comparator 454 is coupled to the input of the counter 456.

[0129] like Figure 4B As shown in FIG, the sense current charges capacitor 452, and the charge stored by capacitor 452 can be calculated as Q=C*V=Isense*Δt, where C is the capacitance of capacitor 452, V is the voltage drop across capacitor 452, and Δt is the charging period. Therefore, Isense can be calculated as Isense=(C*V) / Δt.

[0130] The voltage drop (V) has a ramp signal waveform (at Figure 4B The voltage drop (V) is related to the reference voltage (in Figure 4B The output signal of the comparator 454 has a PWM waveform (marked as "Vref" in FIG. Figure 4B (labeled "464" in the figure). The pulse width of the PWM waveform corresponds to the charging period (Δt). Counter 456 receives a high-frequency clock signal as input and counts the number of cycles of the counter clock signal for each pulse width of the PWM waveform. Thus, the charging period (Δt) is counted, and the sense current Isense can be calculated according to Isense = (C*V) / Δt, as explained above. Thus, the calculated sense current Isense is digitized.

[0131] According to the above description, at different output resistance ( Figure 3B At the R1) value shown in Figure 3A and Figure 3BThe absolute value of the error ratio of the current sensing circuit 300 shown in FIG is between 0.4% and 1.3%. Specifically, when the output resistance is 4 ohms, the error ratio is 0.4%; when the output resistance is 5 ohms, the error ratio is -0.9%; when the output resistance is 6 ohms, the error ratio is -1.3%; when the output resistance is 7 ohms, the error ratio is -1.1%; and when the output resistance is 8 ohms, the error ratio is -1%.

[0132] Therefore, this error ratio is significantly better than Figure 2D The absolute value of the error rate of the current sensing circuit shown in FIG is typically 10%. This advantage is achieved by utilizing the peak detector 310 to capture the peak value of the first output signal OUTM, as explained above.

[0133] Figure 5 is a flow chart of an exemplary method for operating a Class D amplifier according to some embodiments. Figure 5 In the example shown in , method 500 includes operations (or steps) 502, 504, and 506. Optionally, method 500 may perform additional operations or steps.

[0134] At step 502, an output driver stage (eg, a Class D amplifier) ​​is provided at an output node of the output driver stage. Figure 3B The output driver stage 390 shown in FIG. 1 outputs an output signal (eg, Figure 3B OUTM).

[0135] At step 504, a peak detector (e.g., Figure 3B The peak detector 310 shown in FIG. 3 captures the peak value of the output signal.

[0136] At step 506, the current sensor (eg, Figure 3B The current sensor 350 shown in FIG. 3 generates a sense current.

[0137] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same objectives and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A class D amplifier, characterized in that: Include: an output driver stage configured to output an output signal at an output node; a current sensing circuit coupled to the output node of the output driver stage, the current sensing circuit comprising: a peak detector coupled to the output node of the output driver stage, the peak detector being configured to capture a peak value of the output signal; as well as A current sensor is coupled to the peak detector and configured to receive the peak value of the output signal and generate a sensed current based on the peak value of the output signal.

2. The class D amplifier according to claim 1, wherein The peak detector locks onto the peak value of the output signal.

3. The class D amplifier according to claim 1, wherein The peak detector includes an output node, and wherein when the output signal of the output node of the output driver stage increases, the voltage level of the output node of the peak detector increases, and when the output signal of the output node of the output driver stage decreases, the voltage level of the output node of the peak detector remains unchanged.

4. The class D amplifier according to claim 1, wherein The peak detector comprises: a first operational amplifier; a first n-type transistor; and a first capacitor.

5. The class D amplifier according to claim 4, wherein: A positive input of the first operational amplifier is coupled to the output node of the output driver stage, a negative input of the first operational amplifier is coupled to an output node of the peak detector, and an output of the first operational amplifier is coupled to a gate of the first n-type transistor.

6. The class D amplifier according to claim 5, wherein: A drain of the first n-type transistor is coupled to a higher power rail, and a source of the first n-type transistor is coupled to an output node of the peak detector.

7. The class D amplifier according to claim 6, wherein: The first capacitor is coupled between the output node of the peak detector and a lower power rail that is lower than the upper power rail.

8. The class D amplifier according to claim 7, wherein: The peak detector further comprises: a second n-type transistor; a third n-type transistor; and a second capacitor.

9. The class D amplifier according to claim 8, wherein A drain of the second n-type transistor is coupled to the output node of the peak detector, a source of the second n-type transistor is coupled to a second node, and the second capacitor is coupled between the second node and the lower power rail, and a drain of the third n-type transistor is coupled to the second node, and a source of the third n-type transistor is coupled to the lower power rail.

10. The class D amplifier according to claim 9, wherein A gate of the second n-type transistor is coupled to a first clock signal, and a gate of the third n-type transistor is coupled to a second clock signal, and the second clock signal is complementary to the first clock signal.

11. The class D amplifier according to claim 10, wherein: The capacitance of the second capacitor is smaller than the capacitance of the first capacitor.

12. The class D amplifier according to claim 1, wherein The current sensor comprises: a second operational amplifier; a sensing transistor; a first p-type transistor; and A current mirror.

13. The class D amplifier according to claim 12, wherein: A negative input terminal of the second operational amplifier is coupled to the peak detector to receive the peak value of the output signal of the output driver stage, a positive input terminal of the second operational amplifier is coupled to a third node, and an output terminal of the second operational amplifier is coupled to a gate of the first p-type transistor, wherein a source of the first p-type transistor is coupled to the current mirror, and a drain of the first p-type transistor is coupled to the third node.

14. The class D amplifier according to claim 13, wherein: A drain of the sensing transistor is coupled to the third node, and a source of the sensing transistor is coupled to a lower power rail.

15. The class D amplifier according to claim 14, wherein: The current mirror comprises: a second p-type transistor, wherein the source of the first p-type transistor is coupled to a drain and a gate of the second p-type transistor, and a source of the second p-type transistor is coupled to a higher power rail, wherein the higher power rail is higher than the lower power rail; as well as a third p-type transistor, wherein a source of the third p-type transistor is coupled to the higher power rail, a gate of the third p-type transistor is coupled to the gate of the second p-type transistor, and a drain of the third p-type transistor is coupled to an output terminal of the current sensor.

16. The class D amplifier according to claim 15, wherein: The output terminal of the current sensor is coupled to a conversion circuit, and the conversion circuit includes: a capacitor coupled between the output of the current sensor and the lower power rail; a comparator comprising a negative input terminal and a positive input terminal, the negative input terminal being coupled to the output terminal of the current sensor, and the positive input terminal being configured to receive a reference voltage; as well as A counter is coupled to an output terminal of the comparator.

17. A method for operating a class D amplifier, characterized in that The method comprises: outputting an output signal at an output node of an output driver stage; capturing a peak value of the output signal by a peak detector; and A current sensor generates a sensing current based on the peak value of the output signal.

18. The method according to claim 17, wherein Retrieving the peak value of the output signal further comprises: The peak value of the output signal is locked.

19. The method according to claim 18, wherein When the output signal increases, the voltage level of the output node of the peak detector increases, and when the output signal decreases, the voltage level of the output node of the peak detector remains unchanged.

20. The method of claim 17, wherein: Further including: A comparator and a counter are used to convert the sensed current into a digital sensed current.

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