Video signal generator with nanosecond delay control

Abstract

The invention discloses a video signal generator with nanosecond delay control. The video signal generator comprises a test video source input and control module, a test video source receiving and transmission module, a test video algorithm processing module, a real-time video source input module, a test video output module, a power module and a clock module. The FPGA, the double ARMs and the double ASICs serve as a core framework, the problems that a traditional video signal generator is single in output signal type, low in real-time performance, poor in compatibility and simple in testing function are solved, the multi-channel precise synchronous output capacity is achieved, testing of holographic projection, AR, VR, multi-projection circular screen and other novel display technologies is supported, and the testing efficiency is improved. The multi-screen synchronous test, the special resolution output test, the pixel-level video delay adjustable test and the real-time video acquisition function are realized, the limitation of the traditional equipment in the aspects of test diversity and specialty is broken through, and efficient and reliable test support is provided for the development of a novel display technology.

Description

Technical Field

[0001] The present invention relates to the technical field of video signal generation and processing, and in particular to a video signal generator with nanosecond delay control, which aims to solve the problems of traditional video signal generators in terms of single output signal type, low real-time performance, poor compatibility and simple test functions. Background Art

[0002] Video signal generators are a type of electronic test equipment widely used in the video industry, playing a vital role in video equipment calibration, debugging, testing, and verification. Common video signal generators support image resolution, frame rate, brightness, contrast, and color testing. These test images are simple, functionality is minimal, and they lack support for delay and synchronization testing, resulting in poor real-time performance. The development of new display technologies such as holographic projection, AR, VR, multi-projection surround systems, and stereoscopic displays has led to unprecedentedly high standards for the synchronization accuracy and processing delay control of multi-channel video signals.

[0003] In the application of holographic projection technology, the system needs to implement precise amplitude modulation and phase modulation techniques on the video signal to achieve 3D image reproduction. To ensure accurate 3D image reproduction, the system needs to strictly calibrate the tiny time difference between two or more video streams to achieve extremely precise synchronization.

[0004] In applications such as AR, VR, and stereoscopic video, system latency and accurate position perception have become key metrics for user experience and interaction efficiency. Any deviation in depth and orientation significantly interferes with the user's accurate judgment of the spatial position of virtual objects, thereby affecting the overall sense of immersion and the smoothness of interaction. The accuracy of depth information and orientation positioning is highly dependent on the accuracy of parallax calculations between video streams. This calculation process is not only complex but also places extremely stringent requirements on the synchronization of multiple video signals. Therefore, implementing a more accurate video synchronization mechanism and reducing system latency are crucial to ensuring user experience and interaction efficiency.

[0005] With the rapid development of new display technologies, the functional limitations of traditional video signal generators have significantly lagged behind market demand, and their shortcomings have become increasingly prominent during the development and testing of these technologies. Therefore, this paper develops a video signal generator with nanosecond-level delay control to meet the testing requirements of new display technologies for synchronization, system delay, and distorted output, thereby contributing to the development of new display technologies. Summary of the Invention

[0006] The purpose of this invention is to provide a video signal generator with nanosecond-level delay control. This generator not only provides the static image testing capabilities of traditional video signal generators, such as grayscale, color reproduction, and image resolution testing, but also supports output testing of videos with special resolutions, pixel-level precision video synchronization, and delay testing, enabling testing of synchronization issues across various display devices. Furthermore, to support more real-time applications, it incorporates a real-time video capture function, along with pixel-level delay and synchronization control, providing a testing environment for applications such as live broadcasting and real-time motion analysis.

[0007] The specific technical solution for achieving the purpose of the present invention is:

[0008] A video signal generator with nanosecond delay control is characterized in that it includes a test video source input and control module, a test video source receiving and transmission module, a test video algorithm processing module, a real-time video source input module, a test video output module, a power supply module and a clock module;

[0009] The test video source input and control module is respectively connected to the test video source receiving and transmitting module, the test video delay processing and resolution conversion module and the power supply module;

[0010] The test video source input and control module includes a control instruction sending module, a test video source generation module and a test video source data PCIe sending module; the control instruction sending module is connected to the test video source generation module; the control instruction sending module can send a custom test video source selection control instruction to the test video source generation module; the test video source generation module is respectively connected to the control instruction sending module and the test video source data PCIe sending module; the test video source generation module generates a test video source according to the control instruction, including a color bar test, a grayscale test, a resolution test video and a dynamic custom video; the test video source data PCIe sending module is respectively connected to the test video source generation module and the test video source receiving and transmission module; the test video source data PCIe sending module sends the test video source generated by the test video source generation module to the test video source receiving and transmission module through the PCIe interface;

[0011] The test video source receiving and transmission module is respectively connected to the test video source input and control module, the test video algorithm processing module, the power module and the clock module; it receives the ultra-high-definition lossless video stream data sent by the test video source input and control module, and forwards it to the test video algorithm processing module through the optical port;

[0012] The test video algorithm processing module is respectively connected to the test video source receiving and transmission module, the real-time video source input module, the test video output module, the power module and the clock module to realize preprocessing, resolution conversion, delay and synchronization of the video forwarded by the optical port in the test video source receiving and transmission module and the video captured in real time by the image sensor in the real-time video source input module, and then output them to the test video output module;

[0013] The real-time video source input module is connected to the test video algorithm processing module, the power module and the clock module respectively, and transmits the real-time collected video data to the test video algorithm processing module;

[0014] The test video output module is connected to the test video algorithm processing module, the power module and the clock module respectively to realize video timing recovery and output dual-channel videos with different resolutions;

[0015] The power supply module is respectively connected to the test video source input and control module, the test video source receiving and transmission module, the test video algorithm processing module, the real-time video source input module, the test video output module and the clock module to provide the required voltage and current for the test video source receiving and transmission module, the test video algorithm processing module, the real-time video source input module, the test video output module and the clock module;

[0016] The clock module is respectively connected to the test video source receiving and transmission module, the test video algorithm processing module, the real-time video source input module, the test video output module and the power supply module, and provides the required clock for the test video source receiving and transmission module, the test video algorithm processing module, the real-time video source input module, the test video output module and the power supply module.

[0017] Furthermore, the test video source receiving and transmission module includes a test video PCIe receiving module, a video cache and cross-clock domain processing module and an optical port driver sending module. The test video PCIe receiving module is connected to the video cache and cross-clock domain processing module; the test video PCIe receiving module receives the video data sent by the test video source data PCIe sending module, and sends the data to the video cache and cross-clock domain processing module; the video cache and cross-clock domain processing module are respectively connected to the test video PCIe receiving module and the optical port driver sending module; the video cache and cross-clock domain processing module caches the video data, avoids timing violations through cross-clock domain processing, and sends the video data to the optical port driver sending module; the optical port driver sending module is connected to the optical port driver receiving module, and can package the video into a UDP data packet, and send it to the test video algorithm processing module through the optical port for algorithm processing.

[0018] Furthermore, the test video algorithm processing module includes an optical port driver receiving module, a test video source data preprocessing module, a real-time video source data receiving module, a real-time video source data preprocessing module, a low-latency video resolution conversion module, a DDR4 dynamic interleaving access module, a synchronization and delay control instruction parsing module, a multi-channel collaborative nanosecond delay and synchronization algorithm module, and a synchronization signal generation module;

[0019] The optical port driver receiving module is connected to the optical port driver sending module and the test video source data preprocessing module respectively; the optical port driver receiving module receives the test video data packet sent by the optical port driver sending module, performs UDP data packet parsing, and sends the parsed video data to the test video source data preprocessing module;

[0020] The test video source data preprocessing module is connected to the optical port driver receiving module and the low-latency video resolution conversion module respectively; the test video source data preprocessing module realizes data bit width conversion and cross-clock domain processing of video data;

[0021] The real-time video source data receiving module is connected to the real-time video source data preprocessing module and the real-time video source input module respectively; the real-time video source data receiving module receives the video data collected by the real-time video source input module;

[0022] The real-time video source data preprocessing module is connected to the real-time video source data receiving module and the low-latency video resolution conversion module respectively; the real-time video source data preprocessing module realizes data bit width conversion and cross-clock domain processing of the real-time video source data;

[0023] The low-latency video resolution conversion module is connected to the test video source data preprocessing module 32, the real-time video source data preprocessing module and the DDR4 dynamic interleaving access module respectively; the low-latency video resolution conversion module converts the 4K@30Hz video source data into 2560×1600@30Hz;

[0024] The DDR4 dynamic interleaving access module is connected to the low-latency video resolution conversion module, the synchronization signal generation module and the test video output module respectively; the DDR4 dynamic interleaving access module realizes DDR4 dynamic interleaving access of the real-time video source and the test video source;

[0025] The synchronization and delay control instruction parsing module is connected to the control instruction sending module and the multi-channel collaborative nanosecond delay and synchronization algorithm module respectively; the synchronization and delay control instruction parsing module parses the instruction transmitted by the control instruction sending module and transmits the parsed instruction to the multi-channel collaborative nanosecond delay and synchronization algorithm module;

[0026] The multi-channel collaborative nanosecond delay and synchronization algorithm module is respectively connected to the synchronization and delay control instruction parsing module, the synchronization signal generation module and the test video output module; the multi-channel collaborative nanosecond delay and synchronization algorithm module controls the accuracy and range of the relative delay of the two-way video output by the test video output module, and controls the synchronization signal generation module;

[0027] The synchronization signal generation module is respectively connected to the DDR4 dynamic interleaving access module and the multi-channel collaborative nanosecond delay and synchronization algorithm module; the synchronization signal generation module generates a synchronization signal to control the time when the DDR4 dynamic interleaving access module accesses video data.

[0028] Furthermore, the real-time video source input module includes a first image sensor and a second image sensor; the first image sensor and the second image sensor realize real-time dual-view video acquisition; the first image sensor and the second image sensor are respectively connected to the real-time video source data receiving module to transmit the real-time acquired video data to the real-time video source data receiving module.

[0029] Furthermore, the test video output module includes a first video timing recovery module, a first video output GSV2011 chip, a first video output interface, a second video timing recovery module, a second video output GSV2011 chip, and a second video output interface; the first video timing recovery module is respectively connected to the first video output GSV2011 chip and the DDR4 dynamic interleaving access module; the first video timing recovery module is capable of restoring 4K@30Hz HDMI video timing;

[0030] The second video timing recovery module is connected to the second video output GSV2011 chip and the DDR4 dynamic interleaving access module respectively; the second video timing recovery module is capable of recovering 2560×1600@30Hz HDMI video timing;

[0031] The first video output GSV2011 chip is connected to the first video timing recovery module and the first video output interface respectively; the first video output GSV2011 chip encodes the video data and video timing into HDMI format and outputs it to the first video output interface;

[0032] The second video output GSV2011 chip is connected to the second video timing recovery module and the second video output interface respectively; the second video output GSV2011 chip encodes the video data and video timing into HDMI format and outputs it to the second video output interface.

[0033] Furthermore, the first image sensor and the second image sensor are AR1337 ultra-high-definition CMOS image sensors.

[0034] Furthermore, the test video output module supports conventional 4K@30HZ resolution and non-standard resolution 2560×1600@30Hz video output.

[0035] The advantages of the present invention are:

[0036] 1) The present invention has powerful processing capabilities and innovative architecture. The present invention adopts a heterogeneous multi-core processing system architecture, using FPGA + dual ARM + dual ASIC as the core architecture.

[0037] 2) The invention's algorithm innovation supports the production of videos with special resolutions. The invention designs an innovative low-latency resolution downsampling algorithm, which increases the processing rate by more than 3 times.

[0038] 3) The present invention supports nanosecond-level video delay control. The present invention adopts a pipeline structure design and interleaved storage of image data to achieve nanosecond-level ultra-high-definition video delay control.

[0039] 4) The present invention realizes low-latency and uncompressed video transmission. The present invention realizes high-quality and low-latency video transmission by combining PCIe and 10 Gigabit Ethernet.

[0040] 5) The host computer software of the present invention has innovative functions, which can customize the test video source selection, adjust the multi-channel video synchronization and delay parameters in real time, and switch the video source to the PC host computer output video or the video collected in real time by the image sensor.

[0041] 6) The hardware system of the present invention is independently designed, highly reliable, and complies with the design principles of signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMI). BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural block diagram of the present invention;

[0043] Figure 2 It is a structural block diagram of the test video source input and control module;

[0044] Figure 3 This is a structural diagram of the test video source receiving and transmission module;

[0045] Figure 4 This is a structural diagram for testing the video delay processing and resolution conversion module;

[0046] Figure 5 This is the structural diagram of the real-time video source input module;

[0047] Figure 6 This is the structural diagram of the test video output module;

[0048] Figure 7 It is a flowchart of the workflow of the present invention. DETAILED DESCRIPTION

[0049] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0050] See Figure 1 , a video signal generator with nanosecond delay control, which includes a test video source input and control module 1, a test video source receiving and transmission module 2, a test video algorithm processing module 3, a real-time video source input module 4, a test video output module 5, a power supply module 6 and a clock module 7; the test video source input and control module 1 is respectively connected to the test video source receiving and transmission module 2, the test video delay processing and resolution conversion module 3 and the power supply module 6;

[0051] The test video source receiving and transmitting module 2 is respectively connected to the test video source input and control module 1, the test video algorithm processing module 3, the power supply module 6 and the clock module 7;

[0052] The test video algorithm processing module 3 is respectively connected to the test video source receiving and transmitting module 2, the real-time video source input module 4, the test video output module 5, the power module 6 and the clock module 7;

[0053] The real-time video source input module 4 is connected to the test video algorithm processing module 3, the power supply module 6 and the clock module 7 respectively;

[0054] The test video output module 5 is connected to the test video algorithm processing module 3, the power module 6 and the clock module 7 respectively; the test video output module 5 realizes video timing recovery and outputs dual-channel videos with different resolutions to the video output interface;

[0055] The power supply module 6 is respectively connected to the test video source input and control module 1, the test video source receiving and transmission module 2, the test video algorithm processing module 3, the real-time video source input module 4, the test video output module 5 and the clock module 7;

[0056] The clock module 7 is respectively connected to the test video source receiving and transmitting module 2, the test video algorithm processing module 3, the real-time video source input module 4, the test video output module 5 and the power supply module 6;

[0057] See Figure 2 , the test video source input and control module 1 is respectively connected to the test video source receiving and transmission module 2, the test video delay processing and resolution conversion module 3 and the power supply module 6;

[0058] The test video source input and control module 1 includes a control instruction sending module 11, a test video source generating module 12 and a test video source data PCIe sending module 13; the control instruction sending module 11 is connected to the test video source generating module 12 and the synchronization and delay control instruction parsing module 37 respectively; the control instruction sending module 11 can send a custom test video source selection control instruction to the test video source generating module 12; the control instruction sending module 11 can send a synchronization and delay parameter instruction to the synchronization and delay control instruction parsing module 37; the test video source generating module 12 .... The test video source data PCIe sending module 13 is respectively connected to the control instruction sending module 11 and the test video source data PCIe sending module 13; the test video source generating module 12 generates a test video source according to the control instruction, including a color bar test, a grayscale test, a resolution test video and a dynamic custom video; the test video source data PCIe sending module 13 is respectively connected to the test video source generating module 12 and the test video source receiving and transmitting module 2; the test video source data PCIe sending module 13 sends the test video source generated by the test video source generating module 12 to the test video source receiving and transmitting module 2 through the PCIe interface.

[0059] See Figure 3 The test video algorithm processing module 3 includes an optical port driver receiving module 31, a test video source data preprocessing module 32, a real-time video source data receiving module 33, a real-time video source data preprocessing module 34, a low-latency video resolution conversion module 35, a DDR4 dynamic interleaving access module 36, a synchronization and delay control instruction parsing module 37, a multi-channel collaborative nanosecond delay and synchronization algorithm module 38 and a synchronization signal generation module 39; the test video algorithm processing module 3 implements preprocessing, resolution conversion, delay and synchronization processing of the video forwarded by the optical port in the test video source receiving and transmission module 2 and the video captured in real time by the image sensor in the real-time video source input module 4, and then outputs them to the test video output module 5;

[0060] The optical port driver receiving module 31 is connected to the optical port driver sending module 23 and the test video source data preprocessing module 32 respectively; the optical port driver receiving module 31 receives the test video data packet sent by the optical port driver sending module 23, performs UDP data packet parsing, and sends the parsed video data to the test video source data preprocessing module 32;

[0061] The test video source data preprocessing module 32 is connected to the optical port driver receiving module 31 and the low-latency video resolution conversion module 35 respectively; the test video source data preprocessing module 32 realizes data bit width conversion and cross-clock domain processing of video data;

[0062] The real-time video source data receiving module 33 is connected to the real-time video source data preprocessing module 34 and the real-time video source input module 4 respectively; the real-time video source data receiving module 33 receives the video data collected by the real-time video source input module 4;

[0063] The real-time video source data preprocessing module 34 is connected to the real-time video source data receiving module 33 and the low-latency video resolution conversion module 35 respectively; the real-time video source data preprocessing module 34 realizes data bit width conversion and cross-clock domain processing of the real-time video source data;

[0064] The low-latency video resolution conversion module 35 is connected to the test video source data preprocessing module 32, the real-time video source data preprocessing module 34, and the DDR4 dynamic interleaving access module 36 respectively; the low-latency video resolution conversion module 35 converts the 4K@30Hz video source data into 2560×1600@30Hz;

[0065] The DDR4 dynamic interleaving access module 36 is connected to the low-latency video resolution conversion module 35, the synchronization signal generation module 39, and the test video output module 5 respectively; the DDR4 dynamic interleaving access module 36 implements DDR4 dynamic interleaving access of the real-time video source and the test video source;

[0066] The synchronization and delay control instruction parsing module 37 is connected to the control instruction sending module 11 and the multi-channel collaborative nanosecond delay and synchronization algorithm module 38 respectively; the synchronization and delay control instruction parsing module 37 parses the instruction transmitted by the control instruction sending module 11 and transmits the parsed instruction to the multi-channel collaborative nanosecond delay and synchronization algorithm module 38;

[0067] The multi-channel coordinated nanosecond delay and synchronization algorithm module 38 is respectively connected to the synchronization and delay control instruction parsing module 37, the synchronization signal generating module 39, and the test video output module 5; the multi-channel coordinated nanosecond delay and synchronization algorithm module 38 controls the accuracy and range of the relative delay of the two-way video output by the test video output module 5, and controls the synchronization signal generating module 39;

[0068] The synchronization signal generating module 39 is connected to the DDR4 dynamic interleaving access module 36 and the multi-channel coordinated nanosecond delay and synchronization algorithm module 38 respectively; the synchronization signal generating module 39 generates a synchronization signal to control the time when the DDR4 dynamic interleaving access module 36 accesses video data.

[0069] See Figure 4The test video source receiving and transmission module 2 includes a test video PCIe receiving module 21, a video cache and cross-clock domain processing module 22 and an optical port drive sending module 23; the test video source receiving and transmission module 2 receives the ultra-high-definition lossless video stream data sent by the test video source input and control module 1, and forwards it to the test video algorithm processing module 3 through the optical port; the test video PCIe receiving module 21 is connected to the video cache and cross-clock domain processing module 22; the test video PCIe receiving module 21 receives the video sent by the test video source data PCIe sending module 13 The video data is transmitted and sent to the video cache and cross-clock domain processing module 22; the video cache and cross-clock domain processing module 22 are respectively connected to the test video PCIe receiving module 21 and the optical port driver sending module 23; the video cache and cross-clock domain processing module 22 caches the video data, avoids timing violations through cross-clock domain processing, and sends the video data to the optical port driver sending module 23; the optical port driver sending module 23 is connected to the optical port driver receiving module 31, and can package the video into a UDP data packet, and send it to the test video algorithm processing module 3 through the optical port for algorithm processing.

[0070] See Figure 5 The real-time video source input module 4 includes a first image sensor 41 and a second image sensor 42; the first image sensor 41 and the second image sensor 42 realize real-time dual-view video acquisition; the first image sensor 41 and the second image sensor 42 are respectively connected to the real-time video source data receiving module 33, and transmit the real-time acquired video data to the real-time video source data receiving module 33.

[0071] See Figure 6 The test video output module 5 includes a first video timing recovery module 51, a first video output GSV2011 chip 52, a first video output interface 53, a second video timing recovery module 54, a second video output GSV2011 chip 55, and a second video output interface 56; the first video timing recovery module 51 is respectively connected to the first video output GSV2011 chip 52 and the DDR4 dynamic interleaving access module 36; the first video timing recovery module 51 can restore 4K@30Hz HDMI video timing.

[0072] The second video timing recovery module 54 is connected to the second video output GSV2011 chip 55 and the DDR4 dynamic interleaving access module 36 respectively; the second video timing recovery module 54 can recover the 2560×1600@30Hz HDMI video timing.

[0073] The first video output GSV2011 chip 52 is connected to the first video timing recovery module 51 and the first video output interface 53 respectively; the first video output GSV2011 chip 52 encodes the video data and video timing into HDMI format and outputs it to the first video output interface 53.

[0074] The second video output GSV2011 chip 55 is connected to the second video timing recovery module 54 and the second video output interface 56 respectively; the second video output GSV2011 chip 55 encodes the video data and video timing into HDMI format and outputs it to the second video output interface 56.

[0075] Example

[0076] The modules of this embodiment are selected as follows: the test video source receiving and transmission module 2 is implemented using the Xilinx Zynq7045 chip, which has rich hardware resources, including PCIe resources, and supports large-bandwidth video storage and transmission requirements; the test video delay processing and resolution conversion module 3 is implemented using the Xilinx Zynq Ultrascale+ series chip, which has rich logic resources, high processing performance, and strong flexibility.

[0077] See Figure 7This embodiment can constitute a video signal generator with nanosecond-level delay control. By flashing the program to an SD card, the device is powered on and the system begins operation. The control instruction sending module 11 sends instructions to the test video source generation module 12 and the synchronization and delay control instruction parsing module 37. The test video source data PCIe transmission module 13 transmits the selected test video source to the test video PCIe receiving module 21. The video buffering and cross-clock domain processing module 22 buffers and receives the custom test video source and transmits it through the optical port driver transmission module 23. The optical port driver receiving module 31 receives the test video data sent by the optical port driver transmission module 23 and inputs it to the low-latency video resolution conversion module 35 via the test video source data preprocessing module 32. The synchronization and delay control instruction parsing module 37 receives the control instructions sent by the control instruction sending module 11 and transmits them to the multi-channel coordinated nanosecond-level delay and synchronization algorithm module 38 and the synchronization signal generation module 39. The DDR4 dynamic interleaving access module 36 is controlled to output two channels of video with different resolutions and relative delays. The resolution of the first video channel is 2560×1600, and the resolution of the second video channel is 3840×2160. The delay accuracy of both video channels is 7.445ns, with a maximum delay accuracy of 200ms. The first video channel's video timing is restored by the first video timing recovery module 51, and the first video output GSV2011 chip 52 generates an HDMI video signal, which is then output to the display screen via the first video output interface 53. The second video channel's video timing is restored by the second video timing recovery module 54, and the second video output GSV2011 chip 55 generates an HDMI video signal, which is then output to the display screen via the second video output interface 56. Both video channels can be used as test video inputs for new display devices, enabling debugging and calibration of the new display devices.

Claims

1. A video signal generator with nanosecond delay control, characterized in that: It includes a test video source input and control module (1), a test video source receiving and transmission module (2), a test video algorithm processing module (3), a real-time video source input module (4), a test video output module (5), a power supply module (6) and a clock module (7); The test video source input and control module (1) is respectively connected to the test video source receiving and transmission module (2), the test video delay processing and resolution conversion module (3) and the power supply module (6); The test video source input and control module (1) includes a control instruction sending module (11), a test video source generating module (12) and a test video source data PCIe sending module (13); the control instruction sending module (11) is connected to the test video source generating module (12); the control instruction sending module (11) can send a custom test video source selection control instruction to the test video source generating module (12); the test video source generating module (12) is respectively connected to the control instruction sending module (11) and the test video source data PCIe sending module (13); the test video source generating module (12) generates a test video source according to the control instruction, including a color bar test, a grayscale test, a resolution test video and a dynamic custom video; the test video source data PCIe sending module (13) is respectively connected to the test video source generating module (12) and the test video source receiving and transmitting module (2); the test video source data PCIe sending module (13) sends the test video source generated by the test video source generating module (12) to the test video source receiving and transmitting module (2) through the PCIe interface; The test video source receiving and transmitting module (2) is respectively connected to the test video source input and control module (1), the test video algorithm processing module (3), the power supply module (6) and the clock module (7); it receives the ultra-high-definition lossless video stream data sent by the test video source input and control module (1) and forwards it to the test video algorithm processing module (3) through the optical port; The test video algorithm processing module (3) is respectively connected to the test video source receiving and transmission module (2), the real-time video source input module (4), the test video output module (5), the power supply module (6) and the clock module (7), so as to perform pre-processing, resolution conversion, delay and synchronization processing on the video forwarded by the optical port in the test video source receiving and transmission module (2) and the video captured in real time by the image sensor in the real-time video source input module (4), and then output them to the test video output module (5); The real-time video source input module (4) is connected to the test video algorithm processing module (3), the power supply module (6) and the clock module (7) respectively, and transmits the real-time collected video data to the test video algorithm processing module (3); The test video output module (5) is connected to the test video algorithm processing module (3), the power supply module (6) and the clock module (7) respectively to achieve video timing recovery and output of two-way videos with different resolutions; The power supply module (6) is respectively connected to the test video source input and control module (1), the test video source receiving and transmission module (2), the test video algorithm processing module (3), the real-time video source input module (4), the test video output module (5) and the clock module (7), and provides the required voltage and current for the test video source receiving and transmission module (2), the test video algorithm processing module (3), the real-time video source input module (4), the test video output module (5) and the clock module (7); The clock module (7) is respectively connected to the test video source receiving and transmission module (2), the test video algorithm processing module (3), the real-time video source input module (4), the test video output module (5) and the power supply module (6), and provides the required clock for the test video source receiving and transmission module (2), the test video algorithm processing module (3), the real-time video source input module (4), the test video output module (5) and the power supply module (6).

2. The video signal generator according to claim 1, wherein: The test video source receiving and transmission module (2) includes a test video PCIe receiving module (21), a video cache and cross-clock domain processing module (22) and an optical port drive sending module (23), wherein the test video PCIe receiving module (21) is connected to the video cache and cross-clock domain processing module (22); the test video PCIe receiving module (21) receives the video data sent by the test video source data PCIe sending module (13), and sends the data to the video cache and cross-clock domain processing module (22); the video cache and cross-clock domain processing module (22) are respectively connected to the test video PCIe receiving module (21) and the optical port drive sending module (23); the video cache and cross-clock domain processing module (22) caches the video data, avoids timing violations through cross-clock domain processing, and sends the video data to the optical port drive sending module (23); the optical port drive sending module (23) is connected to the optical port drive receiving module (31), and can package the video into a UDP data packet, and send it to the test video algorithm processing module (3) through the optical port for algorithm processing.

3. The video signal generator according to claim 1, characterized in that: The test video algorithm processing module (3) includes an optical port driver receiving module (31), a test video source data preprocessing module (32), a real-time video source data receiving module (33), a real-time video source data preprocessing module (34), a low-latency video resolution conversion module (35), a DDR4 dynamic interleaving access module (36), a synchronization and delay control instruction parsing module (37), a multi-channel coordinated nanosecond delay and synchronization algorithm module (38) and a synchronization signal generation module (39); The optical port driver receiving module (31) is connected to the optical port driver sending module (23) and the test video source data preprocessing module (32) respectively; the optical port driver receiving module (31) receives the test video data packet sent by the optical port driver sending module (23), performs UDP data packet parsing, and sends the parsed video data to the test video source data preprocessing module (32); The test video source data preprocessing module (32) is connected to the optical port drive receiving module (31) and the low-latency video resolution conversion module (35) respectively; the test video source data preprocessing module (32) realizes data bit width conversion and cross-clock domain processing of video data; The real-time video source data receiving module (33) is connected to the real-time video source data pre-processing module (34) and the real-time video source input module (4) respectively; the real-time video source data receiving module (33) receives the video data collected by the real-time video source input module (4); The real-time video source data preprocessing module (34) is connected to the real-time video source data receiving module (33) and the low-latency video resolution conversion module (35) respectively; the real-time video source data preprocessing module (34) realizes data bit width conversion and cross-clock domain processing of the real-time video source data; The low-latency video resolution conversion module (35) is connected to the test video source data preprocessing module (32), the real-time video source data preprocessing module (34) and the DDR4 dynamic interleaving access module (36) respectively; the low-latency video resolution conversion module (35) converts the 4K@30Hz video source data into 2560×1600@30Hz; The DDR4 dynamic interleaving access module (36) is respectively connected to the low-latency video resolution conversion module (35), the synchronization signal generation module (39) and the test video output module (5); the DDR4 dynamic interleaving access module (36) realizes DDR4 dynamic interleaving access of the real-time video source and the test video source; The synchronization and delay control instruction parsing module (37) is connected to the control instruction sending module (11) and the multi-channel coordinated nanosecond delay and synchronization algorithm module (38) respectively; the synchronization and delay control instruction parsing module (37) parses the instruction transmitted by the control instruction sending module (11) and transmits the parsed instruction to the multi-channel coordinated nanosecond delay and synchronization algorithm module (38); The multi-channel coordinated nanosecond delay and synchronization algorithm module (38) is respectively connected to the synchronization and delay control instruction parsing module (37), the synchronization signal generating module (39) and the test video output module (5); the multi-channel coordinated nanosecond delay and synchronization algorithm module (38) controls the accuracy and range of the relative delay of the two-way video output by the test video output module (5), and controls the synchronization signal generating module (39); The synchronization signal generation module (39) is respectively connected to the DDR4 dynamic interleaving access module (36) and the multi-channel coordinated nanosecond delay and synchronization algorithm module (38); the synchronization signal generation module (39) generates a synchronization signal to control the time when the DDR4 dynamic interleaving access module (36) accesses video data.

4. The video signal generator according to claim 1, characterized in that: The real-time video source input module (4) includes a first image sensor (41) and a second image sensor (42); the first image sensor (41) and the second image sensor (42) realize real-time dual-view video acquisition; the first image sensor (41) and the second image sensor (42) are respectively connected to the real-time video source data receiving module (33) to transmit the real-time acquired video data to the real-time video source data receiving module (33).

5. The video signal generator according to claim 1, characterized in that: The test video output module (5) comprises a first video timing recovery module (51), a first video output GSV2011 chip (52), a first video output interface (53), a second video timing recovery module (54), a second video output GSV2011 chip (55) and a second video output interface (56); the first video timing recovery module (51) is connected to the first video output GSV2011 chip (52) and the DDR4 dynamic interleaving access module (36) respectively; the first video timing recovery module (51) is capable of recovering 4K@30Hz HDMI video timing; The second video timing recovery module (54) is connected to the second video output GSV2011 chip (55) and the DDR4 dynamic interleaving access module (36) respectively; the second video timing recovery module (54) is capable of recovering 2560×1600@30Hz HDMI video timing; The first video output GSV2011 chip (52) is connected to the first video timing recovery module (51) and the first video output interface (53) respectively; the first video output GSV2011 chip (52) encodes the video data and the video timing into an HDMI format and outputs the encoded data to the first video output interface (53); The second video output GSV2011 chip (55) is connected to the second video timing recovery module (54) and the second video output interface (56) respectively; the second video output GSV2011 chip (55) encodes the video data and the video timing into an HDMI format and outputs the encoded data to the second video output interface (56).

6. The video signal generator according to claim 1, wherein: The first image sensor (41) and the second image sensor (42) adopt AR1337 ultra-high-definition CMOS image sensors.

7. The video signal generator according to claim 1, characterized in that The test video output module (5) supports video output at 4K@30HZ resolution and non-standard resolution 2560×1600@30Hz.

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