System and method for testing reliability of transistor with nanosecond magnitude delay

Abstract

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

Description

Technical Field

[0001] The present invention belongs to the field of transistor testing, and specifically relates to a transistor reliability testing system and method with nanosecond-level delay. The system and method can realize the switching characteristics and dynamic on-resistance testing of the transistor with nanosecond-level delay under any drain voltage stress value, drain voltage stress duration, and load current. Background Art

[0002] The double-pulse circuit can be used to study the hard-switching characteristics of transistors subjected to drain voltage stress and load current simultaneously. The double-pulse circuit test method applies two consecutive pulses to the gate of the transistor under test, causing the transistor under test to switch on and off twice in succession. When the transistor is turned on, the high-voltage power supply charges the load inductor. When the transistor is turned off, the current in the load inductor flows through the diode and gradually discharges. Controlling the first turn-on duration of the transistor under test can accurately control the current at the end of the first power inductor charging. The first turn-on duration of the transistor under test is generally 2 to 10 microseconds. The transistor under test is then turned off for about 1 to 3 microseconds and then turned on again. When the transistor under test is turned on for the second time, it is simultaneously subjected to the switching of a large drain voltage and drain current, which is a hard switching process. Studying the transient process of the transistor under test when it is turned on for the second time and the on-resistance when it is turned on for the second time can analyze its degradation after drain voltage stress.

[0003] Traditional dual-pulse circuits cannot control the drain voltage stress time of transistors, and switching from the drain voltage stress state to the measurement state after the drain voltage stress ends generally involves a long measurement delay. The delay time includes the time it takes to first turn on the transistor under test (generally 2 to 10 microseconds) and the time it takes to first turn off the transistor and for the inductor current to flow through the Schottky diode (generally 1 to 3 microseconds). According to relevant literature reports, for example, Kailun Zhong published a paper titled "Integrated Circuits for the Measurement of CMOS and CMOS Devices" on pages 8387-8395 in the IEEE Transactions on Industrial Electronics in August 2022. I G - and V GS -DependentDynamic R ONA paper titled "Characterization of Commercial High-Voltage p-GaN Gate Power HEMTs" and a paper titled "Review of Pulse Test Setup for the SwitchingCharacterization of GaN Power Devices" published by Guangze Zu in the IEEE TRANSACTIONS ON ELECTRON DEVICES journal on pages 3003-3013 in June 2022 point out that for new transistors made of certain new materials (gallium nitride, silicon carbide, gallium oxide, etc.), drain voltage stress can cause internal defects in the transistor to capture carriers, threshold voltage drift, and on-resistance degradation; after the drain voltage stress is removed, the internal defects of the transistor gradually release carriers. Depending on the type of defect, the time constant for the defect to release carriers ranges from microseconds to milliseconds to seconds. For defects with microsecond time constants, a measurement delay of several microseconds (for example, 3 to 13 microseconds) will lead to inaccurate measurement results, making it impossible to display the true state of the transistor after drain voltage stress in real time. Obviously, the data measured by the traditional double-pulse circuit cannot reflect the instantaneous switching characteristics and on-resistance of the transistor under test after drain voltage stress. Summary of the Invention

[0004] The present invention aims to provide a transistor reliability testing system and method with nanosecond-scale measurement delay after drain voltage stress. This testing system, based on a conventional dual-pulse circuit, addresses the long delay (typically 3 to 13 microseconds) between the end of drain voltage stress and the start of transistor turn-on transient and on-resistance measurement in conventional dual-pulse testing circuits. This system and method can measure transistor switching transients and on-resistance under any given drain voltage stress value, drain voltage stress duration, or load current, while maintaining nanosecond-scale measurement delay.

[0005] The system of the present invention is divided into three modules, each of which only requires one external input pulse signal. The test system has its own internal logic processing function, and can convert one pulse signal into two pulse signals containing dead time through a hardware circuit (which is more secure), and the dead time can be flexibly adjusted. The transistor reliability test system includes two circuit structures: the power module of the first circuit structure includes five NMOS power transistors, which has the advantage that only one NMOS process is involved when integrating the power circuit. The power module of the second structure includes five NMOS power transistors and two PMOS transistors. The advantage is that it does not require an isolated gate drive chip and an isolated power supply, and can be more conveniently integrated into a power chip. The corresponding circuit structure can be flexibly selected according to actual needs.

[0006] In order to achieve the above objectives, the specific technical solutions adopted are as follows: The first aspect of the present invention provides a nanosecond-level delay transistor reliability testing system, comprising a voltage stress value and stress duration control module, a current control module, and a hard switching transient and on-resistance testing module, wherein the voltage stress value and stress duration control module, the current control module, and the hard switching transient and on-resistance testing module each comprise a logic circuit and a power circuit. Among them, the voltage stress value and stress duration control module is used to control the drain voltage stress value and drain voltage stress duration of the transistor under test; the current control module is used to control the current size during the hard switching test of the transistor under test; the hard switching transient and on-resistance test module is used to control the on-time of the transistor under test after hard switching.

[0007] Furthermore, the logic circuit part of the voltage stress value and stress duration control module of the present invention includes NMOS transistors, resistors, capacitors, Schottky diodes, and gate drive chips; the power circuit part of the voltage stress value and stress duration control module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and voltage regulator diodes; the logic circuit converts an input pulse signal into two inverted pulse signals with "dead time", and inputs the two pulse signals into the power circuit; the power circuit controls the conduction of the module's half-bridge circuit based on the two pulse signals, and thereby controls the midpoint voltage of the bridge arm.

[0008] Furthermore, the logic circuit part of the current control module of the present invention includes a gate drive chip; the power circuit part of the current control module includes an NMOS power transistor, a Schottky diode, and a power inductor; the logic circuit converts an input pulse signal into a pulse signal with "capability to output transient large current" and inputs the pulse signal into the power circuit; the power circuit controls the conduction status of the NMOS power transistor based on the pulse signal, thereby controlling the current of the power inductor.

[0009] Furthermore, the logic circuit part of the hard switching transient and on-resistance test module of the present invention includes NMOS transistors, resistors, capacitors, Schottky diodes, and gate drive chips; the power circuit part of the hard switching transient and on-resistance test module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and voltage-stabilizing diodes; the logic circuit converts an input pulse signal into two inverted pulse signals with "dead time", and inputs the two pulse signals into the power circuit; the power circuit controls the conduction of the module's half-bridge circuit based on the two pulse signals, thereby controlling whether the transistor to be tested is turned on and the drain connection position of the transistor to be tested.

[0010] Furthermore, the logic circuit part of the voltage stress value and stress duration control module includes an NMOS transistor Q A3 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A3 Gate connection V A0 Terminal, NMOS transistor Q A3 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection; resistance R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A3 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 terminal; resistor R One end of 3 is connected V A0 Terminal, resistor R The other end of the resistor 3 is connected ROne end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D 5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND1, gate driver chip U A2 The output terminal OUT and the ground terminal GND2 are V GA2 Duanhe V SA2 end; The power circuit part of the voltage stress value and stress duration control module includes NMOS power transistors Q A1 and Q A2 ; Among them, NMOS power transistor Q A2 The source of the NMOS power transistor Q A1 The drain is connected to form a common terminal with V SA2 Connection, NMOS power transistor Q A2 Drain connection V DD terminal, its gate is connected V GA2 , NMOS power transistor Q A1 The source is grounded and the gate is connected V GA1 .

[0011] Furthermore, the logic circuit part of the current control module includes a gate drive chip U B1 ;Gate driver chip U B1 The input terminal IN is connected V B0 , the output terminal OUT is V GB0 end; The power circuit part of the current control module includes NMOS power transistors Q B0 , Schottky diodeD 1 and D 2. Power inductor L ; Among them, NMOS transistor Q B0 The drain and power inductor L One end of the Schottky diode D 1 and D 2 anode common connection terminal is connected, the power inductor L The other end of the Schottky diode D 1 cathode and voltage stress value and stress duration control module NMOS transistor Q A1 The drain of the NMOS transistor Q A2 The source and V SA2 The common connection terminal of the NMOS transistor is connected; Q B0 The source and voltage stress value and stress duration control module NMOS transistor Q A1 The source of the NMOS transistor is connected; Q B0 Gate connection V GB0 end.

[0012] Furthermore, the logic circuit part of the hard switch transient and on-resistance test module includes an NMOS transistor Q C3 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C3 Gate connection V C0 Terminal, NMOS transistor Q C3 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection; resistance R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitorC The other end of 3 is connected to the NMOS transistor Q C3 Source and gate driver chips U C2 The ground terminal GND1, gate driver chip U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The ground terminal GND2 is V SC2 terminal; resistor R Connect one end of 7 V C0 Terminal, resistor R The other end of the resistor 7 is connected R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1 The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor C The other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end; The power circuit part of the hard switching transient and on-resistance test module includes NMOS power transistors Q C1 and Q C2 ; Among them, NMOS transistor Q C2 The source of the NMOS transistor Q C1 The drain of the current control module forms a common terminal with the Schottky diode D 2 cathodes are connected and V SC2 Connection; NMOS transistor Q C2 The drain and the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module QA1 The drain of the NMOS transistor Q A2 The source, V SA2 The common connection terminal of the NMOS transistor is connected; Q C2 Gate connection V GC2 ;NMOS power transistor Q C1 The source of the NMOS transistor in the current control module is connected Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS power transistor Q C1 Gate connection V GC1 ; The NMOS transistor Q B0 The source of the NMOS transistor Q C1 The source terminal of the NMOS transistor is commonly connected to the Q C2 The source of the NMOS transistor Q C1 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0013] Furthermore, the power circuit portion of the voltage stress value and stress duration control module of the present invention further includes a PMOS transistor Q A3 , power resistor R 9 and R 10 , Zener diode D 3; Among them, NMOS transistor Q A1 The source of the NMOS transistor Q A2 The common terminal of the NMOS transistor is grounded after the source is connected. Q A2 The drain and resistance R Connect one end of 9 to the resistor R The other end of 9 is connected to the voltage stabilizing diode D 3 anode and resistor R 10 one end and with the PMOS transistor Q A3 The gate of the PMOS transistor is connected to QA3 The drain of the NMOS transistor Q A1 The drain of the voltage regulator diode is connected to D 3 cathode and resistor R 10 The other end of the PMOS transistor Q A3 The source is connected to V DD ; The logic circuit part of the voltage stress value and stress duration control module includes NMOS transistors Q A4 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A4 Gate connection V A0 Terminal, NMOS transistor Q A4 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection; resistance R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A4 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 terminal; resistor R One end of 3 is connected V A0 Terminal, resistor R The other end of 3 is connected to the resistor R One end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND, gate driver chip U A2 The output terminal OUT is V GA2 end.

[0014] Furthermore, the logic circuit part of the current control module includes a gate drive chip U B1 ;Gate driver chip U B1 The input terminal IN is connected V B0 , the output terminal OUT is V GB0 end; The power circuit part of the current control module includes NMOS power transistors Q B0 , Schottky diode D 1 and D 2. Power inductor L ; Among them, NMOS transistor Q B0 The drain and power inductor L One end of the Schottky diode D 1 and D 2 anodes are connected to the common connection terminal, as a further embodiment, the power inductor of the present invention L The other end of the Schottky diode D 1 cathode and voltage stress value and stress duration control module PMOS transistor Q A3 The drain of the NMOS transistor Q A1 The drain of the NMOS transistor is connected; Q B0 The source and voltage stress value and stress duration control module NMOS transistor Q A1 The source of the NMOS transistor Q A2 The source of the NMOS transistor is connected; Q B0 Gate connection V GB0end.

[0015] Furthermore, the power circuit portion of the hard switch transient and on-resistance test module of the present invention also includes a PMOS transistor Q C3 , power resistor R 11 and R 12 , Zener diode D 4; Among them, NMOS transistor Q C1 The source of the NMOS transistor Q C2 The common terminal after the source is connected to the NMOS transistor in the current control module Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS transistor Q A2 The source of the NMOS transistor is connected; Q C2 The drain and resistance R 12 Connect one end of the resistor R 12 The other end of the voltage regulator diode is connected D 4 anode and resistor R 11 one end and with the PMOS transistor Q C3 The gate of the PMOS transistor is connected to Q C3 The drain of the NMOS transistor Q C1 The drain of the current control module is connected to the common connection terminal and the Schottky diode D 2 cathodes connected; Zener diode D 4 cathode and resistor R 11 The other end of the PMOS transistor Q C3 The source is connected to the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module Q A1 The drain of the PMOS transistor Q A3 The common connection terminal of the drain is connected; the NMOS transistor Q B0The source of the NMOS transistor Q C1 The common connection terminal and the NMOS transistor Q C1 The drain of the PMOS transistor Q C3 Drain and Schottky diode D 2. A clamping circuit is provided between the common connection terminals of the cathodes; The logic circuit part of the hard switching transient and on-resistance test module includes NMOS transistors Q C4 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C4 Gate connection V C0 Terminal, NMOS transistor Q C4 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection; resistance R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitor C The other end of 3 is connected to the NMOS transistor Q C4 Source and gate driver chips U C2 The ground terminal GND, gate driver chip U C2 The output terminal OUT is V GC2 terminal; resistor R Connect one end of 7 V C0 Terminal, resistor R The other end of 7 is connected to the resistor R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor C The other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0016] The second aspect of the present invention provides a method for testing transistor reliability with nanosecond-level delay, which is implemented by the system provided by the first aspect of the present invention and includes the following steps: 1) Determine the drain voltage stress duration of the transistor under test and thereby determine the pulse width of pulse 1; 2) Determine the current value of the transistor to be tested, and thereby determine the pulse width of pulse 2; 3) Then, the duration of the on-state of the transistor under test is determined, and the pulse width of pulse 3 is determined accordingly; 4) Then determine the drain voltage stress value of the transistor to be tested, and thus determine the required parameters of the high-voltage power supply; 5) Set the high voltage power supply parameters; then input pulse 1, pulse 2, and pulse 3 into the logic circuit; 6) The logic circuit will generate 5 pulse signals, and the 5 pulse signals include adjustable dead time; 7) 5 pulse signals drive 5 transistors through the gate drive module; 8) Improve test accuracy through clamping circuit; 9) Obtain the voltage and current parameters of the transistor to be tested through an oscilloscope; 10) Obtain the switching transient characteristics and conduction characteristics of the transistor to be tested from the voltage and current parameters; 11) Finally, the reliability parameters of the transistor under test are obtained under nanosecond delay.

[0017] The beneficial effects of the present invention are: 1. The present invention can test the transistor switching transient and on-resistance at any drain voltage stress value, drain voltage stress duration, and load current of the transistor under test under the premise of measuring delay at the nanosecond level.

[0018] 2. The present invention is divided into three modules, each module only needs to input one pulse signal. The test system has its own logic processing function, which can convert one pulse signal into two pulse signals containing dead time through hardware circuit (higher safety), and the dead time can be flexibly adjusted.

[0019] 3. This transistor reliability test system proposes two circuit structures. The power module of the first circuit structure contains five NMOS power transistors. The advantage is that only one NMOS process is involved when integrating the power circuit. The disadvantage is that the NMOS on the upper tube in the half-bridge structure requires an isolated gate driver chip and an isolated power supply for isolated drive. The power module of the second structure contains five NMOS power transistors and two PMOS transistors. The advantage is that no isolated gate driver chip and isolated power supply are required, and it can be more conveniently integrated into a power chip. The disadvantage is that it involves two transistor preparation processes, NMOS and PMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The invention will be better understood from the following description, which relates to a preferred embodiment given by way of non-limiting example and explained with reference to the accompanying schematic drawings, in which: Figure 1 The circuit block diagram of the transistor reliability test system with nanosecond-level delay of the present invention is shown.

[0021] Figure 2 The diagram is a circuit diagram of a transistor reliability test system with an NMOS structure according to an embodiment of the present invention.

[0022] Figure 3 It is a circuit principle diagram of a transistor reliability testing system with a CMOS structure according to another embodiment of the present invention.

[0023] Figure 4 This is a flow chart of the transistor reliability testing system with nanosecond-level delay of the present invention.

[0024] Figure 5 This is a circuit embodiment of the transistor reliability testing system of the CMOS structure of the present invention.

[0025] Figure 6 This invention Figure 5 The logic signal of the "voltage stress value and stress duration control module" in the circuit embodiment.

[0026] Figure 7 This invention Figure 5 Logic signal of the “current control module” in the circuit embodiment.

[0027] Figure 8 This invention Figure 5 Logic signal of the “hard switching transient and on-resistance test module” in the circuit embodiment.

[0028] Figure 9 This invention Figure 5 Power signal of the “hard switching transient and on-resistance test module” in the circuit embodiment. DETAILED DESCRIPTION

[0029] The present invention will be described in further detail below with reference to the accompanying drawings. The specific embodiments described herein are only intended to explain the present invention, but are not intended to limit the present invention.

[0030] The present invention relates to a transistor reliability testing system with nanosecond-level delay, which can test the transistor characteristics of a transistor under test at any drain voltage stress value, drain voltage stress duration, and load current under the premise of measuring the delay at the nanosecond level.

[0031] Figure 1 This is a circuit block diagram of a transistor reliability test system with nanosecond delays. It consists of five parts: experimental setup, external input, logic circuit, power circuit, and external monitoring. First, in the experimental setup, the drain voltage stress value, drain voltage stress duration, load current value, and on-time of the transistor under test are designed according to experimental requirements. Next, three pulse signals are designed based on these "drain voltage stress duration, load current value, and on-time of the transistor under test." These three pulse signals are then input into the logic circuit, which converts them into five pulse signals with dead time. These five pulse signals are then input into the gate driver chip in the power circuit, which drives the power transistor. A drain clamp module is also added to the power circuit to improve the test accuracy of the drain voltage of the transistor under test. Finally, external monitoring is performed using test instruments such as an oscilloscope to obtain key information such as the gate drive voltage, drain voltage, and drain-source current of the transistor under test.

[0032] Figure 2 This is a circuit diagram of a transistor reliability test system of an NMOS structure according to an embodiment of the present invention. Figure 2 As shown in the figure, the circuit functions can be divided into three parts: voltage stress value and stress duration control module, current control module, hard switching transient and on-resistance test module. Each module consists of two parts: logic circuit and power circuit.

[0033] Specifically, in this embodiment, the logic circuit portion of the voltage stress value and stress duration control module includes an NMOS transistor Q A3 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A3 Gate connection V A0Terminal, NMOS transistor Q A3 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection. Resistor R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A3 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 Terminal. Resistor R One end of 3 is connected V A0 Terminal, resistor R The other end of 3 is connected to the resistor R One end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D 5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND1, gate driver chip U A2 The output terminal OUT and the ground terminal GND2 are V GA2 Duanhe V SA2 end.

[0034] The power circuit part of the voltage stress value and stress duration control module includes NMOS power transistors Q A1 and Q A2 Among them, NMOS power transistor Q A2 The source of the NMOS power transistor Q A1The drain is connected to form a common terminal with V SA2 Connection, NMOS power transistor Q A2 Drain connection V DD terminal, its gate is connected V GA2 , NMOS power transistor Q A1 The source is grounded and the gate is connected V GA1 .

[0035] In this embodiment, the logic circuit part of the current control module includes a gate drive chip U B1 ;Gate driver chip U B1 The input terminal IN is connected V B0 , the output terminal OUT is V GB0 end.

[0036] The power circuit part of the current control module includes NMOS power transistors Q B0 , Schottky diode D 1 and D 2. Power inductor L Among them, NMOS transistor Q B0 The drain and power inductor L One end of the Schottky diode D 1 and D 2 anode common connection terminal is connected, the power inductor L The other end of the Schottky diode D 1 cathode and voltage stress value and stress duration control module NMOS transistor Q A1 The drain of the NMOS transistor Q A2 The source and V SA2 The common connection terminal of the NMOS transistor is connected; Q B0 The source and voltage stress value and stress duration control module NMOS transistor Q A1 The source of the NMOS transistor is connected; Q B0 Gate connection V GB0 end.

[0037] In this embodiment, the logic circuit part of the hard switching transient and on-resistance test module includes an NMOS transistor Q C3 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C3 Gate connection V C0 Terminal, NMOS transistor Q C3 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection. Resistor R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitor C The other end of 3 is connected to the NMOS transistor Q C3 Source and gate driver chips U C2 The ground terminal GND1, gate driver chip U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The ground terminal GND2 is V SC2 Terminal. Resistor R Connect one end of 7 V C0 Terminal, resistor R The other end of 7 is connected to the resistor R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1 The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor CThe other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0038] The power circuit part of the hard switching transient and on-resistance test module includes NMOS power transistors Q C1 and Q C2 Among them, NMOS transistor Q C2 The source of the NMOS transistor Q C1 The drain of the current control module forms a common terminal with the Schottky diode D 2 cathodes are connected and V SC2 Connection; NMOS transistor Q C2 The drain and the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module Q A1 The drain of the NMOS transistor Q A2 The source, V SA2 The common connection terminal of the NMOS transistor is connected. Q C2 Gate connection V GC2 . NMOS power transistor Q C1 The source of the NMOS transistor in the current control module is connected Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS power transistor Q C1 Gate connection V GC1 The NMOS transistor Q B0 The source of the NMOS transistor Q C1 The source terminal of the NMOS transistor is commonly connected to the Q C2 The source of the NMOS transistor QC1 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0039] The circuit's operating principle in this embodiment is that the logic circuit converts the voltage of an externally input pulse signal to a voltage suitable for driving power transistors and providing a certain load capacity (high output current). The logic circuit also performs logic conversion to generate a complementary pulse signal with a dead time, which is then input into the power transistors in the power circuit via the gate driver chip.

[0040] Taking the logic circuit in the voltage stress value and stress duration control module as an example, there is no pulse signal input in the initial state, and the test point V A1 High level, test point V A2 When the transistor Q A3 Gate input pulse signal V A0 When the transistor Q A3 conduction, capacitance C 1 through the resistor R 2 Start discharging, V A1 The voltage at the point gradually decreases; at the same time, the pulse signal V A0 Through the resistor R 3 and resistors R 4 is the capacitor C 2Charging, capacitor C Voltage at 2 V A2 Gradually increases. When the transistor Q A3 Gate pulse signal V A0 At the end, the transistor Q A3 Shutdown, power V CC Through the resistor R 1 and resistor R 2 is the capacitor C 1. Charging, V A1 The voltage at the capacitor gradually increases; at the same time C 2 through the diode D 5 and resistor R 3 discharge, capacitor C Voltage at 2 V A2The charging and discharging time constants of the RC circuit mentioned above all satisfy T=R×C, which quantifies the time required for the capacitor to charge or discharge to 63.2% of its final voltage value. C Voltage at 1 V A1 and capacitors C Voltage at 2 V A2 Connect the primary side of the gate driver chip respectively. V A1 and voltage V A2 Reach the gate driver chip U A1 and U A2 When the flip threshold is reached, the gate driver chip switches between on and off states. The logic circuits of other modules are similar to the above analysis and will not be repeated here.

[0041] The power circuit parts of the three modules are analyzed below.

[0042] For the voltage stress value and stress duration control module, the upper tube of the half-bridge structure Q A2 and down tube Q A1 Alternate conduction. Q A1 When the upper tube is turned on Q A2 Turn off, at this time the bridge arm midpoint voltage V SA2 0V, there is no high voltage input to the subsequent circuit. Q A1 When shutting down, the upper tube Q A2 The bridge arm midpoint voltage is V SA2 The supply voltage of the high voltage power supply V DD , the back stage circuit has high voltage input. Q A2 The conduction time can control the subsequent circuit to withstand high voltage V DD duration.

[0043] For the current control module, when the transistor Q B0 When conducting, the power inductor L The potential difference between the two ends V DD , flows through the power inductor L The current gradually increases, satisfying the formula L×di / dt= V DD When the transistor Q B0 When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change suddenly, the power inductor L Through the Schottky diode connected in parallel D 1 for freewheeling, so the Schottky diode D 1 Also known as a freewheeling diode. Schottky diode D 2Used to connect power inductor L Low-side port and transistor under test Q C1 Drain. Due to the Schottky diode D 2 unidirectional conductivity, when the Schottky diode D 2 When the anode potential is low, it is in the cut-off state and will not cause the Schottky diode to D 2 cathode (transistor under test Q C1 Drain) potential is pulled low to ensure the power inductor L During the first charge, the Schottky diode D 2 cathode (transistor under test Q C1 Drain) still bears high voltage V DD voltage stress.

[0044] For the hard switching transient and on-resistance test module, the power circuit part includes two transistors in a half-bridge structure. Q C2 , the lower tube is the transistor to be tested Q C1 . Under the current management Q C1 When shutting down, the upper tube Q C2 conduction, making the lower tube Q C1 The drain of the Q C2 Withstand stable high voltage V DD . Under the current management Q C1 When opening, Q C2 It will shut down in advance, making the lower tube Q C1 The drain is connected to the Schottky diode of the current control module D 2 cathode. Lower tube Q C1 When turned on, the power inductor LActs as an inductive load in the circuit. Power inductor L The potential difference between the two ends V DD , flows through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When the transistor Q C1 When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change suddenly, the power inductor L Through the Schottky diode connected in parallel D 1 for continuous current. Test the transistor under test Q C1 The gate voltage, drain voltage, and drain-source current of the transistor under test can be known. Q C1 Switch transient characteristics and on-resistance characteristics during hard switching test. Clamp circuit is used to improve the transistor under test. Q C1 The test accuracy of the drain voltage will not be described here.

[0045] Figure 3 This is a circuit diagram of a transistor reliability test system of a CMOS structure according to another embodiment of the present invention. Figure 2 The circuit shown has been improved, mainly optimizing the voltage stress value and stress duration control module and the hard switching transient and on-resistance test module.

[0046] Specifically, in this embodiment, the power circuit part of the voltage stress value and stress duration control module further includes a PMOS transistor Q A3 , power resistor R 9 and R 10 , Zener diode D 3. Among them, NMOS transistor Q A1 The source of the NMOS transistor Q A2 The common terminal of the NMOS transistor is grounded after the source is connected. Q A2 The drain and resistance R Connect one end of 9 to the resistor R The other end of 9 is connected to the voltage stabilizing diode D 3 anode and resistor R 10 one end and with the PMOS transistor Q A3 The gate of the PMOS transistor is connected toQ A3 The drain of the NMOS transistor Q A1 The drain of the voltage regulator diode is connected to D 3 cathode and resistor R 10 The other end of the PMOS transistor Q A3 The source is connected to V DD .

[0047] Furthermore, based on the power circuit of the voltage stress value and stress duration control module, the logic circuit part of the voltage stress value and stress duration control module of the present invention includes an NMOS transistor Q A4 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A4 Gate connection V A0 Terminal, NMOS transistor Q A4 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection; resistance R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A4 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 end.

[0048] resistance R One end of 3 is connected V A0 Terminal, resistor R The other end of the resistor 3R One end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D 5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND, gate driver chip U A2 The output terminal OUT is V GA2 end.

[0049] In this embodiment, the logic circuit part of the current control module includes a gate drive chip U B1 ;Gate driver chip U B1 The input terminal IN is connected V B0 , the output terminal OUT is V GB0 end.

[0050] The power circuit part of the current control module includes NMOS power transistors Q B0 , Schottky diode D 1 and D 2. Power inductor L Among them, NMOS transistor Q B0 The drain and power inductor L One end of the Schottky diode D 1 and D 2 anode common connection terminal is connected, the power inductor L The other end of the Schottky diode D 1 cathode and voltage stress value and stress duration control module PMOS transistor Q A3 The drain of the NMOS transistor Q A1 The drain of the NMOS transistor is connected; Q B0 The source and voltage stress value and stress duration control module NMOS transistor Q A1 The source of the NMOS transistor QA2 The source of the NMOS transistor is connected; Q B0 Gate connection V GB0 end.

[0051] In this embodiment, the power circuit part of the hard switching transient and on-resistance test module also includes a PMOS transistor Q C3 , power resistor R 11 and R 12 , Zener diode D 4. Among them, NMOS transistor Q C1 The source of the NMOS transistor Q C2 The common terminal after the source is connected to the NMOS transistor in the current control module Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS transistor Q A2 The source of the NMOS transistor is connected; Q C2 The drain and resistance R 12 Connect one end of the resistor R 12 The other end of the voltage regulator diode is connected D 4 anode and resistor R 11 one end and with the PMOS transistor Q C3 The gate of the PMOS transistor is connected to Q C3 The drain of the NMOS transistor Q C1 The drain of the current control module is connected to the common connection terminal and the Schottky diode D 2 cathodes connected; Zener diode D 4 cathode and resistor R 11 The other end of the PMOS transistor Q C3 The source is connected to the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module Q A1The drain of the PMOS transistor Q A3 The common connection terminal of the drain is connected; the NMOS transistor Q B0 The source of the NMOS transistor Q C1 The common connection terminal and the NMOS transistor Q C1 The drain of the PMOS transistor Q C3 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0052] Furthermore, based on the power circuit of the hard switching transient and on-resistance test module, the logic circuit part of the hard switching transient and on-resistance test module of the present invention includes an NMOS transistor Q C4 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C4 Gate connection V C0 Terminal, NMOS transistor Q C4 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection. Resistor R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitor C The other end of 3 is connected to the NMOS transistor Q C4 Source and gate driver chips U C2 The ground terminal GND, gate driver chip U C2 The output terminal OUT is V GC2 end.

[0053] resistance R Connect one end of 7 VC0 Terminal, resistor R The other end of 7 is connected to the resistor R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1 The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor C The other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0054] In this embodiment, the upper tube in the half-bridge structure is modified from an NMOS transistor to a PMOS transistor. At this time, the source of the PMOS transistor does not change with the opening or closing of the lower tube, but is stable at the power supply voltage. V DD Therefore, there's no need for an isolated driver to drive the upper tube of the half-bridge structure, eliminating the need for an isolated driver chip and an isolated power supply module (an isolated power supply module typically includes a transformer consisting of an inductor coil, and large inductors are difficult to integrate within the chip). This simplifies circuit design, saves chip and PCB area, and facilitates subsequent integration of the entire circuit into a single chip.

[0055] For the voltage stress value and stress duration control module, the upper tube of the half-bridge structure Q A3 and down tube Q A1 Alternate conduction. Q A1 When the upper tube is turned on Q A3 When the bridge arm midpoint voltage is 0V, there is no high voltage input to the subsequent circuit. Q A1 When shutting down, the upper tube Q A3 The bridge arm midpoint voltage is the supply voltage of the high voltage power supply. V DD , the back stage circuit has high voltage input. Q A3 The conduction time can control the subsequent circuit to withstand high voltage V DDBy controlling the transistor Q A2 The on and off of the upper tube can indirectly control Q A3 When the transistor is turned on and off Q A2 When conducting, the power resistance R 9. Power resistor R 10 and Zener diodes D 3 constitutes a voltage divider circuit. By controlling the power resistor R 9. Power resistor R 10 and Zener diodes D 3 values ​​can make the PMOS transistor Q A3 The gate-source voltage of the transistor is just its turn-on voltage. Q A2 PMOS transistor when turned off Q A3 The gate-source voltage of the PMOS transistor is 0 volts. Q A3 Shut down.

[0056] For the hard switching transient and on-resistance test modules, the control principle is similar to that of the voltage stress value and stress duration control module and will not be described in detail here.

[0057] Figure 4 This is a flow chart of the transistor reliability testing system with nanosecond-level delay of the present invention.

[0058] In the experimental preset stage, the drain voltage stress duration of the transistor to be tested is first determined, and the pulse width of pulse 1 is determined accordingly; then the current value of the transistor to be tested is determined, and the pulse width of pulse 2 is determined accordingly; then the turn-on duration of the transistor to be tested is determined, and the pulse width of pulse 3 is determined accordingly; then the drain voltage stress value of the transistor to be tested is determined, and the parameters required for the high-voltage power supply are determined accordingly.

[0059] During the test phase, the high-voltage power supply parameters are first set. Pulse 1, Pulse 2, and Pulse 3 are then input into the logic circuit. The logic circuit then generates five pulse signals with adjustable dead time. These five pulse signals then drive five transistors through the gate drive module. The test system also includes a clamping circuit to improve test accuracy.

[0060] During the data analysis phase, the voltage and current parameters of the transistor under test can be obtained through an oscilloscope. The voltage and current parameters can be used to determine the switching transient characteristics and conduction characteristics (on-resistance) of the transistor under test. Finally, the reliability parameters of the transistor under test under nanosecond delay can be obtained through summary and collation.

[0061] Figure 5 This is a circuit embodiment of the transistor reliability testing system of the CMOS structure of the present invention. Figure 5 Circuit structure and Figure 3 The circuit structure is consistent. Figure 5 Specific marking Figure 3 The parameters of each component in the circuit shown will not be described here one by one.

[0062] Figure 6 This invention Figure 5 The logic signal of the "voltage stress value and stress duration control module" in the circuit embodiment. V A0 It is an external input pulse signal; V A1 for V A0 The inverted pulse signal can realize the functions of fast shutdown and slow conduction by controlling the component parameters of the RC module in the logic circuit; V A2 for V A0 The same-phase pulse signal realizes the functions of fast shutdown and slow conduction by controlling the component parameters of the RC module in the logic circuit. V GA1 for V A1 The pulse signal output after the gate driver chip has a threshold voltage for turning on and off. V A1 After reaching the threshold voltage, V GA1 Start level flipping. V GA2 for V A2 The pulse signal output after the gate driver chip has a threshold voltage for turning on and off. V A2 After reaching the threshold voltage, V GA2 Start level flipping. V GSA3 The gate-source voltage of the PMOS transistor is negative, and the PMOS transistor is turned on when the voltage is negative, and turned off when the voltage is 0 volts. Q A2 When turned on, the PMOS transistor Q A3 Synchronous turn on; when the NMOS transistor Q A2 When turned off, the PMOS transistor Q A3 Synchronous shutdown. As shown in the figure, the transistor Q A1 Shutdown (V GA1 drop) and transistors Q A2 Open ( V GA2 Rising) is not at the same time, T 1 and T The time difference between the two is the dead time, which is determined by V A2 The rising edge time determines the transistor Q A2 Shutdown ( V GA2 drop) and transistors Q A1 Open ( V GA1 Rising) is not at the same time, T 9 and T 10 The time difference between the two is the dead time, which is determined by V A1 The rising edge time determines

[0063] Figure 7 This invention Figure 5 Logic signal of the “current control module” in the circuit embodiment. V B0 It is an external input pulse signal; V GB0 for V B0 The pulse signal after passing through the gate driver chip can output a larger drive current and has the ability to carry a load, which can better drive the subsequent transistors. The logic circuit of this module does not involve complementary pulse signals or dead time.

[0064] Figure 8 This invention Figure 5 Logic signal of the “hard switching transient and on-resistance test module” in the circuit embodiment. V C0 It is an external input pulse signal; V C1 for V C0 The same-phase pulse signal can realize the functions of fast shutdown and slow conduction by controlling the component parameters of the RC module in the logic circuit; V C2 for V A0 The inverted pulse signal realizes the functions of fast shutdown and slow conduction by controlling the component parameters of the RC module in the logic circuit. V GC1 for VC1 The pulse signal output after the gate driver chip has a threshold voltage for turning on and off. V C1 After reaching the threshold voltage, V GC1 Start level flipping. V GC2 for V C2 The pulse signal output after the gate driver chip has a threshold voltage for turning on and off. V C2 After reaching the threshold voltage, V GC2 Start level flipping. V GSC3 The gate-source voltage of the PMOS transistor is turned on when the voltage is negative and turned off when it is 0 volts. T 2 time arrives T 9 The following relationship is satisfied between the moments: When the NMOS transistor Q C2 When turned on, the PMOS transistor Q C3 Synchronous turn on; when the NMOS transistor Q C2 When turned off, the PMOS transistor Q C3 Synchronous shutdown. As shown in the figure, the transistor Q C2 Shutdown ( V GC2 drop) and transistors Q C1 Open ( V GC1 Rising) is not at the same time, T 5 and T 6 The time difference between the two is the dead time, which is determined by V C1 The rising edge time determines the transistor Q C1 Shutdown ( V GC1 drop) and transistors Q C2 Open ( V GC2 Rising) is not at the same time, T 7 and T 8 The time difference between the two is the dead time, which is determined by V C2 The rising edge time determines

[0065] Figure 9 This invention Figure 5Power signal of the “hard switching transient and on-resistance test module” in the circuit embodiment. V DA1 Represents a transistor Q A1 The drain voltage; V DC1 Indicates the transistor under test Q C1 The drain voltage; I L Indicates power inductance L Current; R ON Indicates the measured transistor Q C1 on-resistance. V DA1 exist T 2 time arrives T 9 is high level, indicating that the transistor Q A1 The drain and subsequent circuit modules are subjected to high voltage stress. V DC1 exist T 2 time arrives T 6 is high level, indicating that the transistor Q C1 The drain is subjected to high voltage stress, T 2 time arrives T The time between the 6 moments can be flexibly adjusted according to experimental needs, ranging from a few microseconds to several hours. T 6 o'clock T 7 times between the transistor under test Q C1 The transistor under test is turned on. Q C1 Drain voltage V DC1 is low level, the value is Q C1 The on-resistance multiplied by the drain-source current. I L Indicates power inductance L The current is I L exist T 3 to T 4 between and T 6 to T 7, respectively, because the transistor Q B0 and transistors Q C1 The high voltage is turned on V DDThrough the transistor to the power inductor L Charge. R ON Indicates the measured transistor Q C1 The on-resistance of the transistor under test is Q C1 The drain voltage of the transistor under test Q C1 The drain-source current ( Q C1 The drain-source current is equal to T 6 to T 7 The current of the power inductor between I L ) divided by

[0066] It will be easily understood by those skilled in the art that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A transistor reliability test system with nanosecond delay, characterized in that: It includes a voltage stress value and stress duration control module, a current control module, a hard switch transient and on-resistance test module, and the voltage stress value and stress duration control module, the current control module, the hard switch transient and on-resistance test module each include a logic circuit and a power circuit; Among them, the voltage stress value and stress duration control module is used to control the drain voltage stress value and drain voltage stress duration of the transistor under test; the current control module is used to control the current size during the hard switching test of the transistor under test; the hard switching transient and on-resistance test module is used to control the on-time of the transistor under test after hard switching.

2. The transistor reliability testing system with nanosecond delay according to claim 1, characterized in that: The logic circuit part of the voltage stress value and stress duration control module includes NMOS transistors, resistors, capacitors, Schottky diodes, and gate drive chips; the power circuit part of the voltage stress value and stress duration control module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and voltage-stabilizing diodes; the logic circuit converts an input pulse signal into two inverted pulse signals with "dead time" and inputs the two pulse signals into the power circuit; the power circuit controls the conduction of the module's half-bridge circuit based on the two pulse signals, thereby controlling the midpoint voltage of the bridge arm.

3. The transistor reliability testing system with nanosecond delay according to claim 1, characterized in that: The logic circuit portion of the current control module includes a gate driver chip; the power circuit portion of the current control module includes an NMOS power transistor, a Schottky diode, and a power inductor; the logic circuit converts an input pulse signal into a pulse signal "capable of outputting transient large currents" and inputs the pulse signal into the power circuit; the power circuit controls the conduction of the NMOS power transistor based on the pulse signal, thereby controlling the current of the power inductor.

4. The transistor reliability testing system with nanosecond delay according to claim 1, characterized in that: The logic circuit portion of the hard-switching transient and on-resistance test module includes NMOS transistors, resistors, capacitors, Schottky diodes, and gate driver chips; the power circuit portion of the hard-switching transient and on-resistance test module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and Zener diodes; the logic circuit converts an input pulse signal into two inverted pulse signals with "dead time" and inputs the two pulse signals into the power circuit; the power circuit controls the conduction of the module's half-bridge circuit based on the two pulse signals, thereby controlling whether the transistor under test is conductive and the drain connection position of the transistor under test.

5. The transistor reliability testing system with nanosecond delay according to claim 1 or 2, characterized in that: The logic circuit part of the voltage stress value and stress duration control module includes NMOS transistors Q A3 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A3 Gate connection V A0 Terminal, NMOS transistor Q A3 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection; resistance R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A3 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 terminal; resistor R One end of 3 is connected V A0 Terminal, resistor R The other end of 3 is connected to the resistor R One end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D 5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND1, gate driver chip U A2 The output terminal OUT and the ground terminal GND2 are V GA2 Duanhe V SA2 end; The power circuit part of the voltage stress value and stress duration control module includes NMOS power transistors Q A1 and Q A2 ; Among them, NMOS power transistor Q A2 The source of the NMOS power transistor Q A1 The drain is connected to form a common terminal with V SA2 Connection, NMOS power transistor Q A2 Drain connection V DD terminal, its gate is connected V GA2 , NMOS power transistor Q A1 The source is grounded and the gate is connected V GA1 .

6. The transistor reliability testing system with nanosecond delay according to claim 1 or 3, characterized in that: The logic circuit part of the current control module includes the gate drive chip U B1 ;Gate driver chip U B1 The input terminal IN is connected V B0 , the output terminal OUT is V GB0 end; The power circuit part of the current control module includes NMOS power transistors Q B0 , Schottky diode D 1 and D 2. Power inductor L ; Among them, NMOS transistor Q B0 The drain and power inductor L One end of the Schottky diode D 1 and D 2 anode common connection terminal is connected, the power inductor L The other end of the Schottky diode D 1 cathode and voltage stress value and stress duration control module NMOS transistor Q A1 The drain of the NMOS transistor Q A2 The source and V SA2 The common connection terminal of the NMOS transistor is connected; Q B0 The source and voltage stress value and stress duration control module NMOS transistor Q A1 The source of the NMOS transistor is connected; Q B0 Gate connection V GB0 end.

7. The transistor reliability testing system with nanosecond delay according to claim 1 or 4, characterized in that: The logic circuit part of the hard switching transient and on-resistance test module includes NMOS transistors Q C3 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C3 Gate connection V C0 Terminal, NMOS transistor Q C3 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection; resistance R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitor C The other end of 3 is connected to the NMOS transistor Q C3 Source and gate driver chips U C2 The ground terminal GND1, gate driver chip U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The ground terminal GND2 is V SC2 terminal; resistor R Connect one end of 7 V C0 Terminal, resistor R The other end of 7 is connected to the resistor R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1 The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor C The other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end; The power circuit part of the hard switching transient and on-resistance test module includes NMOS power transistors Q C1 and Q C2 ; Among them, NMOS transistor Q C2 The source of the NMOS transistor Q C1 The drain of the current control module forms a common terminal with the Schottky diode D 2 cathodes are connected and V SC2 Connection; NMOS transistor Q C2 The drain and the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module Q A1 The drain of the NMOS transistor Q A2 The source, V SA2 The common connection terminal of the NMOS transistor is connected; Q C2 Gate connection V GC2 ;NMOS power transistor Q C1 The source of the NMOS transistor in the current control module is connected Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS power transistor Q C1 Gate connection V GC1 ; The NMOS transistor Q B0 The source of the NMOS transistor Q C1 The source terminal of the NMOS transistor is commonly connected to the Q C2 The source of the NMOS transistor Q C1 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

8. The transistor reliability testing system with nanosecond delay according to claim 1 or 2, characterized in that: The power circuit part of the voltage stress value and stress duration control module also includes a PMOS transistor Q A3 , power resistor R 9 and R 10 , Zener diode D 3; Among them, NMOS transistor Q A1 The source of the NMOS transistor Q A2 The common terminal of the NMOS transistor is grounded after the source is connected. Q A2 The drain and resistance R Connect one end of 9 to the resistor R The other end of 9 is connected to the voltage stabilizing diode D 3 anode and resistor R 10 one end and with the PMOS transistor Q A3 The gate of the PMOS transistor is connected to Q A3 The drain of the NMOS transistor Q A1 The drain of the voltage regulator diode is connected to D 3 cathode and resistor R 10 The other end of the PMOS transistor Q A3 The source is connected to V DD ; The logic circuit part of the voltage stress value and stress duration control module includes NMOS transistors Q A4 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 ; Among them, NMOS transistor Q A4 Gate connection V A0 Terminal, NMOS transistor Q A4 Drain connection resistance R 1 and R One end of 2, resistor R The other end of 1 and V CC Connection; resistance R The other end of 2 is connected to the capacitor C One end of 1 and the gate driver chip U A1 Input terminal IN, capacitor C The other end of 1 is connected to the NMOS transistor Q A4 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 terminal; resistor R One end of 3 is connected V A0 Terminal, resistor R The other end of 3 is connected to the resistor R One end of 4, resistor R The other end of 4 is connected to the capacitor C One end of 2 and Schottky diode D 5 anode, and with the gate driver chip U A2 The input terminal IN is connected to the Schottky diode D 5 Cathode connection resistance R 3 and resistors R 4 common connection terminal; capacitor C The other end of 2 is connected to the gate driver chip U A2 The ground terminal GND, gate driver chip U A2 The output terminal OUT is V GA2 end.

9. The transistor reliability testing system with nanosecond delay according to claim 1 or 4, characterized in that: The power circuit part of the hard switching transient and on-resistance test module also includes PMOS transistors Q C3 , power resistor R 11 and R 12 , Zener diode D 4; Among them, NMOS transistor Q C1 The source of the NMOS transistor Q C2 The common terminal after the source is connected to the NMOS transistor in the current control module Q B0 The source and the NMOS transistor of the voltage stress value and stress duration control module Q A1 The source of the NMOS transistor Q A2 The source of the NMOS transistor is connected; Q C2 The drain and resistance R 12 Connect one end of the resistor R 12 The other end of the voltage regulator diode is connected D 4 anode and resistor R 11 one end and with the PMOS transistor Q C3 The gate of the PMOS transistor is connected to Q C3 The drain of the NMOS transistor Q C1 The drain of the current control module is connected to the common connection terminal and the Schottky diode D 2 cathodes connected; Zener diode D 4 cathode and resistor R 11 The other end of the PMOS transistor Q C3 The source is connected to the Schottky diode of the current control module D 1 cathode, power inductor L , and NMOS transistors of the voltage stress value and stress duration control module Q A1 The drain of the PMOS transistor Q A3 The common connection terminal of the drain is connected; the NMOS transistor Q B0 The source of the NMOS transistor Q C1 The common connection terminal and the NMOS transistor Q C1 The drain of the PMOS transistor Q C3 Drain and Schottky diode D 2. A clamping circuit is provided between the common connection terminals of the cathodes; The logic circuit part of the hard switching transient and on-resistance test module includes NMOS transistors Q C4 ,resistance R 5- R 8. Capacitor C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 ; Among them, NMOS transistor Q C4 Gate connection V C0 Terminal, NMOS transistor Q C4 Drain connection resistance R 5 and R One end of 6, resistor R The other end of 5 V CC Connection; resistance R The other end of 6 is connected to the capacitor C One end of 3 and the gate driver chip U C2 Input terminal IN, capacitor C The other end of 3 is connected to the NMOS transistor Q C4 Source and gate driver chips U C2 The ground terminal GND, gate driver chip U C2 The output terminal OUT is V GC2 terminal; resistor R Connect one end of 7 V C0 Terminal, resistor R The other end of 7 is connected to the resistor R One end of 8, resistor R The other end of 8 is connected to the capacitor C One end of 4 and Schottky diode D 6 anodes, and with the gate driver chip U C1 The input terminal IN is connected to the Schottky diode D 6 cathode connection resistor R 7 and resistor R Common connection terminal of 8; capacitor C The other end of 4 is connected to the gate driver chip U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

10. A transistor reliability testing method with nanosecond delay, implemented by the system according to any one of claims 1 to 9, characterized in that: The following steps are involved: 1) Determine the drain voltage stress duration of the transistor under test and thereby determine the pulse width of pulse 1; 2) Determine the current value of the transistor to be tested, and thereby determine the pulse width of pulse 2; 3) Then, the duration of the on-state of the transistor under test is determined, and the pulse width of pulse 3 is determined accordingly; 4) Then determine the drain voltage stress value of the transistor to be tested, and thus determine the required parameters of the high-voltage power supply; 5) Set the high voltage power supply parameters; Then pulse 1, pulse 2, and pulse 3 are input into the logic circuit; 6) The logic circuit will generate 5 pulse signals, and the 5 pulse signals include adjustable dead time; 7) 5 pulse signals drive 5 transistors through the gate drive module; 8) Improve test accuracy through clamping circuit; 9) Obtain the voltage and current parameters of the transistor to be tested through an oscilloscope; 10) Obtain the switching transient characteristics and conduction characteristics of the transistor to be tested from the voltage and current parameters; 11) Finally, the reliability parameters of the transistor under test are obtained under nanosecond delay.

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