Boundary scan test structure and method

Abstract

The invention discloses a boundary scan test structure which is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a test main control and data backhaul JTAG (Joint Test Action Group) channel. According to the invention, a plurality of return JTAG wires in a traditional boundary scan test structure are canceled, and connectors, wire harnesses and EMI fault points can be reduced, so that the breakage rate of a production line is remarkably reduced, and the test reliability can be improved. According to the invention, only one JTAG line is needed on hardware, and the Dummy Card does not need an additional JTAG interface, so that the wiring complexity and the material cost are reduced. When the slot signals are independent, a plurality of slots can be tested in parallel, the test time of the whole board is shortened, and the test efficiency can be improved. The method can be implemented for any CPU with boundary scanning capability and FPGA logic conforming to IEEE 1581, is suitable for production lines of various high-reliability board cards such as server mainboards and backboards, and is high in universality.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a boundary scan test structure and method. Background Art

[0002] Boundary scan testing was developed in the 1990s. With the advent of large-scale integrated circuits (LSIs), printed circuit board (PCB) manufacturing processes evolved towards smaller, thinner, and more compact designs. Traditional ICT testing could no longer meet the testing requirements of these products. Due to the large number of chip pins, the small size of components, and the extremely high density of boards, probing was impossible. This led to the emergence of a new testing technology, defined by the Joint Test Action Group (JTAG), as boundary scan testing. Boundary scan is a collection of design rules applied at the IC level that allows software to reduce the ever-increasing costs of designing, producing, and testing digital systems.

[0003] Traditional boundary scan testing primarily tests the interconnections between integrated circuit chips. Using built-in commands specified by the IEEE 1149.1 / 1149.6 protocols, it puts the ICs in the boundary scan chain into boundary scan mode. By controlling the input / output states of the IC pins, it tests for open and short circuit faults in the interconnections between the chips. Boundary scan testing can quickly and accurately verify the reliability of connections between multiple chip pins, improving test efficiency. Due to its short test times and high reliability, boundary scan testing has gained widespread adoption in the consumer electronics and semiconductor sectors.

[0004] When producing and testing circuit boards with high reliability requirements (such as server motherboards), it is necessary to perform boundary scan testing on the plug-in interconnection characteristics of all connector slots on the motherboard under test. A typical test system is as follows: Figure 1 As shown in the figure, the "test platform main control unit" sends a boundary scan test pattern to the CPU unit on the "tested motherboard" through the "test pattern output JTAG" channel, causing the specified test vector levels to be generated on the pins of "Slot 1...Slot N" under test. The "test platform main control unit" then uses the "test data return JTAG" channel to allow the "dummy cards" inserted in each slot to capture the voltage levels received on each pin of the slot and transmit these captured measurement results back to the "test platform main control unit". The "test platform main control unit" can then compare the sent test pattern with the received return test voltage values ​​to determine whether the interconnect characteristics of each pin of each slot on the tested motherboard have passed the test.

[0005] A drawback of existing boundary scan testing technology is that, when the motherboard under test has a large number of slots, multiple JTAG cables are required to transmit test data. In complex production environments, these multiple JTAG cables are prone to unreliable contact and unstable operation due to electromagnetic interference, significantly reducing the reliability of the entire test system and leading to serious consequences such as frequent disconnections on the production line.

[0006] Dummy Card: Also known as Dummy Load or Dummy Board, it is a testing tool that simulates a real chip or load.

[0007] Dummy Card FPGA: Simulates and verifies the onboard FPGA.

[0008] IEEE Standard 1581-2011, "IEEE Standard for Static ComponentInterconnection Test Protocol and Architecture", IEEE Computer Society, 20June2011. Summary of the Invention

[0009] The Summary of the Invention introduces a series of simplified concepts, which are simplifications of existing technologies in the field and are further described in detail in the Detailed Description of the Invention. The Summary of the Invention is not intended to define the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0010] The technical problem to be solved by the present invention is to provide a boundary scan test structure that can simplify the lines between the main control unit of the test platform and the motherboard under test and the dummy card, especially save data return lines, and improve the reliability and anti-interference in complex production test environments.

[0011] To solve the above technical problems, the present invention provides a boundary scan test structure, which is used for circuit board card interface interconnection testing. The test platform main control unit and the tested motherboard only interact with each other through the test main control and data return JTAG channel.

[0012] Furthermore, the data interaction is based on the IEEE 1581 protocol.

[0013] To solve the above technical problems, the present invention provides a boundary scan test method, which is implemented based on the boundary scan test structure and includes the following steps:

[0014] S1, the test platform main control unit generates a test signal to trigger the Dummy Card FPGA to enter the test mode;

[0015] S2, executing the basic test control channel signal interconnection test selected in the tested slot;

[0016] S3, perform interconnection test of all remaining output signals (Dummy Card to tested mainboard) in the tested slot;

[0017] S4, performing interconnection testing of all remaining input signals in the tested slot (from the tested mainboard to the dummy card);

[0018] S5, and so on to test each slot until all slots are tested.

[0019] The "test mode control" signal lines selected for each motherboard slot are also part of the interconnect test. When selected for test mode control, it's crucial to ensure that interconnect test coverage isn't compromised. To ensure this, the interconnect characteristics of the test mode control signals themselves are verified.

[0020] Preferably, a further improvement is provided in that the boundary scan test method, when implementing step S2, includes reporting a test mode control signal interconnection error if the test signal level capture results read under all test pattern level combination conditions are erroneous and the erroneous patterns are consistent with each other, and no subsequent tests on the tested slot will be performed.

[0021] Preferably, in the boundary scan test method, if the input and output signal lines on different slots do not intersect, the interconnection tests of the various slots are performed in parallel.

[0022] The working principle of the present invention is described as follows:

[0023] This invention reuses the IEEE 1581 static interconnect test protocol, porting the 1581 protocol, originally used for storage device interconnects, to board interface testing. This establishes a "minimum reliable channel"—the basic test control channel—through which subsequent test commands are issued. This ensures that all data (command issuance and result transmission) enters and exits the CPU's boundary scan chain, eliminating the need for dedicated return cables from the dummy card to the main control unit.

[0024] The present invention can achieve at least the following technical effects:

[0025] 1. The present invention eliminates the multi-path return JTAG lines in the traditional boundary scan test structure, which can reduce connectors, wiring harnesses and EMI failure points, thereby significantly reducing the line break rate of the production line and improving test reliability.

[0026] 2. The present invention only requires one JTAG line in hardware, and the Dummy Card does not need an additional JTAG interface, reducing wiring complexity and material costs.

[0027] 3. When the slot signals are independent, the present invention can test multiple slots in parallel, shortening the entire board test time and improving test efficiency.

[0028] 4. The present invention can be implemented on any CPU with boundary scan capability and FPGA logic that complies with IEEE 1581. It is applicable to various high-reliability board production lines such as server motherboards and backplanes, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain exemplary embodiments of the present invention, supplementing the descriptions in the specification. However, the drawings herein are schematic diagrams not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment. The drawings herein should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0030] Figure 1 This is a schematic diagram of the existing boundary scan test structure.

[0031] Figure 2 It is a schematic diagram of the boundary scan test structure of the present invention.

[0032] Figure 3 This is a schematic diagram of the test control and data return architecture of the tested slot.

[0033] Figure 4 It is a schematic flow chart of the present invention.

[0034] Figure 5 This is the IEEE 1581 test logic diagram. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can fully understand the other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features therein can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same figure numbers always represent the same elements.

[0036] First embodiment;

[0037] refer to Figure 2 Combine Figure 3 As shown, the present invention provides a boundary scan test structure, which is used for circuit board card interface interconnection testing. The test platform main control unit and the tested motherboard only interact with each other through the test main control and data return JTAG channel. That is, the present invention eliminates the need for Figure 1 Multiple return JTAG lines in a traditional boundary scan test structure as shown in ;

[0038] The data interaction is based on the IEEE 1581 protocol.

[0039] When the above-mentioned boundary scan test structure is applied, one signal line is allocated on each interface of the mainboard under test for controlling entry into the test mode, and Mi signal lines entering the Dummy Card FPGA and Mo signal lines output from the Dummy Card FPGA (Mi>=4, Mo>=4) are allocated for basic test control channels; in the Dummy Card FPGA, the above-mentioned Mi signal lines are connected to the input ends of "test function selection" and "test function 1"; the output end of "test function 1" is connected to the above-mentioned Mo output signals; "test function 2" has no input signal under test, and the output end of "test function 2" is connected to all output signals on the interface under test except Mo signal lines; the input end of "test function 3" is connected to all input signals on the interface under test except Mi signal lines, and the output end of "test function 3" is connected to all output signals of the interface under test; the input end of "test mode control" is connected to the test mode control signal line of the interface under test.

[0040] Second embodiment;

[0041] refer to Figure 4 As shown, the present invention provides a boundary scan test method, which is implemented based on the above boundary scan test structure and includes the following steps:

[0042] S1, the test platform main control unit generates a test signal to trigger the Dummy Card FPGA to enter the test mode. The test signal is a specific or specified level signal, and the corresponding "test mode control" module in the Dummy Card FPGA selects the default "test function 1";

[0043] S2, executing the basic test control channel signal interconnection test selected in the tested slot;

[0044] The test platform main control unit tests the interconnection characteristics of the basic test control channel signal lines in accordance with the provisions of the IEEE 1581 static component interconnection test protocol: multiple test pattern level combinations are sequentially generated on the Mi input signal lines, and the test result level combinations are sequentially captured on the Mo output signal lines; if the expected test results and the captured test results are inconsistent, the interconnection error of the basic test control channel signal is located and reported, and the process proceeds to step S5; otherwise, the process proceeds to the next step;

[0045] If the test signal level capture results read under all test pattern level combination conditions are erroneous and the erroneous patterns are consistent with each other, a test mode control signal interconnection error is reported and subsequent tests on this tested slot are not performed;

[0046] If the test result bit returned contains an error, locate and report the interconnection error;

[0047] S3: Perform an interconnection test on all remaining output signals in the tested slot (from the Dummy Card to the tested motherboard). The Dummy Card generates a test pattern on the remaining output signals in the tested slot to confirm the interconnection characteristics of these output signals. If the returned test result bit contains an error, the interconnection error is located and reported.

[0048] The test platform main control unit generates multiple "test function 2" selection commands on the Mi signal lines of the basic test control channel signal through the JTAG channel, so that the "test function 2" module in the Dummy Card FPGA sequentially generates multiple test pattern level combinations on all output signal lines except the Mo output signal lines. The test platform main control unit sequentially captures the test result level combinations of these signals through the JTAG channel. If the expected test result and the captured test result are inconsistent, the interconnection error of these output signal lines is located and reported, and the process proceeds to step S5; otherwise, the process proceeds to the next step;

[0049] S4, performs interconnection testing of all remaining input signals in the tested slot (from the tested motherboard to the dummy card); the tested motherboard CPU generates a test pattern on the remaining input signals in the tested slot, and the dummy card captures the input level and feeds back the level capture result on the output signal; if the returned test result bit contains an error, the interconnection error is located and reported;

[0050] The test platform main control unit generates one or more "test function 3" selection commands on the Mi signal lines of the basic test control channel signal through the JTAG channel, so that the "test function 3" module in the Dummy Card FPGA captures the level values ​​on all input signal lines except the Mi input signal lines, and reflects these level values ​​on the output signal lines. The test platform main control unit captures the test result level combination on the output signal line through the JTAG channel. If the expected test result is inconsistent with the captured test result, the interconnection error of these input signal lines is located and reported;

[0051] S5, and so on to test each slot until all slots are tested.

[0052] As a further improvement to the second embodiment, if the input and output signal lines on different slots do not intersect, the interconnection tests of the various slots are executed in parallel.

[0053] The present invention will be further illustrated below using a typical test system configuration as an example. Assume that a tested slot in the system under test has a total of 200 interface signals, of which 160 signals can be tested as IO interconnect signals, and 40 signals can only be input to the Dummy Card as fixed-level signals. Of the 160 IO interconnect signals, one is selected for use as a "test mode control" signal, 30 are used as "basic test control channels," and the remaining 129 IO interconnect signals are used as test objects for "test function 2," or test pattern generation. The 40 signals that can only be input to the Dummy Card as fixed-level signals are used as test objects for "test function 3," or input level capture and capture result transmission.

[0054] refer to Figure 5 As shown, a preferred implementation of the IEEE 1581 test logic on the basic test control channel is given for the above test system. In the figure, K=3, that is, the basic test control channel has Mi=6K=18 input signals and Mo=4K=12 output signals.

[0055] The specific test process is described as follows: When the test platform main control unit tests the tested slot, it first controls the boundary scan chain of the tested motherboard CPU to output a low level (preferably) on the "test mode control" signal line. Under the action of this low level, the Dummy Card FPGA enters the test mode and selects "test function 1" by default. Figure 5The IEEE 1581 test logic is shown. At this point, the test platform main control unit further generates test patterns one by one on the input signal of the basic test control channel (preferred test pattern sequences are an all-0 sequence, an all-1 sequence, a zero sequence where each offset position in the all-1 sequence is changed to 0 one by one, and a one sequence where each offset position in the all-0 sequence is changed to 1 one by one). It then captures the test result level combination on the output signal of the basic test control channel and compares it with the expected result level combination to determine whether there is a problem with the interconnection characteristics of the basic test control channel and which signal is problematic. If the test result is OK, it means that the interconnection characteristics of the "test mode control" signal and the "basic test control channel" signal are both normal. At this time, the test platform main control unit further sends the "test function 2" command on the basic test control channel, and controls the generation of multiple test patterns on the 129 output signals through the parameters carried by the command (the preferred test pattern sequence is an all-0 sequence, an all-1 sequence, a 0 sequence in which each offset position on the all-1 sequence becomes 0 one by one, and a 1 sequence in which each offset position on the all-0 sequence becomes 1 one by one). The test platform main control unit captures the test result level combination generated by each test pattern in the scan chain of the CPU of the motherboard under test, and compares it with the expected result level combination, so as to determine whether there is a problem with the interconnection characteristics of the 129 output signals and which signal has a problem. If the test results are positive, the test platform's main control unit then issues a "Test Function 3" command on the basic test control channel, capturing the levels of 40 input signals and outputting these levels in parallel to the motherboard's CPU on the first 40 I / O interconnects. Within the motherboard's CPU scan chain, the test platform's main control unit captures the 40 fixed input signal test result combinations forwarded by the Dummy Card and compares them with the expected result combinations, thereby determining whether any of the 40 input signal interconnect characteristics are faulty and which signal is at fault. Following this test sequence, the test platform's main control unit can complete interconnect testing for all slots on the motherboard, one by one.

[0056] Table 1 below further illustrates a preferred test function selection command set for the aforementioned test. This command set is sent via the input signal of the basic test control channel. The resulting output is then transmitted back to the boundary scan unit of the MCU on the motherboard under test via the output signal of the basic test control channel and other output signals.

[0057] Appendix 1: Test function selection command set of an embodiment of the invention;

[0058]

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, rather than being interpreted in an idealized or overly formal sense.

[0060] The present invention has been described in detail above by way of specific embodiments and examples, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered within the scope of protection of the present invention.

Claims

1. A boundary scan test structure for testing circuit board card interfaces, characterized in that: The test platform main control unit and the motherboard under test only exchange data through the test main control and data return JTAG channel.

2. The boundary scan test structure according to claim 1, wherein: The data interaction is based on the IEEE 1581 protocol.

3. A boundary scan test method, which is implemented based on the boundary scan test structure according to claim 1 or 2, characterized in that: The following steps are involved: S1, the test platform main control unit generates a test signal to trigger the Dummy Card FPGA to enter the test mode; S2, executing the basic test control channel signal interconnection test selected in the tested slot; S3, performing interconnection testing of all remaining output signals in the tested slot; S4, performing interconnection testing of all remaining input signals in the tested slot; S5, and so on to test each slot until all slots are tested.

4. The boundary scan test method according to claim 3, wherein: The implementation of step S2 includes: If the test signal level capture results read under all test pattern level combination conditions are erroneous and the erroneous patterns are consistent with each other, a test mode control signal interconnection error is reported and subsequent tests on the tested slot are no longer performed.

5. The boundary scan test method according to claim 1, wherein: If the input and output signal lines on different slots do not intersect, the interconnection tests of each slot are executed in parallel.

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