Method and equipment for predicting etching structure of semiconductor device, and storage medium

Abstract

The invention discloses a semiconductor device etching structure prediction method and equipment, and a storage medium. The method comprises the following steps: acquiring three-dimensional etching evolution simulation data of a semiconductor structure to be etched under different etching process conditions; extracting a two-dimensional section image from the three-dimensional etching evolution simulation data; generating an etching morphology evolution sequence under high time resolution based on the two-dimensional cross section image; and obtaining an etched target contour image of the semiconductor structure according to the etching morphology evolution sequence under the high time resolution. Constructing a contour prediction model based on deep learning, and training the contour prediction model by using the data set; the input of the contour prediction model based on deep learning comprises etching process conditions and an initial contour image of the semiconductor structure before etching, and the output of the contour prediction model based on deep learning is a predicted contour image after etching evolving along with etching time. According to the method, physical modeling and a data driving method are combined, high-precision prediction and intelligent optimization control of the etching process are achieved, and the process stability and the product yield are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a semiconductor device etching structure prediction method and equipment, and a storage medium, which are applied to etching process optimization in the wafer manufacturing process. Background Art

[0002] As semiconductor devices continue to advance toward miniaturization, high performance, and complexity, precise control of the etching process, a key step in microelectronics manufacturing, is crucial. Currently, as device dimensions shrink to the nanometer scale, small variations in the etching process can lead to significant differences in device performance, or even cause device failure. With the continuous evolution of process nodes, from the traditional 0.18 μm and 0.13 μm to 16 nm, 7 nm, and even 5 nm, acceptable morphological deviations during etching are becoming increasingly smaller. As integrated circuit feature sizes continue to shrink, traditional prediction methods that rely on manual experience, static parameters, or simple data-driven approaches are increasingly unable to meet the stringent etching accuracy and real-time performance requirements of advanced process nodes. Currently, existing technologies still suffer from the following shortcomings: First, purely physical modeling methods have high computational complexity, making real-time control difficult to achieve. Second, purely data-driven methods rely on extensive experimental data and lack guidance from physical mechanisms, resulting in low prediction accuracy when faced with complex structures or novel process conditions.

[0003] Therefore, there is an urgent need for a hybrid modeling strategy that can combine physical models and data-driven methods, and realize predictive control of the etching process based on this model to improve the accuracy, reliability and efficiency of the etching process. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems existing in the prior art and provide a method and equipment for predicting the etching structure of semiconductor devices, as well as a storage medium. By combining physical modeling based on dynamic Monte Carlo and a data-driven method based on deep learning, high-precision prediction and real-time control of the etching process can be achieved.

[0005] In order to achieve the above objectives, in a first aspect, the present invention provides a semiconductor etching process prediction method, the method comprising: Acquire three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions; the three-dimensional etching evolution simulation data includes three-dimensional contour images of the semiconductor structure at different etching time points during the etching process; Extracting a two-dimensional cross-sectional image from three-dimensional etching evolution simulation data; the two-dimensional cross-sectional image includes a plurality of longitudinal cross-sectional images and a plurality of transverse cross-sectional images; generating an etching morphology evolution sequence at a high temporal resolution based on the two-dimensional cross-sectional image; obtaining a target contour image of the semiconductor structure after etching from the etching morphology evolution sequence at a high temporal resolution; The data set is composed of an initial contour image of the semiconductor structure before etching and a corresponding target contour image after etching; A deep learning-based contour prediction model is constructed and trained using a data set. The input of the deep learning-based contour prediction model includes etching process conditions and an initial contour image of the semiconductor structure before etching, and the output is a predicted contour image after etching that evolves with etching time.

[0006] The etching process conditions and the initial contour image of the semiconductor structure before etching are input into the trained deep learning-based contour prediction model to obtain the predicted contour image of the semiconductor structure after etching.

[0007] Preferably, the process of obtaining the three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions includes: Establish a three-dimensional lattice model and discretize the surface of the semiconductor structure into a three-dimensional lattice structure; Constructing a surface reaction event library; the surface reaction event library includes multiple surface reaction events of different etching processes, each surface reaction event is adsorption, desorption, migration or ion bombardment; Defining the probability equation and reaction rate of each surface reaction event, where the reaction rate is related to the etching process conditions; A kinetic Monte Carlo algorithm is used to iteratively simulate the etching process of the current semiconductor structure, randomly select and execute the next surface reaction event according to the reaction rate, and simultaneously update the state of the three-dimensional semiconductor structure; Record the 3D contour image of the semiconductor structure at the current stage at the preset etching time point to form a 3D etching evolution simulation data set; By changing the etching process conditions, the three-dimensional lattice model is re-established, and finally a three-dimensional etching evolution simulation data set covering a variety of etching process conditions is generated.

[0008] More preferably, updating the state of the three-dimensional semiconductor structure includes: updating the material type of the etched lattice site, and recalculating the local environmental parameters of the adjacent lattice sites affected by the current surface reaction event and the probability of future surface reaction events.

[0009] Preferably, the process of extracting a two-dimensional cross-sectional image from three-dimensional etching evolution simulation data includes: Extract multiple longitudinal cross-sectional images along the key feature area or the transverse coordinates at fixed intervals; extract multiple transverse cross-sectional images at different depths along the key feature area or the preset area; convert the extracted longitudinal cross-sectional images and transverse cross-sectional images into binary images or grayscale images.

[0010] More preferably, the key feature areas include the center line of the groove, the edge of the groove, the central axis of the high aspect ratio hole, and the interface between different material layers.

[0011] Preferably, the process of generating the etching morphology evolution sequence at high time resolution based on the two-dimensional cross-sectional image includes: Obtaining a sequence of two-dimensional cross-sectional images at different etching time points and extracting contour evolution features from the sequence; the contour evolution features are a set of time series parameters used to quantitatively describe the contour morphology; Based on the contour evolution characteristics, a two-dimensional cross-sectional image representing the contour morphology at the intermediate moment is generated as the intermediate contour; Introducing physical constraint-based smoothing to ensure that the generated intermediate contours conform to the laws of physical evolution; Extract multi-scale features of contour evolution for intermediate contours; Based on the multi-scale characteristics of profile evolution, an etching morphology evolution sequence with high temporal resolution is generated.

[0012] Preferably, the method further comprises: Perform defect detection on the predicted contour image of the semiconductor structure after etching to identify the potential defect types and severity in the predicted semiconductor structure after etching; Based on the predicted contour image after etching and the type and severity of potential defects, the etching process conditions of the current semiconductor structure are adjusted to achieve closed-loop optimization.

[0013] More preferably, the process of performing defect detection on the predicted contour image of the semiconductor structure after etching and identifying the potential defect types and severity in the predicted semiconductor structure after etching includes: Establish a defect type library; Extract key geometric features from the predicted contour image after etching of semiconductor structures; Build a defect recognition classifier to determine the potential defect type based on the extracted key geometric features; The severity of the potential defects is obtained based on the predicted profile image of the semiconductor structure after etching and the type of potential defects.

[0014] In a second aspect, the present invention provides an electronic device, comprising a memory, a processor, and an industrial interface, wherein a computer program is stored in the memory, and the method is executed when the program is run on the processor.

[0015] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program implements the method when executed by a processor.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1) This paper combines the physics-based KMC simulation with the data-driven deep learning method, giving full play to the advantages of both, ensuring the physical rationality of the model while improving the computational efficiency and adaptability.

[0017] 2) By constructing a high-time-resolution etching morphology evolution sequence, the present invention can capture the transient characteristics and subtle changes in the etching process, providing a new perspective for a deeper understanding of the etching mechanism.

[0018] 3) The present invention establishes a profile prediction model based on deep learning, which can quickly and accurately predict the etching results under different process parameters, greatly reducing the need for experimental verification and reducing development costs.

[0019] 4) The present invention can automatically identify potential etching defects and their locations, and provide early warning of possible quality problems.

[0020] 5) Based on the feedback mechanism of reinforcement learning or model predictive control strategy, the present invention realizes intelligent optimization and closed-loop control of the etching process, significantly improving process stability and product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is the overall flow chart of the intelligent prediction method for semiconductor device etching structure.

[0023] Figure 2 It is a physical modeling process based on Kinetic Monte Carlo (KMC).

[0024] Figure 3 Examples of two-dimensional cross-sectional images of semiconductor device structures, where (a) is a transverse cross-sectional image and (b) is a longitudinal cross-sectional image.

[0025] Figure 4 The simulated structure and two-dimensional cross-sectional image of a semiconductor device, where (a) is a schematic diagram of the three-dimensional simulation structure and (b) is a two-dimensional cross-sectional dimension marking diagram.

[0026] Figure 5 Generate a process flow chart for the etch topography evolution sequence.

[0027] Figure 6 Schematic diagram of timing prediction results for different structures.

[0028] Figure 7This is the architecture diagram of the deep learning prediction model based on the U-Net architecture.

[0029] Figure 8 This is the architecture diagram of the hierarchical perception deep learning prediction model. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] The terms "including," "having," and any variations thereof, as used in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0032] This embodiment provides a method for predicting semiconductor etching processes. The semiconductor structures described in this embodiment refer to the microscopic or nanoscale three-dimensional features formed on semiconductor wafers through processes such as photolithography and etching during integrated circuit manufacturing. These structures are the basic units that constitute devices such as transistors, capacitors, and interconnects. Specifically, these structures may include, but are not limited to, shallow trench isolation (STI) structures used for device isolation, transistor gate structures, fin structures in FinFETs, high-aspect-ratio storage holes in 3D NAND memories, and contact holes and through-hole structures used for conductive connections.

[0033] Specifically, see the attached Figure 1 , the semiconductor etching process prediction method includes: S1. Obtain three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions through a physical modeling module based on the Kinetic Monte Carlo (KMC) method; the three-dimensional etching evolution simulation data includes three-dimensional contour images of the semiconductor structure at different etching time points during the etching process.

[0034] S2. Extracting two-dimensional cross-sectional images from the three-dimensional etching evolution simulation data; the two-dimensional cross-sectional images include multiple longitudinal cross-sectional images and multiple transverse cross-sectional images; the extraction position of the cross-sectional images can be flexibly selected according to the structural characteristics to fully characterize the etching characteristics.

[0035] S3. Generate a high-temporal-resolution etch topography evolution sequence based on the two-dimensional cross-sectional image; and obtain a post-etch target contour image of the semiconductor structure from the high-temporal-resolution etch topography evolution sequence. This operation can generate continuous or more dense time series data from limited discrete time point data, thereby increasing data richness.

[0036] The data set is composed of an initial contour image of the semiconductor structure before etching and a corresponding target contour image after etching; S4. Build a deep learning-based contour prediction model and train it using the dataset; The deep learning-based profile prediction model takes as input the etching process conditions and an initial profile image of the semiconductor structure before etching. Its output is a predicted profile image after etching that evolves over time. The model can employ a variety of network structures and learning strategies, and is not limited to a specific architecture.

[0037] S5. Input the etching process conditions and the initial contour image of the semiconductor structure before etching into the trained deep learning-based contour prediction model to obtain the predicted contour image of the semiconductor structure after etching.

[0038] In one embodiment, the above method may further include: S6. performing defect detection on the predicted contour image of the semiconductor structure after etching to identify the type and severity of potential defects in the predicted semiconductor structure after etching; S7. A feedback mechanism based on reinforcement learning, model predictive control, or other optimization algorithms can be used to adjust the etching process conditions of the current semiconductor structure based on the predicted post-etch profile image and the type and severity of potential defects, achieving closed-loop optimization. The specific implementation of reinforcement learning, model predictive control, or other optimization algorithms can be flexibly selected based on the application scenario.

[0039] It should be noted that the execution order of the above steps can be adjusted according to actual needs, and there can also be interaction and iteration between the steps. The present invention is not limited to a fixed linear process.

[0040] One implementation method, such as Figure 2 As shown, step S1 specifically includes: S11. Establish a three-dimensional lattice model and discretize the surface of the semiconductor structure to be etched into a three-dimensional lattice structure; the lattice type can be selected according to the material properties, and the parameters can be set according to the actual material properties.

[0041] S12. Construct a surface reaction event library; the surface reaction event library includes multiple surface reaction events of different etching processes, each surface reaction event is a basic etching process such as adsorption, desorption, migration or ion bombardment; for different etching systems, corresponding surface reaction event sets can be defined, and the type and number of surface reaction events can be flexibly set according to the complexity of the etching chemistry.

[0042] S13. Define a probability equation and reaction rate for each surface reaction event, where the reaction rate is associated with the etching process conditions (temperature, gas flow rate, RF power, pressure, etc.). The relationship between the reaction rate and the etching process conditions can be a functional relationship based on physical and chemical principles or an empirical relationship based on experimental data fitting. The present invention is not limited to a specific functional form.

[0043] S14. A Kinetic Monte Carlo (KMC) algorithm is used to iteratively simulate the etching process of the current semiconductor structure. The next surface reaction event is randomly selected and executed based on the reaction rate, while simultaneously updating the state of the three-dimensional semiconductor structure. The iterative time step can be adaptively adjusted to balance computational efficiency and simulation accuracy.

[0044] Specifically, updating the state of the three-dimensional semiconductor structure includes: updating the material type of the etched lattice site (for example, changing from semiconductor material to vacuum), and recalculating the local environmental parameters of the adjacent lattice sites affected by the current surface reaction event and the probability of future surface reaction events.

[0045] S15. Record the 3D profile image of the semiconductor structure at the current etching stage at a preset etching time point to form a 3D etching evolution simulation dataset. The recording frequency can be flexibly set based on the complexity and rate of change of the etching process to capture key evolution characteristics.

[0046] S16. Repeat steps S11 to S15 by varying the etching process conditions to generate a 3D etching evolution simulation dataset covering a variety of etching process conditions. For example, the etching process parameters include temperature, gas flow rate, RF power, and pressure. Parameter selection can employ various experimental design methods to effectively cover the parameter space within a limited number of simulations.

[0047] It is understandable that the physical modeling method is not limited to Kinetic Monte Carlo (KMC), and various simulation methods such as molecular dynamics, Monte Carlo, continuum method or a combination thereof may also be used.

[0048] like Figure 2 As shown in , the implementation process of step S1 may also include a parameter optimization loop, which continuously adjusts the physical model parameters by comparing the model prediction with the experimental results to improve the model accuracy.

[0049] In one embodiment, step S2 specifically includes: Before executing step S2, a unified 3D Cartesian coordinate system is first established for the 3D etch evolution simulation data to be analyzed. In a preferred embodiment, the plane of the semiconductor wafer surface is defined as the XY plane, and the positive Z-axis is defined as the direction perpendicular to the wafer surface and pointing into the substrate. The Z-axis value represents the etch depth. The coordinate origin (0, 0, 0) can be set at the center of the pattern to be etched or at a specific corner. All 2D cross-section extractions are performed based on this coordinate system.

[0050] S21. Extract multiple longitudinal cross-sectional images along the key feature area or the transverse coordinates at fixed intervals; wherein the key feature area is a specific area selected to comprehensively characterize the non-uniformity of the etching morphology in three-dimensional space, including but not limited to: the center line of the groove, the edge of the groove, the center line of the high aspect ratio hole, and the interface between different material layers.

[0051] In one embodiment, the key feature areas include but are not limited to one or more of the following combinations: For groove or line array structures: Select the lines at the center of the array, the lines at the edge of the array, and the lines at the junction of dense and sparse areas as key features.

[0052] For a single structure (such as a groove or fin): Select the structure's geometric centerline, the structure's edge contour, and the structure's corners (such as the corners of an L-shaped or T-shaped structure) as key features.

[0053] For high aspect ratio hole structures: Select the center area of ​​the hole as the key feature.

[0054] For structures containing different materials: Select the interface area of ​​two or more materials as the key feature to analyze the etching selectivity.

[0055] Areas predicted based on physical effects: Areas predicted by preliminary physical analysis to be likely to experience significant loading effects, micro-loading effects, or changes in the critical dimension (CD) of the sidewall angle are selected as key features.

[0056] S22. Extract multiple transverse cross-sectional images at different depths along the key feature area or the preset area; S23. Convert the extracted longitudinal cross-sectional images and transverse cross-sectional images into binary images or grayscale images to facilitate subsequent morphological feature extraction.

[0057] As an example, for the same extraction area, the transverse cross-sectional image and the longitudinal cross-sectional image of the semiconductor device structure are as follows: Figure 3 Middle (a) - Figure 3 As shown in (b).

[0058] A lateral cross-sectional image observes the etched structure perpendicular to the wafer surface, showing the outline and distribution of the planar pattern. By comparing the top views before and after etching, the accuracy and consistency of pattern transfer can be assessed and changes in critical dimensions can be measured.

[0059] A longitudinal cross-sectional image slices the structure along a specific direction, showing a cross-section perpendicular to the cut surface. This image is used to evaluate key parameters such as etch depth, sidewall angle, and bottom shape. The cut position can be flexibly selected based on the structural characteristics to fully characterize the etch characteristics.

[0060] The aforementioned transverse and longitudinal cross-sectional images reveal a variety of etching characteristics, including but not limited to: etching depth, sidewall angle, sidewall roughness, bottom shape, under-mask etching, interface features, etc. These characteristics constitute a multi-dimensional indicator system for evaluating etching quality.

[0061] like Figure 4 The three-dimensional semiconductor simulation structure after etching shown in (a) Figure 4 (b) is a transverse section of (a) cut to obtain an XY two-dimensional section. Similarly, all sections in Figure 6 are longitudinal xz sections and their predicted results.

[0062] The 3D schematic diagram constructs a 3D model of the etched structure based on simulated lattice data. This data can be represented using voxels, surface meshes, or other appropriate data structures to effectively represent 3D features. The diagram shows the 3D topography formed by the etch, such as trenches, holes, or composite structures, and indicates the location and orientation of cross-section extraction.

[0063] The Cross-Sections section displays 2D cross-section images extracted from the 3D model, including but not limited to: Longitudinal section: extracted along a specific transverse coordinate, showing structural changes in the depth direction; Transverse cross section: extracted along a specific depth, showing the structural distribution in the plane direction.

[0064] like Figure 4 As shown, the extracted cross-sectional images can be subjected to appropriate image processing to highlight the structural contours, facilitating feature extraction and quantitative analysis. The processing method can be flexibly selected according to specific application requirements, and the present invention is not limited to a specific image processing technology.

[0065] like Figure 6 As shown, the method of the present invention can be applied to the prediction of etching morphologies of different structural types, including but not limited to simple grooves, groove arrays, hole arrays, line structures and composite structures.

[0066] For each structure, the initial, intermediate, and final state profiles can be predicted, forming a complete etch evolution sequence. The predictions reveal key characteristic changes during the etch process, such as depth increase, sidewall angle evolution, and bottom shape changes.

[0067] like Figure 6 As shown in Figure 2, for different types of structures, the prediction results reveal different etching characteristics: The trench structure can show the change of depth and the evolution of sidewall angle over time; Array structures can exhibit the influence of density effects, reflecting the interactions between adjacent units; High aspect ratio structures can exhibit changes in etching characteristics with increasing depth; Composite structures can exhibit changes in etching behavior at the interfaces between different materials.

[0068] One implementation method, such as Figure 5 As shown, step S3 specifically includes: S31. Obtain a sequence of two-dimensional cross-sectional images at different etching time points and extract profile evolution features from them; the profile evolution features are a set of time series parameters used to quantitatively describe the profile morphology, and the parameters include but are not limited to: etching depth, sidewall angle, critical dimension (CD), curvature of the groove bottom, sidewall roughness, and lateral etching amount under the mask.

[0069] S32. Based on the profile evolution characteristics, a curve fitting or time-series interpolation algorithm is used to generate a two-dimensional cross-sectional image representing the profile topography at the intermediate moment as the intermediate profile. The algorithm can be flexibly determined based on the data characteristics to balance computational efficiency and interpolation accuracy.

[0070] S33. Introduce smoothing processing based on physical constraints to ensure that the generated intermediate contour conforms to the laws of physical evolution; physical constraints may include but are not limited to material removal monotonicity, contour continuity, etching rate variation law, etc., to ensure the physical rationality of the generated data.

[0071] S34. Combine methods such as wavelet transform or Fourier analysis to extract multi-scale features of contour evolution; the multi-scale features of contour evolution include: low-frequency components that characterize changes in the overall morphology of the contour, and high-frequency components that characterize changes in local details of the contour (such as sidewall roughness and microgrooves).

[0072] Signal analysis methods such as wavelet transform or Fourier analysis can decompose morphological changes into components of different frequencies or scales, making it easier to understand and model the evolutionary characteristics of different scales.

[0073] S35. Based on the multi-scale characteristics of the profile evolution, generate the etching morphology evolution sequence at high time resolution. The specific implementation process is: Based on the multi-scale characteristics of the contour evolution, a parametric evolution model with time as input and contour geometric parameters as output is constructed. By evaluating the parametric evolution model at dense time points and reconstructing a two-dimensional cross-sectional image, an etching morphology evolution sequence with high temporal resolution is generated; wherein the above-mentioned two-dimensional cross-sectional image is the target contour image of the semiconductor structure after etching.

[0074] The parameterized evolution model can describe the evolution trajectory of contour points over time and realize the morphology prediction at any time point.

[0075] Through the above steps, the present invention, through the time series data generation module, can expand low-temporal-resolution raw data into high-resolution sequences, increasing data richness while ensuring the physical rationality of the generated data. It should be noted that the above steps can be flexibly adjusted according to specific application scenarios, and the present invention is not limited to a specific data generation method or processing sequence.

[0076] In one embodiment, in step S4, the specific method of constructing the contour prediction model based on deep learning includes: S41. Design a deep neural network structure with multi-channel input, including an etching process condition channel and a pre-etching initial contour image channel; The deep neural network structure selects a suitable network structure as the basic framework, and can adopt U-Net, convolutional LSTM, Transformer or a combination thereof; S42. Define multi-task learning objectives to simultaneously optimize the accuracy of shape prediction and the accuracy of key feature parameter prediction; S43. Use a physical constraint loss function to ensure that the prediction results conform to physical laws and topological consistency; S44. Use the data generated in steps S1 to S3 to perform model training and validation; S45. Apply transfer learning strategies and use experimental data to fine-tune the model to improve prediction accuracy under actual etching process conditions.

[0077] The etching process condition channel receives one or more combinations of etching process parameters, such as temperature, gas flow, RF power, and pressure. The pre-etching initial profile image channel receives an image of the structural morphology before etching. This multi-channel design allows the model to simultaneously learn the relationship between process parameters and etching results, and between initial profile and etching results.

[0078] For example, the deep neural network architecture can employ an encoder-decoder structure combined with a temporal modeling module. In the encoder, convolutional layers, attention mechanisms, or other feature extraction methods can be used to extract feature representations of the input data. Features from different sources can be integrated using a feature fusion module to form a unified feature representation.

[0079] The time series modeling module can use recurrent neural networks, attention mechanisms, or other sequence modeling methods to learn the temporal evolution of the etching morphology. This module can capture the dynamic characteristics of the etching process and predict the etching state at different time points.

[0080] The decoder converts temporal features back into the spatial domain, reconstructing images of the etched outline at different time points. The decoder can employ transposed convolution, upsampling, or other image generation methods to gradually restore the spatial resolution of the features. Skip connections can be introduced to pass features from the encoder directly to the corresponding decoder layer, preserving detailed information.

[0081] Model training can adopt a multi-objective learning method, and the optimized loss function may include: Shape prediction loss: measures the difference between the predicted contour and the actual contour; Feature parameter loss: prediction accuracy for key parameters; Physical constraint loss: a regularization term designed based on the physical laws of the etching process.

[0082] The total loss function can be a weighted combination of the above losses, with weights that can be flexibly adjusted based on the specific application scenario. Training data can come from physical simulations and time series data generation steps, and appropriate data partitioning and learning strategies can be used.

[0083] It should be noted that the above network structure and training method are only examples. The deep learning prediction model of the present invention is not limited to a specific network architecture, loss function or learning algorithm, and can be flexibly selected and combined according to specific application requirements.

[0084] In one embodiment, step S6 specifically includes: S61. Establish a defect type library, wherein the defect types include bridging, necking, under-etching, over-etching, sidewall roughness, and CD variation. S62. Extract key geometric features from the predicted contour image after etching of the semiconductor structure; the key geometric features include but are not limited to: the spacing between adjacent key areas, the final depth of the groove or hole, the deviation value of the sidewall inclination angle, quantitative indicators such as line width roughness (LWR), and the curvature radius at the bottom or corner, etching depth, sidewall angle, critical dimension (CD), curvature of the groove bottom, sidewall roughness, and lateral etching amount under the mask.

[0085] S63. Build a defect recognition classifier to determine the potential defect type based on the extracted key geometric features; specifically, Combined with preset mapping rules, potential defect areas are determined based on key geometric features; For potential defect areas, support vector machine classifier is used to determine the potential defect type.

[0086] S64. Obtain the severity of the potential defect based on the predicted contour image of the semiconductor structure after etching and the type of potential defect; specifically: S641. A defect spatial distribution map is established based on the predicted contour image of the semiconductor structure after etching and the potential defect types, and high-risk areas in the predicted contour are located. Specifically, this step assigns a defect risk index to each pixel or local area on the predicted contour image based on the proximity of its key geometric features to the preset defect criteria, thereby generating a defect risk heatmap that is aligned with the predicted contour image. In the heatmap, areas with higher risk indices are identified as high-risk areas.

[0087] S642. Calculate the defect risk index and quantitatively assess the defect risk level under the current process parameters.

[0088] In one embodiment, the specific method of step S7 includes: S71. Construct a process parameter-structure quality mapping model to establish the relationship between process parameter adjustment and structure improvement; S71. Design a deep learning-based parameter optimization framework that uses the negative value of the defect risk index as a reward function. S73. Alternatively, a model predictive control (MPC) framework is established to minimize the weighted sum of defect risk and parameter adjustment cost; S74. Set process parameter adjustment constraints to ensure that parameter changes are within a feasible range; S75. Perform parameter optimization calculations and output optimal process parameter adjustment suggestions; S76. Apply the optimized parameters to the actual etching process or the next round of simulation to form a closed-loop control.

[0089] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that the present invention can have many different forms, and the following embodiments are only for illustration and should not be understood as limiting the present invention.

[0090] Example 1: Trench etching process optimization: This example applies the semiconductor etching process prediction method of the present invention to optimize the fin trench etching process of the advanced technology node FinFET device.

[0091] (1) Initial conditions: Initial structure: A hard mask is pre-deposited on a silicon substrate and patterned to form a wire grid array. For example, the initial structure is a SiO2 hard mask (50nm thick) pre-deposited on a silicon substrate and patterned to form a wire grid array with a line width of 40nm and a pitch of 40nm.

[0092] Etch target: Form a fin trench with a specific depth, width, and sidewall angle, while controlling sidewall roughness and CD variation. For example, the etch target is to form a fin trench with a depth of 120nm, a width of 30nm (±2nm), and a sidewall angle of 89° (±1°), while minimizing sidewall roughness and CD variation.

[0093] Etching process conditions: Fluorine-containing mixed gas, ICP etching, with initial parameter settings. As an example, the etching process conditions are CF4 / O2 / Ar mixed gas, ICP etching, with initial parameters of RF power 500W, bias power 100W, pressure 10mTorr, gas flow ratio CF4:O2:Ar = 60:10:30, and substrate temperature 60°C.

[0094] (2) Implementation steps: Step 1: A physical model for fin trench etching was established using the kinetic Monte Carlo method. Considering the surface reaction mechanism of Si in a fluorine-containing plasma, simulations were performed under multiple sets of process parameters to generate an etch topography database covering the parameter space. For each parameter set, 3D structural data was recorded every 5 seconds from 0 to 200 seconds.

[0095] Step 2: Extract 2D cross-sections at key locations from the 3D simulation data, including longitudinal cross-sections along the fin length and transverse cross-sections at different depths. Extract data from 20 evenly spaced time points to form an initial time series. Then, apply the Time Series Data Generation module to increase the temporal resolution to one data point every 0.5 seconds.

[0096] Step 3: Use the deep learning prediction model based on the U-Net architecture to predict the contour image after etching.

[0097] The input channels of the deep learning prediction model based on the U-Net architecture include process parameters (RF power, bias power, pressure, and three gas flow rates) and an initial profile image (128×128 pixels, 1nm / pixel resolution). The output is a sequence of 40 etch profiles at time points (0-200 seconds, with 5-second intervals). 80% of the simulation data is used for training, and 20% is used for validation. An additional 10 sets of experimental data are used for transfer learning to fine-tune the model to actual etching process conditions.

[0098] In one embodiment, the deep learning prediction model based on the U-Net architecture uses the U-Net network as the basic framework. Figure 7 , which includes an encoder, a bottleneck layer, a decoder, a process parameter processing module, and an output layer; The process parameter processing module, Figure 5 Its input end is configured to receive a parameter vector including at least one etching process condition parameter, and the process parameter processing module is configured to convert the parameter vector into a set of parameter features; In an optional embodiment, the process parameter processing module includes at least one fully connected layer.

[0099] The input end of the encoder is configured to receive an initial contour image representing a pre-etching image, and includes multiple encoding layers for extracting a set of multi-scale spatial features from the initial contour image; each encoding layer is connected in series with a downsampling unit; In an optional embodiment, each coding layer includes at least one convolutional layer and one pooling layer.

[0100] The bottleneck layer adopts a timing evolution module, whose input end is connected to the output end of the last encoding layer and the output end of the process parameter processing module. The timing evolution module is configured as follows: (a) fusing the spatial features output by the last encoding layer and the parameter features output by the process parameter processing module to form an initial state feature map; (b) Based on the initial state feature map, a hidden state sequence including multiple hidden states is generated through a recurrent neural network unit, where each hidden state corresponds to a future prediction time point.

[0101] Furthermore, the recurrent neural network unit is a convolutional long short-term memory network (ConvLSTM) unit or a gated recurrent unit (GRU).

[0102] The input end of the decoder is connected to the output end of the temporal evolution module, which includes the same number of decoding layers as the encoding layers, and is configured to receive the hidden state sequence and generate a corresponding predicted contour image for each hidden state decoding in the sequence, thereby forming a predicted contour image sequence; an upsampling unit is connected in series after each decoding layer, and skip connections are used between the encoding layer and the decoding layer at the same layer.

[0103] The multi-scale spatial features are received and fused during the decoding process through skip connections to improve the accuracy of the details of the predicted contour image.

[0104] The output layer receives the feature map transmitted by the upsampling unit from the last decoding layer and fuses it with the initial contour feature map to obtain the next frame contour image.

[0105] Step 4: Defect detection is performed on the predicted post-etch profile image of the semiconductor structure to identify the types and severity of potential defects in the predicted post-etch semiconductor structure. Potential defect types include insufficient / excessive depth, sidewall angle deviation, and abnormal trench bottom shape. For detected defects, a model predictive control (MPC) strategy is used to optimize process parameters.

[0106] Step 5: Apply the optimized process parameters to the actual etching equipment, etch a test sample, and measure the profile using SEM / TEM. The measurement results are fed back to the system to update the prediction model, forming a closed-loop optimization loop. After 3-5 rounds of iterations, convergence is achieved on the optimal process window.

[0107] The process parameters obtained by the above method are optimized, improving etching quality and stability. The deep learning prediction model based on the U-Net architecture in this embodiment demonstrates high accuracy, with critical dimension prediction errors within an acceptable range. This widens the process window, enhances process robustness, and improves key indicators such as uniformity and roughness. This resolves specific defect issues, increases the success rate of subsequent processes, significantly shortens development cycles, and reduces silicon wafer consumption.

[0108] Example 2, 3D NAND memory hole etching control: This example applies the semiconductor etching process prediction method of the present invention to optimize the high aspect ratio hole etching process in 3D NAND flash memory manufacturing.

[0109] Initial conditions: Initial structure: 48 layers of alternating SiO2 / Si3N4 (each 30nm thick), topped with a 200nm thick SiO2 hard mask, patterned to form a circular opening with a diameter of 90nm.

[0110] Etching goal: Form through-holes with a total depth of 3000nm, a diameter of 80nm (±5nm), and a sidewall angle of 88°-90°, while minimizing interlayer step effects and sidewall roughness.

[0111] Etching process conditions: C4F8 / O2 / CO / Ar composite gas, dual-frequency ICP etching, initial parameters are high-frequency power 1200W, low-frequency power 400W, pressure 25mTorr, gas flow ratio C4F8:O2:CO:Ar=20:10:40:100, substrate temperature 20℃.

[0112] Implementation steps: Step 1: Using a layered KMC physical modeling strategy, we established microscopic reaction models for SiO2 and Si3N4 etching, focusing on selectivity changes and transition behavior at the interface. Factors such as reactant diffusion limitations, variations in ion bombardment angle distribution with depth, and charging effects were considered. Each parameter set simulated the etching process from 0 to 600 seconds, with 3D structural data recorded every 15 seconds.

[0113] Step 2: Extract key information from the 3D simulation data, including longitudinal cross-sections along the pore depth, transverse cross-sections at different depths (with particular attention to the SiO2 / Si3N4 interface), and pore diameter versus depth curves. A time series data generation module is used to generate a high-resolution (one data point every 3 seconds) morphology evolution sequence. Physical constraints, such as a diffusion-limited rate decay model, are introduced to predict the morphology of deep regions.

[0114] Step 3: Use the hierarchical perception deep learning prediction model to predict the contour image after etching.

[0115] This layer-aware deep learning prediction model utilizes an attention-enhanced U-Net architecture. Input channels include process parameters (dual-frequency power, pressure, four gas flow rates, and temperature), an initial profile image, and a material layer marker (identifying the locations of different material layers). The output is a sequence of 40 time points of etch profiles, covering the entire process from 0 to 600 seconds. The model uses a layer-weighted loss function, giving higher weight to deep regions and material interfaces.

[0116] In another embodiment, the hierarchical perception deep learning prediction model is embodied as a device or system for semiconductor etching profile prediction, such as Figure 8 As shown in the figure, the U-Net network is used as the basic framework, which includes a multimodal input processing unit, an encoder, a bottleneck layer, a decoder, a process parameter processing module, and an output layer; The multimodal input processing unit is configured to receive an initial contour image and a material layer marker image registered therewith, and merge the two into a multi-channel input feature map; The material layer labeling map is a digital atlas that is precisely spatially aligned with the initial contour image and contains key prior knowledge about the chemical composition and physical properties of the etched object. The digital atlas assigns a unique numerical label to each different material in the initial structure at the pixel level. In a typical shallow trench isolation (STI) etch process, this atlas clearly identifies hard mask layers such as photoresist, silicon dioxide (SiO2), and silicon nitride (Si3N4), as well as areas of the silicon (Si) substrate to be etched.

[0117] By combining the geometric contour image and the material label map into a multi-channel input (for example, one channel represents the geometry and the other channel represents the material label), it is possible to ensure that the neural network can simultaneously perceive the "morphology" and "composition" of the structure at each step of feature extraction, thereby learning a more accurate and physically consistent etching dynamic process.

[0118] The process parameter processing module, whose input end is configured to receive a parameter vector including at least one etching process condition parameter, and the process parameter processing module is configured to convert the parameter vector into a set of parameter features; In an optional embodiment, the process parameter processing module includes at least one fully connected layer.

[0119] The input end of the encoder is configured to receive an initial contour image representing a pre-etching image, and includes multiple encoding layers for extracting a set of multi-scale spatial features from the initial contour image; each encoding layer is connected in series with a downsampling unit; In an optional embodiment, each coding layer includes at least one convolutional layer and one pooling layer.

[0120] The bottleneck layer adopts a timing evolution module, whose input end is connected to the output end of the last encoding layer and the output end of the process parameter processing module. The timing evolution module is configured as follows: (a) fusing the spatial features output by the last encoding layer and the parameter features output by the process parameter processing module to form an initial state feature map; (b) Based on the initial state feature map, a hidden state sequence including multiple hidden states is generated through a recurrent neural network unit, where each hidden state corresponds to a future prediction time point.

[0121] Furthermore, the recurrent neural network unit is a convolutional long short-term memory network (ConvLSTM) unit or a gated recurrent unit (GRU).

[0122] The input of the decoder is connected to the output of the temporal evolution module. It includes the same number of decoding layers as the encoding layers and is configured to receive the hidden state sequence and generate a corresponding predicted contour image for each hidden state in the sequence, thereby forming a predicted contour image sequence. An upsampling unit is connected in series after each decoding layer, and skip connections are used between the encoding layer and the decoding layer at the same layer. An attention gate unit is connected in series with each skip connection. The attention gate unit is configured to: based on the high-level semantic features transmitted from the current decoding layer via the upsampling unit, adaptively adjust and filter the low-level spatial features from the encoding layer, so that the current decoding layer can focus on the key areas most relevant to the current task (such as material interfaces or deep areas) when reconstructing the predicted contour image.

[0123] The output layer receives the feature map transmitted by the upsampling unit from the last decoding layer and fuses it with the initial contour feature map to obtain the next frame contour image.

[0124] Furthermore, the loss function used to train the device / system is a hierarchical weighted loss function, which is configured to: when calculating the error between the predicted contour image and the true contour image, apply higher weights to the errors in preset key areas (including but not limited to deep areas and material interface areas), thereby guiding the model to prioritize optimizing the prediction accuracy of these key areas.

[0125] Step 4: Develop a detection system for 3D NAND-specific defects, focusing on defects such as aperture variation, sidewall tilt, interface steps, and abnormal hole bottom shape. Based on the detection results, a reinforcement learning strategy is used to optimize process parameters and achieve adaptive adjustments during the etching process.

[0126] Step 5: Based on the model predictions and reinforcement learning optimization results, a segmented etching strategy is designed, dividing the entire deep hole etching process into 3-5 segments, each using an optimized parameter combination. For example, a highly selective formulation may be used in the shallow region, a balanced etching rate and uniformity may be achieved in the middle region, and enhanced reactant transport and product removal capabilities may be achieved in the deep region. Parameters and switching points for each segment are optimized through experimental verification and model feedback.

[0127] The etch process optimized by the above method achieves high-quality, high-aspect-ratio structures, effectively controls critical dimensional variations, and maintains key structural parameters within target ranges, meeting subsequent process requirements. Clearly, the application of the present method improves etch efficiency and shortens process time; improves interface features and enhances structural quality; significantly reduces defect rates, particularly for deep critical defects; improves finished product yield and reduces manufacturing costs; and enhances process stability and adaptability to material and equipment variations.

[0128] The above examples demonstrate that the intelligent prediction method for semiconductor device etching structures provided by the present invention, by combining physical models with data-driven methods, can be effectively applied to optimize different types of semiconductor etching processes, improving process stability and product yield. Those skilled in the art will understand that the above embodiments are merely illustrative, and the scope of protection of the present invention shall be subject to the claims.

[0129] An embodiment of the present invention provides an electronic device. Specifically, the electronic device includes a memory and a processor. The memory stores executable code. When the processor executes the executable code, the method described in any one of the embodiments is implemented.

[0130] The memory may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The system network element communicates with at least one other network element via at least one communication interface (which may be wired or wireless), such as the Internet, a wide area network (WAN), a local area network (LAN), or a metropolitan area network (MAN).

[0131] The bus may be an ISA bus, a PCI bus or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0132] The memory is used to store the program, and the processor executes the program after receiving the execution instruction. The method executed by the device for flow process definition disclosed in any of the aforementioned embodiments of the present invention can be applied to the processor or implemented by the processor.

[0133] The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method may be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present invention may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present invention may be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or the like. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0134] The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be referred to the previous method embodiment and will not be repeated here.

[0135] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0136] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A semiconductor etching process prediction method, characterized in that: The method comprises: Acquire three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions; the three-dimensional etching evolution simulation data includes three-dimensional contour images of the semiconductor structure at different etching time points during the etching process; Extracting a two-dimensional cross-sectional image from three-dimensional etching evolution simulation data; the two-dimensional cross-sectional image includes a plurality of longitudinal cross-sectional images and a plurality of transverse cross-sectional images; generating an etching morphology evolution sequence at a high temporal resolution based on the two-dimensional cross-sectional image; obtaining a target contour image of the semiconductor structure after etching from the etching morphology evolution sequence at a high temporal resolution; The data set is composed of an initial contour image of the semiconductor structure before etching and a corresponding target contour image after etching; Constructing a deep learning-based contour prediction model and training it using a data set; wherein the input of the deep learning-based contour prediction model includes etching process conditions and an initial contour image of the semiconductor structure before etching, and the output is a predicted contour image after etching that evolves with etching time; The etching process conditions and the initial contour image of the semiconductor structure before etching are input into the trained deep learning-based contour prediction model to obtain the predicted contour image of the semiconductor structure after etching.

2. The method according to claim 1, characterized in that The process of obtaining the three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions includes: Establish a three-dimensional lattice model and discretize the surface of the semiconductor structure into a three-dimensional lattice structure; Constructing a surface reaction event library; the surface reaction event library includes multiple surface reaction events of different etching processes, each surface reaction event is adsorption, desorption, migration or ion bombardment; Defining the probability equation and reaction rate of each surface reaction event, where the reaction rate is related to the etching process conditions; A kinetic Monte Carlo algorithm is used to iteratively simulate the etching process of the current semiconductor structure, randomly select and execute the next surface reaction event according to the reaction rate, and simultaneously update the state of the three-dimensional semiconductor structure; Record the 3D contour image of the semiconductor structure at the current stage at the preset etching time point to form a 3D etching evolution simulation data set; By changing the etching process conditions, the three-dimensional lattice model is re-established, and finally a three-dimensional etching evolution simulation data set covering a variety of etching process conditions is generated.

3. The method according to claim 2, characterized in that The updating of the state of the three-dimensional semiconductor structure includes: updating the material type of the etched lattice site, and recalculating the local environmental parameters of the adjacent lattice sites affected by the current surface reaction event and the probability of future surface reaction events.

4. The method according to claim 1, characterized in that The process of extracting a two-dimensional cross-sectional image from three-dimensional etching evolution simulation data includes: Extract multiple longitudinal cross-sectional images along the key feature area or the transverse coordinates at fixed intervals; extract multiple transverse cross-sectional images at different depths along the key feature area or the preset area; convert the extracted longitudinal cross-sectional images and transverse cross-sectional images into binary images or grayscale images.

5. The method according to claim 4, characterized in that: The key feature areas include the center line of the trench, the edge of the trench, the central axis of the high aspect ratio hole, and the interface between different material layers.

6. The method according to claim 1, characterized in that The process of generating an etching morphology evolution sequence at high time resolution based on the two-dimensional cross-sectional image includes: Obtaining a sequence of two-dimensional cross-sectional images at different etching time points and extracting contour evolution features from the sequence; the contour evolution features are a set of time series parameters used to quantitatively describe the contour morphology; Based on the contour evolution characteristics, a two-dimensional cross-sectional image representing the contour morphology at the intermediate moment is generated as the intermediate contour; Introducing physical constraint-based smoothing to ensure that the generated intermediate contours conform to the laws of physical evolution; Extract multi-scale features of contour evolution for intermediate contours; Based on the multi-scale characteristics of profile evolution, an etching morphology evolution sequence with high temporal resolution is generated.

7. The method according to claim 1, characterized in that: The method further comprises: Perform defect detection on the predicted contour image of the semiconductor structure after etching to identify the potential defect types and severity in the predicted semiconductor structure after etching; Based on the predicted contour image after etching and the type and severity of potential defects, the etching process conditions of the current semiconductor structure are adjusted to achieve closed-loop optimization.

8. The method according to claim 7, characterized in that: The process of performing defect detection on the predicted contour image of the semiconductor structure after etching and identifying the potential defect types and severity in the predicted semiconductor structure after etching includes: Establish a defect type library; Extract key geometric features from the predicted contour image after etching of semiconductor structures; Build a defect recognition classifier to determine the potential defect type based on the extracted key geometric features; The severity of the potential defects is obtained based on the predicted profile image of the semiconductor structure after etching and the type of potential defects.

9. An electronic device comprising a memory, a processor and an industrial interface, wherein a computer program is stored in the memory, and when the program is run on the processor, the method according to any one of claims 1 to 8 is executed.

10. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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