Test method and device based on FRT table, equipment and storage medium

Abstract

The invention provides a test method and device based on an FRT table, equipment and a storage medium, and relates to the technical field of computers. The method comprises: generating a test sequence; the test sequence can cover the voltage combination in the FRT table; determining a test mode based on the test sequence; the test mode is an index mode or a global mode; reading a corresponding voltage offset in an FRT table based on the test mode and the test sequence; based on the voltage offset, reading the target data from an NAND flash memory of a solid state disk SSD; determining a test result based on the reading state of the target data; the reading state comprises the number of rereading times of the FRT table, the number of hard decoding times of the target data, the number of soft decoding times of the target data and the data recovery time delay. The test efficiency can be improved, the dependence on the environment is reduced, and the fault mode coverage rate is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a testing method, apparatus, device, and storage medium based on an FRT table. Background Art

[0002] With the continuous development of 3D NAND flash memory technology, the application of multi-level cell (MLC, TLC, QLC, etc.) technology has significantly increased storage density, but this has also introduced physical degradation issues such as charge leakage and read disturb. These issues cause the error rate of storage cells to rise sharply with the increase in P / E (program / erase) cycles. In particular, in QLC NAND, the raw bit error rate (RBER) can reach levels of 1E-3. To maintain data integrity, solid-state drives (SSDs) typically use a cascaded low-density parity-check (LDPC) decoding mechanism. However, traditional LDPC verification methods suffer from strong environmental dependence and low fault mode coverage, making them inadequate for error handling logic verification in modern SSDs. NAND flash memory is a type of non-volatile memory. MLC stands for multi-level cell, TLC stands for triple-level cell, and QLC stands for quad-level cell. Summary of the Invention

[0003] The present disclosure provides a testing method, apparatus, device and storage medium based on an FRT table to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a test method based on an FRT table is provided, comprising: generating a test sequence; the test sequence being capable of covering voltage combinations in the FRT table; determining a test mode based on the test sequence; the test mode being an index mode or a global mode; reading a corresponding voltage offset in the FRT table based on the test mode and the test sequence; reading target data from a NAND flash memory of a solid-state drive (SSD) based on the voltage offset; and determining a test result based on a read status of the target data; the read status comprising the number of rereads of the FRT table, the number of hard decodings of the target data, the number of soft decodings of the target data, and a data recovery delay.

[0005] In one embodiment, generating a test sequence includes: constructing a two-dimensional parameter space corresponding to the FRT table; writing a reference voltage offset set into the two-dimensional parameter space to obtain the FRT table; and generating a test sequence that can cover the voltage combinations in the FRT table based on the voltage combinations in the FRT table.

[0006] In one embodiment, constructing a two-dimensional parameter space corresponding to the FRT table includes: determining an index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points; determining a voltage offset dimension corresponding to each of the adjustable voltage points; the voltage offset dimension represents the maximum offset range of the adjustable voltage point; and constructing a two-dimensional parameter space corresponding to the FRT table based on the index dimension and the voltage offset dimension.

[0007] In one possible implementation, writing the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table includes: writing the reference voltage offset set into the two-dimensional parameter space; establishing a register mapping space of the FRT table to obtain the FRT table; the register mapping space is used to dynamically modify the voltage value in the FRT table.

[0008] In one embodiment, generating a test sequence capable of covering the voltage combinations in the FRT table based on the voltage combinations in the FRT table includes: generating a test sequence capable of covering the voltage combinations in the FRT table based on a deterministic traversal algorithm and a Monte Carlo random sampling algorithm.

[0009] In one possible implementation manner, determining the test mode based on the test sequence includes: parsing the test sequence to determine the test parameters corresponding to each data in the test sequence; the test parameters include an error annotation mode corresponding to the data, and the error annotation mode includes index error annotation and global error annotation; determining the test mode based on the error annotation mode.

[0010] In one embodiment, before reading the corresponding voltage offset in the FRT table based on the test mode and the test sequence, the method further includes: in response to the test mode being an index mode, adjusting the voltage offset corresponding to the current data in the test sequence through the register mapping space in the FRT table.

[0011] In one embodiment, before reading the corresponding voltage offset in the FRT table based on the test mode and the test sequence, the method further includes: in response to the test mode being a global mode, adjusting all voltage offsets in the FRT table using a pseudo-random number generator.

[0012] In one possible implementation, after the target data is read from the NAND flash memory of the solid-state drive (SSD) based on the voltage offset, the method further includes: performing low-density parity check code (LDPC) hard decoding on the target data; in response to the number of hard decodings being less than a first threshold and the hard decoding being unsuccessful, re-performing LDPC hard decoding on the target data until the hard decoding is successful, and counting the number of hard decodings; in response to the number of hard decodings being greater than a first threshold, re-reading a new voltage offset in the FRT table based on the test sequence, and reading the target data from the NAND flash memory of the solid-state drive (SSD) based on the new voltage offset until the target data is hard-decoded successfully or the number of rereads of the FRT table is greater than a second threshold.

[0013] In one possible implementation, a testing method based on an FRT table further includes: in response to the target data being hard-decoded successfully after re-reading a new voltage offset in the FRT table, counting the number of hard decoding times and the number of rereadings of the FRT table; in response to the number of rereadings of the FRT table being greater than a second threshold, performing LDPC soft decoding on the target data until the soft decoding is successful, and counting the number of soft decoding times.

[0014] In one embodiment, a testing method based on an FRT table further includes: determining the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine; and determining test completeness based on the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine.

[0015] According to a second aspect of the present disclosure, a test device based on an FRT table is provided, comprising: a generation module for generating a test sequence; the test sequence can cover the voltage combinations in the FRT table; a first determination module for determining a test mode based on the test sequence; the test mode is an index mode or a global mode; a first reading module for reading a corresponding voltage offset in the FRT table based on the test mode and the test sequence; a second reading module for reading target data from a NAND flash memory of a solid-state drive (SSD) based on the voltage offset; a second determination module for determining a test result based on a read status of the target data; the read status includes the number of rereads of the FRT table, the number of hard decodings of the target data, the number of soft decodings of the target data, and a data recovery delay.

[0016] In one embodiment, the generation module is further used to: construct a two-dimensional parameter space corresponding to the FRT table; write the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table; and generate a test sequence that can cover the voltage combinations in the FRT table based on the voltage combinations in the FRT table.

[0017] In one embodiment, the generation module is also used to: determine the index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points; determine the voltage offset dimension corresponding to each of the adjustable voltage points; the voltage offset dimension represents the maximum offset range of the adjustable voltage point; based on the index dimension and the voltage offset dimension, construct a two-dimensional parameter space corresponding to the FRT table.

[0018] In one embodiment, the generation module is further used to: write the reference voltage offset set into the two-dimensional parameter space; establish a register mapping space of the FRT table to obtain the FRT table; and the register mapping space is used to dynamically modify the voltage value in the FRT table.

[0019] In one possible implementation, the generation module is further configured to generate a test sequence capable of covering the voltage combinations in the FRT table based on a deterministic traversal algorithm and a Monte Carlo random sampling algorithm.

[0020] In one embodiment, the first determination module is further used to: parse the test sequence to determine the test parameters corresponding to each data in the test sequence; the test parameters include the error annotation mode corresponding to the data, and the error annotation mode includes index error annotation and global error annotation; based on the error annotation mode, determine the test mode.

[0021] In one embodiment, a test device based on an FRT table further includes: an adjustment module for: in response to the test mode being an index mode, adjusting a voltage offset corresponding to current data in the test sequence through a register mapping space in the FRT table.

[0022] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0023] at least one processor; and

[0024] a memory communicatively connected to the at least one processor; wherein,

[0025] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0026] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0027] The disclosed FRT table-based testing method, apparatus, device, and storage medium generate a test sequence; determine a test mode based on the test sequence; read the corresponding voltage offset from the FRT table based on the test mode and test sequence; read target data from the NAND flash memory of a solid-state drive (SSD) based on the voltage offset; and determine the test result based on the read status of the target data. This significantly improves test efficiency and reduces R&D costs by replacing the physical aging process with electrical parameter simulation. A dual-mode error injection mechanism enhances test comprehensiveness. The automated testing framework records a wealth of key data to support subsequent analysis, reducing environmental dependency and improving fault mode coverage.

[0028] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0030] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0031] Figure 1 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 1 ;

[0032] Figure 2 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 2 ;

[0033] Figure 3 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 3 ;

[0034] Figure 4 A schematic structural diagram of a test device based on an FRT table according to an embodiment of the present disclosure is shown;

[0035] Figure 5 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0036] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0037] Figure 1 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 1 ,like Figure 1 As shown, a testing method based on the FRT table includes:

[0038] Step S101: Generate a test sequence.

[0039] In this embodiment, the generated test sequence can cover the voltage combinations in the FRT table. The FRT table contains the voltage values ​​required for NAND flash memory reads and records the voltage offsets required for different read operations. By generating a test sequence that covers all voltage combinations in the FRT table, it is ensured that subsequent testing can simulate NAND flash memory read conditions under various voltage conditions, thereby providing a basis for triggering the error correction logic in the SSD driver.

[0040] Step S102: Determine a test mode based on the test sequence.

[0041] In this embodiment, the test mode is determined based on the generated test sequence. Test modes are divided into index mode and global mode. Index mode refers to testing specific indexes in the FRT table. It can accurately test one or more specific voltage points in the FRT table and is suitable for situations where detailed analysis and verification of reading conditions under specific voltage conditions are required. Global mode comprehensively tests all voltage points in the FRT table, which can more widely cover the voltage combinations in the FRT table and is suitable for situations where the performance of the SSD driver error correction logic under various voltage conditions needs to be fully evaluated.

[0042] Step S103: Based on the test mode and the test sequence, read the corresponding voltage offset in the FRT table.

[0043] In this embodiment, after determining the test mode and generating the test sequence, it is necessary to read the corresponding voltage offset from the FRT table based on the test mode and test sequence. If the test mode is indexed, then the voltage offset corresponding to the index specified in the test sequence is read from the FRT table. If the test mode is global, then the voltage offsets of all voltage points need to be read from the FRT table.

[0044] Step S104 : Reading target data from the NAND flash memory of the solid state drive (SSD) based on the voltage offset.

[0045] In this embodiment, after obtaining the voltage offsets from the FRT table, the target data is read from the NAND flash memory of the solid-state drive (SSD) based on these voltage offsets. Specifically, when reading data from the NAND flash memory, the voltage parameters of the read operation are adjusted based on the voltage offsets in the FRT table, thereby simulating the reading behavior of the NAND flash memory under different voltage conditions. This is done to trigger the error correction logic in the SSD driver, thereby testing and verifying its functionality and performance.

[0046] Step S105 : determining a test result based on the read status of the target data.

[0047] In this embodiment, the test result is determined based on the read status of the target data. The read status of the target data includes the number of FRT table rereads, the number of hard decoding attempts of the target data, the number of soft decoding attempts of the target data, and the data recovery delay. The number of FRT table rereads refers to the number of times the target data needs to be reread based on the voltage offset in the FRT table due to reasons such as hard decoding failure. The number of hard decoding attempts refers to the number of hard decoding operations performed on the target data. Hard decoding is a decoding method that directly makes decisions based on the received signal or LLR value. By counting the number of hard decoding attempts, the probability of successfully recovering the target data through hard decoding under different voltage conditions can be understood. The number of soft decoding attempts refers to the number of soft decoding operations performed on the target data after hard decoding fails. Soft decoding utilizes soft information from the received signal for decoding. By counting the number of soft decoding attempts, the effectiveness of soft decoding for data recovery in the event of hard decoding failure can be evaluated. The data recovery delay refers to the time elapsed from the start of reading the target data to the final successful data recovery, which can reflect the efficiency of the entire error correction process. By organizing the read status of the target data, the test results can be obtained.

[0048] In one example, the test results may be as follows:

[0049] Test data 1: Hard decoding failed, FRT reread once, hard decoding succeeded, data recovery delay 10ms;

[0050] Test data 2: Hard decoding failed, FRT reread twice, hard decoding failed, soft decoding succeeded, data recovery delay 20ms;

[0051] Test data 3: Hard decoding successful, FRT reread 0 times, data recovery delay 5ms.

[0052] In the present disclosure, by generating a test sequence that can cover the voltage combinations in the FRT table, determining the test mode according to the test sequence, then reading the corresponding voltage offset in the FRT table, reading the target data from the NAND flash memory, and finally determining the test result according to the read status of the target data, the entire process can effectively simulate various read error conditions of the NAND flash memory and comprehensively verify and evaluate the error correction logic of the SSD drive, which can not only improve the coverage and accuracy of the test, but also provide strong support for the optimization and improvement of the error correction logic of the SSD drive.

[0053] Figure 2 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 2 ,like Figure 2 As shown, a testing method based on the FRT table includes:

[0054] Step S201: construct a two-dimensional parameter space corresponding to the FRT table.

[0055] In this embodiment, the two-dimensional parameter space corresponding to the FRT table consists of an FRT index dimension and a voltage offset dimension. The FRT index dimension corresponds to different index positions in the FRT table, each index position representing the voltage value required for a specific read operation; the voltage offset dimension represents the range within which the voltage value corresponding to each index position can be offset. This range is typically a programmable interval used to simulate NAND flash memory reads under different voltage conditions. By constructing such a two-dimensional parameter space, all possible voltage combinations in the FRT table can be fully represented, providing a basic framework for subsequent test sequence generation.

[0056] Step S202 : writing the reference voltage offset set into the two-dimensional parameter space to obtain an FRT table.

[0057] In this embodiment, after constructing the two-dimensional parameter space, the next step is to write a set of reference voltage offsets into this space to complete the FRT table. The reference voltage offset set is a set of preset voltage offset values, which are typically the voltage offsets required for NAND flash memory read operations under normal operating conditions. Writing these reference voltage offsets into the two-dimensional parameter space effectively initializes the FRT table, determining the base voltage offset for each index position in the FRT table.

[0058] Step S203: Based on the voltage combinations in the FRT table, a test sequence that can cover the voltage combinations in the FRT table is generated.

[0059] In this embodiment, based on the voltage combinations in the initialized FRT table, a test sequence that can cover these voltage combinations is generated. In one example, a test sequence that can effectively cover all voltage combinations can be determined based on the voltage distribution characteristics and patterns in the FRT table. The generation of the test sequence needs to consider various factors, including the distribution range of the voltage offset, the voltage relationship between different index positions, etc. The generated test sequence will serve as input for subsequent test operations to guide the entire test process.

[0060] Step S204: Determine a test mode based on the test sequence.

[0061] Step S205 : Based on the test mode and the test sequence, read the corresponding voltage offset in the FRT table.

[0062] Step S206 : Reading target data from the NAND flash memory of the solid state drive (SSD) based on the voltage offset.

[0063] Step S207: determining a test result based on the read status of the target data.

[0064] The specific implementation process of steps S204 to S207 is similar to that of steps S102 to S105 and will not be repeated here.

[0065] In this disclosure, by constructing a two-dimensional parameter space corresponding to an FRT table and writing a reference voltage offset set into this space to obtain an FRT table, and then generating a test sequence based on the voltage combinations in the FRT table, a test sequence that fully covers the voltage combinations in the FRT table can be effectively generated. This not only ensures the comprehensiveness and effectiveness of the test sequence, but also provides accurate input for subsequent test operations, thereby improving the accuracy and reliability of the entire test process.

[0066] In another embodiment, step S201 “constructing a two-dimensional parameter space corresponding to the FRT table” includes:

[0067] Determine the index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points;

[0068] Determine the voltage offset dimension corresponding to each adjustable voltage point; the voltage offset dimension represents the maximum offset range of the adjustable voltage point;

[0069] Based on the index dimension and the voltage offset dimension, a two-dimensional parameter space corresponding to the FRT table is constructed.

[0070] In this embodiment, the index dimension refers to the index position in the FRT table. Each index position corresponds to a voltage value required for a specific read operation. The N adjustable voltage points represent N different index positions in the FRT table, each of which can have its corresponding voltage value adjusted as needed. The index dimension is determined based on the physical characteristics of the NAND flash memory and the requirements of the read operation, ensuring that each index position accurately reflects the voltage requirements of the NAND flash memory under different read conditions.

[0071] In this embodiment, after determining the index dimension, the next step is to determine the voltage offset dimension corresponding to each adjustable voltage point. The voltage offset dimension refers to the range within which the voltage value corresponding to each index position can be offset. This range is typically a programmable interval used to simulate NAND flash memory read conditions under different voltage conditions. The process of determining the voltage offset dimension needs to be based on the physical characteristics of the NAND flash memory and the requirements of the read operation, ensuring that the offset range of each voltage point can cover all voltage variations that may occur during actual NAND flash memory operation.

[0072] In this embodiment, it is also necessary to construct a two-dimensional parameter space corresponding to the FRT table based on the determined index dimension and voltage offset dimension. The two-dimensional parameter space is a matrix composed of the index dimension and the voltage offset dimension, in which each element represents a specific voltage point. By constructing this two-dimensional parameter space, all possible voltage combinations in the FRT table can be fully represented, providing a basic framework for subsequent generation of test sequences. The process of constructing the two-dimensional parameter space requires accurately defining the parameter range and distribution law of each dimension to ensure that all voltage conditions in the FRT table can be accurately covered.

[0073] In this disclosure, by determining the index dimension corresponding to the FRT table and the voltage offset dimension corresponding to each adjustable voltage point, and constructing a two-dimensional parameter space based on these two dimensions, a two-dimensional parameter space that can fully cover all voltage combinations in the FRT table can be effectively constructed. This not only ensures the accuracy and completeness of the two-dimensional parameter space, but also provides a solid foundation for subsequent test sequence generation, thereby improving the accuracy and reliability of the entire test process.

[0074] In another embodiment, step S202 of “writing the reference voltage offset set into the two-dimensional parameter space to obtain an FRT table” includes:

[0075] Writing the reference voltage offset set into the two-dimensional parameter space;

[0076] A register mapping space of the FRT table is established to obtain the FRT table; the register mapping space is used to dynamically modify the voltage value in the FRT table.

[0077] In this embodiment, after constructing the two-dimensional parameter space, the next step is to write a reference voltage offset set into this space. The reference voltage offset set is a set of preset voltage offset values, typically the voltage offsets required for NAND flash memory read operations under normal operating conditions. Writing these reference voltage offsets into the two-dimensional parameter space effectively initializes the FRT table, determining the base voltage offset for each index position in the FRT table.

[0078] In this embodiment, after writing the reference voltage offset set into the two-dimensional parameter space, it is necessary to establish a register mapping space for the FRT table. The register mapping space is a mechanism for dynamically modifying the voltage values ​​in the FRT table. By establishing the register mapping space, the voltage values ​​in the FRT table can be dynamically adjusted as needed during the test process, thereby simulating the reading of NAND flash memory under different voltage conditions. The establishment of the register mapping space must ensure that it can accurately reflect the voltage values ​​in the FRT table and can be easily modified dynamically.

[0079] In this disclosure, by writing a set of reference voltage offsets into a two-dimensional parameter space and establishing a register mapping space for a FRT table, the present invention effectively initializes the FRT table and dynamically modifies the voltage values ​​within the FRT table. This not only ensures the accuracy and integrity of the FRT table but also provides strong support for subsequent test operations, thereby improving the flexibility and adaptability of the entire test process.

[0080] In another embodiment, step S203 of “generating a test sequence capable of covering the voltage combinations in the FRT table based on the voltage combinations in the FRT table” includes:

[0081] Based on the deterministic traversal algorithm and the Monte Carlo random sampling algorithm, a test sequence that can cover the voltage combinations in the FRT table is generated.

[0082] In this embodiment, in the process of generating a test sequence, a method combining a deterministic traversal algorithm and a Monte Carlo random sampling algorithm is adopted. The deterministic traversal algorithm ensures that each voltage point is tested by traversing all index positions in the FRT table, which can ensure the comprehensiveness and accuracy of the test, but may result in low test efficiency due to too many test points. The Monte Carlo random sampling algorithm is a randomized method. By randomly selecting voltage points in the FRT table for testing, a representative sample of the overall voltage distribution can be obtained at fewer test points, which can improve test efficiency, but some voltage points may be missed due to randomness. By combining these two algorithms, the test efficiency can be improved while ensuring the comprehensiveness of the test. The generated test sequence can cover all voltage combinations in the FRT table, providing comprehensive input for subsequent test operations.

[0083] In this disclosure, by combining a deterministic traversal algorithm with a Monte Carlo random sampling algorithm to generate a test sequence, a test sequence that fully covers the voltage combinations in the FRT table can be effectively generated. This not only ensures the comprehensiveness and accuracy of the test, but also improves test efficiency, thereby providing strong support for subsequent test operations.

[0084] In another embodiment, step S102 “determine a test mode based on a test sequence” includes:

[0085] Parse the test sequence to determine the test parameters corresponding to each data in the test sequence; the test parameters include the error annotation mode corresponding to the data, and the error annotation mode includes index error annotation and global error annotation;

[0086] Based on the injection error pattern, the test pattern is determined.

[0087] In this embodiment, in the process of determining the test mode, it is first necessary to parse the test sequence. The test sequence contains multiple data points, and each data point has corresponding test parameters. These test parameters include the error annotation mode corresponding to the data point, and the error annotation mode is divided into index error annotation and global error annotation. Index error annotation refers to error annotation for a specific index in the FRT table. This method can accurately test one or some specific voltage points in the FRT table; global error annotation is to perform comprehensive error annotation on all voltage points in the FRT table. This method can more widely cover the voltage combinations in the FRT table.

[0088] In this embodiment, after parsing the test parameters in the test sequence, the test mode can be determined based on the error injection mode. If the error injection mode is indexed, the test mode will be indexed; if the error injection mode is global, the test mode will be global. The index mode is suitable for situations requiring detailed analysis and verification of specific voltage points, while the global mode is suitable for situations requiring a comprehensive evaluation of the SSD driver error correction logic's performance under various voltage conditions.

[0089] In this disclosure, by parsing the test sequence, determining the test parameters corresponding to each data point, and determining the test mode based on the error injection pattern, the appropriate test mode can be effectively selected and implemented. This not only ensures the pertinence and effectiveness of the test operation, but also improves the accuracy and reliability of the test, thereby providing strong support for subsequent test operations.

[0090] In another embodiment, before step S103 of “reading a corresponding voltage offset in an FRT table based on a test mode and a test sequence”, a test method based on an FRT table further includes:

[0091] In response to the test mode being the index mode, the voltage offset corresponding to the current data in the test sequence is adjusted through the register mapping space in the FRT table.

[0092] In this embodiment, when the test mode is the index mode, it is necessary to adjust the voltage offset corresponding to the current data in the test sequence through the register mapping space in the FRT table. The register mapping space is a mechanism for dynamically modifying the voltage value in the FRT table. Through this mechanism, the voltage value in the FRT table can be dynamically adjusted as needed during the test process. In index mode, the process of adjusting the voltage offset is performed for a specific index in the FRT table. This method can accurately test one or some specific voltage points in the FRT table. In one example, for a test data in the FRT table, if its original test parameters are: index 0, offset 0V; in the register mapping space, there is: register 0: change the voltage offset of index 0 from 0V to +0.1V, then the test data in the adjusted FRT table is: index 0, offset +0.1V.

[0093] In this disclosure, by adjusting the voltage offset corresponding to the current data in the test sequence through the register mapping space in index mode, it is possible to effectively simulate the reading of NAND flash memory under different voltage conditions, thereby triggering the error correction logic in the SSD driver. This not only ensures the targetedness and effectiveness of the test, but also improves the accuracy and reliability of the test, providing strong support for subsequent test operations.

[0094] In another embodiment, before step S103 of “reading a corresponding voltage offset in an FRT table based on a test mode and a test sequence”, a test method based on an FRT table further includes:

[0095] In response to the test mode being the global mode, a pseudo-random number generator is used to adjust all voltage offsets in the FRT table.

[0096] In this embodiment, when the test mode is the global mode, a pseudo-random number generator is required to adjust all voltage offsets in the FRT table, and the adjustment trend can be performed based on a Gaussian distribution or a uniform distribution. A pseudo-random number generator is an algorithm that can generate pseudo-random numbers, and this algorithm can be used to randomly adjust the voltage offsets in the FRT table during the test. In the global mode, the process of adjusting the voltage offset is performed for all voltage points in the FRT table. This method can cover the voltage combinations in the FRT table more widely. By using a pseudo-random number generator for adjustment, the reading of the NAND flash memory under the condition of global threshold voltage drift can be simulated, thereby triggering the error correction logic in the SSD driver.

[0097] In this disclosure, by using a pseudo-random number generator in global mode to adjust all voltage offsets in the FRT table, the present invention effectively simulates NAND flash memory reads under global threshold voltage drift, thereby triggering the error correction logic in the SSD driver. This method not only ensures the comprehensiveness and randomness of the test, but also improves the accuracy and reliability of the test, providing strong support for subsequent test operations.

[0098] Figure 3 The following is a flow chart showing a test method based on FRT table according to an embodiment of the present disclosure. Figure 3 ,like Figure 3 As shown, a testing method based on an FRT table further includes:

[0099] Step S301: FRT read, that is, read the corresponding voltage offset in the FRT table.

[0100] Step S302, NAND data. That is, based on the voltage offset, target data is read from the NAND flash memory of the solid-state drive (SSD). The NAND data is also the target data.

[0101] Step S303: hard decoding, that is, performing low-density parity check code LDPC hard decoding on the target data.

[0102] If the verification passes, that is, the hard decoding is successful, then the “record hard decoding times” in step S304 is executed, that is, the hard decoding times are counted.

[0103] If the check fails, that is, the hard decoding is unsuccessful, the target data is re-LDPC hard-decoded until the hard decoding is successful, and the number of hard decodings is counted.

[0104] If the number of hard decoding times exceeds the first threshold, step S305 is executed to reread the FRT. That is, based on the test sequence, a new voltage offset is read from the FRT table, and target data is read from the NAND flash memory of the solid-state drive (SSD) based on the new voltage offset until the target data is successfully hard-decoded or the number of FRT table reread times exceeds the second threshold.

[0105] In this embodiment, after reading the target data from the NAND flash memory, it is necessary to perform low-density parity-check (LDPC) hard decoding on the target data. LDPC hard decoding is a decoding method that uses hard decision making to determine the value of each encoded bit. During the hard decoding process, the received signal or LLR value is thresholded. Any signal above a specific threshold is considered 1, and any signal below the threshold is considered 0. By performing LDPC hard decoding, it is possible to preliminarily assess whether there are errors in the target data and attempt to correct these errors. The number of hard decodes is an important parameter, reflecting the probability that the target data can be successfully recovered through hard decoding under specific voltage conditions.

[0106] In this embodiment, if the number of hard decoding attempts is less than a first threshold and the hard decoding is unsuccessful, LDPC hard decoding of the target data needs to be performed again. The first threshold is a preset value that limits the number of hard decoding attempts. By re-performing hard decoding, errors in the target data can be corrected under different conditions. Each re-hard decoding requires rereading the target data based on the voltage offset in the FRT table until the hard decoding is successful. During this process, the number of hard decoding attempts needs to be counted. This parameter can reflect the probability that the target data can be successfully recovered through hard decoding under specific voltage conditions.

[0107] In this embodiment, if the number of hard decodings is greater than the first threshold, it is necessary to re-read the new voltage offset in the FRT table based on the test sequence, and read the target data from the NAND flash memory based on the new voltage offset. This process is to try to correct errors in the target data under different voltage conditions. The number of rereads of the FRT table is an important parameter, which reflects the number of times the target data needs to be reread under specific voltage conditions. By rereading the target data, it is possible to try to correct errors in the target data under different voltage conditions until the target data is hard-decoded successfully or the number of rereads of the FRT table is greater than the second threshold. The second threshold is a preset value used to limit the number of rereads of the FRT table.

[0108] In this disclosure, by performing LDPC hard decoding on target data and performing corresponding operations based on the number of hard decoding attempts and results, it is possible to effectively assess the error conditions of the target data and attempt to correct these errors. This not only improves the accuracy and reliability of error correction logic testing, but also provides strong support for subsequent error correction operations, thereby improving the effectiveness of the entire testing process.

[0109] In another embodiment, after step S305, a testing method based on an FRT table further includes:

[0110] In response to the target data being hard-decoded successfully after the new voltage offset is re-read from the FRT table, the number of hard decoding times and the number of re-readings of the FRT table are counted.

[0111] Step S306: soft decoding. That is, in response to the number of rereads of the FRT table being greater than the second threshold, LDPC soft decoding is performed on the target data until the soft decoding is successful, and the number of soft decodings is counted.

[0112] In this embodiment, if the target data is successfully hard-decoded after rereading the new voltage offset from the FRT table, the number of hard decodes and the number of FRT table rereads are counted. The number of hard decodes reflects the probability that the target data can be successfully recovered through hard decoding under specific voltage conditions. The number of FRT table rereads reflects the number of times the target data needs to be reread under specific voltage conditions. By counting these parameters, the error status of the target data can be more accurately assessed, providing more accurate information for subsequent error correction operations.

[0113] In this embodiment, if the number of rereads of the FRT table is greater than the second threshold, LDPC soft decoding is required for the target data. LDPC soft decoding is a method for decoding LDPC codes using soft information from the received signal. Soft decoding can be triggered after hard decoding fails, attempting to correct errors in the target data by utilizing soft information. The number of soft decoding attempts is an important parameter that reflects the probability that the target data can be successfully recovered through soft decoding under specific voltage conditions. By counting the number of soft decoding attempts, the error condition of the target data can be more accurately assessed, providing more accurate information for subsequent error correction operations.

[0114] In this disclosure, by counting the number of hard decodes and the number of FRT table rereads when hard decoding is successful, and performing LDPC soft decoding and counting the number of soft decodes when the number of FRT table rereads exceeds a second threshold, it is possible to more accurately assess the error status of the target data and provide more accurate information for subsequent error correction operations. This not only improves the accuracy and reliability of error correction logic testing, but also provides strong support for subsequent error correction operations, thereby improving the effectiveness of the entire testing process.

[0115] In another embodiment, a testing method based on an FRT table further includes:

[0116] Determine the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine;

[0117] The test completeness is determined based on the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine.

[0118] In this embodiment, during the test, it is necessary to determine the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine. The number of LDPC state transition paths refers to the number of successfully triggered LDPC decoder state transitions during the test. The total number of state paths defined by the NFC fault-tolerant state machine refers to the total number of all possible state transition paths defined in the NFC fault-tolerant state machine. By determining these two parameters, the completeness of the test can be assessed, that is, whether the test covers all possible error correction logic state transitions.

[0119] In one example, the state machine of the LDPC decoder can be defined first, including all possible states and transitions between states. For example, the states may include "initialization", "hard decoding", "soft decoding", "error correction success", "error correction failure", etc.; during the test, each state transition is recorded; for example, from "initialization" to "hard decoding", from "hard decoding" to "soft decoding", from "soft decoding" to "error correction success", etc.; then the number of all successful state transition paths from error detection to successful error correction is counted. For example, if in a test, the LDPC decoder successfully experiences 10 paths from "initialization" to "hard decoding" to "soft decoding" and finally to "error correction success", the number of successfully triggered LDPC state transition paths is 10.

[0120] In another example, an NFC fault-tolerant state machine can be defined, including all possible states and transitions between them. For example, states may include "initialization," "FRT reread," "LDPC hard decoding," "LDPC soft decoding," "error correction successful," and "error correction failed." Based on the state machine definition, the number of all possible state transition paths can be calculated. For example, if the NFC fault-tolerant state machine has five states, each with two possible transitions, the total number of state paths is 5 × 2 = 10.

[0121] In this embodiment, the completeness of the test is determined based on the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine. Test completeness refers to whether the test covers all possible error-correction logic state transitions. The completeness of the test can be quantitatively assessed by calculating the ratio of the number of successfully triggered LDPC state transition paths to the total number of state paths defined by the NFC fault-tolerant state machine. A higher ratio indicates better test completeness, meaning that the test more comprehensively covers all possible error-correction logic state transitions.

[0122] In an example, assuming that in a test, the number of successfully triggered LDPC state transition paths is 10, and the total number of state paths defined by the NFC fault-tolerant FSM is 20, the test completeness is: 10 / 20 = 0.5

[0123] In this disclosure, by determining the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine, and based on these two parameters, determining the completeness of the test, it is possible to more accurately assess the effectiveness and reliability of the test. This not only improves the accuracy and reliability of the test, but also provides strong support for subsequent test optimization and improvement, thereby improving the quality and efficiency of the entire test process.

[0124] Figure 4 FIG. 1 shows a schematic diagram of a structure of a test device based on an FRT table according to an embodiment of the present disclosure. Figure 4 As shown, a test device based on an FRT table includes:

[0125] A generation module 10 is used to generate a test sequence; the test sequence can cover the voltage combinations in the FRT table; a first determination module 11 is used to determine a test mode based on the test sequence; the test mode is an index mode or a global mode; a first reading module 12 is used to read the corresponding voltage offset in the FRT table based on the test mode and the test sequence; a second reading module 13 is used to read target data from the NAND flash memory of the solid-state drive (SSD) based on the voltage offset; a second determination module 14 is used to determine a test result based on the read status of the target data; the read status includes the number of rereads of the FRT table, the number of hard decodings of the target data, the number of soft decodings of the target data, and the data recovery delay.

[0126] In another embodiment, the generation module 10 is further used to: construct a two-dimensional parameter space corresponding to the FRT table; write the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table; and generate a test sequence that can cover the voltage combinations in the FRT table based on the voltage combinations in the FRT table.

[0127] In another embodiment, the generation module 10 is also used to: determine the index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points; determine the voltage offset dimension corresponding to each adjustable voltage point; the voltage offset dimension represents the maximum offset range of the adjustable voltage point; based on the index dimension and the voltage offset dimension, construct a two-dimensional parameter space corresponding to the FRT table.

[0128] In another embodiment, the generation module 10 is further used to: write the reference voltage offset set into the two-dimensional parameter space; establish a register mapping space of the FRT table to obtain the FRT table; and the register mapping space is used to dynamically modify the voltage value in the FRT table.

[0129] In another embodiment, the generating module 10 is further configured to generate a test sequence capable of covering the voltage combinations in the FRT table based on a deterministic traversal algorithm and a Monte Carlo random sampling algorithm.

[0130] In another embodiment, the first determination module 11 is further used to: parse the test sequence to determine the test parameters corresponding to each data in the test sequence; the test parameters include the error annotation mode corresponding to the data, and the error annotation mode includes index error annotation and global error annotation; based on the error annotation mode, determine the test mode.

[0131] In another embodiment, a test device based on an FRT table further includes an adjustment module configured to adjust a voltage offset corresponding to current data in a test sequence through a register mapping space in the FRT table in response to the test mode being an index mode.

[0132] In another embodiment, the adjustment module is further configured to: in response to the test mode being the global mode, use a pseudo-random number generator to adjust all voltage offsets in the FRT table.

[0133] In another embodiment, a test device based on an FRT table further includes: a test module for performing low-density parity-check code LDPC hard decoding on target data; in response to the number of hard decoding being less than a first threshold and the hard decoding being unsuccessful, re-performing LDPC hard decoding on the target data until the hard decoding is successful, and counting the number of hard decoding times; in response to the number of hard decoding being greater than the first threshold, re-reading a new voltage offset in the FRT table based on a test sequence, and reading the target data from the NAND flash memory of the solid-state drive (SSD) based on the new voltage offset, until the target data is hard-decoded successfully or the number of rereads of the FRT table is greater than a second threshold.

[0134] In another embodiment, the test module is further used to: in response to the target data being hard-decoded successfully after re-reading the new voltage offset in the FRT table, count the number of hard decoding times and the number of rereadings of the FRT table; in response to the number of rereadings of the FRT table being greater than a second threshold, perform LDPC soft decoding on the target data until the soft decoding is successful, and count the number of soft decoding times.

[0135] In another embodiment, the test module is further used to: determine the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine; and determine the test completeness based on the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine.

[0136] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0137] Figure 5A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0138] like Figure 5 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0139] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0140] The computing unit 801 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a test method based on an FRT table. For example, in some embodiments, a test method based on an FRT table can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the test method based on the FRT table described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute a testing method based on an FRT table in any other appropriate manner (eg, by means of firmware).

[0141] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0142] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0143] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0144] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0145] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0146] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0147] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of this disclosure can be achieved, and this document is not limited here.

[0148] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0149] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A testing method based on FRT table, characterized in that: The method comprises: Generate a test sequence; the test sequence can cover the voltage combination in the FRT table; Determine a test mode based on the test sequence; the test mode is an index mode or a global mode; Based on the test mode and the test sequence, reading a corresponding voltage offset in an FRT table; Reading target data from a NAND flash memory of a solid-state drive (SSD) based on the voltage offset; A test result is determined based on a read status of the target data; the read status includes the number of rereads of the FRT table, the number of hard decodings of the target data, the number of soft decodings of the target data, and a data recovery delay.

2. The method according to claim 1, characterized in that The generating of the test sequence comprises: Construct the two-dimensional parameter space corresponding to the FRT table; Writing the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table; Based on the voltage combinations in the FRT table, a test sequence capable of covering the voltage combinations in the FRT table is generated.

3. The method according to claim 2, characterized in that The two-dimensional parameter space corresponding to the FRT table is constructed, including: Determine an index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points; Determining a voltage offset dimension corresponding to each of the adjustable voltage points; the voltage offset dimension represents a maximum offset range of the adjustable voltage point; Based on the index dimension and the voltage offset dimension, a two-dimensional parameter space corresponding to the FRT table is constructed.

4. The method according to claim 2, characterized in that Writing the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table includes: Writing a reference voltage offset set into the two-dimensional parameter space; A register mapping space of an FRT table is established to obtain the FRT table; the register mapping space is used to dynamically modify the voltage value in the FRT table.

5. The method according to claim 2, characterized in that The generating, based on the voltage combinations in the FRT table, a test sequence capable of covering the voltage combinations in the FRT table, comprises: Based on the deterministic traversal algorithm and the Monte Carlo random sampling algorithm, a test sequence that can cover the voltage combinations in the FRT table is generated.

6. The method according to claim 1, characterized in that The determining of a test mode based on the test sequence includes: Parsing the test sequence to determine test parameters corresponding to each data in the test sequence; the test parameters include an error injection mode corresponding to the data, and the error injection mode includes index error injection and global error injection; The test mode is determined based on the misinjection mode.

7. The method according to claim 1, characterized in that Before reading the corresponding voltage offset in the FRT table based on the test mode and the test sequence, the method further includes: In response to the test mode being the index mode, the voltage offset corresponding to the current data in the test sequence is adjusted through the register mapping space in the FRT table.

8. The method according to claim 1, characterized in that Before reading the corresponding voltage offset in the FRT table based on the test mode and the test sequence, the method further includes: In response to the test mode being the global mode, a pseudo-random number generator is used to adjust all voltage offsets in the FRT table.

9. The method according to claim 1, characterized in that After reading the target data from the NAND flash memory of the solid-state drive (SSD) based on the voltage offset, the method further includes: Performing low-density parity check code LDPC hard decoding on the target data; In response to the number of hard decoding being less than a first threshold and the hard decoding being unsuccessful, re-performing LDPC hard decoding on the target data until the hard decoding is successful, and counting the number of hard decoding times; In response to the number of hard decodings being greater than a first threshold, a new voltage offset is re-read from the FRT table based on the test sequence, and target data is read from the NAND flash memory of the solid-state drive (SSD) based on the new voltage offset until the target data is hard-decoded successfully or the number of rereads of the FRT table is greater than a second threshold.

10. The method according to claim 9, characterized in that The method further comprises: In response to the target data being hard-decoded successfully after the new voltage offset is re-read from the FRT table, the number of hard decodings and the number of re-reads of the FRT table are counted; In response to the number of rereads of the FRT table being greater than a second threshold, LDPC soft decoding is performed on the target data until the soft decoding is successful, and the number of soft decodings is counted.

11. The method according to claim 1, wherein The method further comprises: Determine the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine; The test completeness is determined based on the number of successfully triggered LDPC state transition paths and the total number of state paths defined by the NFC fault-tolerant state machine.

12. A test device based on FRT table, characterized in that: The device comprises: A generation module, configured to generate a test sequence; the test sequence can cover the voltage combinations in the FRT table; A first determining module is configured to determine a test mode based on the test sequence; the test mode is an index mode or a global mode; A first reading module is configured to read a corresponding voltage offset in an FRT table based on the test mode and the test sequence; A second reading module is configured to read target data from a NAND flash memory of a solid-state drive (SSD) based on the voltage offset; The second determination module is used to determine the test result based on the read status of the target data; the read status includes the number of rereads of the FRT table, the number of hard decoding times of the target data, the number of soft decoding times of the target data and the data recovery delay.

13. The device according to claim 12, characterized in that The generation module is further configured to: Construct the two-dimensional parameter space corresponding to the FRT table; Writing the reference voltage offset set into the two-dimensional parameter space to obtain the FRT table; Based on the voltage combinations in the FRT table, a test sequence capable of covering the voltage combinations in the FRT table is generated.

14. The device according to claim 13, characterized in that The generation module is further configured to: Determine an index dimension corresponding to the FRT table; the index dimension corresponds to N adjustable voltage points; Determining a voltage offset dimension corresponding to each of the adjustable voltage points; the voltage offset dimension represents a maximum offset range of the adjustable voltage point; Based on the index dimension and the voltage offset dimension, a two-dimensional parameter space corresponding to the FRT table is constructed.

15. The device according to claim 13, characterized in that The generation module is further configured to: Writing a reference voltage offset set into the two-dimensional parameter space; A register mapping space of an FRT table is established to obtain the FRT table; the register mapping space is used to dynamically modify the voltage value in the FRT table.

16. The device according to claim 13, characterized in that The generation module is further configured to: Based on the deterministic traversal algorithm and the Monte Carlo random sampling algorithm, a test sequence that can cover the voltage combinations in the FRT table is generated.

17. The device according to claim 12, characterized in that The first determining module is further configured to: Parsing the test sequence to determine test parameters corresponding to each data in the test sequence; the test parameters include an error injection mode corresponding to the data, and the error injection mode includes index error injection and global error injection; The test mode is determined based on the misinjection mode.

18. The device according to claim 12, characterized in that The device further includes an adjustment module, configured to: In response to the test mode being the index mode, the voltage offset corresponding to the current data in the test sequence is adjusted through the register mapping space in the FRT table.

19. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1-11.

Images