Analog fast automatic gain control circuit for trans-impedance amplifier

Abstract

The invention discloses an analog fast automatic gain control circuit for a transimpedance amplifier, which belongs to the field of optical communication transimpedance amplifiers, and adopts the technical scheme that a gain compensation unit is introduced into a feedback loop, the analog fast automatic gain control circuit comprises an operational amplifier A2, a resistor R2, an MOS (Metal Oxide Semiconductor) tube M1, an MOS tube M2, a resistor R1, a current source, an MOS tube M3, a resistor R3 and a capacitor C2, the equivalent resistance of the MOS tube M1 is reduced when the MOS tube M1 works in a linear region, and the equivalent resistance of the MOS tube M2 is reduced when the MOS tube M2 works in a linear region; under the synergistic effect of the source negative feedback circuit, the transconductance reduction of the controlled gain adjusting element is compensated, so that the open-loop gain stability of an automatic gain control loop is maintained; according to the scheme, the problem that the response time is inconsistent when the amplitude of the input signal is changed in the traditional analog automatic gain control is solved, the loop response time is consistent under different input amplitudes, the design upper limit of the circuit response speed is remarkably improved, meanwhile, the defect that the output amplitude is suddenly changed when a digital gain control scheme is switched is avoided, and the circuit reliability is improved. And the output stability and the high-speed performance are ensured.

Description

Technical Field

[0001] The present invention relates to the field of optical communication transimpedance amplifiers, and in particular to an analog fast automatic gain control circuit for a transimpedance amplifier. Background Art

[0002] In the application of transimpedance amplifiers in optical communications, since the input signal amplitude varies greatly, a gain control circuit is required to adjust the gain of the transimpedance amplifier to adapt to the input signal amplitude and avoid the output signal amplitude being too large, causing the circuit to operate in an undesirable working area.

[0003] Because manual gain control is cumbersome, transimpedance amplifiers typically have built-in automatic gain control, which controls gain by detecting signal amplitude. This creates a feedback loop. Due to the existence of the feedback loop, loop stability must be considered during design; excessively fast response speeds can lead to loop instability.

[0004] The automatic gain control function will not start until the input signal amplitude reaches a certain level. The transimpedance gain it controls decreases as the input signal amplitude increases. When it first starts, the transimpedance gain is relatively large, and its loop stability is the worst. It is necessary to ensure the loop stability when the automatic gain control loop is turned on. When the input signal amplitude increases, the MOS tube that controls the Rf in the transimpedance enters the linear region and the gain decreases. The smaller the loop open-loop gain, the longer the loop response time will be. Figure 1 .

[0005] In existing transimpedance amplifiers, some applications do not require circuit settling time. The main pole of the automatic gain control loop stability of the transimpedance amplifier can be controlled to an extremely low level, thereby achieving reliable stability at the expense of response speed.

[0006] Some applications have high requirements for the circuit operating point establishment time and need to establish it quickly. In the analog automatic gain control solution, when the input signal amplitude changes, the transimpedance gain of the transimpedance amplifier will be adaptively adjusted accordingly. The open-loop gain of the automatic gain control circuit loop will also change with the change of the device state in the loop. Figure 1 After the MOS tube M1 is turned on, the gain formed by the resistor RF will change with the state of the MOS tube M1, and then the response of the loop will slow down as the open-loop gain of the loop decreases. The voltage response is as follows: Figure 4 As shown in the figure, due to the transmission rate limitations of existing analog AGCs, fast-response transimpedance amplifiers use digital automatic gain control. Digital gain control offers significant advantages in response speed, but its output amplitude suddenly decreases during gain switching, making it unsuitable for higher-speed linear transimpedance amplifiers. Summary of the Invention

[0007] In view of the above-mentioned deficiencies in the prior art, the present invention provides an analog fast automatic gain control circuit for a transimpedance amplifier.

[0008] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: An analog fast automatic gain control circuit for a transimpedance amplifier includes an existing gain control loop and a gain compensation unit added to the existing gain notification loop. The gain compensation unit is configured to compensate for gain variations of a controlled gain adjustment element to maintain a stable open-loop gain of the automatic gain control loop, thereby ensuring that the loop response time is consistent under different input signal amplitudes.

[0009] Furthermore, the gain compensation unit includes an operational amplifier A2, a resistor R2, a MOS transistor M1, a MOS transistor M2, a resistor R1, a current source, a MOS transistor M3, a resistor R3, and a capacitor C2; wherein the operational amplifier A2 is connected to the digital logic module; the resistor R2 is connected to the MOS transistor M1, the operational amplifier A2, and the MOS transistor M2; the MOS transistor M1 is connected to the resistor R2 and the MOS transistor M2; the MOS transistor M2 is connected to the resistor R2, the operational amplifier A2, the MOS transistor M1, and the resistor R1; the resistor R1 is connected to the MOS transistor M2, the MOS transistor M3, and the resistor R3; the current source is connected to the resistor R1; the MOS transistor M3 is connected to the resistor R1, the MOS transistor M2, the resistor R3, and the capacitor C2; the resistor R3 is connected to the MOS transistor M3, the resistor R1, the MOS transistor M2, and the capacitor C2; and the capacitor C2 is connected to the MOS transistor M3 and the resistor R3.

[0010] Furthermore, the MOS transistor M1 acts as a gain compensation element, and its equivalent resistance decreases when operating in the linear region, thereby increasing the gain of the source-level negative feedback circuit composed of the resistor R1, the MOS transistor M2, the resistor R2, and the MOS transistor M1, to offset the gain reduction caused by the reduced transconductance of the MOS transistor M1. The MOS transistor M1 is connected in parallel with the resistor R2, and the change in its equivalent resistance is opposite to the gain change of the controlled gain adjustment element.

[0011] Furthermore, the MOS transistor M3 acts as a reset switch, and reduces the filtering time constant after being turned on; the resistor R3 is connected in parallel with the MOS transistor M3 and forms a main pole of the automatic gain control loop with the capacitor C2; when the MOS transistor M3 is turned on, the main pole moves toward the high frequency; and the capacitor C2 is used for filtering.

[0012] Furthermore, the operational amplifier A2 is configured to output a boosted voltage when the input signal voltage vin is lower than the reference voltage VREF, controlling the MOS tube M2 to turn on to form a feedback loop; the digital logic module is used to detect the logic output state; and the current source provides a bias current.

[0013] The present invention has the following beneficial effects: The automatic gain control of the present invention has stability and fast response. By detecting and compensating the gain of the automatic gain control loop, its gain change is offset by the change of the controlled transimpedance gain, ensuring that the response characteristics of the automatic gain control loop are consistent at different transimpedance gains, and improving the design upper limit of the slowest response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of an automatic gain control loop in the prior art.

[0015] Figure 2 Schematic diagram of the automatic gain control circuit of the present invention.

[0016] Figure 3 The present invention is an embodiment of a conventional automatic gain control circuit.

[0017] Figure 4 Response of the traditional architecture to the automatic gain control signal at different input amplitudes.

[0018] Figure 5 This is the response of the patented structure of the present invention to the automatic gain control signal under different input amplitudes. DETAILED DESCRIPTION

[0019] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0020] An analog fast automatic gain control circuit for a transimpedance amplifier includes an existing gain control loop and a gain compensation unit added to the existing gain notification loop. The gain compensation unit is configured to compensate for gain variations of a controlled gain adjustment element to maintain a stable open-loop gain of the automatic gain control loop, thereby ensuring that the loop response time is consistent under different input signal amplitudes.

[0021] like Figure 2As shown, the gain compensation unit includes an operational amplifier A2, a resistor R2, a MOS transistor M1, a MOS transistor M2, a resistor R1, a current source, a MOS transistor M3, a resistor R3, and a capacitor C2; wherein the operational amplifier A2 is connected to the digital logic module; the resistor R2 is connected to the MOS transistor M1, the operational amplifier A2, and the MOS transistor M2; the MOS transistor M1 is connected to the resistor R2 and the MOS transistor M2; the MOS transistor M2 is connected to the resistor R2, the operational amplifier A2, the MOS transistor M1, and the resistor R1; the resistor R1 is connected to the MOS transistor M2, the MOS transistor M3, and the resistor R3; the current source is connected to the resistor R1; the MOS transistor M3 is connected to the resistor R1, the MOS transistor M2, the resistor R3, and the capacitor C2; the resistor R3 is connected to the MOS transistor M3, the resistor R1, the MOS transistor M2, and the capacitor C2; and the capacitor C2 is connected to the MOS transistor M3 and the resistor R3.

[0022] Figure 2 Chinese vin is Figure 1 Output signal of the AGC pre-stage. When the photodiode does not generate light, the Vin level is higher than VREF, amplifier A2 outputs a high level, and Vout1 outputs a low level.

[0023] when Figure 1 When the photodiode generates current, the first stage output drops, and Figure 2 The price of vin is declining. Figure 2 In the case of vin being lower than VREF, the amplifier A2 will be activated. When the voltage of Vout1 is high enough, Figure 1 M1 is turned on, and a feedback loop is formed.

[0024] Figure 1 The middle resistor Rf and MOS tube M1 are connected in parallel. Figure 2 The resistor R2 and MOS tube M1 are connected in parallel. Figure 1 When the current generated by the photodiode is large enough, Figure 1 Middle MOS tube M1 and Figure 2 The MOS tube M1 in the middle will be turned on at the same time. When the MOS tube M1 in the two figures enters the linear region, Figure 1 The MOS tube M1 in the middle will reduce its own transconductance, resulting in a decrease in loop gain. Figure 2 The role of M1 is a degenerate resistor. When working in the linear region, its equivalent resistance will become smaller, which will increase the source level negative feedback circuit formed by it ( Figure 2 The MOS transistor M1 in both figures has an opposite effect on the gain of the automatic gain control loop, which has a canceling effect. This keeps the gain of the entire automatic gain control loop relatively stable, and its response time varies little under different transimpedance gains.

[0025] If adopted Figure 3 The integrator in the AGC is used as the voltage control. Figure 1 After the middle MOS tube M1 enters the linear region, its transconductance decreases, and the loop open-loop gain also decreases accordingly. The loop response speed decreases as the MOS tube gate voltage increases (MOS tube transconductance decreases).

[0026] like Figure 1 As shown, the external photodiode generates photocurrent after receiving light, and the current is input into the TIA, converted by resistor R1 (Rf) and output as a voltage signal; the converted voltage signal is used as the input signal of the automatic gain control circuit 4 (AGC) ( Figure 2 vin), and the reference level ( Figure 2 VREF) and outputs the control voltage ( Figure 2 vout1) to adjust Figure 1 The on-resistance of the MOS tube M1 in the middle. When the TIA input current increases to a certain level, the AGC control Figure 1 The middle MOS tube M1 is turned on and connected in parallel with the resistor Rf to reduce the equivalent feedback transresistance and prevent the output voltage from being too large, causing the circuit to operate in an undesirable area.

[0027] exist Figure 1 The larger the current generated by the photodiode, Figure 2 The lower the vin voltage is, when the vin voltage is lower than VREF, the amplifier A2 starts to work, the amplifier output voltage becomes lower, and the Vout1 voltage increases. When the Vout1 voltage is higher, it will control Figure 1 The middle MOS tube M1 is turned on to prevent the vin voltage from being too low, thus forming a feedback loop.

[0028] Figure 2 Capacitor C2 primarily functions as a filter. Resistor R3, connected in parallel with MOS transistor M3, forms the main pole of the automatic gain control loop with capacitor C2. Because the circuit requires fast settling time, MOS transistor M3 is added as a switch. Turning on MOS transistor M3 at specific times reduces the filtering time constant and improves chip response speed. When MOS transistor M3 is turned on, the loop's main pole shifts toward higher frequencies, but this reduces overall loop stability.

[0029] When the loop is first formed, Figure 1 The middle MOS tube M1 is still in the saturation region, at which point the loop gain is maximum and most prone to instability. In order to consider the loop stability, Figure 2 The switch resistance cannot be made too small to avoid the main pole being too high. If the main pole remains unchanged and there is no other treatment, when Figure 1 After the middle MOS tube M1 enters the linear region, the open-loop gain of the feedback loop will become lower. The lower the open-loop gain, the slower the loop response speed.

[0030] Figure 2 Feedback MOS tube M1 is introduced. Figure 1 After the middle MOS tube M1 is turned on and the AGC forms a feedback loop with other circuits, Figure 1 M1 will also be turned on. Figure 2 When the Vout1 voltage increases, Figure 1 The gain of the middle MOS tube M1 decreases. Figure 2 MOS transistor M1 in the middle acts as the degeneration resistor of the source-level negative feedback circuit (R1, M2, R2, M1). A reduction in equivalent resistance increases the AGC circuit's gain. The two MOS transistors M1 in the two figures have opposite effects on the gain, canceling each other out and ensuring consistent open-loop gain across all input signals. Assuming the dominant pole and open-loop gain remain unchanged, the circuit's loop response time also remains constant.

[0031] The traditional architecture uses an integrator. Due to factors such as power consumption, area, and design ideas, its output drive is limited. Before the Tsetup time, since the control voltage is too low, the capacitor of the control voltage is driven by the current source, and the charging and discharging speed of the capacitor is consistent.

[0032] After Tsetup time, the loop starts to work because the working point begins to be established.

[0033] As above Figure 1 In the example, MOS transistor M1 is in the linear region with low gain when a large input signal is input, and in the saturation region with high gain when a small input signal is input. Therefore, the loop response time constants of the two are different. The smaller the transimpedance gain (RF and M1 in parallel), the smaller the gain of MOS transistor M1, the smaller the loop gain, and the slower the response.

[0034] The new architecture does not use current to drive the capacitor. Before the loop starts working, the capacitor is charged and discharged by the resistor. The larger the input signal, the faster the initial response speed. Figure 1 When the middle MOS tube M1 enters the linear region and reduces the loop gain, the Figure 2 The middle MOS tube M1 makes Figure 2 The middle MOS tube M1 is turned on and Figure 2 The middle resistor R2 is connected in parallel to reduce the degeneration resistance, improve the loop gain, and ensure that the loop time constant is consistent under different input amplitudes.

[0035] Specific embodiments are used in the present invention to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

[0036] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific descriptions and embodiments. Those skilled in the art can make various other specific variations and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such variations and combinations are still within the scope of protection of the present invention.

Claims

1. An analog fast automatic gain control circuit for a transimpedance amplifier, comprising an existing gain control loop, characterized in that: A gain compensation unit is added to the existing gain notification loop, wherein the gain compensation unit is configured to compensate for the gain variation of the controlled gain adjustment element to maintain the open-loop gain stability of the automatic gain control loop, thereby ensuring that the loop response time is consistent under different input signal amplitudes.

2. The analog fast automatic gain control circuit for a transimpedance amplifier according to claim 1, characterized in that: The gain compensation unit includes an operational amplifier A2, a resistor R2, a MOS transistor M1, a MOS transistor M2, a resistor R1, a current source, a MOS transistor M3, a resistor R3, and a capacitor C2; wherein the operational amplifier A2 is connected to the digital logic module; the resistor R2 is connected to the MOS transistor M1, the operational amplifier A2, and the MOS transistor M2; the MOS transistor M1 is connected to the resistor R2 and the MOS transistor M2; the MOS transistor M2 is connected to the resistor R2, the operational amplifier A2, the MOS transistor M1, and the resistor R1; the resistor R1 is connected to the MOS transistor M2, the MOS transistor M3, and the resistor R3; the current source is connected to the resistor R1; the MOS transistor M3 is connected to the resistor R1, the MOS transistor M2, the resistor R3, and the capacitor C2; the resistor R3 is connected to the MOS transistor M3, the resistor R1, the MOS transistor M2, and the capacitor C2; and the capacitor C2 is connected to the MOS transistor M3 and the resistor R3.

3. The analog fast automatic gain control circuit for a transimpedance amplifier according to claim 2, characterized in that: The MOS transistor M1 serves as a gain compensation element. When operating in the linear region, its equivalent resistance decreases, thereby increasing the gain of the source-level negative feedback circuit composed of the resistor R1, the MOS transistor M2, the resistor R2, and the MOS transistor M1, to offset the gain reduction caused by the reduced transconductance of the MOS transistor M1. The MOS transistor M1 is connected in parallel with the resistor R2, and the change in its equivalent resistance is opposite to the gain change of the controlled gain adjustment element.

4. The analog fast automatic gain control circuit for a transimpedance amplifier according to claim 2, characterized in that: The MOS transistor M3 acts as a reset switch and reduces the filtering time constant after being turned on. The resistor R3 is connected in parallel with the MOS transistor M3 and forms the main pole of the automatic gain control loop with the capacitor C2. When the MOS transistor M3 is turned on, the main pole moves toward the high frequency. The capacitor C2 is used for filtering.

5. The analog fast automatic gain control circuit for a transimpedance amplifier according to claim 2, characterized in that: The operational amplifier A2 is configured to output a boosted voltage when the input signal voltage vin is lower than the reference voltage VREF, and control the MOS transistor M2 to turn on to form a feedback loop; the digital logic module is used to detect the logic output state; and the current source provides a bias current.

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