Method and apparatus for correcting nonlinearities in transmitter

Abstract

Methods, apparatus, systems, and articles of manufacture to correct non-linearity in a transmitter are described. An example system includes: an input stage (202); a driver (204), an input terminal of the driver (204) being coupled to an output terminal of the input stage (202); an output buffer (208), an input terminal of the output buffer (208) being coupled to an output terminal of the driver (204), an output terminal of the output buffer (208) being coupled to a first input terminal of the input stage (202) via a resistor (212); and a non-linear correction circuitry (218) having an input terminal and an output terminal, the input terminal of the non-linear correction circuitry (218) being coupled to the output terminal of the output buffer (208) and the first input terminal of the input stage (202) via the resistor (212), the output terminal of the non-linearity correction circuitry (218) is coupled to the output terminal of the input stage (202) and the input terminal of the driver (204).

Description

Technical Field

[0001] The present description relates generally to circuit systems and, more particularly, to methods and apparatus for correcting nonlinearities in transmitters. Background Art

[0002] A transmitter is an electrical device that emits, projects, or outputs analog signals. Transmitters are used in a wide range of fields, including medical imaging, telecommunications, data transmission, and other fields that utilize analog signals. For example, a medical imaging device (e.g., an ultrasound device) uses a transmitter to transmit an analog ultrasound signal toward a subject (e.g., an organ). After transmitting the output analog signal, the medical imaging device obtains a reflection of the transmitted analog signal from the subject and processes the obtained reflected signal to produce an image of the subject. Summary of the Invention

[0003] To correct for nonlinearities in a transmitter, an example device includes a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor being coupled to the second current terminal of the first transistor, the first current terminal of the first transistor being coupled to a power supply terminal via a first resistor. The device also includes a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor and the second current terminal of the first transistor, the first current terminal of the second transistor being coupled to the power supply terminal via a second resistor and a capacitor. The device also includes a current source having a first terminal and a second terminal, the first terminal of the current source being coupled to the control terminals of the first and second transistors and the second current terminal of the first transistor, the second terminal of the current source being coupled to a common terminal. The device also includes a switch having a first terminal and a second terminal, the first terminal of the switch being coupled to the second current terminal of the second transistor. Other examples are described.

[0004] To correct for nonlinearities in a transmitter, an example device includes a second error current correction circuitry having a first terminal and a second terminal. The device also includes a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to the second terminal of the first error current correction circuitry, and the second terminal of the first switch coupled to the second terminal of the second error current correction circuitry. The device also includes a second switch having a first terminal and a second terminal, the first terminal of the second switch coupled to the second terminal of the first switch and the second terminal of the second error current correction circuitry, and the second terminal of the second switch coupled to a current buffer. The device also includes a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the second terminal of the first error current correction circuitry and the first terminal of the first switch, and the second terminal of the resistor coupled to a common terminal. The device also includes a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the first error current correction circuitry, the first terminal of the first switch, and the first terminal of the resistor, and the second terminal of the capacitor coupled to the second terminal of the second switch and the current buffer. Other examples are described.

[0005] To correct for nonlinearities in a transmitter, an example transmitter includes an input stage having a first input terminal, a second input terminal, and an output terminal. The transmitter also includes a driver having an input terminal and an output terminal, the input terminal of the driver being coupled to the output terminal of the input stage. The transmitter also includes an output buffer having an input terminal and an output terminal, the input terminal of the output buffer being coupled to the output terminal of the driver, the output terminal of the output buffer being coupled to the first input terminal of the input stage via a resistor. The transmitter also includes nonlinearity correction circuitry having an input terminal and an output terminal, the input terminal of the nonlinearity correction circuitry being coupled to the output terminal of the output buffer and the first input terminal of the input stage via the resistor, and the output terminal of the nonlinearity correction circuitry being coupled to the output terminal of the input stage and the input terminal of the driver. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is an example imaging scanner including transmitter circuitry in conjunction with the examples described herein.

[0007] Figure 2 yes Figure 1 Figure 2 is a diagram of an example circuit implementation of a transmitter circuit system.

[0008] Figure 3 for Figure 2 FIG. 1 is a diagram of an example circuit implementation of a nonlinear correction circuit system.

[0009] Figure 4 yes Figure 3 FIG. 1 is a diagram of an example circuit implementation of a first error current correction circuit system.

[0010] Figure 5 yes Figure 3 FIG. 1 is a diagram of an example circuit implementation of a second error current correction circuit system.

[0011] Figure 6 yes Figure 3 FIG. 1 is a diagram of an example circuit implementation of a second error current correction circuit system.

[0012] Figure 7 yes Figure 3 FIG. 1 is a diagram of an example circuit implementation of a current correction combination circuit system and a current buffer.

[0013] Figure 8 for Figure 2 FIG. 2 is a diagram of an alternative example circuit implementation of a nonlinear correction circuit system.

[0014] The use of the same reference numbers or other reference designators in the drawings indicates the same or similar features (either functionally or structurally). DETAILED DESCRIPTION

[0015] The figures are not necessarily drawn to scale. Generally, like reference numerals in the figures and in this specification refer to like or similar parts. Although the figures show regions with distinct lines and boundaries, some or all of these lines or boundaries may be idealized. In practice, boundaries or lines may be invisible, blended, or irregular.

[0016] Medical imaging devices, such as ultrasound devices, use transmitted and reflected analog signals to produce images of an object (e.g., an organ). For example, an ultrasound device uses a transmitter (also called transmitter circuitry) to transmit ultrasound pulses toward the object. After transmitting the ultrasound waves, the ultrasound device uses a receiver to obtain reflected echoes and processes the echoes to form an image of the object.

[0017] The transmitters of medical imaging devices are designed to have good second harmonic distortion (HD2) performance. HD2 is the ratio of the amplitude of the second harmonic to the amplitude of the first harmonic of the output of the medical imaging device's pulse generator, also known as the fundamental frequency. To achieve good HD2 performance, the medical imaging device selects the input frequency (e.g., fin) for the transmit signal.

[0018] As a transmitted ultrasound signal propagates through a medium, the signal attenuates within the propagation depth in proportion to the fin. The taller the fin, the higher the resolution of the object represented by the reflection. However, the deeper the signal penetrates into the object, the shallower it is. After the transmitter outputs a signal at the fin frequency, the object reflects an echo signal equal to 2*fin back to the medical imaging device.

[0019] Some transmitters include a linear amplifier to generate ultrasound waves transmitted to the subject during imaging. These amplifiers may include a signal generator to generate a low-voltage analog signal; a transconductor that creates a low impedance at a virtual ground and senses an error current; a high-voltage driver to increase the gain of the sensed error current; and an output buffer to drive the output signal. However, such transmitters can introduce undesirable nonlinearity. Nonlinearity is generated by nonlinear active devices such as transistors and capacitors, which introduce distortion into the amplifier's output signal. For example, a linear amplifier may operate with a large voltage supply (e.g., + / - 100 volts (V)) at a high load current (e.g., + / - 3 amperes (A)). Therefore, such linear amplifiers require large, high-voltage (e.g., 200V) transistors to operate with this large voltage supply. These high-voltage transistors require low quiescent current for lower power consumption. The high current drawn by the output buffer with its low quiescent current results in large nonlinear errors in the output buffer. Large transistors with low quiescent current result in a low loop bandwidth for the feedback loop that detects the error current. Therefore, the feedback loop of this transmitter is limited, slow, and inaccurate for high-bandwidth applications. The main nonlinear error in the transmitter is rectification error, because the signal current in the output buffer is much larger than the bias current in the output buffer. For example, rectification error is caused by the sourcing and sinking of high currents at the output buffer, and the mismatch between the sourcing and sinking errors.

[0020] Examples described herein provide techniques for reducing or otherwise eliminating nonlinearities in linear amplifiers. For example, the examples described herein insert signals into the linear amplifier to mitigate nonlinearities measured during manufacturing. For example, during manufacturing, transmitter nonlinearities can be measured, and signals can be input into nodes of the linear amplifier to mitigate the measured nonlinearities. The examples described herein mitigate rectified capacitive current nonlinearity error (|SCV|, where S is the complex frequency of the Laplace transform, C is the capacitance, V is the output voltage of the output stage, and SCV corresponds to the current through the capacitive element), rectified voltage capacitive current nonlinearity error (SC|V|), and squared frequency nonlinearity error (ST*|SCV|, where T is the time constant). Rectified capacitive current error is error rectification that occurs on the current in the output buffer. Error rectification can occur based on gain errors between the source and sink paths of the high-voltage driver and output buffer. Rectified voltage capacitive current nonlinearity error can occur at the high-voltage switch. The rectified voltage capacitive current nonlinearity error will be 90 degrees out of phase with the rectified capacitive current error. Frequency-squared nonlinearity error is an error magnitude proportional to the square of the frequency of the input signal. Frequency-squared nonlinearity error can occur due to delay / phase errors between the source and sink paths of the high-voltage driver and output buffer. The examples described herein result in an approximately 8 to 10 decibel (dB) improvement in linearity. Furthermore, the examples described herein improve HD2 from 40 dB relative to carrier (dBc) to 50 dBc. Although the examples described herein are described in conjunction with an image scanner, the transmitter or linear amplifier may be described in conjunction with any technology in which a transmitter or linear amplifier with nonlinearity error is used.

[0021] Figure 1 An example image scanner 100 is described. Figure 1 The image scanner 100 includes an example transducer 104 , an example transmitter (Tx) circuitry 102 , an example transmitter-receiver (T / R) switch 106 , an example receiver (Rx) analog front end 108 , an example digital signal processor (DSP) 110 , and an example display 112 . Figure 1 The image scanner 100 is a medical image scanner, such as a magnetic resonance imaging (MRI) machine, an ultrasound machine, etc. However, the image scanner 100 may be any type of image scanner or any device utilizing a Tx circuit system.

[0022] Figure 1The Tx circuit system 102 is coupled to the transducer 104 and the T / R switch 106. The Tx circuit system 102 includes a linear amplifier that amplifies the analog signal output to the transducer 104. The linear amplifier utilizes negative feedback to reduce errors in the output signal of the linear amplifier. In addition, the Tx circuit system 102 utilizes a nonlinear correction circuit system to reduce the nonlinearity of the linear amplifier implemented by the Tx circuit system 102. Figure 2 The Tx circuitry 102 is further described.

[0023] Figure 1 The transducer 104 is coupled to the Tx circuitry 102 and the T / R switch 106. The transducer 104 is a device that transmits signals and receives reflected signals to produce an image. For example, in an ultrasound system, the transducer 104 transmits signals (e.g., sound waves, ultrasonic waves, etc.) into the body. After transmitting the ultrasonic waves, the transducer 104 receives or senses the reflected waves, also known as echoes or reflected waves, which reflect off the body's tissue. In an MRI system, the transducer 104 can generate a magnetic field and detect the energy released when protons realign with the magnetic field. The transducer 104 transmits one or more analog signals corresponding to the image to the Rx analog front end 108.

[0024] Figure 1 The T / R switch 106 is coupled to the transducer 104, the Tx circuitry 102, and the Rx analog front end 108. If the Tx circuitry 102 is generating an output signal to be output by the transducer 104, the T / R switch 106 can be deactivated to form an open circuit between the transducer 104 / Tx circuitry 102 and the Rx analog front end 108. In this manner, if the Tx circuitry 102 is outputting a high-voltage analog signal to the transducer 104, the Rx analog front end 108, the DSP 110, and the display 112 are protected from the one or more high voltages output by the Tx circuitry 102. After the Tx circuitry 102 stops outputting the high-voltage analog signal to the transducer 104, the T / R switch 106 can form a short circuit between the transducer 104 and the Rx analog front end 108. In this manner, the Rx analog front end 108 can obtain an echo signal obtained at the transducer 104.

[0025] Figure 1 The Rx analog front end 108 is coupled to the T / R switch 106 and the DSP 110. The Rx analog front end 108 is an instrumentation amplifier topology that amplifies the signal from the transducer 104 and converts the analog echo signal into a digital signal. The Rx analog front end 108 outputs the amplified digital signal to the DSP 110.

[0026] Figure 1The DSP 110 is coupled to the Rx analog front end 108 and the display 112. The DSP 110 processes the digital signal from the Rx analog front end 108 to generate an image of the object sensed by the transducer 104. The DSP 110 outputs the generated image to the display 112. In addition, the DSP 110 may store the image data or any data related to the capture of the image in a storage device (e.g., a memory).

[0027] Figure 2 yes Figure 1 1 . An example implementation of transmitter circuitry 102 is shown. Transmitter circuitry 102 includes an example linear amplifier 200 and example signal generation circuitry 201. Linear amplifier 200 includes an example input stage 202, an example high voltage (HV) driver 204, an example capacitor 206, an example output stage 208, an example high voltage (HV) switch 210, example resistors 212, 214, and example nonlinear correction (NLC) circuitry 216, 218.

[0028] Figure 2 Signal generator circuitry 201 includes two terminals. A first terminal of signal generator circuitry 201 is coupled to a second input terminal of input stage 202. A second terminal of signal generator circuitry 201 is coupled to a common terminal (e.g., a ground terminal). Signal generator circuitry 201 generates an analog signal. The analog signal can be a low voltage analog signal (e.g., + / - 5V). In some examples, signal generator circuitry 201 is external to transmitter circuitry 102. In such examples, transmitter circuitry 102 includes an input terminal to obtain the analog signal from signal generation circuitry implemented external to transmitter circuitry 102.

[0029] Figure 2Input stage 202 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of input stage 202 is coupled to the second terminal of resistor 212 and the first terminal of resistor 214. The second input terminal of input stage 202 is coupled to the second terminal of signal generator circuitry 201. In some examples, the second input terminal of input stage 202 is coupled to the input terminal of NLC circuitry 216. The output terminal of input stage 202 is coupled to the input terminal of HV driver 204 and the output terminal of NLC circuitry 218. In some examples, the output terminal of input stage 202 is coupled to the output terminal of NLC circuitry 216. Input stage 202 is a transconductor that compares the voltage of the output signal output by signal generator circuitry 201 with a feedback voltage corresponding to the output signal of output stage 208. The input stage outputs a current representing the difference between the two output voltages. The output current of input stage 202 represents the error between the input signal of signal generator circuitry 201 and the output signal of output stage 208. The greater the error between the input and output signals, the greater the output current. The smaller the error between the input signal and the output signal, the smaller the output current.

[0030] Figure 2 The HV driver 204 includes an input terminal and an output terminal. The input terminal of the HV driver 204 is coupled to the output terminal of the input stage 202, the output terminal of the NLC 218, and optionally the output terminal of the NLC circuitry 216. The output terminal of the HV driver 204 is coupled to the first terminal of the HV switch 210, the first terminal of the capacitor 206, and the input terminal of the output stage 208. The HV driver 204 increases the gain (e.g., K times) of the error signal output by the input signal 202, the gain being adjusted by one or more NLC circuitry 216, 218. The amount of gain can be based on user or manufacturer preferences. The HV driver 204 outputs the amplified error signal to the output stage 208.

[0031] Figure 2 Capacitor 206 includes a first terminal and a second terminal. The first terminal of capacitor 206 is coupled to the output terminal of HV driver 204, the input terminal of output stage 208, and the first terminal of HV switch 210. The second terminal of capacitor 206 is coupled to a common terminal (e.g., a ground terminal). Capacitor 206 acts as a compensation capacitor and filters out high-frequency noise.

[0032] Figure 21. Example output stage 208 includes an input terminal and an output terminal. The input terminal of output stage 208 is coupled to the output terminal of HV driver 204, a first terminal of capacitor 206, and a first terminal of switch 210. The output terminal of output stage 208 is coupled to a first terminal of resistor 212, an input terminal of NLC circuitry 218, and transducer 104. Output stage 208 operates as a voltage buffer to drive the load of transducer 104. As further described above, HV driver 204 and output stage 208 can generate nonlinear errors (e.g., |SCV| error, SC|V| error, and ST*|SCV| error) that are reduced by NLC circuitry 216, 218.

[0033] Figure 2 The HV switch (HV SW) 210 includes a first terminal and a second terminal. The first terminal of the HV SW 210 is coupled to the output terminal of the HV driver 204, the input terminal of the output stage 208, and the first terminal of the capacitor 206. The second terminal of the HV SW 210 is coupled to a common terminal. The HV SW 210 provides glitch reduction during power-up and power-down of the image scanner 100.

[0034] Figure 2 Resistors 212 and 214 each include a first terminal and a second terminal. The first terminal of resistor 212 is coupled to the output terminal of output stage 208, the input terminal of NLC circuitry 218, and transducer 104. The second terminal of resistor 212 is coupled to the first terminal of resistor 214 and the first input terminal of input stage 202. The first terminal of resistor 214 is coupled to the second terminal of resistor 212 and the first input terminal of input stage 202. The second terminal of resistor 214 is coupled to a common terminal. Resistors 212 and 214 create a feedback path from output stage 208 to input stage 202. Furthermore, resistors 212 and 214 reduce the amplitude or voltage of output stage 208 to the amplitude of the signal output by signal generating circuitry 201. In this way, if there is no error between the input signal of signal generating circuitry 201 and the output signal of output stage 208, input stage 202 will detect zero error current and output a signal corresponding to the zero error current. However, if there is some difference between the input signal of the signal generating circuit system 201 and the output signal of the output stage 208, the input stage 202 will output a signal corresponding to the amount of the difference. As described above, the HV driver 204 increases the gain of the error signal, and the output stage 208 outputs a signal based on the amplified error signal to drive the transducer 104.

[0035] Figure 1NLC circuitry 216 is an optional component that can be implemented to mitigate some nonlinear errors. NLC circuitry 216 includes an input terminal and an output terminal. The input terminal of NLC circuitry 216 is coupled to the output terminal of signal generation circuitry 201 and the second input terminal of input stage 202. The output terminal of NLC circuitry 216 is coupled to the output terminal of input stage 202, the input terminal of HV driver 204, and the output terminal of NLC 218. NLC circuitry 216 introduces nonlinearity into the output of input stage 202 based on the input signal generated by signal generation circuitry 201 to mitigate the nonlinearity measured at the output of linear amplifier 200. For example, during manufacturing, the nonlinearity of linear amplifier 200 is determined, and the gains associated with the components of NLC circuitry 216 are adjusted based on the input signal generated by signal generator circuitry 201 to mitigate the output of input stage 202. Although NLC circuitry 216 mitigates some nonlinearity, it may not be effective for amplifiers with low bandwidth. Furthermore, the nonlinearity is a strong function of the output signal. Thus, the example NLC circuitry 218 is implemented to provide strong mitigation of nonlinearities, which is also effective for low BW amplifiers.

[0036] Figure 2 1. Example NLC circuitry 218 includes an input terminal and an output terminal. The input terminal of NLC circuitry 218 is coupled to the output terminal of output stage 208, the first terminal of resistor 212, and transducer 104. The output terminal of NLC circuitry 218 is coupled to the output terminal of input stage 202, the input terminal of HV driver 204, and optionally the output terminal of NLC circuitry 216. Figure 2 The NLC circuit system 218 generates a signal to mitigate nonlinearity based on the output of the linear amplifier 200 as part of a feedback loop. The NLC circuit system 218 generates one or more signals that mitigate different nonlinear current errors (e.g., |SCV|, SC|V|, ST*|SVC|) based on the output of the linear amplifier 200. The NLC circuit system 218 senses the high voltage output and generates a low voltage signal whose amplitude and phase are proportional to the output signal of the linear amplifier 200. The amplitude of the one or more mitigation signals is based on the gain selected during manufacturing based on the measured nonlinearity of the linear amplifier 200. Figure 3 The NLC circuitry 218 is further described.

[0037] Figure 3 yes Figure 21 is an example block diagram of NLC circuitry 216. NLC circuitry 216 includes example first error current correction circuitry 300, example second error current correction circuitry 302, example third error current correction circuitry 304, example current correction combining circuitry 306, and example current buffer 308.

[0038] Figure 3 The first error current correction circuit system 300 includes an input terminal and an output terminal. The input terminal of the first error current correction circuit system 300 is coupled to Figure 2 The output stage 208 of the first error current correction circuit system 300 is coupled to the output terminal of the current correction combination circuit system 306. In some examples, the output terminal of the first error current correction circuit system 300 is coupled to the output terminal of the second error current correction circuit system 302, the output terminal of the third error current correction circuit system 304, and the input terminal of the current buffer 308. The first error current correction circuit system 300 generates a signal corresponding to the rectified capacitive current (|SCV|) error, which is obtained from Figure 2 The gain of the first error current correction circuit system 300 can be selected to mitigate the |SCV| error after the amount of |SCV| nonlinear error is determined during manufacturing. The gain is applied to the input terminals of the HV driver 204 via the feedback path, as described above in conjunction with the first error current correction circuit system 300. Figure 2 Described below. Figure 4 The first error current correction circuitry 300 is further described.

[0039] Figure 3 The second error current correction circuit system 302 includes an input terminal and an output terminal. The input terminal of the second error current correction circuit system 302 is coupled to Figure 2output stage 208. In some instances, the output terminal of the second error current correction circuit system 302 is coupled to the current correction combination circuit system 306. In some instances, the output terminal of the second error current correction circuit system 302 is coupled to the output terminal of the first error current correction circuit system 300, the output terminal of the third error current correction circuit system 304, and the input terminal of the current buffer 308. The second error current correction circuit system 302 generates a signal corresponding to the capacitive current (SC|V|) error of the rectified voltage occurring from the HV driver 204. The error is 90 degrees out of phase with the |SCV| error. In this way, the second error current correction circuit system 302 generates a signal that is 90 degrees out of phase with the |SCV| error current. After determining the amount of SC|V| nonlinear error during manufacturing, the gain of the second error current correction circuit system 302 can be selected to mitigate the SC|V| error, and the gain is applied to the input terminal of the HV driver 204 via a feedback path, as described above in conjunction with Figure 2 Because the mitigation signals generated by the first error current correction circuit system 300 and the second error current correction circuit system 302 correspond to phases that are 90 degrees apart, the first error current correction circuit system 300 and the second error current correction circuit system 302 can mitigate any phase error by adjusting the amplitudes of the two generated mitigation signals. Figure 5 The second error current correction circuitry 302 is further described.

[0040] Figure 3 The third error current correction circuit system 304 includes an input terminal and an output terminal. The input terminal of the third error current correction circuit system 304 is coupled to Figure 2 The output terminal of the third error current correction circuit system 304 is coupled to the output terminal of the first error current correction circuit system 300, the output terminal of the second error current correction circuit system 302, and the input terminal of the current buffer 308. The third error current correction circuit system 304 generates a signal corresponding to the frequency squared (ST*|SCV|) error, which is obtained from Figure 2 The delay or phase difference between the sourcing and sinking paths of the HV driver 204 and the output stage 208 occurs, and because the amplitude is proportional to the square of the frequency. After determining the amount of the ST*|SCV| nonlinear error during manufacturing, the gain of the third error current correction circuit system 304 can be selected to mitigate the ST*|SCV| error, and the gain is applied to the input terminal of the HV driver 204 via the feedback path, as described above in conjunction with Figure 2 Described below. Figure 6 The third error current correction circuitry 304 is further described.

[0041] Figure 3The current correction combination circuit system 306 is an optional circuit system that can be implemented to eliminate the third error current correction circuit system 304 but maintain functionality. Therefore, if the current correction combination circuit system 306 is implemented, the third error current correction circuit system 304 can be removed while maintaining the functionality of the third error current correction circuit system 304. The current correction combination circuit system 306 includes an input terminal and an output terminal. The input terminal of the current correction combination circuit system 306 is coupled to the output terminal of the first error current correction circuit system 300 and the output terminal of the second error current correction circuit system 302. The output terminal of the current correction combination circuit system 306 is coupled to the input terminal of the current buffer 308. Figure 7 The current correction combination circuitry 306 is further described.

[0042] Figure 3 Current buffer 308 includes an input terminal and an output terminal. The input terminal of current buffer 308 is coupled to the output terminal of current correction combination circuitry 306. Alternatively, the input terminal of current buffer 308 may be coupled to the output terminals of error current correction circuitry 300, 302, 304. The output terminal of current buffer 308 is coupled to the output terminal of input stage 202, the input terminal of HV driver 204, and optionally, the output terminal of NLC circuitry 216. Current buffer 308 prevents the output signal from input stage 202 or the output signal from NLC circuitry 216 from entering error current correction circuitry 300, 302, 304 and current correction combination circuitry 306.

[0043] Figure 4 yes Figure 3 1 . An example circuit implementation of first error current correction circuitry 300 is shown. First error current correction circuitry 300 includes an example current rectifier 400 and an example capacitor 401. Current rectifier 400 includes a positive current rectifier 402 and a negative current rectifier 404. Positive current rectifier 402 includes transistors 406, 408, 412, resistors 410, 414, current source circuitry 411, capacitor 416, and switch 418. Negative current rectifier 402 includes transistors 420, 422, 426, resistors 424, 428, current source circuitry 425, capacitor 430, and switch 432.

[0044] Figure 4Capacitor 401 is a sensing capacitor having an input terminal and an output terminal. The input terminal of capacitor 401 is coupled to the output terminal of output stage 208, the first terminal of resistor 212, and transducer 104. The output terminal of capacitor 401 is coupled to the second current terminal of transistor 406 and the first current terminal of transistor 420. The current through capacitor 401 is represented by SCV (e.g., the complex frequency of the Laplace transform multiplied by the capacitance of capacitor 401). The sensed current is applied to current rectifier 400.

[0045] Figure 4 The current rectifier 400 includes a positive current rectifier 402 and a negative current rectifier 404. The positive current rectifier 402 generates a positive rectified signal (e.g., an absolute value signal) corresponding to the positive portion of the input current (e.g., with the negative portion set to zero). The negative current rectifier 404 generates a negative rectified signal (e.g., a negative absolute value signal) corresponding to the negative portion of the input current (e.g., with the positive portion set to zero).

[0046] Figure 4 Positive current rectifier 402 includes transistor 406 for rectifying the sensed current from capacitor 401. Transistor 406 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a drain terminal), and a second current terminal (e.g., a source terminal). The control terminal of transistor 406 is coupled to a bias current source. The bias current source provides a low quiescent current (e.g., less than 1 microampere (μA)) to bias transistor 406. The first current terminal of transistor 406 is coupled to the second current terminal of transistor 408, the control terminals of transistors 408 and 412, and the first terminal of current source circuitry 411. The second current terminal of transistor 406 is coupled to the second terminal of capacitor 401 and the first current terminal of transistor 420. Transistor 406 is an n-channel metal oxide semiconductor field effect (NMOS or N-MOSFET) transistor. However, transistor 406 can be a different type of transistor. Transistor 406 is biased based on the low quiescent current (e.g., less than 1 microampere (μA)) provided by the bias current source. Transistor 406 rectifies the sensed current to allow current to flow from a first current terminal of transistor 406 to a second current terminal of transistor 406 for a positive portion of the sensed current (eg, blocks a negative portion of the sensed current).

[0047] Figure 4Transistors 408 and 412 each include a control terminal (e.g., a gate terminal), a first current terminal (e.g., a source terminal), and a second current terminal (e.g., a drain terminal). The control terminal of transistor 408 is coupled to the control terminal of transistor 412, the second current terminal of transistor 408, the first current terminal of transistor 406, and the first terminal of current source circuitry 411. The first current terminal of transistor 408 is coupled to the second terminal of resistor 410. The second current terminal of transistor 408 is coupled to the control terminals of transistors 408 and 412, the first current terminal of transistor 406, and the first terminal of current source circuitry 411. The control terminal of transistor 412 is coupled to the control terminal of transistor 408, the second current terminal of transistor 408, the first current terminal of transistor 406, and the first terminal of current source circuitry 411. The first current terminal of transistor 412 is coupled to the second terminal of capacitor 416 and the second terminal of resistor 414. The second terminal of transistor 412 is coupled to the first terminal of switch 418. Transistors 408 and 412 are p-channel MOSFETs (e.g., PMOS transistors). However, transistors 408, 412 can be any type of transistor. Transistors 408, 412 are configured to operate as a current mirror. Thus, the current flowing from the second terminal of transistor 412 to the first terminal of switch 418 is proportional (e.g., has the same or different gain) to the current flowing from the second current terminal of transistor 408 to the first current terminal of transistor 406. Thus, if switch 418 is closed (e.g., forming a short circuit), the output current of current rectifier 400 corresponds to a positive rectified current based on the current through capacitor 401. The amount of gain corresponding to the current mirror of transistors 408, 412 is based on the capacitance of capacitor 416 and the size of transistor 412 (e.g., channel width and length). Also, a programmable capacitor can be used to adjust the capacitance of capacitor 430 for phase adjustment for trimming. The amount of capacitance or the size of transistor 412 can be selected to correspond to the amount of nonlinearity detected during manufacturing. In this way, the current output can mitigate the detected |SCV| nonlinearity. In Figure 4 、 5 , 6, 7 and 8, the diagonal arrows through the components indicate that the amount of capacitance or the size of the components can be selected to correspond to the amount of nonlinearity detected during manufacturing.

[0048] Figure 4 Current source circuitry 411 includes a first terminal and a second terminal. The first terminal of current source circuitry 411 is coupled to the control terminals of transistors 408 and 412. The second terminal of current source circuitry 411 is coupled to the second terminal of current source circuitry 425 and a common terminal. The current source circuitry pulls a small current (e.g., 100 μA) to ground to reduce the minimum current corresponding to the mirror delay of the current mirror generated by transistors 408 and 412.

[0049] Resistors 410, 414, and capacitor 416 each have a first terminal and a second terminal. The first terminal of resistor 410 is coupled to a positive power supply terminal (e.g., +5V). The second terminal of resistor 410 is coupled to a first current source of transistor 408. The first terminal of resistor 414 is coupled to the positive power supply terminal. The second terminal of resistor 410 is coupled to a first current terminal of transistor 412 and a second terminal of capacitor 416. The first current terminal of capacitor 416 is coupled to the positive power supply terminal. The second current terminal of capacitor 416 is coupled to the second terminal of resistor 414 and the first current terminal of transistor 412. The resistance of resistor 414 or the size of transistor 412 can be combined into a single unit to adjust gain. Resistor 414 also creates a phase lead. Resistors 410, 414 improve noise and matching.

[0050] Figure 4 The switch 418 includes a first terminal and a second terminal. The first terminal of the switch 418 is coupled to the second current terminal of the transistor 412. The second terminal of the switch 418 may be (for example, depending on Figure 3 304, and an input terminal of the current correction combination circuitry 306 or current buffer 308. Switch 418 may be a MOSFET (e.g., a PMOS or NMOS) or any other switch. If the switch is open or disabled (e.g., forming an open circuit), the positive rectified current is blocked or not output at the output terminal of the first error current correction circuitry 300. If the switch is closed or enabled (e.g., forming a short circuit), the positive rectified current is passed to the output terminal of the first error current correction circuitry 300. For example, during manufacturing, if a negative |SCV| error is detected, switch 418 may be enabled so that the positive rectified current can be fed into the feedback loop to mitigate the detected negative |SCV| error. However, if the |SCV| error is positive, switch 418 may be disabled and switch 432 may be enabled to mitigate the positive |SCV| error, as further described below.

[0051] Figure 4Negative current rectifier 404 includes transistor 420 to rectify the sensed current from capacitor 401. Transistor 420 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a drain terminal), and a second current terminal (e.g., a source terminal). The control terminal of transistor 420 is coupled to a bias current source. The bias current source provides a low quiescent current (e.g., less than 1 microampere (μA)) to bias transistor 420. The first current terminal of transistor 420 is coupled to the second current terminal of transistor 422, the control terminals of transistors 422 and 426, and the first terminal of current source circuitry 425. The second current terminal of transistor 420 is coupled to the second terminal of capacitor 401 and the second current terminal of transistor 406. Transistor 420 is a p-channel metal oxide semiconductor field effect (PMOS or P-MOSFET) transistor. However, transistor 420 can be a different type of transistor. Transistor 420 is biased based on the low quiescent current (e.g., less than 1 microampere (μA)) provided by the bias current source. Transistor 420 rectifies the sensed current to allow current to flow from a first current terminal of transistor 420 to a second current terminal of transistor 420 for the negative portion of the sensed current (eg, blocks the positive portion of the sensed current).

[0052] Figure 4Transistors 422 and 426 each include a control terminal (e.g., a gate terminal), a first current terminal (e.g., a source terminal), and a second current terminal (e.g., a drain terminal). The control terminal of transistor 422 is coupled to the control terminal of transistor 426, the second current terminal of transistor 422, the first current terminal of transistor 420, and the first terminal of current source circuitry 425. The first current terminal of transistor 422 is coupled to the second terminal of resistor 424. The second current terminal of transistor 422 is coupled to the control terminals of transistors 422 and 426, the first current terminal of transistor 420, and the first terminal of current source circuitry 425. The control terminal of transistor 426 is coupled to the control terminal of transistor 422, the second current terminal of transistor 422, the first current terminal of transistor 420, and the first terminal of current source circuitry 425. The first current terminal of transistor 426 is coupled to the second terminal of capacitor 430 and the second terminal of resistor 428. The second terminal of transistor 426 is coupled to the first terminal of switch 432. Transistors 422 and 426 are n-channel MOSFETs (e.g., NMOS transistors). However, transistors 422 and 426 can be any type of transistor. Transistors 422 and 426 are configured to operate as a current mirror. Thus, the current flowing from the second terminal of transistor 426 to the first terminal of switch 432 is proportional to (e.g., has the same or different gain) the current flowing from the second current terminal of transistor 422 to the first current terminal of transistor 420. Therefore, if switch 432 is closed (e.g., forming a short circuit), the output current of current rectifier 400 corresponds to a negative rectified current based on the current through capacitor 401. The amount of gain corresponding to the current mirror of transistors 422 and 426 is based on the capacitance of capacitor 430 and the size of transistor 426 (e.g., channel width and length). Furthermore, a programmable capacitor can be used to adjust the capacitance of capacitor 430 to perform phase adjustment for trimming. The amount of capacitance or the size of transistor 426 can be selected to correspond to the amount of nonlinearity detected during manufacturing. In this way, the current output can mitigate the detected |SCV| nonlinearity.

[0053] Figure 4 Current source circuitry 425 includes a first terminal and a second terminal. The first terminal of current source circuitry 425 is coupled to the control terminals of transistors 422 and 426. The second terminal of current source circuitry 425 is coupled to the second terminal of current source circuitry 411 and a common terminal. The current source circuitry pulls a small current (e.g., 100 μA) to ground to reduce the minimum current corresponding to the mirror delay of the current mirror generated by transistors 422 and 426.

[0054] Resistors 424, 428, and capacitor 430 each have a first terminal and a second terminal. The first terminal of resistor 424 is coupled to a negative power supply terminal (e.g., -5V). The second terminal of resistor 424 is coupled to the first current source of transistor 422. The first terminal of resistor 428 is coupled to the negative power supply terminal. The second terminal of resistor 424 is coupled to the first current terminal of transistor 426 and the second terminal of capacitor 430. The first current terminal of capacitor 430 is coupled to the negative power supply terminal. The second current terminal of capacitor 430 is coupled to the second terminal of resistor 428 and the first current terminal of transistor 426. The resistance of resistor 428 or the size of transistor 426 can be combined into a single unit to adjust the gain. Resistor 428 also creates a phase lead. Resistors 424, 428 improve noise and matching.

[0055] Figure 4 The switch 432 includes a first terminal and a second terminal. The first terminal of the switch 432 is coupled to the second current terminal of the transistor 426. The second terminal of the switch 432 may be (e.g., depending on Figure 3 300 ). The first terminal of switch 418 is coupled to one or more output terminals of second error current correction circuitry 302 and third error current correction circuitry 304, and an input terminal of current correction combination circuitry 306 or current buffer 308. Switch 432 can be a MOSFET (e.g., a PMOS or NMOS) or any other switch. If the switch is open or disabled (e.g., forming an open circuit), the negative rectified current is blocked or not output at the output terminal of first error current correction circuitry 300. If the switch is closed or enabled (e.g., forming a short circuit), the negative rectified current is passed to the output terminal of first error current correction circuitry 300. For example, during manufacturing, if a positive |SCV| error is detected, switch 432 can be enabled so that the negative rectified current can be fed into the feedback loop to mitigate the detected positive |SCV| error. However, if the |SCV| error is negative, switch 432 can be disabled and switch 418 can be enabled to mitigate the negative |SCV| error, as described further below.

[0056] Figure 5 yes Figure 31 . An example circuit implementation of second error current correction circuitry 302 is shown. Second error current correction circuitry 302 includes an example current rectifier 500. Current rectifier 500 includes a positive current rectifier 502 and a negative current rectifier 504. Positive current rectifier 502 includes transistors 506, 508, 512, resistors 510, 514, a current source 511, a capacitor 516, and a switch 518. Negative current rectifier 504 includes transistors 520, 522, 526, resistors 524, 528, a current source 525, a capacitor 280, and a switch 532. Second error current correction circuitry 302 further includes a resistor 550 and a capacitor 556. Figure 5 Further included are example capacitor 552 and resistor 554. The operation of current rectifier 500 is similar to Figure 4 The current rectifier 400 is the same. However, Figure 5 The input and output terminals of the current rectifier 500 are coupled to the Figure 4 Therefore, for the sake of simplicity, since the components of the rectifier 500 correspond structurally and functionally to those of the current rectifier 400, Figure 4 Components of the rectifier 400, but for different input connections and different output connections, in addition to Figure 4 Aside from the differences between the rectifier 400 and the rectifier 500, the structure and function of the components of the rectifier 500 will not be further described. A further description of the components can be found in Figure 4 Determined in the above description.

[0057] Figure 5 Resistors 550 and 554 each include a first terminal and a second terminal. The first terminal of resistor 550 is coupled to the output terminal of output stage 208, the first terminal of resistor 212, transducer 104, and the first terminal of capacitor 556. The second terminal of resistor 550 is coupled to the second terminal of capacitor 556, the second current terminal of transistor 506, and the second current terminal of transistor 520. The first terminal of resistor 554 is coupled to the second terminals of switch 518 and switch 532, and the first terminal of capacitor 552. The second terminal of resistor 554 is coupled to the common terminal.

[0058] Figure 5 The capacitors 552 and 556 each include a first terminal and a second terminal. The first terminal of the capacitor 552 is coupled to the second terminals of the switches 518 and 532 and the first terminal of the resistor 554. The second terminal of the capacitor 552 may be (e.g., depending on Figure 35 (an embodiment of NLC circuitry 216) is coupled to one or more output terminals of first error current correction circuitry 300 and third error current correction circuitry 304, an input terminal of current correction combination circuitry 306, or current buffer 308. A first terminal of capacitor 556 is coupled to the output terminal of output stage 208, a first terminal of resistor 212, transducer 104, and a first terminal of resistor 550. A second terminal of capacitor 556 is coupled to a second terminal of resistor 550 and second current terminals of transistors 506 and 520.

[0059] Resistor 550 operates as a sense resistor to sense the output voltage corresponding to the input current entering rectifier 500. (For example, the input current is Vout / R1, where Vout is the output voltage of output stage 208 and R1 is the resistance of resistor 550). Because rectifier 500 rectifies the input current, rectifier 500 pumps the rectified current (e.g., |Vout / R1|) into resistor 554 to generate the output voltage (VHD2) of rectifier 500 (e.g., VHD2=|Vout / R1|*R2=K*|Vout|, where R2 is the resistance of resistor 554 and K=R2 / R1). Capacitor 552 obtains the received output voltage to generate SC|V| error current (Iout2) (e.g., Iout2=SC2*K*|Vout|, where C2 is the capacitance of capacitor 552), ignoring capacitor 556. Capacitor 556 compensates for the phase lag caused by capacitor 552. However, adding capacitor 552 to the output of rectifier 500 adds a pole that can cause a phase error in the correction current. Therefore, capacitor 556 is connected in parallel with resistor 550 to compensate for the phase error from the pole by adding a zero. Therefore, the output current (Iout2) of the second error current correction circuit system 302 is shown in Equation 1 below.

[0060]

[0061] As described above, the SC|V| current can be used to mitigate SC|V| nonlinearity errors. For example, during manufacturing, the SC|V| nonlinearity error can be determined. Accordingly, the resistance of resistors 514, 528, 550, 554, the capacitance of capacitors 516, 530, 552, 556, the size of transistors 512, 526, or the operation of switches 518, 532 can be selected to generate an SC|V| error mitigation signal that is fed back into HV driver 204 to mitigate the determined SC|V| error. As described above, the SC|V| signal is 90 degrees out of phase with the |SCV| signal generated by the first error current correction circuitry 300.

[0062] Figure 6 yes Figure 3 1 . An example circuit implementation of third error current correction circuitry 304 is shown. Third error current correction circuitry 304 includes an example current rectifier 600. Current rectifier 600 includes a positive current rectifier 602 and a negative current rectifier 604. Positive current rectifier 602 includes transistors 606, 608, 612, resistors 610, 614, a current source 611, a capacitor 616, and a switch 318. Negative current rectifier 604 includes transistors 620, 622, 626, resistors 624, 628, a current source 625, a capacitor 280, and a switch 632. Third error current correction circuitry 304 further includes a capacitor 650. Figure 6 It further includes a capacitor 652 and a resistor 654. The operation of the current rectifier 600 is similar to Figure 4 The current rectifier 400 is the same. However, Figure 6 The input and output terminals of the current rectifier 600 are coupled to the Figure 4 Therefore, for the sake of simplicity, since the components of the rectifier 600 correspond structurally and functionally to those of the current rectifier 400, Figure 4 Components of the rectifier 400, but for different input connections and different output connections, in addition to Figure 4 The structure and function of the components of rectifier 600 will not be further described except for the differences from rectifier 400. Further description of the components can be found in the above Figure 4 Confirmed in.

[0063] Figure 6 Resistor 654 includes a first terminal and a second terminal. The first terminal of resistor 654 is coupled to the second terminals of switch 618 and switch 632 and the first terminal of capacitor 652. The second terminal of resistor 654 is coupled to the common terminal.

[0064] Figure 6 Capacitors 650 and 652 each include a first terminal and a second terminal. The first terminal of capacitor 650 is coupled to the output terminal of output stage 208, the first terminal of resistor 212, and transducer 104. The second terminal of capacitor 650 is coupled to the second current terminals of transistors 606 and 620. The first terminal of capacitor 652 is coupled to the second terminals of switches 618 and 632 and the first terminal of resistor 654. The second terminal of capacitor 652 may be (e.g., depending on Figure 3 An embodiment of the NLC circuit system 216 is coupled to one or more output terminals of the first error current correction circuit system 300 and the second error current correction circuit system 302, an input terminal of the current correction combination circuit system 306 or the current buffer 308.

[0065] Similar to Figure 4 The capacitor 401, Figure 6 Capacitor 650 is a sensing capacitor. The current through capacitor 650 is represented by SCV (e.g., the complex frequency of the Laplace transform multiplied by the capacitance of capacitor 650). The sensed current is applied to current rectifier 600. Because rectifier 600 rectifies the input current, rectifier 600 pumps the rectified current (e.g., |SCV|) into resistor 654 to generate the output voltage (VHD3) of rectifier 600, as shown in Equation 2 below.

[0066]

[0067] Capacitor 652 obtains the received output voltage to produce ST*|SCV| error current (Iout3), where the pole created by capacitor 562 is cancelled based on the introduced zero in the |SCV| current produced by capacitor 650 and rectifier 600. The output error mitigation current corresponds to Equation 3 below.

[0068] Iout3≈K*SR2C2*|SC*Vout| (Equation 3)

[0069] In some instances, the amplitude distribution varies with the swing amplitude, rather than being linearly proportional. In such instances, resistor 654 can be replaced with a diode-connected transistor to produce reduced nonlinearity with respect to the swing amplitude.

[0070] As described above, the ST*|SCV| current can be used to mitigate ST*|SCV| nonlinearity errors. For example, during manufacturing, ST*|SCV| nonlinearity errors can be determined. Accordingly, one or more of the resistance of resistors 614, 628, 654, the capacitance of capacitors 616, 630, 650, 652, the size of transistors 612, 626, or the operation of switches 618, 632 can be selected to generate an ST*|SCV| error mitigation signal that is fed back to the HV driver 204 to mitigate the determined ST*|SCV| error.

[0071] Figure 7 The first error current correction circuit system 300 and the second error current correction circuit system 302 are described. Figure 3 Example circuit implementations of the current correction combination circuit system 306 and Figure 3706 . The current correction combination circuitry 306 includes example switches 702 and 704, an example resistor 706, and an example capacitor 708. The current buffer 308 includes example transistors 710, 716, 720, 722, and 726, example resistors 714, 718, 724, and 730, and example capacitors 719 and 728.

[0072] Figure 3 Current combining circuitry 306 combines the outputs of first error current correction circuitry 300 and second error current correction circuitry 302. Current combining circuitry 306 includes three terminals. A first terminal of current combining circuitry 306 is coupled to first error current correction circuitry 300. A second terminal of current combining circuitry 306 is coupled to second error current correction circuitry 302. A third terminal of current combining circuitry 306 is coupled to an input terminal of current buffer 308. Resistor 706 and capacitor 708 correspond to Figure 5 The resistor 554 and capacitor 552 or Figure 6 The resistor 654 and the capacitor 652 are connected to each other. The switch 702 includes a first terminal and a second terminal. The first terminal of the switch 702 is coupled to Figure 5 The second terminal of switches 518, 532, the first terminal of resistor 706 and the first terminal of capacitor 708. The second terminal of switch 702 is coupled to Figure 4 The second terminals of switches 418 and 432 and the first terminal of switch 704. The first terminal of switch 704 is coupled to Figure 4 The second terminal of switches 418, 432 and the second terminal of switch 702. The second terminal of switch 704 is coupled to the second terminal of capacitor 708 and the input terminal of current buffer 308. Switches 702, 704 can be transistors (e.g., PMOS transistors, NMOS transistors, etc.).

[0073] The resistor 706 includes a first terminal and a second terminal. The first terminal of the resistor 706 is coupled to Figure 5 The second terminals of switches 518 and 532, the first terminal of switch 702, and the first terminal of capacitor 708. The second terminal of resistor 706 is coupled to a common terminal (e.g., ground). Capacitor 708 includes a first terminal and a second terminal. The first terminal of capacitor 708 is coupled to Figure 5 The second terminal of the switches 518 and 532 are coupled to the first terminal of the switch 702 and the first terminal of the resistor 706. The second terminal of the capacitor 708 is coupled to the second terminal of the switch 704 and the input terminal of the current buffer 308.

[0074] Because the difference between first error current correction circuitry 300 and third error current correction circuitry 304 is the output circuitry, the output of first error current correction circuitry 300 can be input to resistor 706 and capacitor 708 to generate the output of third error current correction circuitry 304 without including the circuitry of third error current correction circuitry 304. Thus, current combining circuitry 306 facilitates different combinations of error current correction without implementing all three error current correction circuitry, thereby reducing area and resources. For example, if switch 702 is off or disabled (e.g., forming an open circuit) and switch 704 is on or enabled (e.g., forming a short circuit), the output of second error current circuitry 302 is applied to resistor 706 and capacitor 708 to generate an SC|V| output current flowing from capacitor 708 to current buffer 308. Furthermore, the output of first error current correction circuitry 300 (e.g., |SCV| output current) flows from the output of first error current correction circuitry 300 to current buffer 308. Because the output of first error current correction circuitry 300 is coupled to the output of capacitor 708, the SC|V| output signal is combined with the |SCV| output signal. Thus, the output signal of current combining circuitry 306 is the sum of the |SCV| output current and the SC|V| output current. The output of current combining circuitry 306 (e.g., |SCV| + SC|V|) is used to mitigate |SCV| and SC|V| nonlinear errors.

[0075] If switch 702 is on or enabled and switch 704 is off or disabled, the output of the first error current correction circuitry 300 is added to the output of the second error current correction circuitry 302 to produce a summed output current (e.g., |SCV| + |V|). The summed output current is applied to resistor 706 and capacitor 708 to produce an ST*|SCV| + SC|V| output current that flows from capacitor 708 to current buffer 308. The ST*|SCV| + SC|V| output current is used to mitigate the SC|V| error and the ST*|SCV| error.

[0076] If both switches 702 and 704 are disabled, the first error current correction circuitry 300 is decoupled from the current buffer 308. Consequently, the output of the current combining circuitry 306 will correspond to the SC|V| output signal to mitigate the SC|V| error. The control of switches 702 and 704 may be based on measured nonlinearities of the transmitter circuitry 102 during manufacturing. For example, if SC|V| and ST*|SCV| errors are identified during manufacturing, the manufacturer may enable switch 702 and disable switch 704, and adjust the structure (e.g., gain and switches) of the first and second error current correction circuitry 300 and 302 to produce output signals that mitigate the SC|V| and ST*|SCV| errors.

[0077] Transistor 710 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a drain terminal), and a second current terminal (e.g., a source terminal). The control terminal of transistor 710 is coupled to a bias current source. The bias current source provides a low quiescent current (e.g., less than 1 microampere (μA)) to bias transistor 710. The first current terminal of transistor 710 is coupled to the second current terminal of transistor 712 and the control terminals of transistors 712 and 716. The second current terminal of transistor 710 is coupled to the second terminal of capacitor 401 and the first current terminal of transistor 720. Transistor 710 is an n-channel metal oxide semiconductor field effect (NMOS or N-MOSFET) transistor. However, transistor 710 may be a different type of transistor. Transistor 710 is biased based on the low quiescent current (e.g., less than 1 microampere (μA)) provided by the bias current source.

[0078] Figure 7Each of transistors 712 and 716 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a source terminal), and a second current terminal (e.g., a drain terminal). The control terminal of transistor 712 is coupled to the control terminal of transistor 716, the second current terminal of transistor 712, and the first current terminal of transistor 710. The first current terminal of transistor 712 is coupled to the second terminal of resistor 714. The second current terminal of transistor 712 is coupled to the control terminals of transistors 712 and 716, and the first current terminal of transistor 710. The control terminal of transistor 716 is coupled to the control terminal of transistor 712, the second current terminal of transistor 712, and the first current terminal of transistor 710. The first current terminal of transistor 716 is coupled to the second terminal of capacitor 719 and the second terminal of resistor 718. The second terminal of transistor 716 is coupled to the second terminal of transistor 726 and the first terminal of HV driver 204. Transistors 712 and 716 are p-channel MOSFETs (e.g., PMOS transistors). However, transistors 712 and 716 can be any type of transistor. Transistors 712 and 716 are configured to operate as a current mirror. Thus, the current flowing from the second terminal of transistor 716 to the HV driver 204 is proportional to (e.g., has the same or different gain) the current flowing from the second current terminal of transistor 712 to the first current terminal of transistor 710. Thus, the output current of current rectifier 400 corresponds to a positive rectified current based on the current through capacitor 401. The amount of gain corresponding to the current mirror of transistors 712 and 716 is based on the capacitance of capacitor 719 and the size of transistor 716 (e.g., channel width and length). The amount of capacitance or the size of transistor 716 can be selected to adjust the gain and phase of current buffer 308.

[0079] Resistors 714, 718, and capacitor 719 each have a first terminal and a second terminal. The first terminal of resistor 714 is coupled to a positive power supply terminal (e.g., +5V). The second terminal of resistor 714 is coupled to a first current source of transistor 712. The first terminal of resistor 718 is coupled to the positive power supply terminal. The second terminal of resistor 714 is coupled to a first current terminal of transistor 716 and a second terminal of capacitor 719. The first current terminal of capacitor 719 is coupled to the positive power supply terminal. The second current terminal of capacitor 719 is coupled to the second terminal of resistor 718 and the first current terminal of transistor 716.

[0080] Transistor 720 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a drain terminal), and a second current terminal (e.g., a source terminal). The control terminal of transistor 720 is coupled to a bias current source. The bias current source provides a current (e.g., 100 microamperes (μA)) to bias transistor 720. The first current terminal of transistor 720 is coupled to the second current terminal of transistor 722 and the control terminals of transistors 722 and 726. The second current terminal of transistor 720 is coupled to the second terminal of capacitor 401 and the second current terminal of transistor 710. Transistor 720 is a p-channel metal oxide semiconductor field effect (PMOS or P-MOSFET) transistor. However, transistor 720 may be a different type of transistor. Transistor 720 is biased based on the current (e.g., 100 microamperes (μA)) provided by the bias current source.

[0081] Figure 7Each of transistors 722 and 726 includes a control terminal (e.g., a gate terminal), a first current terminal (e.g., a source terminal), and a second current terminal (e.g., a drain terminal). The control terminal of transistor 722 is coupled to the control terminal of transistor 726, the second current terminal of transistor 722, and the first current terminal of transistor 720. The first current terminal of transistor 722 is coupled to the second terminal of resistor 724. The second current terminal of transistor 722 is coupled to the control terminals of transistors 722 and 726, and the first current terminal of transistor 720. The control terminal of transistor 726 is coupled to the control terminal of transistor 722, the second current terminal of transistor 722, and the first current terminal of transistor 720. The first current terminal of transistor 726 is coupled to the second terminal of capacitor 728 and the second terminal of resistor 730. The second terminal of transistor 726 is coupled to the second terminal of transistor 716 and the first terminal of HV driver 204. Transistors 722 and 726 are n-channel MOSFETs (e.g., NMOS transistors). However, transistors 722 and 726 can be any type of transistor. Transistors 722 and 726 are configured to operate as a current mirror. Thus, the current flowing from the second terminal of transistor 726 to the HV driver 204 is proportional to (e.g., has the same or different gain) the current flowing from the second current terminal of transistor 722 to the first current terminal of transistor 720. Thus, the current flowing from the second current terminal of transistor 726 to the HV driver 204 corresponds to the negative rectified current of the output of the current combining circuitry 306. The amount of gain and phase corresponding to the current mirror of transistors 722 and 726 is based on the capacitance of capacitor 728 and the size of transistor 726 (e.g., channel width and length). Because the second current terminal of transistor 716 is coupled to the second current terminal of transistor 726, the negative rectified current from the second current terminal of transistor 726 is added to the positive rectified current from the first current terminal of transistor 716 to produce an output signal that is proportional to (e.g., has the same or different gain) the output current signal from the current combining circuitry 306.

[0082] Resistors 724, 730, and capacitor 728 each have a first terminal and a second terminal. The first terminal of resistor 724 is coupled to a negative power supply terminal (e.g., -5V). The second terminal of resistor 724 is coupled to a first current source of transistor 722. The first terminal of resistor 730 is coupled to the negative power supply terminal. The second terminal of resistor 724 is coupled to a first current terminal of transistor 726 and a second terminal of capacitor 728. The first current terminal of capacitor 728 is coupled to the negative power supply terminal. The second current terminal of capacitor 728 is coupled to the second terminal of resistor 730 and a first current terminal of transistor 726.

[0083] Figure 8Description combination Figure 3 The first error current correction circuit system 300, the second error current correction circuit system 302 and the third error current correction circuit system 304 Figure 3 The current buffer 308 includes an example circuit implementation of the current buffer 308. Figure 7 Example transistors 710 , 716 , 720 , 722 , 726 , example resistors 714 , 718 , 724 , 730 , and example capacitors 719 , 728 . Figure 8 The operation of the current buffer 308 is Figure 7 The current buffer 308 is the same. However, Figure 8 The input terminal of the current buffer 308 is coupled to the Figure 7 The current buffer 308 has different components. Therefore, for the sake of simplicity, because Figure 8 The components of the current buffer 308 correspond in structure and function to Figure 7 components of the current buffer 308, but with different input connections, in addition to Figure 7 The difference of the current buffer 308 is Figure 7 The structure and function of the components of the current buffer 308 will not be further described. A further description of the components can be found in Figure 7 Determined in the above description.

[0084] exist Figure 8 In the example of FIG, an output terminal of the first error current correction circuitry 300 (e.g., the second terminals of switches 418, 432) is coupled to an output terminal of the second error current correction circuitry 302 (e.g., the second terminal of capacitor 552), an output of the third error current correction circuitry 304 (e.g., the second terminal of capacitor 652), and an input terminal of the current buffer 308. An output terminal of the second error current correction circuitry 302 is coupled to an output terminal of the first error current correction circuitry 300, an output terminal of the third error current correction circuitry 304, and an input terminal of the current buffer 308. An output terminal of the third error current correction circuitry 304 is coupled to an output terminal of the first error current correction circuitry 300, an output terminal of the second error current correction circuitry 302, and an input terminal of the current buffer 308.

[0085] exist Figure 8In the example of FIG, current combining circuitry 306 is not included. Specifically, the output current signals from first error current correction circuitry 300, second error current correction circuitry 302, and third error current correction circuitry 304 are all combined (e.g., summed) and applied to the input terminal of current buffer 308. Thus, the input current signal to current buffer 308 corresponds to a combination of signals used to mitigate |SCV| nonlinearity, SC|V| nonlinearity, and ST*|SCV| nonlinearity.

[0086] exist Figures 2 to 8 Implementation Figure 1 However, Figure 1 One or more of the elements, processes, or means described in the drawings may be combined, divided, rearranged, omitted, eliminated, or implemented in any other manner.

[0087] Furthermore, one or more of the input stage 202, the HV driver 204, the output stage 208, and the NLC circuitry 216, 218 may be implemented by one or more of hardware, software, firmware, or any combination of hardware, software, or firmware. Thus, for example, any one or more of the input stage 202, the HV driver 204, the output stage 208, and the NLC circuitry 216, 218 may be implemented by one or more of the following: one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application specific integrated circuits (ASICs), one or more programmable logic devices (PLDs), and / or one or more field programmable logic devices (FPLDs).

[0088] When any of the apparatus or system claims of this patent are read to cover only software and / or firmware implementations, at least one of the input stage 202, HV driver 204, output stage 208, NLC circuitry 216, 218 is expressly defined herein as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disc (DVD), a compact disc (CD), a Blu-ray disc, etc., comprising the software and / or firmware. In addition, one or more of the input stage 202, HV driver 204, output stage 208, NLC circuitry 216, 218 may comprise a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disc (DVD), a compact disc (CD), a Blu-ray disc, etc., comprising the software and / or firmware. Figure 2 In addition to or in lieu of those described in Figure 2As used herein, the phrase "communication," including variations thereof, encompasses direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or continuous communication, but also includes selective communication at one or more of periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0089] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture falling within the scope of the claims of this patent.

[0090] The descriptors "first," "second," "third," etc., are used herein to identify multiple elements or components that can be referenced separately. Unless otherwise specified or indicated by the context in which these descriptors are used, these descriptors do not confer any priority, physical order, arrangement in a list, or temporal ordering, but are merely used as labels to refer to multiple elements or components separately to facilitate understanding of the described examples. In some instances, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to by a different descriptor, such as "second" or "third," in the claims. In such cases, such descriptors are used solely for convenience in referring to the multiple elements or components.

[0091] In this specification and claims, unless otherwise indicated, the terms "including" and "having" and variations thereof are included in a manner similar to the term "comprising." Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. In another example, "about," "approximately," or "substantially" preceding a value means + / - 5% of the stated value. In another example, "about," "approximately," or "substantially" preceding a value means + / - 1% of the stated value.

[0092] As used herein, the terms "couple," "coupled," "couples," and variations thereof may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: if a first example device A is coupled to device B; or if a second example device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A. Furthermore, the terms "couple," "coupled," "couples," and variations thereof encompass indirect or direct electrical or mechanical connections.

[0093] A device that is "configured to" perform a task or function may be configured (e.g., at least one of programmed or hardwired) to perform the function when manufactured by the manufacturer, or may be configurable (or reconfigurable) by a user after manufacture to perform the function or other additional or alternative functions. The configuration may be achieved through at least one firmware or software programming of the device, through the construction or layout of the hardware components and interconnections of the device, or a combination thereof.

[0094] Although not in Figure 2 Although not all components or elements of the systems and circuits described herein are individually labeled, the components or elements have one or more conductors or terminals that allow signals to enter or leave the components or elements. The conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0095] As used herein, a "terminal" of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally refers to a conductor, such as a wire, trace, pin, pad, or other connector or interconnect, that enables the component, device, system, etc. to be electrically or mechanically connected to another component, device, system, etc. For example, a terminal can be used to receive or provide an analog or digital electrical signal (or simply a signal), or to electrically connect to a common or ground reference. Thus, an input terminal or input is used to receive a signal from another component, device, system, etc. An output terminal or output is used to provide a signal to another component, device, system, etc. Other terminals can be used to connect to a common, ground, or voltage reference, such as a reference terminal or ground terminal. A terminal of an IC or PCB may also be referred to as a pin (vertical conductor) or pad (planar conductor). A node refers to the connection point or interconnection point between two or more terminals. An example number of terminals and nodes may be shown. However, depending on the specific circuit system or system topology, there may be more or fewer terminals and nodes. However, in some cases, "terminal," "node," "interconnect," "pad," and "pin" are used interchangeably.

[0096] The term "or" when used in the form of, for example, A, B, or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C.

[0097] Example methods, apparatus, systems, and articles of manufacture for correcting nonlinearities in a transmitter are described herein. Other examples and combinations thereof include the following: Embodiment 1 includes an apparatus comprising: a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor being coupled to the second current terminal of the first transistor, the first current terminal of the first transistor being coupled to a power supply terminal via a first resistor; a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor and the second current terminal of the first transistor, the first current terminal of the second transistor being coupled to the power supply terminal via a second resistor and a capacitor; a current source having a first terminal and a second terminal, the first terminal of the current source being coupled to the control terminals of the first and second transistors and the second current terminal of the first transistor, the second terminal of the current source being coupled to a common terminal; and a switch having a first terminal and a second terminal, the first terminal of the switch being coupled to the second current terminal of the second transistor.

[0098] Example 2 includes the apparatus of Example 1, wherein the capacitor and the first transistor are coupled in parallel.

[0099] Example 3 includes the apparatus of Example 1, further including a third transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the third transistor being coupled to the second current terminal and the control terminal of the first transistor, the first terminal of the current source, and the control terminal of the second transistor.

[0100] Example 4 includes the apparatus of Example 3, wherein the capacitor is a first capacitor, the apparatus further comprising a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the output of the buffer, the second terminal of the second capacitor coupled to the second current terminal of the third transistor.

[0101] Example 5 includes the apparatus of Example 4, further including a third resistor having a first terminal and a second terminal, the first terminal of the third resistor being coupled to the first terminal of the second capacitor and the output of the buffer, the second terminal of the third resistor being coupled to the second terminal of the second capacitor and the second current terminal of the third transistor.

[0102] Example 6 includes the apparatus of Example 5, further including a fourth resistor and a third capacitor, the fourth resistor having a first terminal and a second terminal, the first terminal of the fourth resistor being coupled to the second terminal of the switch, the second terminal of the fourth resistor being coupled to the common terminal, the third capacitor having a first terminal and a second terminal, the first terminal of the third capacitor being coupled to the first terminal of the fourth resistor and the second terminal of the switch, and the second terminal of the third transistor being coupled to the current buffer.

[0103] Example 7 includes the apparatus of Example 4, further including a third resistor and a third capacitor, the third resistor having a first terminal and a second terminal, the first terminal of the third resistor coupled to the second terminal of the switch, the second terminal of the third resistor coupled to the common terminal, the first terminal of the third capacitor coupled to the first terminal of the third resistor and the second terminal of the switch, and the second terminal of the third capacitor coupled to the current buffer.

[0104] Example 8 includes the apparatus of Example 3, wherein the current source is a first current source, the switch is a first switch, and the capacitor is a first capacitor, the apparatus further comprising: a fourth transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the fourth transistor being coupled to the first current terminal of the fourth transistor, the second current terminal of the fourth transistor being coupled to the negative power supply terminal via a third resistor; a fifth transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the fifth transistor being coupled to the control terminal of the fourth transistor and the first current terminal of the fourth transistor, the second current terminal of the fifth transistor being coupled to the negative power supply terminal via a fourth resistor and a second capacitor; a second current source having a first terminal and a second terminal, the first terminal of the second current source being coupled to a common terminal and the second terminal of the first current source, the second terminal of the second current source being coupled to the control terminals of the first transistor and the fifth transistor, and the second current terminal of the fourth transistor; and a second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled to the second terminal of the first switch, and the second terminal of the second switch being coupled to the first current terminal of the fifth transistor.

[0105] Example 9 includes a device comprising: a first error current correction circuit system having a first terminal and a second terminal; a second error current correction circuit system having a first terminal and a second terminal; a first switch having a first terminal and a second terminal, the first terminal of the first switch being coupled to the second terminal of the first error current correction circuit system, and the second terminal of the first switch being coupled to the second terminal of the second error current correction circuit system; a second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled to the second terminal of the first switch and the second terminal of the second error current correction circuit system, and the second terminal of the second switch being coupled to a current buffer; a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the first error current correction circuit system and the first terminal of the first switch, and the second terminal of the resistor being coupled to a common terminal; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the first error current correction circuit system, the first terminal of the first switch, and the first terminal of the resistor, and the second terminal of the capacitor being coupled to the second terminal of the second switch and the current buffer.

[0106] Example 10 includes the apparatus of Example 9, wherein the first error current correction circuit system includes a positive half rectifier circuit system and a negative half rectifier circuit system, wherein the positive half rectifier circuit system has an input terminal and an output terminal, the output terminal of the positive half rectifier circuit system is the second terminal of the first error current correction circuit system, and the negative half rectifier circuit system has an input terminal and an output terminal, the input terminal of the negative half rectifier circuit system is the input terminal of the positive half rectifier circuit system, and the output terminal of the negative half rectifier circuit system is the output terminal of the positive half rectifier circuit system.

[0107] Example 11 includes the apparatus of Example 10, wherein the capacitor is a first capacitor, the apparatus further including a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the output buffer, the second terminal of the second capacitor being coupled to an input terminal of the positive half rectifier circuit system and an input terminal of the negative half rectifier circuit system.

[0108] Example 12 includes the apparatus of Example 9, wherein the second error current correction circuit system includes a positive half rectifier circuit system and a negative half rectifier circuit system, wherein the positive half rectifier circuit system has an input terminal and an output terminal, the output terminal of the positive half rectifier circuit system is a second terminal of the second error current correction circuit system, and the negative half rectifier circuit system has an input terminal and an output terminal, the input terminal of the negative half rectifier circuit system is the input terminal of the positive half rectifier circuit system, and the output terminal of the negative half rectifier circuit system is the output terminal of the positive half rectifier circuit system.

[0109] Example 13 includes the apparatus of Example 10, wherein the resistor is a first resistor and the capacitor is a first capacitor, the apparatus further comprising: a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the output buffer, the second terminal of the second capacitor being coupled to an input terminal of the positive half rectifier circuit system and an input terminal of the negative half rectifier circuit system; and a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the first terminal of the second capacitor and the output buffer, the second terminal of the second resistor being coupled to the second terminal of the second capacitor and the input terminal of the positive half rectifier circuit system and the input terminal of the negative half rectifier circuit system.

[0110] Example 14 includes the apparatus of Example 9, wherein the resistor is a first resistor and the capacitor is a first capacitor, the first error current correction circuit system including: a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor being coupled to the second current terminal of the first transistor, the first current terminal of the first transistor being coupled to the power supply terminal via the second resistor; a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor and the second current terminal of the first transistor, the first current terminal of the second transistor being coupled to the power supply terminal via the third resistor and the second capacitor; a current source having a first terminal and a second terminal, the first terminal of the current source being coupled to the control terminals of the first and second transistors and the second current terminal of the first transistor, the second terminal of the current source being coupled to a common terminal; and a switch having a first terminal and a second terminal, the first terminal of the switch being coupled to the second current terminal of the second transistor, the second terminal of the switch being the second terminal of the first error current correction circuit system.

[0111] Example 15 includes a transmitter comprising: an input stage having a first input terminal, a second input terminal, and an output terminal; a driver having an input terminal and an output terminal, the input terminal of the driver being coupled to the output terminal of the input stage; an output buffer having an input terminal and an output terminal, the input terminal of the output buffer being coupled to the output terminal of the driver, the output terminal of the output buffer being coupled to the first input terminal of the input stage via a resistor; and a nonlinear correction circuit system having an input terminal and an output terminal, the input terminal of the nonlinear correction circuit system being coupled to the output terminal of the output buffer and the first input terminal of the input stage via a resistor, the output terminal of the nonlinear correction circuit system being coupled to the output terminal of the input stage and the input terminal of the driver.

[0112] Example 16 includes the transmitter of Example 15, further including a signal generator having a first terminal and a second terminal, the first terminal coupled to the second terminal of the input stage, the second terminal of the signal generator coupled to the common terminal.

[0113] Example 17 includes the transmitter of Example 15, wherein the resistor is a first resistor having a first terminal and a second terminal, the transmitter further including a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the second terminal of the first resistor and the first input terminal of the input stage, the second terminal of the second resistor being coupled to the common terminal.

[0114] Example 18 includes the transmitter of Example 15, wherein the nonlinear correction circuitry is a first nonlinear correction circuitry, the transmitter further comprising a second nonlinear correction circuitry, the second nonlinear correction circuitry comprising an input terminal and an output terminal, the input terminal of the second nonlinear correction circuitry being coupled to the second input terminal of the input stage, the output terminal of the second nonlinear correction circuitry being coupled to the output terminal of the input stage, the input terminal of the driver, and the output terminal of the first nonlinear correction circuitry.

[0115] Example 19 includes the transmitter of Example 15, wherein the output terminal of the output buffer is configured to be coupled to the transducer.

[0116] Example 20 includes the transmitter of Example 15, wherein the nonlinear correction circuit system includes: a capacitor including a first terminal and a second terminal, the first terminal of the capacitor being the first terminal of the nonlinear correction circuit system; a positive half rectifier circuit system having an input terminal and an output terminal, the input terminal of the positive half rectifier circuit system being coupled to the second terminal of the capacitor, the output terminal of the positive half rectifier circuit system being coupled to the input terminal of the driver via a current buffer; and a negative half rectifier circuit system having an input terminal and an output terminal, the input terminal of the negative half rectifier circuit system being coupled to the second terminal of the capacitor and the first terminal of the negative half rectifier circuit system, the output terminal of the negative half rectifier circuit system being coupled to the input terminal of the driver via the current buffer and the output terminal of the positive half rectifier circuit system.

[0117] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: a first capacitor having a first terminal and a second terminal; a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor being coupled to the second current terminal of the first transistor, the second current terminal of the first transistor being coupled to the second terminal of the first capacitor; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor being coupled to a power supply terminal and the second terminal of the first resistor being coupled to the first current terminal of the first transistor; a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor and the first current terminal of the first transistor; a second current terminal; a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the power supply terminal and the second terminal of the second capacitor being coupled to the first current terminal of the second transistor; a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the power supply terminal, the second terminal of the second resistor being coupled to the first current terminal of the second transistor and the second terminal of the second capacitor; a current source circuit having a first terminal and a second terminal, the first terminal of the current source circuit being coupled to the control terminals of the first and second transistors and the second current terminal of the first transistor, and the second terminal of the current source circuit being coupled to a common terminal; and A switch has a first terminal and a second terminal, the first terminal of the switch being coupled to the second current terminal of the second transistor.

2. The apparatus of claim 1, wherein the second capacitor and the second resistor are coupled in parallel.

3. The apparatus of claim 1 , further comprising a third transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the third transistor being coupled to the second current terminal and the control terminal of the first transistor, the first terminal of the current source circuit, and the control terminal of the second transistor. 4 . The apparatus of claim 3 , wherein the second terminal of the first capacitor is coupled to the second terminal of the first transistor via the third transistor.

5. The apparatus of claim 4 , further comprising a third resistor having a first terminal and a second terminal, the first terminal of the third resistor being coupled to the first terminal of the first capacitor, the second terminal of the third resistor being coupled to the second terminal of the first capacitor and the second current terminal of the third transistor.

6. The apparatus of claim 5, further comprising: a fourth resistor having a first terminal and a second terminal, the first terminal of the fourth resistor being coupled to the second terminal of the switch and the second terminal of the fourth resistor being coupled to the common terminal; and A third capacitor has a first terminal and a second terminal, the first terminal of the third capacitor is coupled to the first terminal of the fourth resistor and the second terminal of the switch, and the second terminal of the third transistor is coupled to a current buffer.

7. The apparatus of claim 4, further comprising: a third resistor having a first terminal and a second terminal, the first terminal of the third resistor being coupled to the second terminal of the switch and the second terminal of the third resistor being coupled to the common terminal; and A third capacitor has its first terminal coupled to the first terminal of the third resistor and the second terminal of the switch, and its second terminal coupled to a current buffer.

8. The apparatus of claim 3, wherein the current source circuit is a first current source circuit and the switch is a first switch, the apparatus further comprising: a fourth transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the fourth transistor being coupled to the first current terminal of the fourth transistor, the second current terminal of the fourth transistor being coupled to a negative power supply terminal via a third resistor; a fifth transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the fifth transistor being coupled to the control terminal of the fourth transistor and the first current terminal of the fourth transistor; a first current terminal, the second current terminal of the fifth transistor being coupled to the negative power supply terminal via a fourth resistor and a third capacitor; a second current source circuit having a first terminal and a second terminal, the first terminal of the second current source circuit being coupled to the common terminal and the second terminal of the first current source circuit, the second terminal of the second current source circuit being coupled to the control terminals of the first and fifth transistors and the second current terminal of the fourth transistor; and A second switch has a first terminal and a second terminal, the first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is coupled to the first current terminal of the fifth transistor.

9. A device comprising: a current buffer comprising a first terminal and a second terminal; a first error current correction circuit system having a first terminal and a second terminal; a second error current correction circuit system having a first terminal and a second terminal; a first switch having a first terminal and a second terminal, the first terminal of the first switch being coupled to the second terminal of the first error current correction circuitry, the second terminal of the first switch being coupled to the second terminal of the second error current correction circuitry; a second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled to the second terminal of the first switch and the second terminal of the second error current correction circuitry, the second terminal of the second switch being coupled to the first terminal of the current buffer; a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the first error current correction circuitry and the first terminal of the first switch, the second terminal of the resistor being coupled to a common terminal; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the first error current correction circuitry, the first terminal of the first switch, and the first terminal of the resistor, and the second terminal of the capacitor being coupled to the second terminal of the second switch and the first terminal of the current buffer.

10. The apparatus of claim 9, wherein the first error current correction circuitry comprises: a positive half-rectifier circuit system having an input terminal and an output terminal, the output terminal of the positive half-rectifier circuit system being the second terminal of the first error current correction circuit system; and A negative half rectifier circuit system has an input terminal and an output terminal, wherein the input terminal of the negative half rectifier circuit system is the input terminal of the positive half rectifier circuit system, and the output terminal of the negative half rectifier circuit system is the output terminal of the positive half rectifier circuit system.

11. The apparatus of claim 10 , wherein the capacitor is a first capacitor, the apparatus further comprising a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to an output buffer, the second terminal of the second capacitor being coupled to the input terminal of the positive half-rectifier circuitry and the input terminal of the negative half-rectifier circuitry.

12. The apparatus of claim 9, wherein the second error current correction circuitry comprises: a positive half-rectifier circuit system having an input terminal and an output terminal, the output terminal of the positive half-rectifier circuit system being the second terminal of the second error current correction circuit system; and A negative half rectifier circuit system has an input terminal and an output terminal, wherein the input terminal of the negative half rectifier circuit system is the input terminal of the positive half rectifier circuit system, and the output terminal of the negative half rectifier circuit system is the output terminal of the positive half rectifier circuit system.

13. The apparatus of claim 10, wherein the resistor is a first resistor and the capacitor is a first capacitor, the apparatus further comprising: a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the output buffer, the second terminal of the second capacitor being coupled to the input terminal of the positive half rectifier circuitry and the input terminal of the negative half rectifier circuitry; and a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the first terminal of the second capacitor and the output buffer, the second terminal of the second resistor being coupled to the second terminal of the second capacitor and the input terminal of the positive half rectifier circuitry and the input terminal of the negative half rectifier circuitry.

14. The apparatus of claim 9, wherein the resistor is a first resistor and the capacitor is a first capacitor, the first error current correction circuitry comprising: a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor being coupled to the second current terminal of the first transistor, the first current terminal of the first transistor being coupled to a power supply terminal via a second resistor; a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor and the second current terminal of the first transistor, the first current terminal of the second transistor being coupled to the power supply terminal via a third resistor and a second capacitor; a current source circuit having a first terminal and a second terminal, the first terminal of the current source circuit being coupled to the control terminals of the first and second transistors and the second current terminal of the first transistor, and the second terminal of the current source circuit being coupled to a common terminal; and A switch has a first terminal and a second terminal, the first terminal of the switch being coupled to the second current terminal of the second transistor, the second terminal of the switch being the second terminal of the first error current correction circuitry.

15. A transmitter comprising: an input stage having a first input terminal, a second input terminal and an output terminal, a driver having an input terminal and an output terminal, the input terminal of the driver being coupled to the output terminal of the input stage; an output buffer having an input terminal and an output terminal, the input terminal of the output buffer being coupled to the output terminal of the driver, the output terminal of the output buffer being coupled to the first input terminal of the input stage via a resistor; and A nonlinear correction circuit system having an input terminal and an output terminal, the input terminal of the nonlinear correction circuit system being coupled to the output terminal of the output buffer and the first input terminal of the input stage via the resistor, and the output terminal of the nonlinear correction circuit system being coupled to the output terminal of the input stage and the input terminal of the driver.

16. The transmitter of claim 15, further comprising a signal generator having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the input stage, the second terminal of the signal generator being coupled to a common terminal.

17. The transmitter of claim 15 , wherein the resistor is a first resistor having a first terminal and a second terminal, the transmitter further comprising a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the second terminal of the first resistor and the first input terminal of the input stage, the second terminal of the second resistor being coupled to a common terminal.

18. The transmitter of claim 15 , wherein the nonlinear correction circuitry is a first nonlinear correction circuitry, the transmitter further comprising a second nonlinear correction circuitry, the second nonlinear correction circuitry comprising an input terminal and an output terminal, the input terminal of the second nonlinear correction circuitry being coupled to the second input terminal of the input stage, the output terminal of the second nonlinear correction circuitry being coupled to the output terminal of the input stage, the input terminal of the driver, and the output terminal of the first nonlinear correction circuitry.

19. The transmitter of claim 15, wherein the output terminal of the output buffer is configured to be coupled to a transducer.

20. The transmitter of claim 15, wherein the nonlinear correction circuitry comprises: Current buffer; a capacitor comprising a first terminal and a second terminal, the first terminal of the capacitor being the first terminal of the nonlinear correction circuit system; a positive half-rectifier circuit system having an input terminal and an output terminal, the input terminal of the positive half-rectifier circuit system being coupled to the second terminal of the capacitor, the output terminal of the positive half-rectifier circuit system being coupled to the input terminal of the driver via the current buffer; and a negative half-rectifier circuit system having an input terminal and an output terminal, the input terminal of the negative half-rectifier circuit system being coupled to the second terminal of the capacitor and the first terminal of the negative half-rectifier circuit system, the output terminal of the negative half-rectifier circuit system being coupled to the input terminal of the driver via the current buffer and the output terminal of the positive half-rectifier circuit system.

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