GaN power device with high dynamic stability and high voltage resistance and preparation method thereof

Abstract

The invention belongs to the technical field of power electronic devices, and particularly relates to a GaN power device with high dynamic stability and high voltage resistance and a preparation method thereof. According to the GaN power device with high dynamic stability and high voltage resistance provided by the invention, the barrier layer is additionally arranged on the silicon substrate, the barrier layer is made of an insulating material, and electrons in the substrate cannot pass through the barrier layer, so that the electrons in the substrate are prevented from being trapped by a buffer layer, and the problem of dynamic resistance is weakened; meanwhile, due to the existence of the barrier layer, the anti-pressure capability of a vertical path from the drain electrode to the silicon substrate is improved, so that the withstand voltage of the device is higher.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic devices, and in particular relates to a GaN power device with high dynamic stability and high withstand voltage and a preparation method thereof. Background Art

[0002] Compared to first-generation semiconductors like silicon and second-generation semiconductors like gallium arsenide, GaN (gallium nitride) materials belong to the third generation of semiconductors and offer distinct advantages in material properties, most notably a wide bandgap, high breakdown electric field, and high electron saturation velocity. In the field of power electronics, these advantages can help overcome the development bottlenecks of silicon semiconductor devices and enable electronic systems to achieve faster operating frequencies, lower losses, and smaller sizes.

[0003] However, the current collapse caused by the trap effect under high voltage stress is a common problem of GaN devices, which is also called the dynamic resistance problem of GaN devices. The dynamic resistance problem is mainly caused by two parts of trap effects: one is the barrier layer trap, and the other is the buffer layer trap, such as Figure 5 As shown in the figure. When a device is subjected to high voltage stress, a high electric field develops within the device, accelerating electrons in the two-dimensional electron gas (2DEG). When traps form in the barrier layer, the accelerated electrons are captured by these traps. When traps exist in the buffer layer, the accelerated electrons may also be captured by these traps. Simultaneously, electrons in the silicon substrate are attracted to the buffer layer and captured by these traps. After the stress is removed, the device turns on normally, but these trapped electrons cannot be released in time. Shallower trap levels lead to faster electron release, while deeper trap levels lead to slower release. Electrons trapped in these traps form charged centers, affecting electron mobility in the channel and increasing channel resistance, which manifests as an increase in device electrical resistance.

[0004] Due to cost considerations, current commercial GaN devices all use silicon substrates. The second type of trap (buffer layer trap) can cause electrons in the silicon substrate to be trapped by the buffer layer, resulting in a decrease in dynamic resistance. Furthermore, because the silicon substrate itself has a certain degree of conductivity, the device's withstand voltage is limited by its vertical withstand voltage. That is, when a high voltage is applied to the drain, the vertical path from the drain to the silicon substrate is insufficiently withstandable due to the silicon substrate's conductivity. Summary of the Invention

[0005] The purpose of the present invention is to provide a GaN power device with high dynamic stability and high withstand voltage and a preparation method thereof. The GaN power device obtained by the method provided by the present invention has high dynamic stability and high withstand voltage characteristics.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: The present invention provides a high dynamic stability and high withstand voltage GaN power device, comprising a substrate, a barrier layer arranged on the upper surface of the substrate, a GaN buffer layer arranged on the upper surface of the barrier layer, a GaN channel layer arranged on the upper surface of the GaN buffer layer, and an Al2O3 layer arranged on the upper surface of the GaN channel layer. x Ga 1-x N barrier layer, provided on the Al x Ga 1-x The gate electrode on the upper surface of the N barrier layer and the passivation layer surrounding the gate electrode are arranged between the GaN channel layer and the Al x Ga 1-x Both ends of the N barrier layer are connected to the GaN channel layer and the Al x Ga 1-x The source electrode and the drain electrode of the N barrier layer are in ohmic contact; The material of the barrier layer includes Al2O3 or AlN; The Al x Ga 1-x The value range of x in the N barrier layer is 0.25.

[0007] Preferably, the substrate comprises a silicon wafer, and the thickness of the substrate is 600-1000 μm.

[0008] Preferably, the thickness of the barrier layer is 20-30 nm.

[0009] Preferably, the thickness of the GaN buffer layer is 0.5-3 μm.

[0010] Preferably, the thickness of the GaN channel layer is 100-2000 nm.

[0011] Preferably, the Al x Ga 1-x The thickness of the N barrier layer is 10~30nm.

[0012] Preferably, the source electrode and the drain electrode independently include a titanium layer and an aluminum layer stacked sequentially from bottom to top; The thickness of the aluminum layer is 500-5000 nm, and the thickness of the titanium layer is 1-20 nm.

[0013] Preferably, the gate electrode comprises a first TiN layer, an Al layer and a second TiN layer stacked in sequence from bottom to top; The thickness of the first TiN layer and the second TiN layer are independently 10-100 nm; The thickness of the Al layer is 1000 nm.

[0014] Preferably, the material of the passivation layer is SiN; the thickness of the passivation layer is 10-100 nm.

[0015] The present invention also provides a method for preparing the high dynamic stability and high withstand voltage GaN power device described in the above technical solution, comprising the following steps: The barrier layer, GaN buffer layer, GaN channel layer, Al x Ga 1-x N barrier layer and passivation layer to obtain a semi-finished product; A source electrode, a drain electrode and a gate electrode are prepared on the semi-finished product to obtain the high dynamic stability and high withstand voltage GaN power device.

[0016] The present invention provides a high dynamic stability and high withstand voltage GaN power device, comprising a substrate, a barrier layer arranged on the upper surface of the substrate, a GaN buffer layer arranged on the upper surface of the barrier layer, a GaN channel layer arranged on the upper surface of the GaN buffer layer, and an Al2O3 layer arranged on the upper surface of the GaN channel layer. x Ga 1-x N barrier layer, provided on the Al x Ga 1-x The gate electrode on the upper surface of the N barrier layer and the passivation layer surrounding the gate electrode are arranged between the GaN channel layer and the Al x Ga 1-x Both ends of the N barrier layer are connected to the GaN channel layer and the Al x Ga 1-x The source electrode and drain electrode of the N barrier layer are in ohmic contact; the material of the barrier layer includes Al2O3 or AlN; the Al x Ga 1-x The value range of x in the N barrier layer is 0.25.

[0017] The high dynamic stability and high withstand voltage GaN power device provided by the present invention adds a barrier layer on the silicon substrate. Since the material of the barrier layer is an insulating material, electrons in the substrate cannot pass through the barrier layer, thereby preventing the substrate electrons from being trapped in the buffer layer and reducing the dynamic resistance problem; at the same time, due to the presence of the barrier layer, the pressure resistance of the vertical path from the drain to the silicon substrate is improved, which in turn leads to a higher withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The silicon wafer with the Al2O3 layer grown thereon obtained in Example 1; Figure 2 For the preparation of Al in Example 1 x Ga 1-x Schematic diagram of the device structure obtained after the N barrier layer; Figure 3Schematic diagram of the structure of the device obtained after preparing the source electrode and the drain electrode in Example 1; Figure 4 A schematic structural diagram of a high dynamic stability and high withstand voltage GaN power device provided by the present invention; Figure 5 It is a schematic structural diagram of a GaN power device in the prior art; Among them, 1 is the substrate, 2 is the barrier layer, 3 is the GaN buffer layer, 4 is the GaN channel layer, 5 is the Al x Ga 1-x N barrier layer, 6 is the source electrode, 7 is the drain electrode, 8 is the gate electrode, 9 is the passivation layer, and 10 is the two-dimensional electron gas. DETAILED DESCRIPTION

[0019] The present invention provides a high dynamic stability and high withstand voltage GaN power device, comprising a substrate, a barrier layer arranged on the upper surface of the substrate, a GaN buffer layer arranged on the upper surface of the barrier layer, a GaN channel layer arranged on the upper surface of the GaN buffer layer, and an Al2O3 layer arranged on the upper surface of the GaN channel layer. x Ga 1-x N barrier layer, provided on the Al x Ga 1-x The gate electrode on the upper surface of the N barrier layer and the passivation layer surrounding the gate electrode are arranged between the GaN channel layer and the Al x Ga 1-x Both ends of the N barrier layer are connected to the GaN channel layer and the Al x Ga 1-x The source electrode and the drain electrode of the N barrier layer are in ohmic contact; The material of the barrier layer includes Al2O3 or AlN; The Al x Ga 1-x The value range of x in the N barrier layer is 0.25.

[0020] Figure 4 The schematic diagram of the structure of the high dynamic stability and high withstand voltage GaN power device provided by the present invention is shown below. Figure 4 The high dynamic stability and high withstand voltage GaN power device provided by the present invention is described in detail.

[0021] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a substrate. In the present invention, the substrate preferably includes a silicon wafer, and the thickness of the substrate is preferably 600-1000 μm.

[0022] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a barrier layer disposed on the upper surface of the substrate. In the present invention, the material of the barrier layer includes Al2O3 or AlN. In the present invention, the thickness of the barrier layer is preferably 20-30 nm, specifically 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm. In the present invention, the thickness of the barrier layer cannot be too thick, as this will risk cracking, nor can it be too thin, as this will result in poor quality of the GaN material that continues to grow thereon. In the present invention, the material of the barrier layer is an insulating material, and electrons in the substrate cannot pass through the barrier layer, thereby preventing substrate electrons from being trapped by the buffer layer and reducing the dynamic resistance problem. At the same time, due to the presence of the barrier layer, the pressure resistance of the vertical path from the drain to the substrate is improved, thereby making the device's withstand voltage higher.

[0023] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a GaN buffer layer disposed on the upper surface of the barrier layer. In the present invention, the thickness of the GaN buffer layer is preferably 0.5-3 μm, specifically 0.5 μm, 1.0 μm, 2.0 μm, or 3.0 μm.

[0024] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a GaN channel layer disposed on the upper surface of the GaN buffer layer. In the present invention, the thickness of the GaN channel layer is preferably 100-2000 nm, and specifically can be 100 nm, 300 nm, 500 nm, 1000 nm, 1500 nm, or 2000 nm.

[0025] The high dynamic stability and high withstand voltage GaN power device provided by the present invention comprises an Al2O3 layer arranged on the upper surface of the GaN channel layer. x Ga 1-x N barrier layer. In the present invention, the Al x Ga 1-x The value range of x in the N barrier layer is 0.25; the Al x Ga 1-x The thickness of the N barrier layer is 10-30 nm, and specifically can be 10 nm, 15 nm, 20 nm, 23 nm, 25 nm, or 30 nm.

[0026] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a device arranged in the Al x Ga 1-xA gate electrode on the upper surface of the N barrier layer and a passivation layer surrounding the gate electrode. In the present invention, the gate electrode preferably comprises a first TiN layer, an Al layer, and a second TiN layer stacked sequentially from bottom to top; the thicknesses of the first and second TiN layers are preferably 10-100 nm, specifically 10 nm, 50 nm, and 100 nm, respectively; the thickness of the Al layer is preferably 1000 nm. In the present invention, the material of the passivation layer is preferably SiN; the thickness of the passivation layer is preferably 10-100 nm, specifically 10 nm, 50 nm, and 100 nm.

[0027] The high dynamic stability and high withstand voltage GaN power device provided by the present invention includes a GaN channel layer and an Al x Ga 1-x Both ends of the N barrier layer are connected to the GaN channel layer and the Al x Ga 1-x The source electrode and drain electrode are ohmically contacted to the N barrier layer. In the present invention, the source electrode and drain electrode independently preferably include a titanium layer and an aluminum layer stacked sequentially from bottom to top; the thickness of the aluminum layer is preferably 500-5000 nm, specifically 500 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, or 5000 nm; the thickness of the titanium layer is preferably 1-20 nm, specifically 1 nm, 5 nm, 10 nm, 15 nm, or 20 nm.

[0028] The present invention also provides a method for preparing the high dynamic stability and high withstand voltage GaN power device described in the above technical solution, comprising the following steps: A barrier layer, a GaN buffer layer, a GaN channel layer, an AlxGa1-xN barrier layer and a passivation layer are sequentially prepared on the surface of the substrate to obtain a semi-finished product; A source electrode, a drain electrode and a gate electrode are prepared on the semi-finished product to obtain the high dynamic stability and high withstand voltage GaN power device.

[0029] In the present invention, the preparation of the barrier layer preferably adopts an atomic layer deposition process. The present invention has no special limitation on the specific process of the atomic layer deposition process, and it is sufficient to adopt the process well known to those skilled in the art. In the present invention, after the atomic layer deposition process, it is also preferably included in the process of annealing the obtained thin film, and the annealing temperature is preferably 400~600℃, specifically 400℃, 500℃, 600℃; the holding time is preferably 1~50min, specifically 1min, 10min, 20min, 30min, 40min, 50min; the annealing is preferably carried out in a nitrogen atmosphere. In the present invention, the film obtained by the atomic layer deposition process has good density; after further annealing, the grown film can be transformed into a crystal with a more complete lattice arrangement. Compared with silicon, the lattice constant of the barrier layer is closer to that of GaN, so the quality of the GaN material grown on the crystallized barrier layer is better.

[0030] The present invention provides the GaN buffer layer, GaN channel layer, Al x Ga 1-x The preparation method of the N barrier layer and the passivation layer is not particularly limited and can be carried out using a process well known to those skilled in the art. In the present invention, due to the spontaneous polarization effect of the GaN material and the Al x Ga 1-x The piezoelectric effect formed by the N material will form a layer of two-dimensional electron gas in the GaN channel layer. The conductivity of the GaN device is based on this layer of two-dimensional electron gas.

[0031] The present invention has no special limitation on the method for preparing the source electrode, the drain electrode and the gate electrode, and they can be prepared using processes well known to those skilled in the art.

[0032] Unless otherwise specified, the materials and equipment used in the present invention are all commercially available products in the art.

[0033] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] Example 1 The silicon wafer was placed in the ALD equipment to grow a layer of Al2O3 film with a thickness of 25nm. After the growth was completed, it was annealed at 500℃ in a nitrogen atmosphere for 10 minutes. The obtained structure is as follows Figure 1 As shown (where 2 is the Al2O3 layer); Then the silicon wafer with Al2O3 layer is placed in MOCVD equipment to grow GaN buffer layer, GaN channel layer and Al x Ga 1-x N (x = 0.25) barrier layer, wherein the thickness of the GaN buffer layer is 2 μm, the thickness of the channel layer is 300 nm, and the thickness of the barrier layer is 23 nm; due to the spontaneous polarization effect of the GaN material and the Al x Ga 1-x The piezoelectric effect formed by the N material will form a two-dimensional electron gas in the GaN channel layer, the structure is as follows Figure 2 As shown; Then in Al x Ga 1-x On top of the N barrier layer, a layer of SiN is grown as a passivation layer using PECVD equipment with a thickness of 50nm; then the source and drain electrodes are made. The electrodes use a Ti / Al structure with thicknesses of 10nm / 1000nm respectively. The structure is as follows Figure 3 As shown; Then make the gate electrode, the gate electrode adopts TiN / Al / TiN structure with thickness of 50nm / 1000nm / 50nm, and the device is completed. Figure 4 shown.

[0035] It can be seen from the above embodiments that the present invention adopts the atomic layer deposition process to grow an Al2O3 thin film on the surface of a silicon substrate, and the obtained thin film has good density; after further annealing, the grown thin film can be transformed into a crystal with a more complete lattice arrangement. Compared with silicon, the lattice constant of the Al2O3 layer is closer to that of GaN, so the quality of the GaN material grown on the crystallized Al2O3 layer is better; at the same time, the Al2O3 layer is an insulating layer, and the electrons in the substrate cannot pass through the Al2O3 layer, thereby preventing the substrate electrons from being trapped in the buffer layer and reducing the dynamic resistance problem; at the same time, due to the presence of the Al2O3 layer, the pressure resistance of the vertical path from the drain to the substrate is improved, thereby making the device's voltage resistance higher.

[0036] Although the above embodiment provides a detailed description of the present invention, it is only a part of the embodiments of the present invention, not all of the embodiments. Other embodiments can be obtained based on this embodiment without creativity, and these embodiments all fall within the scope of protection of the present invention.

Claims

1. A GaN power device with high dynamic stability and high withstand voltage, characterized in that: The present invention comprises a substrate, a barrier layer arranged on the upper surface of the substrate, a GaN buffer layer arranged on the upper surface of the barrier layer, a GaN channel layer arranged on the upper surface of the GaN buffer layer, and an Al2O3 layer arranged on the upper surface of the GaN channel layer. x Ga 1-x N barrier layer, provided on the Al x Ga 1-x The gate electrode on the upper surface of the N barrier layer and the passivation layer surrounding the gate electrode are arranged between the GaN channel layer and the Al x Ga 1-x Both ends of the N barrier layer are connected to the GaN channel layer and the Al x Ga 1-x The source electrode and the drain electrode of the N barrier layer are in ohmic contact; The material of the barrier layer includes Al2O3 or AlN; The Al x Ga 1-x The value range of x in the N barrier layer is 0.

25.

2. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The substrate comprises a silicon wafer, and the thickness of the substrate is 600-1000 μm.

3. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The thickness of the barrier layer is 20-30 nm.

4. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The thickness of the GaN buffer layer is 0.5-3 μm.

5. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The thickness of the GaN channel layer is 100-2000 nm.

6. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The Al x Ga 1-x The thickness of the N barrier layer is 10~30nm.

7. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The source electrode and the drain electrode independently include a titanium layer and an aluminum layer stacked sequentially from bottom to top; The thickness of the aluminum layer is 500-5000 nm, and the thickness of the titanium layer is 1-20 nm.

8. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The gate electrode comprises a first TiN layer, an Al layer and a second TiN layer stacked in sequence from bottom to top; The thickness of the first TiN layer and the second TiN layer are independently 10-100 nm; The thickness of the Al layer is 1000 nm.

9. The high dynamic stability and high withstand voltage GaN power device according to claim 1, characterized in that: The material of the passivation layer is SiN; the thickness of the passivation layer is 10-100 nm.

10. The method for preparing a high dynamic stability and high withstand voltage GaN power device according to any one of claims 1 to 9, characterized in that: The following steps are involved: The barrier layer, GaN buffer layer, GaN channel layer, Al x Ga 1-x N barrier layer and passivation layer to obtain a semi-finished product; A source electrode, a drain electrode and a gate electrode are prepared on the semi-finished product to obtain the high dynamic stability and high withstand voltage GaN power device.

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