System and method for accurately measuring the dynamic resistance of power devices

Abstract

The test measurement system includes a DUT interface configured to be coupled to at least one device under test (DUT), and a measuring device coupled to this interface. This measuring device has one or more processors configured to receive a measurement signal on a first input channel during DUT testing, generate a first sample waveform from the measurement signal using a first parameter set, receive a measurement signal on a second input channel, generate a second sample waveform from the measurement signal using a second parameter set, and generate a measurement waveform from the combination of the first and second sample waveforms. Furthermore, the measuring device is configured to measure the settling error in the first pulse of a double-pulse test and correct the measured values ​​in subsequent pulses for the settling error.

Description

Technical Field

[0001] The present disclosure relates to a test measurement system, and particularly to a technology for evaluating dynamic characteristics of power semiconductor devices.

Background Art

[0002] Wide-bandgap semiconductors offer advantages in the manufacture of high-voltage, high-speed, high-output, and high-frequency electronic devices compared to conventional bandgap semiconductor materials.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Measuring and evaluating the electrical properties of devices made from wide-bandgap materials is more difficult in several ways than measuring those made from conventional materials. For example, wide-bandgap transistors have on-state voltages of only a few volts, while off-state voltages can exceed hundreds or even thousands of volts. Such a large difference can cause wide-bandgap transistors to exhibit a shift in on-state channel resistance over time. This is due to charge trapping near the gate caused by the high drain-gate electric field during the off-state. The gate drive energy may decrease during the subsequent on-state until the trapped charge dissipates. This dissipation occurs too quickly to be accurately measured by conventional electrostatic resistance measurement techniques, but it occurs fast enough to affect the average conduction loss of the device under test in the 100 kHz to 1 MHz frequency range.

[0005] Therefore, dynamic on-resistance Rds(on), one of the measurements frequently performed in characterizing wide-bandgap power devices, is typically measured using time-domain instruments such as oscilloscopes with circuit probes or test fixtures. Probe settling errors and oscilloscope channel settling errors, as mentioned above, significantly limit the ability to accurately measure Vds(on), which is a preliminary step to Rds(on) measurement, due to the large difference between the on-voltage and off-voltage in power devices. For example, in modern electric vehicle chargers and motor drives, the off-voltage Vds(off) is around 800 volts, while the on-voltage Vds(on) can be as low as 2-4 volts. Measuring the effect of dynamic Rds(on) with an accuracy of 10% or less requires an accuracy of 0.2 volts, which represents a dynamic range of 800V / 0.2V, or 4000:1, exceeding the dynamic range of many conventional oscilloscopes.

[0006] A conventional solution to accurately measure Rds(on) by sufficiently reducing the dynamic range is to add a hardware voltage clamp circuit (clamp circuit) between the device under test and the voltage probe of the measuring instrument, limiting Vds to a voltage low enough to observe the Vds(on) voltage but much smaller than the Vds(off) voltage. For example, setting the clamp voltage to 5 volts limits the dynamic range to approximately 5V / 0.2V = 25:1, which is easily achievable. While hardware clamp circuits may help with the dynamic range problem, using hardware clamps increases the cost of the test equipment, and parasitic components such as RC (resistivity-capacitance) attenuation and voltage offset may appear in the circuit under test, which can negatively affect measurement accuracy. Furthermore, using hardware clamps requires additional time and effort to properly couple the clamp to the power device under test, and the clamp needs to be impedance-matched to the test board, thus delaying the test setup.

[0007] In addition to the dynamic range issues mentioned above, other problems hinder the accurate measurement of the dynamic characteristics of power devices in conventional test environments. For example, the high operating voltage of acquisition (waveform data acquisition) systems can cause overdrive, leading to the acquisition of inaccurate values ​​during testing and reducing measurement accuracy. Furthermore, some wide-bandgap materials, such as gallium nitride (GaN) materials, experience current collapse under certain test conditions, reducing the DC drain current of GaN-based transistors. Since Rds(on) is usually determined by measuring the drain current, this current collapse can lead to inconsistencies in Rds(on) measurements for these devices. Moreover, power devices can overheat during testing due to increased resistance, which contributes to a decrease in the measurement accuracy of power devices. Therefore, the industry needs new technologies to measure and characterize power devices with higher accuracy than conventional test equipment and methods. [Means for solving the problem]

[0008] Embodiments of this disclosure are used for measuring, testing, and characterizing power semiconductor devices, such as wide-bandgap devices. These devices may be formed from silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), but other materials may be used, and embodiments are not limited to devices made from these materials alone. As described above, when testing power semiconductor devices with oscilloscopes and other measuring instruments, these wide-bandgap power devices present challenges compared to standard bandgap devices such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs) due to their much higher voltages and currents. Power devices can have high operating voltages (i.e., off-state voltages), but their on-state voltages can be only a few volts. Therefore, any device attempting to accurately measure both the operating and standby states of a power device faces the challenge of a limited dynamic range and the resulting quantization errors. Embodiments of this disclosure utilize various techniques, either in combination or independently, to reduce errors associated with the characterization of power devices. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram according to an embodiment of the present disclosure, showing a test system that includes a test measurement device for accurately measuring electronic devices, in addition to a DUT fixture or test platform. [Figure 2] Figure 2 is a partial circuit diagram of the test system based on Figure 1, showing its specific connections. [Figure 3] Figure 3 shows graphs illustrating the conventional gate-source voltage characteristics (Figure 3A), conventional drain-source voltage characteristics (Figure 3B), and conventional drain current characteristics (Figure 3C) of an ideal power device under test. [Figure 4]Figure 4 shows a method for improving the measurement accuracy of a test platform by accurately measuring the error characteristics according to an embodiment of the present disclosure. [Figure 5] Figure 5 shows an example of Vds voltage measured from a power transistor, illustrating the difficulty of accurate measurement. [Figure 6A] Figure 6A shows an example of a setup menu screen of the type seen in the test and measurement device of Figure 1, according to an example of an embodiment. [Figure 6B] Figure 6B shows an example of a setup menu screen of the type seen in the test measurement device of Figure 1, according to an example of an embodiment. [Figure 7] Figure 7 is an embodiment block diagram showing how a measuring device according to an example of the embodiments of this disclosure is set up to receive test waveforms from the DUT. [Figure 8] Figure 8 is a graph showing an example of a waveform that can be received by the measuring device in Figure 7, according to the embodiment. [Figure 9] Figure 9 shows an example of the operation available to the measuring apparatus in Figure 7 for generating a reconstructed graph from the components of the input waveform, according to an embodiment of the present disclosure. [Figure 10] Figure 10 shows an example of the operation of an embodiment that can be used with the measuring device in Figure 7 to generate a reconstructed graph from the input waveform components according to an embodiment of the present disclosure. [Figure 11] Figure 11 is a screen of the output signal illustrating the operation of generating a reconstructed graph from the input waveform component to the constituent waveform input according to an embodiment of the present disclosure. [Figure 12] Figure 12 is a screen showing an example of the output signal of the measuring device in Figure 7 according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] To evaluate the power characteristics of one or more devices under test (DUTs), a separate test platform is generally required to operate the DUTs during the test, in addition to test measurement equipment such as an oscilloscope. Figure 1 shows a test system 10 including a DUT test platform 20 and test measurement equipment 40. The test system 10 may include some or all of the components shown in Figure 1.

[0011] The DUT test platform 20 is configured to hold and operate one or more DUTs 27 during testing by the test measurement device 40. The test platform 20 includes one or more test boards 26 that support one or more DUTs 27 under test. The DUTs 27 are connected to the test measurement device 40 via one or more measuring probes 24 in known ways to test various voltages and currents of the DUT at various stages of the test process. The test boards 26 may also be connected to a gate drive circuit 28, which generally switches one or two DUTs 27 on and off at desired time intervals and, in some cases, also provides power protection for the DUTs. The DC circuit 32 may include a DC link capacitor, a DC power supply, and a load inductor. A current transducer 30 and a signal generator 34 are connected to the test board 26 to enable testing of the DUTs 27. The operation of the DC circuit 32 and the DUTs 27 may generate heat, and the DUTs may require a specific temperature range for testing. Therefore, the power test platform 20 may include a temperature control circuit 36 ​​for controlling the temperature of the DUT 27.

[0012] The test measurement device 40 may have a wide variety of components, including a user interface 42 that allows the user to interactively operate various menus. The user interface 42 provides an interface for the user to make selections and set parameters in the test being performed, such as a touchscreen display or various buttons and knobs. Although shown as a component of the test measurement device 40 in Figure 1, the user interface 42 may be a separate device independent of the test measurement device, such as a personal computer or other computing device. The user interface 42 may receive commands from a control device connected to the test measurement device, for example, via the Internet.

[0013] The test measurement device 40 has one or more processors 44, which control the operation of the test measurement device and cause the test measurement device to perform the requested tests on the DUT 27. As used in this application, the term "processor" means any electronic component that can receive instructions and execute operations, such as, for example, a microcontroller, a field programmable gate array (FPGA), and an application specific integrated circuit (ASIC), which will be described in detail below. The one or more processors 44 communicate with a memory 45, which stores operations such as programs and subroutines, and data collected during the operation of the test measurement device 40. The memory 45 is shown as a single memory in FIG. 1 for convenience, but in reality, the test measurement device 40 has a number of memories distributed throughout the test measurement device for various storage purposes. The measurement unit 46 typically tests and measures the parameters of the DUT 27 connected to the test measurement device 40 via one or more probes 24 such as voltage probes and current probes. One such test described in this application is called a double pulse test (DPT), in which one or more DUTs 27 receive pulses from the gate drive circuit 28 in a specific pattern to facilitate the test by operating the circuit connected to the DUT in a specific way. This test is called a double pulse test, but the test procedure may involve performing multiple pulses at various timings, and it is important to control one or more DUTs. Furthermore, the double pulse test and other various tests performed by the test measurement device on the DUT may be repeated depending on the specific test being performed and its purpose. Some tests may involve thousands to millions of individual steps, while some tests may be performed with very few steps.

[0014] Figure 2 shows a test system 50 containing many of the same components as the test system 10 described with reference to Figure 1, but presented in a manner that facilitates the explanation of the various tests performed on the DUT. The test system 50 connects a power supply 52 and a signal generator 56 to a gate drive circuit 54 to drive the gates and other terminals of the Low Side DUT 72 and High Side DUT 74. In Figure 2, DUTs 72 and 74 are shown as power MOSFET (power Metal-Oxide-Semiconductor-Field-Effect Transistor) devices, but the embodiments are not limited to these devices and can also be used to test, for example, MOSFETs, insulated-gate bipolar transistors (IGBTs), diodes, etc. In some configurations, the high-side DUT 74 may be diode-connected, with its gate connected to its source. Other test configurations may arise in a manner different from those shown in Figure 2. The measuring device 60 may be an embodiment of the measuring device 40 described with reference to Figure 1. The measuring device 60 is coupled in known ways to specific nodes and components of the circuit shown in Figure 2, as will be described in detail below, to detect and measure various voltages and currents at various stages of operation of the DUTs 72 and 74. The circuit connected to the DUT 72 includes a variable voltage source 80, a capacitor bank 82, and an inductor 84, which operate to control the operation of the DUT. These circuit components may also be driven by the components of the DUT test platform 20 described above with reference to Figure 1.

[0015] Generally speaking, during operation, the user supplies input, either remotely or directly, through the user interface 42 (FIG. 1) to control the operation of the test platform 20, and measures the characteristics of the DUTs 72 and 74. The measurement of dynamic characteristics is generally performed using a half-bridge circuit as shown in FIG. 2. The half-bridge circuit consists of a high-side device DUT74 and a low-side device DUT72, which correspond to the DUT27 shown in the test system 10 of FIG. 1. In the illustrated half-bridge circuit, the high-side device DUT74 and the low-side device DUT72 are coupled in series between the power supply voltage node and the reference voltage node. In normal operation, when the low-side device DUT72 is turned on, the desired current flows from the voltage source 80, through the test inductor 84, through the low-side device DUT72 to the reference voltage. Subsequently, the low-side device DUT72 is turned off and the high-side device DUT74 is turned on. This operation first initiates the inductor current from the inductor 84 and then circulates it through the high-side device DUT74. Alternatively, when only one DUT27 is being tested, the high-side device DUT74 may be replaced with a diode. After a specific time according to the characteristics of the high-side and low-side DUTs 72 and 74, the high-side device DUT74 is turned off and the low-side device DUT72 is turned on again. During these transitions, the test measurement device 60 collects the data necessary for testing and characterizing the DUTs 72 and 74, and then the test measurement device 60 calculates or determines specific parameters and displays these parameters to the user testing the DUT.

[0016] Reduction of setting error

[0017] As mentioned above, measuring the characteristics of wide-bandgap power devices requires conventional measuring instruments to operate at a wider dynamic range than standard bandgap devices. Operating measuring instruments at a wider dynamic range can reduce their ability to detect small variations in the parameters under test. The dynamic range of measuring instruments used to test wide-bandgap power semiconductor devices can be limited by various factors, including settling error, noise, and the bit resolution of the analog-to-digital converter (ADC). Settling error can be the biggest factor reducing the dynamic range of a measuring instrument. Settling error can be observed in the input channels of an oscilloscope, and also in the measuring probe, and is usually related to mismatches in parallel RC voltage divider circuits in both the probe and the instrument's test channels. Furthermore, overdrive error can cause additional settling error. In modern oscilloscopes and probes, the settling error is typically specified as around ±2%, and in combinations of probes with low settling error and channels with similarly low settling error, the settling error can reach up to ±4%. Measurement errors of this magnitude can deviate significantly from actual measurements and potentially lead to a deterioration of the measurement results.

[0018] In some embodiments of this disclosure, the first pulse of a double-pulse test (DPT) is used to measure the characteristics of the settling error of the channels of the measuring probe and measuring device in the actual test environment of the DUT under test. The settling error obtained during the operation of the first pulse may then be corrected by subtracting it from the measurement value of the second (or subsequent) pulse of the DPT, or by other means, so that the effect of the settling error is eliminated or significantly reduced, and Rds(on) is accurately measured.

[0019] Referring to Figures 2, 3A, 3B, and 3C, in a conventional DPT test, the device under test (DUT), such as the low-side device 72 (Figure 2), is turned on during the first drive pulse. The first drive pulse may take the form shown during period P1 in Figure 3A, which is a graph of the gate drive voltage applied to the exemplary DUT. The simulated measurements of the DUT in Figures 3A, 3B, and 3C are based on an ideal semiconductor, and therefore the graphs are also ideal graphs, but are sufficiently similar to actual device operation for illustrating embodiments of the present invention. Typically, two pulses are applied to the DUT, as shown during periods P1 and P3 in Figure 3A. Period P2 represents the time between the two pulses of the DPT. In this example, a drive voltage of approximately 15 volts is applied to the gate of the DUT over a period of 20 to 25 microseconds (μs).

[0020] Figure 3B shows the drain-source voltage Vds of the DUT. At time 0, the gate drive voltage (see Figure 3A) was below the DUT's on-voltage, so the DUT was off. In this test setup, the off-voltage between the drain and source of the DUT is approximately 600 volts. Then, around 3-4 microseconds from the start of DPT, the pulse drive circuit increases the gate drive voltage at the gate of the DUT to approximately 15 volts, thereby turning the DUT on. When the ideal transistor is on, the drain-source voltage across the ideal transistor is zero, so Vds drops from approximately 600 volts at the start of P1 to zero volts (see Figure 3B). When the DUT (e.g., the low-side device 72 in Figure 2) is turned on at the start of P1, the current flowing through the load inductor 84, and therefore through the DUT, becomes a linear ramp current that reaches the desired test current value. The current flowing through the DUT is shown in the graph of Figure 3C, which is temporally consistent with the graphs of Figures 3A and 3B. The current flowing through the load inductor 84 continues to increase until the start of period P2, at which point the gate drive circuit reduces the voltage applied to the gate of the DUT to 0 volts or less (Figure 3A), causing the DUT to turn off.

[0021] During period P2, the DUT remains off, which returns the Vds voltage to approximately 600 volts (Figure 3B), and the current flowing through the DUT also decreases to zero. Any pulse of the DPT may cause a certain amount of overshoot in Vds and Id, as shown in Figures 3B and 3C.

[0022] At the start of period P3, the DUT is turned on again by applying a second pulse to the gate (Figure 3A). Note that the current flowing through the DUT begins to rise from around the time the first pulse ended, i.e., the start of period P2 (60 amperes). Referring back to Figure 2, the inductor current flowing through inductor 84 is maintained through other switching devices such as the diode and the high-side device 74 in the half-bridge circuit during the DUT's off-time. This means that the second pulse (during period P3) begins with approximately the same current as that flowing at the end of the first pulse, as shown in Figure 3C. Measurements of one or more DUTs are typically performed during the second pulse or subsequent pulses of the DPT, i.e., during period P3, rather than during the first pulse P1, so that the switching operation of the DUT can be measured or determined at or near the desired test current.

[0023] Referring to Figure 2B, note that the step of Vds from 600V to approximately 0V is almost the same at the start of periods P1 and P3. Therefore, the settling error of the measuring probe (reference numeral 24 in Figure 1) and the channel settling error of the test measuring device 40 (Figure 1) should also be essentially the same, provided that the interval between DPT pulses is long enough for the measuring probe and measuring device to settle to the same state as before the first DPT pulse.

[0024] Typically, the width of the first pulse of the DPT is chosen so that the inductor current measured at Id (Figure 3C) increases (ramp) at a constant rate to the desired test level, and the width of the second pulse is set to mimic the pulse width of the intended application so that the DUT is tested under conditions close to its operating conditions. However, the length of period P2, i.e., the time between DPT pulses, does not significantly affect the DPT test, so the period of P2 can be set to a period that ensures the test system can reliably settle, as long as extending the period of P2 does not significantly affect the state of the DUT test. The time constants of the probe and oscilloscope measurement channels are typically in the range of about 10 μs, and a time constant of 5 times is a typical waiting time to minimize the effect of the RC time constant. Therefore, a settling time of about 50 μs for the period of P2, which is the time between the first and second pulses of the DPT, should in most cases be sufficient for the measurement channel and probe to settle (settle down, stabilize) after measuring the first pulse of the DPT. In other embodiments, the time between the first pulse and the subsequent pulse may be between 30 and 50 μs. In other embodiments, the time may be between 30 and 100 μs.

[0025] Figure 4 is a graph illustrating the operation of an embodiment according to this disclosure. The graph in Figure 4 is similar to the graph in Figure 3B, but the period P2 in Figure 4 is much longer than the period P2 in Figure 3B. In the embodiment, the settling error of the test channel and probe of the measuring device is determined using a large voltage drop at the beginning of period P1. Note that this settling error is determined using the same test channel, the same probe, the same DUT and the same temperature as the actual measurement performed during period P3, and is therefore likely to be in very good agreement with the settling error experienced during the actual measurement during period P3. The measuring device can then remove the settling error just determined in period P1 by subtracting it from the measurement value of the second pulse by the measuring device.

[0026] After removing the settling error, the measured dynamic Rds(on) of the DUT is calculated by the measuring instrument as Rds(t) = ΔVds(t) / ΔIds(t). Here, the two deltas are calculated as the difference between the second and first pulses of each parameter measured at time t. The settling error of the measuring instrument and probe is formally canceled out based on this ΔVds(t) calculation, leaving only the difference in drain-source voltage between them, which is caused by multiplying the dynamic Rds by the different drain currents. Since the inductor current flowing through inductor 84 is basically ramped (defined as di / dt = V / L) during the duration of the two pulses of the DPT, the calculation of ΔIds(t) is basically constant and represents the current flow at the start of the second pulse.

[0027] This method, which reduces the impact of settling errors in dynamic measurements of power devices, utilizes the first pulse of the DPT to measure the settling error characteristics for a period shorter than 1 millisecond before measuring Vds(on) during the second pulse period, under the same settings and environmental conditions. Therefore, the error measured in the first pulse is considered to be significantly more reliable than attempts using correction factors or specific evaluation factors provided by the probe or measuring instrument manufacturer, which may vary considerably from the date of manufacture of the instrument. In embodiments, the only requirement added to a standard DPT setup is that the time between pulses (period P2 in the above example) must be set long enough so that everything except the inductor current settles to the same state before the second pulse as it was before the first pulse of the DPT. In another embodiment, the impact of noise measured during testing can be minimized by performing multiple characterizations and tests and averaging their results with each other.

[0028] Minimizing errors through clipping using a high dynamic range.

[0029] As mentioned above, in addition to settling errors in measuring devices and probes that negatively affect measurements, high-precision power device measurements can also suffer from problems stemming from the need for a high dynamic range. As stated above, power devices can operate under conditions exceeding 1000 volts, and it is best to test these devices near their operating conditions. Therefore, measuring devices used to test power devices must be capable of accurate measurements exceeding 1000 volts.

[0030] When a signal under test is input to a measuring device, the input signal is typically an analog signal that is digitized into numerous digital samples by one or more analog-to-digital converters (ADCs) within the device. When the input needs to be measured over a wide range, the ADC's output steps are more widely spaced than when the input voltage range is narrower, making it difficult to fully utilize the ADC. For example, Figure 5 is a chart showing an example of Vds voltage measured from a power transistor. The off-voltage in this graph is approximately 550 volts, but the circled on-voltage is only a very small portion, like 30 volts out of a total of 600 volts. This is an example of a measuring device that requires a high dynamic range. Also, because the on-voltage covers only a small portion of the total voltage range, the ADC's capabilities are not fully utilized, making it difficult for the measuring device to accurately distinguish small changes in the on-voltage.

[0031] As mentioned above, one way to address dynamic range mismatch is to use hardware voltage clamping to clamp voltages like the Vds voltage shown in Figure 5 to much smaller values ​​such as 25 or 50 volts. In this way, the on-voltage of the object being measured is limited to approximately 50% of the total voltage range by the hardware voltage clamping, allowing the ADC of the measuring instrument to be used effectively. However, as mentioned above, hardware clamping is an additional component that needs to be designed to suit the test environment, and its use also has the disadvantage of incurring additional costs.

[0032] Some embodiments of this disclosure address this problem by modifying certain values ​​measured by the device without requiring additional hardware. More specifically, these embodiments perform a software “clamping” operation to replace sampling values ​​exceeding a maximum value with the maximum value. This maximum value may be selected to ensure that the measuring device operates within a dynamic range that can accurately measure a region of interest, such as the Vgs(on) value of a power transistor. This allows a lower (narrower) dynamic range to be used to cover the operating voltage limited by the selected maximum value.

[0033] In various embodiments, this operation of limiting the input value to a maximum value can be performed in various ways. In one embodiment, an automated process scans the measured values ​​and replaces any values ​​exceeding the maximum value with the maximum value. In another embodiment, the measuring device's "scaler" function is used to identify a portion of the waveform and determine the minimum and maximum voltages from it. The measuring device then adjusts the scale of the input waveform to match the size of the waveform determined by this scaler function. This embodiment works well for test patterns that tend to repeat within a specific range. In another embodiment, the ADC may be controlled to analyze the input value and, if it is above the maximum level, to generate an output value at the maximum level. The ADC can also be configured to digitize this "clipped" waveform, i.e., the input limited to a maximum value, at a relatively fine level, so that subtle differences in the clipped waveform can be identified. In another embodiment, or as an extension of the embodiments described above, the measuring device is configured to change the configuration of the input signal for a particular input channel based on a value provided by the user, even if the value actually received on that channel exceeds the value provided by the user. For example, the user can specify that the maximum value of the waveform received on channel 1 of the measuring device should not exceed 25 volts. Accordingly, the measuring device is set to adjust to a scale that matches the maximum value, for example, setting the input channel to 10 volts per division on the screen (10V / div). In practice, the user knows that the voltage on channel 1 exceeds 25 volts, and in some cases reaches 800-1000 volts. However, by setting the input in this way, the ADC digitizes the input sample at the fine level set to 10V / div. For example, very high voltages exceeding 200 volts on a channel set to 10V / div may be digitized at the ADC's maximum value, so that, for example, there is almost no distinction between a 250-volt sample and an 800-volt sample received on an input set to measure at 10V / div. However, this is not a problem if the voltage that the user is only interested in is less than 25 volts. In yet another embodiment, the user may manually set the vertical scale that the device measures for a particular channel.In any of the above embodiments or other embodiments, the measuring device may be used to capture or modify the input waveform with high fidelity in areas or parts that are important to the user.

[0034] In this disclosure, “clipped” waveform or similarly identified means a waveform having one or more portions with high resolution in a particular region of interest, in addition to one or more portions with low resolution in a region outside the region of interest.

[0035] Figures 6A and 6B show setup screens provided to the user via the user interface 42 (Figure 1), etc., which allow the test and measurement device 40 to be configured to perform some of the clamping and clipping operations described above.

[0036] Typically, the user sets the source of one or more DUTs under test in the measuring device. In the setting menu 600 of Figure 6A, the channel through which the signal acquired with high resolution using any of the above techniques or the input signal passes, or the reference code of the signal, can be specified. This reference code of the signal is referred to here as "clipped". In practice, the signal reference code specified in the setting menu 602 (for example, the voltage source (Vds) is selected as reference 1, meaning that the waveform of reference 1 in the measuring device 40 is coupled to measure the drain-source voltage of a DUT such as the low-side device DUT 72 in Figure 2) may also be acquired, and in this example, it is acquired as reference 4. The method of using the measurement of the "unclipped" voltage is described below with reference to another embodiment of this disclosure. In the setting menu, the current source is set to be received as reference 2, and the gate-source voltage is set to be received as reference 3.

[0037] A dedicated menu for measuring the Rds(on) value is shown as menu 602 in Figure 6B. This menu 602 allows specifying the maximum on-voltage. This value sets all measurement voltages exceeding this maximum value using the clipping process described above. In another embodiment, the measuring device scales the input channel based on the specified maximum on-voltage. The maximum values ​​for current and gate voltage can also be set in a similar manner.

[0038] Pressing the "Power Preset" button shown in menu 602 causes the measuring device 40 to set the vertical and horizontal scales, as well as a trigger synchronized with the gate drive signal so that driving the gate of the DUT turns on the DUT and indicates the start of the DPT pulse. Referring again to menu 600 in Figure 6A, note that there are two versions of the Vds signal that the measuring device receives. The first one, labeled "Reference 1," is the measurement of the "clipped" voltage, while the second one, labeled "Reference 4," is the measurement of the "unclipped" voltage. In practice, in some embodiments, the measuring device receives the same signal as both Reference 1 and Reference 4, but the input channels associated with these reference codes are set to have different measurement characteristics. Most importantly, the clipped voltage measurement is set to a much lower V / div (voltage scale) level than the unclipped voltage measurement, so that the accuracy of the measurement at this lower V / div is maintained. For example, the measured value of the clipped voltage is set to 10V / div (10 volts per division), while the measured value of the unclipped voltage is set to, for example, 100V / div (100 volts per division). 10V / div is far more effective at detecting small voltage fluctuations than 100V / div. The following describes in detail how the measuring device utilizes these measurements, which are performed using different input parameters such as the granularity of the input signal.

[0039] After the input channel is set, the user then activates the DPT using the gate drive circuit 28 (Figure 2) to drive the gate of the DUT. The gate drive circuit 28 can be activated by activating the signal generator 34. Once the gate drive circuit 28 activates the DPT, the measuring device operates and records all waveforms used for power device analysis, such as the gate-source voltage, drain-source voltage (measured on two different input scales), and drain current waveform, as described above. In some embodiments, the measuring device may refine the edges of pulses in the DPT. The setting menu 600 indicates this function as an option.

[0040] By clipping the waveform using the method described above, the device can perform detailed analysis of data acquired at a fine scale while retaining input data of an unclipped waveform acquired at a standard scale.

[0041] Reconstruct the waveform from the two acquired waveforms.

[0042] Embodiments of this disclosure reconstruct a composite waveform using both clipped and unclipped waveforms. This involves combining some components from the clipped waveform with other components from the unclipped waveform to generate a composite waveform with higher accuracy than either the clipped or unclipped waveform alone.

[0043] Figure 7 is a high-level circuit diagram illustrating various waveforms from the DUT test board 726 measured by the measuring device 740. The measuring device 740 may be an example of the test measuring device 40 (Figure 2), and the measuring device 726 may be an example of the test board 26 or other components of the test platform 20 (Figure 2). The measuring device 740 processes the unclipped waveform of the Vds waveform in channel 1 of the measuring device and the clipped waveform of the Vds waveform in channel 2 of the measuring device. Depending on the implementation details, the clipping process may be carried out in several different ways. In one embodiment, the V / div in channels 1 and 2 are set to different values ​​when the Vds waveform is acquired from the DUT test board 726. In addition, the measured current flowing through the DUT is recorded in channel 3 of the measuring device.

[0044] Figure 8 provides a highly simplified graphical illustration of the generation of a reconstructed waveform using two different measurement waveforms to illustrate the general concept of an embodiment of this disclosure. The waveform shown in Figure 8A represents the full-scale, i.e., unclipped, idealized Vds waveform 802 of a power device measured by the measuring instrument. For example, this waveform 802 represents the unclipped Vds waveform acquired on channel 1 (Figure 7) of the measuring instrument 740. The waveform 804 shown in Figure 8B represents the clipped waveform of the same waveform and may be created by any of the techniques described above. Note that the vertical scale of the unclipped waveform 802 in Figure 8A is approximately 200 volts, while the vertical scale of the clipped waveform 804 in Figure 8B is approximately 20 volts. Also note that the region of waveform 804 near 0 volts has identifiable features, while the region of the unclipped waveform 804 near the same region does not have identifiable features. This is because the resolution of the clipped waveform 804 is higher than that of the unclipped waveform 802.

[0045] Figure 8C shows a reconstructed or synthesized waveform 806 generated from portions of both the unclipped waveform 802 and the clipped waveform 804. There are numerous ways to reconstruct waveform 806 from the clipped and unclipped components. The simplest method may be time-based reconstruction (not shown). This method starts at time 0, the beginning of both the clipped and unclipped waveforms, and selects data from only one of these waveforms to include in the synthesized waveform. For example, data from the unclipped waveform 802 can be used for the first part of the reconstructed waveform 806 up to the point where a ripple appears in the clipped waveform 804. Then, data from the clipped waveform 804 can be used for the middle part of the waveform until the Vds signal begins to rise, and at the point where the Vds signal begins to rise, data from the unclipped waveform 802 can be used again. While this resynthesis system is perhaps the easiest to implement, the quality and accuracy of the reconstructed waveform 806 using this technique may be compromised.

[0046] Another embodiment for generating the reconstructed waveform 806 is shown in Figure 8C, in which a portion of the unclipped waveform 802 is used for the beginning and end of the waveform 806. However, the central portion is divided into two sections. In the first section 810, the reconstructed waveform 806 is generated from both the unclipped waveform 802 and the clipped waveform 804. In the second section of the central portion, the clipped waveform 804 is selected for the reconstructed waveform 806 to be synthesized. This technique may yield better results than the time-based method by combining both the clipped and unclipped waveforms in the first section 810, but embodiments of this disclosure employ more advanced techniques in the reconstruction of the synthesized waveform, which will be described in detail below.

[0047] Figure 9 shows an example of the process of flow 900 used to generate a waveform representing a measurement from a DUT, such as a waveform representing the dynamic Rds(on) of a power device with improved accuracy compared to current devices. Although this embodiment is described using Vds as the input waveform and generating an Rds signal from both Vds and Id measurements, embodiments of the present disclosure can use the same technique described herein to generate and analyze a composite waveform of measurable or calculable waveforms from any DUT under measurement.

[0048] Flow 900 begins with step 902, where the optimal parameters for the measuring device to test the DUTs are set, for example, so that the test measuring device 40 (Figure 1) is set up to test one or more DUTs 27. Such parameter settings include setting the ADC to 12-bit mode or to a high-resolution acquisition mode such as high-resolution (HiRes). Next, in the parallel steps 904 and 905, the measuring device acquires a measurement signal, such as the Vds signal from the DUTs, from two different input channels at two different resolutions. A standard version of the measurement signal is acquired in step 904 as a high dynamic range signal at full resolution on one of the multiple channels. The version of the input signal acquired in step 904 is called the full-scale signal or unclipped signal and is generated at the standard resolution for the high dynamic range signal. In some embodiments of power devices, the Vd acquired on this channel may exceed 600 volts or 800 volts and may be quantized at, for example, 100 V / div. Simultaneously, in step 905, a clipped version of the measurement signal is acquired on a separate channel. This clipped waveform is received or processed with a higher resolution than the unclipped waveform received on the other channel. For example, the clipped version of the input signal may be quantized at 10V / div. The high-resolution region may be a specific waveform region on the clipped channel, such as the test region when the DUT is ON. By sampling the same waveform at two different resolutions, embodiments of the present disclosure can reduce quantization noise compared to conventional methods. The quantization levels actually used in steps 904 and 905 are specific to the implementation, but typically the clipped waveform is quantized at a lower scale than the unclipped waveform. Examples of scale levels for the clipped waveform in step 905 may be between 5V / div and 70V / div, preferably between 10V / div and 50V / div, and more preferably between approximately 10V and 20V / div.The unclipped waveform may be quantized in step 904 on a scale of 50V / div to 200V / div, preferably 100V / div or other scales, depending on the signal being measured.

[0049] Step 906 is a configurable process in which the user can average one or both of these acquired copies of signals. Averaging multiple signals received over time reduces noise that may be present in the input channels of the test setup, probe, or measuring device. In some embodiments, each of the two received signals (clipped and unclipped) is averaged independently. Signal averaging can reduce noise by up to 30-40% in some embodiments.

[0050] In step 908, the measuring device stitches together the first and second pulses of the DPT using both the clipped and unclipped versions of the input waveforms acquired in steps 904 and 905. The stitching process in step 908 may be the same as or similar to the process described above with reference to Figure 8C. In this case, the synthesized waveform includes elements of both the unclipped and clipped waveforms. In some embodiments, the unclipped waveform is used for a portion of the stitched Vds waveform during the DPT period when the DUT is off, and the clipped waveform is used when the DUT is on. In other embodiments, various methods are used to stitch together any combination of the clipped and unclipped versions of the waveforms.

[0051] Step 910 performs mathematical modeling, including different slopes for both the clipped and unclipped waveforms, to generate an intermediate waveform that includes both the overall trend characteristics of the full-scale waveform and the high resolution of the clipped waveform.

[0052] In step 912, sinc interpolation is performed at a low-scale digital level to suppress unwanted components from the final waveform and generate a smooth shape.

[0053] In step 914, as detailed above, the length of the settling time required between two pulses of the DPT is determined in order to reduce or minimize the overdrive error (error due to excessive drive), and the measuring device is set to settle within that time. For example, a settling time of 30 μs to 100 μs, preferably around 50 μs, may be set as the optimal time to eliminate or minimize the overdrive error of the measuring device and enable settling. By performing this step 914, deviations in measurement values, settling errors, and deterministic errors that may occur when there is insufficient settling time are minimized.

[0054] Next, in step 916, a new waveform (e.g., Vds waveform) for the test system portion where the DUT is ON is finalized and displayed. In some embodiments, the waveform is generated using the calculation function of the measuring device. A specific example of reconstructing the new waveform is described below with reference to Figure 10.

[0055] After completing the Vds(on) waveform in step 916, the Vds(on) waveform may be used to calculate the Rds(on) waveform by dividing the new Vds(on) waveform completed in step 916 by the drain current of the DUT using the following formula.

number

number

[0056] After the new waveform is displayed, for example, on the display screen of the measuring device, in step 918, the measuring device scans the Rds(on) waveform generated in the above step and selects waveform features such as minimum value, maximum value, and other values ​​of interest. These selected features can be displayed as badges or otherwise presented to the user of the measuring device to facilitate specific tests performed on the DUT.

[0057] Figure 10 is a flowchart illustrating the process of example flow 1000 used to create a new Vds(on) waveform, which is a synthesis of both the clipped and unclipped Vds waveforms described above. Flow 100 in Figure 10 is further explained with reference to Figure 11. Figure 11 is an output display of the composite waveform generated from both the clipped and unclipped Vds waveforms received by the measuring device.

[0058] Flow 1000 begins with step 1002, in which the measuring device acquires both clipped and unclipped waveforms, as described above with reference to flow 900 in Figure 9. Next, in step 1004, the ON portion of each waveform is divided horizontally, i.e., divided into time slices (thin sections), also called chunks. Then, the average value of each chunk is obtained in step 1006. These functions are shown in Figure 11, where the waveform labeled Ch2 is the unclipped waveform, and the waveform labeled Ch3 is the clipped, i.e., low-scale waveform. As described above, the ON portion of the waveform indicates that the DUT is turned on, which is caused by the Vgs voltage. This is shown in Figure 11 to occur at approximately 1 μs.

[0059] Returning to Figure 10, step 1008 examines multiple chunks to find the chunk with the smallest difference, and in step 1010, the chunk with the smallest average difference is selected as the reference chunk among the multiple chunks.

[0060] At this point, flow 1000 begins moving outward from the reference chunk, process 1012 takes place in the next (adjacent) chunk after the reference chunk, and process 1013 takes place in the adjacent chunk before the reference chunk.

[0061] Steps 1014 and 1015 calculate the slope difference in each direction between the current chunk, i.e., the reference chunk, and adjacent chunks. Then, steps 1016 and 1017 generate increment values ​​according to Equation 3.

[0062] [Math 3] Increment value (n) = Average difference of the current chunk (n) - Average difference of the previous chunk (n) n = from base chunk + 1 to the number of chunks

[0063] Next, the sample values ​​of the current chunks before and after the reference chunk are updated according to the increment value in steps 1018, 1019, 1020, and 1021.

[0064] This flow ends in step 1022 after the values ​​of each chunk are updated according to the flow 1000 described above. As a final result, a composite Vds(on) waveform is obtained that considers both clipped and unclipped waveforms and generates a Vds(on) waveform that accurately represents the measured values ​​of the DUT. Compared with conventional methods for measuring the Vds(on) signal based on conventional equipment, the embodiments of this disclosure described above can more accurately determine the actual Vds(on) and Id signals, and thus can calculate and present to the user an Rds(on) signal that accurately describes the operation of the DUT.

[0065] Figure 12 shows an output screen 1200 illustrating an example of the measurement device's output. The output screen displays six different waveforms related to the same period to the user, providing measurement values ​​for the DUT under test. As mentioned above, power devices operate over a very wide operating range, and therefore the embodiments of this disclosure are particularly well-suited for measuring such power devices.

[0066] In this example of output screen 1200, the top waveform labeled Ch2 is the full-scale (unclipped Vds) waveform, while the waveform labeled Ch3 shows the clipped Vds signal. Note the difference between the clipped and unclipped waveforms, which are produced by different processing by the measuring instrument. The clipped Vds signal Ch3 has much higher resolution than the unclipped signal.

[0067] The current flowing through the DUT is shown as a waveform labeled Ch4, and the gate signal applied to the DUT's gate is labeled Ch5. The sharp rise of the gate signal matches the clipped Vds signal, indicating that the DUT was turned on precisely at that point.

[0068] The waveform labeled M1 is the regenerated or reconstructed Vds signal, as explained with reference to Figures 10 and 11. Finally, the waveform labeled M2 is the Rds waveform, which is generated using Equation 1 described above.

[0069] The user interface section 1210 of the output screen 1200 allows for the execution of further functions related to inspection, modification, analysis, operation, and DUT testing. A badge indicating the test results is also displayed in the user interface section 1210.

[0070] By using the above technology, users can accurately measure the characteristics of power devices made from wide-bandgap materials.

[0071] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data type expressions. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, and RAM. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0072] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0073] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0074] A communication medium means any medium that can be used to transmit computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, sound, or other types of signals.

[0075] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0076] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities. Examples

[0077] The following examples are provided that are useful for understanding the technology disclosed herein. These embodiments may include one or more of the examples described below, or any combination thereof.

[0078] Embodiment 1 is a test measurement system comprising a DUT interface configured to be coupled to at least one device under test (DUT), and a measuring device coupled to the DUT interface and having one or more processors, wherein the one or more processors are configured to execute a program that causes the one or more processors to perform the following when performing a double-pulse test: measuring the characteristics of the settling error during the first pulse of the double-pulse test, and correcting the settling error whose characteristics were measured during the first pulse of the double-pulse test from the measured values ​​generated during the second pulse or subsequent pulses of the double-pulse test.

[0079] Example 2 is a test measurement system based on Example 1, wherein the program that causes one or more processors to perform a process to correct the settling error includes a program that causes one or more processors to perform a process to determine the change in voltage measured in the first pulse and the second or subsequent pulse, and a process to determine the change in current measured in the first pulse and the second or subsequent pulse.

[0080] Example 3 is a test measurement system based on Example 2, wherein one or more processors are further configured to execute a program that causes one or more processors to perform a process of determining the dynamic resistance measurement value of the DUT by dividing the voltage change by the current change.

[0081] Example 4 is a test measurement system based on any of the above examples, wherein the first pulse and the second pulse of the double-pulse test are separated by a period determined by the settling time.

[0082] Embodiment 5 is a test measurement system comprising a DUT interface configured to be coupled to at least one device under test (DUT), and a measuring device coupled to the DUT interface and having one or more processors, wherein the one or more processors are configured to execute a program that causes the one or more processors to perform the following processes when testing the DUT: receiving a measurement signal on a first input channel and generating a first sample waveform from the measurement signal using a first parameter set; receiving the measurement signal on a second input channel and generating a second sample waveform from the measurement signal using a second parameter set; and generating a measurement waveform from a combination of the first sample waveform and the second sample waveform.

[0083] Example 6 is a test measurement system based on Example 5, in which the first and second parameter sets are signal quantization parameters.

[0084] Example 7 is a test measurement system based on Example 6, wherein the first quantization parameter set is selected to capture the entire dynamic range of the measurement signal.

[0085] Example 8 is a test measurement system based on Example 7, wherein the second quantization parameter set is selected to capture only a portion of the dynamic range of the measurement signal.

[0086] Example 9 is a test measurement system based on Example 8, wherein the user selects a portion of the above-mentioned dynamic range.

[0087] Example 10 is a test measurement system based on Example 8, wherein the portion of the dynamic range is determined by the measuring device based on user input.

[0088] Example 11 is a test measurement system based on any of Examples 5 to 10 described above, wherein one or more processors are configured to generate separate weighting coefficients for each of the first and second sample waveforms, and to generate a measurement waveform from the combination of the first and second sample waveforms by combining the first and second sample waveforms according to their respective separate weighting coefficients.

[0089] Example 12 is a test measurement system based on any of Examples 5 to 11 described above, wherein one or more processors are configured to generate a measurement waveform from a combination of the first sample waveform and the second sample waveform by performing a process to calculate an increment value and a process to apply the increment value to a set of sample values ​​determined to be a reference value set.

[0090] Example 13 is a method in a test measurement system comprising: a process of providing a DUT interface configured to be coupled to at least one device under test (DUT); a process of measuring the characteristics of a settling error during the first pulse of a double-pulse test performed on the DUT in a measuring device coupled to the DUT interface; and a process of correcting the settling error, whose characteristics were measured during the first pulse of the double-pulse test performed on the DUT, from a measurement value generated during the second pulse or a subsequent pulse of the double-pulse test.

[0091] Example 14 is a test measurement system based on Example 13, wherein the process for correcting the settling error includes a process for determining the change in voltage measured during the first pulse and the second pulse or subsequent pulse, and a process for determining the change in current measured during the first pulse and the second pulse or subsequent pulse.

[0092] Example 15 is a test measurement system based on Example 14, further comprising a process for determining the dynamic resistance measurement value of the DUT by dividing the voltage change by the current change.

[0093] Example 16 is a test measurement system based on any of Examples 13 to 15 described above, further comprising a process of initiating the second pulse of the double pulse test during a period determined by the settling time after the first pulse of the double pulse test.

[0094] Example 17 is a method in a test measurement system, comprising: a process of providing a DUT interface configured to be coupled to at least one device under test (DUT); a process of receiving a measurement signal on a first input channel and generating a first sample waveform from the measurement signal using a first parameter set in a measuring device coupled to the DUT interface; a process of receiving the measurement signal on a second input channel and generating a second sample waveform from the measurement signal using a second parameter set; and a process of generating a measurement waveform from a combination of the first sample waveform and the second sample waveform.

[0095] Example 18 is a method based on Example 17, wherein the first parameter set and the second parameter set are signal quantization parameters.

[0096] Example 19 is a method based on Example 18, wherein the first quantization parameter set is selected to capture the entire dynamic range of the measurement signal.

[0097] Example 20 is a method based on Example 19, wherein the second quantization parameter set is selected to capture only a portion of the dynamic range of the measurement signal.

[0098] Example 21 is a method based on Example 20, wherein the portion of the dynamic range is selected by the user.

[0099] Example 22 is a method based on Example 20, wherein the measuring device determines the portion of the dynamic range based on user input.

[0100] Example 23 is a method based on any of Examples 17 to 22 described above, wherein the process of generating a measurement waveform from a combination of the first sample waveform and the second sample waveform comprises the process of generating separate weighting coefficients for the first sample waveform and the second sample waveform, and the process of combining the first sample waveform and the second sample waveform according to the separate weighting coefficients.

[0101] Example 24 is a method based on any of Examples 17 to 23 described above, wherein the process of generating a measurement waveform from a combination of the first sample waveform and the second sample waveform includes the process of calculating an increment value and the process of applying the increment value to a sample value set determined to be a reference value set.

[0102] The above description of the present invention is provided solely for illustrative purposes and is not intended to limit it. Since modifications to the disclosed embodiments can be conceivable to those skilled in the art, the invention should be construed as encompassing the entirety of the present invention.

[0103] The above-described versions of the subject matter of this disclosure have many effects that have been described or will be apparent to those skilled in the art. Nevertheless, not all of these effects or features are required in all versions of the disclosed apparatus, system or method. All features disclosed herein, including the claims, abstract and drawings, and all steps in all disclosed methods or processes, may be combined as they see fit, as long as at least a portion of each is not mutually exclusive. Each of the features disclosed herein, including the claims, abstract and drawings, may be replaced by alternative features that serve the same, equivalent or similar purpose, unless otherwise specified.

[0104] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0105] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the invention. Therefore, the present invention should not be limited to anything other than the appended claims.

Claims

1. A DUT interface configured to be coupled to at least one device under test (DUT), A measuring device having one or more processors is coupled to the DUT interface. Equipped with, When performing a double-pulse test, one or more of the above processors A process for measuring the characteristics of the settling error during the first pulse of the double-pulse test, The process involves correcting the settling error, whose characteristics were measured during the first pulse of the double-pulse test, using measurements generated during the second pulse or subsequent pulses of the double-pulse test. A test and measurement system configured to execute a program that causes one or more of the above-mentioned processors to perform the above task.

2. A test measurement system according to claim 1, comprising a program that causes one or more processors to perform a process to correct the settling error described above, the program which causes one or more processors to perform a process to determine the change in voltage measured in the first pulse and the second or subsequent pulse, and a process to determine the change in current measured in the first pulse and the second or subsequent pulse.

3. A test and measurement system according to claim 2, further configured such that one or more of the above-mentioned processors execute a program that causes the one or more processors to perform a process of determining the dynamic resistance measurement value of the DUT by dividing the change in voltage by the change in current.

4. A test measurement system according to claim 1, wherein the first pulse and the second pulse of the double-pulse test described above are separated by a period determined by the settling time.

5. A DUT interface configured to be coupled to at least one device under test (DUT), A measuring device having one or more processors is coupled to the DUT interface. Equipped with, When testing the above DUT, one or more of the above processors The process involves receiving a measurement signal on the first input channel and generating a first sample waveform from the measurement signal using the first parameter set, The process involves receiving the above measurement signal on the second input channel and generating a second sample waveform from the above measurement signal using the second parameter set, A process to generate a measurement waveform from a combination of the above first sample waveform and the above second sample waveform. A test and measurement system configured to execute a program that causes one or more of the above-mentioned processors to perform the above task.

6. The above first and second parameter sets are signal quantization parameters in the test measurement system according to claim 5.

7. A test measurement system according to claim 6, wherein the first quantization parameter set is selected to capture the entire dynamic range of the measurement signal.

8. A test measurement system according to claim 7, wherein the second quantization parameter set is selected to capture only a portion of the dynamic range of the measurement signal.

9. A test measurement system according to claim 8, wherein the user selects a portion of the above-mentioned dynamic range.

10. A test measurement system according to claim 8, wherein the portion of the above dynamic range is determined by the measuring device based on user input.

11. A test measurement system according to claim 5, wherein one or more processors are configured to generate separate weighting coefficients for each of the first and second sample waveforms, and to generate a measurement waveform from the combination of the first and second sample waveforms by combining the first and second sample waveforms according to the respective separate weighting coefficients.

12. One or more of the above processors The process of calculating the increment value, The process involves applying the above increment value to the sample value set that has been determined to be the reference value set. A test measurement system according to claim 5, configured to generate a measurement waveform from a combination of the first sample waveform and the second sample waveform.

13. A method in a test measurement system, A process to provide a DUT interface configured to be coupled to at least one device under test (DUT), and a measuring device coupled to the DUT interface, The process of measuring the settling error characteristics during the first pulse of the double-pulse test performed on the above DUT, The process involves correcting the settling error, whose characteristics were measured during the first pulse of the double-pulse test performed on the above DUT, using the measured value generated during the second pulse or subsequent pulse of the double-pulse test. A method in a test and measurement system equipped with [a specific feature].

14. A method according to claim 13, wherein the process for correcting the above-mentioned settling error comprises a process for determining the change in voltage measured in the first pulse and the second pulse or subsequent pulse, and a process for determining the change in current measured in the first pulse and the second pulse or subsequent pulse.

15. The method according to claim 14, further comprising a process for determining the dynamic resistance measurement value of the DUT by dividing the change in voltage by the change in current.

16. The method according to claim 13, further comprising the step of initiating the second pulse of the double pulse test during a period determined by the settling time after the first pulse of the double pulse test.

17. A method in a test measurement system, A process to provide a DUT interface configured to be coupled to at least one device under test (DUT), and a measuring device coupled to the DUT interface, The process involves receiving a measurement signal on the first input channel and generating a first sample waveform from the measurement signal using the first parameter set, The process involves receiving the above measurement signal on the second input channel and generating a second sample waveform from the above measurement signal using the second parameter set, A process to generate a measurement waveform from a combination of the above first sample waveform and the above second sample waveform. A method in a test and measurement system equipped with [a specific feature].

18. The method according to claim 17, wherein the first parameter set and the second parameter set are signal quantization parameters.

19. A method according to claim 18, wherein the first set of quantization parameters is selected to capture the entire dynamic range of the measurement signal.

20. A method according to claim 19, wherein the second quantization parameter set is selected to capture only a portion of the dynamic range of the measurement signal.

21. The above portion of the dynamic range is selected by the user according to the method of claim 20.

22. A method according to claim 20, wherein the measuring device determines the portion of the dynamic range based on user input.

23. A method according to claim 17, wherein the process for generating a measurement waveform from a combination of the first sample waveform and the second sample waveform comprises the process of generating separate weighting coefficients for the first sample waveform and the second sample waveform, and the process of combining the first sample waveform and the second sample waveform according to the separate weighting coefficients.

24. A method according to claim 17, wherein the process of generating a measurement waveform from a combination of the above-mentioned first sample waveform and the above-mentioned second sample waveform comprises the process of calculating an increment value and the process of applying the above-mentioned increment value to a sample value set determined to be a reference value set.

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