Wafer-level gold etchant

By preparing a wafer-level gold etching solution of sodium thiosulfate, thiourea, potassium ferrocyanide and potassium iodide solution, the problems of excessive side drilling and metal shedding in the existing technology are solved, and smaller side drilling and a wider process window are achieved, which is suitable for high-precision gold patterning.

CN120738646APending Publication Date: 2025-10-03NORTH ELECTRON RES INST ANHUI CO LTD
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Patent Information

Application Number
CN202510964982.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-14
Publication Date
2025-10-03

AI Technical Summary

Technical Problem

Existing gold etching solutions have excessive side drilling during the etching process, resulting in line CD exceeding the limit or metal falling off, and cannot meet the needs of high-precision gold patterning.

Method used

A wafer-level gold etching solution composed of sodium thiosulfate, thiourea, potassium ferrocyanide and potassium iodide solutions in specific proportions is used. The proportions of complexing ligands, stabilizers, inhibitors and pH buffer are adjusted to control the etching rate and side drilling size.

Benefits of technology

It achieves smaller side drilling and a wider process window, improves process compatibility, is suitable for circuits with gold film layers above 0.5μm, and supports the manufacture of high-speed, high-power optoelectronic semiconductors and microsystem devices.

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Abstract

The invention relates to a wafer-level gold etchant which is characterized by being prepared from the following raw materials in percentage by weight: 8-12% of a sodium thiosulfate solution, 28-32% of a thiourea solution, 8-12% of a potassium ferricyanide solution and 48-52% of a potassium iodide solution. The wafer-level gold corrosive liquid disclosed by the invention has the advantages that the wafer-level gold corrosive liquid can be widely applied to a circuit which has a gold film layer thickness of more than 0.5 mu m and has a relatively high requirement on sidetrack control, so that the problems of overlarge sidetrack, line CD (Compact Disc) over-limit and even metal falling caused by corrosion of the original gold corrosive liquid are avoided. When the wafer-level gold etching liquid is used for etching, smaller sidetracking is achieved, a process window is wider, process compatibility is better, and process support is provided for high-speed and high-power photoelectric semiconductors and micro-system devices.
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